WO2023151544A1 - 一种滤波电路 - Google Patents

一种滤波电路 Download PDF

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Publication number
WO2023151544A1
WO2023151544A1 PCT/CN2023/074689 CN2023074689W WO2023151544A1 WO 2023151544 A1 WO2023151544 A1 WO 2023151544A1 CN 2023074689 W CN2023074689 W CN 2023074689W WO 2023151544 A1 WO2023151544 A1 WO 2023151544A1
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Prior art keywords
terminal
subunit
filter
current mirror
mirror group
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PCT/CN2023/074689
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English (en)
French (fr)
Inventor
杨晓风
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深圳市九天睿芯科技有限公司
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Publication of WO2023151544A1 publication Critical patent/WO2023151544A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/1213—Frequency selective two-port networks using amplifiers with feedback using transistor amplifiers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40—Arrangements for reducing harmonics

Definitions

  • the invention belongs to the technical field of electronic circuits, and in particular relates to a filter circuit.
  • the band-pass filter is a key module in signal frequency domain processing, and is the basis for analyzing the frequency domain characteristics of the input signal.
  • the filter can be divided into a digital filter and an analog filter according to different implementation methods.
  • analog filters Compared with high-speed high-precision analog-to-digital converters plus digital filters, analog filters have advantages in power consumption and chip area in application scenarios with strong low power consumption requirements.
  • Traditional analog filters are based on the transconductance of transistors and the capacitance of on-chip capacitors to achieve band-pass filtering. The transconductance of the transistor will work in the sub-threshold region, linear region and saturation region according to the gate-source voltage.
  • the transconductance of the transistor will change, which limits the output amplitude range of the filter signal without distortion.
  • the output of large signal amplitude can reduce the noise, interference and other requirements of other modules of the signal chain circuit connected after the filter, simplify its circuit design requirements, and improve accuracy.
  • the transconductance of a filter based on switched capacitors is determined by the capacitance of the capacitor and the switching frequency of the switch, and these parameters have nothing to do with the magnitude of the signal amplitude. Therefore, a switched-capacitor-based bandpass filter can achieve a large signal output while maintaining low distortion.
  • the traditional switched-capacitor-based bandpass filter has the disadvantage of requiring a large bias current to ensure that the transconductance variation of the transistor will not affect Effective transconductance of the filter.
  • a large bias current will generate a large offset current in a mirror circuit with the same matching degree, which will eventually lead to a large output offset voltage and affect the normal operation of the filter.
  • the traditional way to solve the output offset voltage is to strengthen the matching degree of the current mirror. However, this requires a large-sized current mirror, which increases the chip area and production cost.
  • the analog filter solves the power consumption problem of using high-speed and high-precision analog-to-digital converters and digital filters.
  • this often requires a set of Multi-channel band-pass filters with different center frequencies perform frequency-domain analysis and feature extraction on the signal, which requires a very high area.
  • Bluetooth earphones, smart watches, etc. whose printed circuit board area is very small, which limits the size of the chips used.
  • How to reduce power consumption and area while ensuring that the analog filter bank can meet the signal filtering requirements in the system has become a problem. A major technical difficulty.
  • the present application provides a filter circuit, which can ensure that the analog filter bank can meet the signal filtering requirements in the system while reducing power consumption and area.
  • the present invention provides following scheme:
  • a filter circuit including a second-order filter, a filter signal source and a common-mode voltage source;
  • One end of the filter signal source is connected to the first input end of the second-order filter, and one end of the common-mode voltage source is connected to the second input end of the second-order filter;
  • the second-order filter is configured to obtain a filter signal through the first input terminal, perform filtering processing on the filter signal according to the common-mode voltage obtained by the second input terminal, and output a target filter signal.
  • the second-order filter includes a first transconductance unit and a second transconductance unit;
  • the first end of the first transconductance unit is used to input the filter signal
  • the first end of the second transconductance unit is used to input the common mode voltage
  • the second end of the first transconductance unit and the The second terminal of the second transconductance unit is connected to output the target filter signal.
  • the second-order filter further includes a first integrating capacitor and a second integrating capacitor;
  • the first end of the first integrating capacitor is respectively connected to the second end of the first transconductance unit and the second end of the second transconductance unit, and the second end of the first integrating capacitor is grounded;
  • the first terminal of the second integrating capacitor is respectively connected to the third terminal and the fourth terminal of the first transconductance unit and the third terminal of the second transconductance unit, and the second terminal of the second integrating capacitor end grounded.
  • the first transconductance unit includes a first input subunit, a first output subunit, a first current mirror group, and a second current mirror group;
  • the first input subunit is configured to convert an input differential signal into a differential current
  • the first output subunit is connected to the first input subunit, and is used to guide the differential current to an output terminal of the first output subunit to output a target filter signal;
  • the first current mirror group is connected to the first input subunit and the first output subunit respectively, and is used to provide bias current for the first input subunit and the first output subunit;
  • the second current mirror group is connected to the first current mirror group, the first input subunit and the first output subunit respectively, and is used to provide bias for the first input subunit and the first output subunit current.
  • both the first terminal and the second terminal of the first input subunit are used to input the differential signal, and the third terminal and the fourth terminal of the first input subunit are respectively connected to the first current
  • the first end and the second end of the mirror group are connected correspondingly, the fifth end of the first input subunit is respectively connected with the first end and the second end of the second current mirror group, and the first input subunit
  • the sixth end is connected to the first end of the first output subunit;
  • Both the second terminal and the third terminal of the first output subunit are used to output the differential current, and the fourth terminal and the fifth terminal of the first output subunit are respectively connected to the first current mirror set of the first current mirror group.
  • the three terminals are correspondingly connected to the fourth terminal, and the sixth terminal and the seventh terminal of the first output subunit are correspondingly connected to the first terminal and the second terminal of the second current mirror group;
  • the fifth terminal of the first current mirror group is connected to the third terminal of the second current mirror group, the sixth terminal of the first current mirror group is connected to the power supply, and the seventh terminal of the first current mirror group is connected to the power supply.
  • the terminal is grounded; the fourth terminal of the second current mirror group is grounded.
  • the first input subunit includes a first filter bank and a second filter bank, and the first filter bank and the second filter bank respectively include several groups of filters connected in parallel;
  • the first output subunit includes a third filter bank and a fourth filter bank, and the third filter bank and the fourth filter bank respectively include several groups of filters connected in parallel;
  • the first current mirror one group includes a plurality of parallel-connected PMOS transistors;
  • the second current mirror group includes a plurality of parallel-connected NMOS transistors.
  • the first input subunit further includes a first switch controlled by a first clock signal and a second switch controlled by a second clock signal, the first switch is connected to the second switch, and the The first switch is also connected to the first filter bank, and the second switch is also connected to the second filter bank;
  • the second current mirror group further includes a third switch, a fourth switch, a fifth switch and a sixth switch controlled by a third clock signal, and the third switch, the fourth switch, the fifth switch and the sixth switch are respectively
  • the four PMOS transistors in the first current mirror group are correspondingly connected;
  • the second current mirror group also includes a seventh switch and an eighth switch controlled by a third clock signal, and the seventh switch and the eighth switch are respectively The two NMOS transistors in the second current mirror group are correspondingly connected.
  • the second transconductance unit includes a second input subunit, a second output subunit, a third current mirror group, and a fourth current mirror group;
  • the second input subunit is configured to convert an input differential signal into a differential current
  • the second output subunit is connected to the second input subunit, and is used to guide the differential current to an output terminal of the second output subunit to output a target filter signal;
  • the third current mirror group is connected to the second input subunit and the second output subunit respectively, and is used to provide bias current for the second input subunit and the second output subunit;
  • the fourth current mirror group is connected to the third current mirror group, the second input subunit and the second output subunit respectively, and is used to provide bias for the second input subunit and the second output subunit current.
  • both the first terminal and the second terminal of the second input subunit are used to input the differential signal, and the third terminal and the fourth terminal of the second input subunit are respectively connected to the third current
  • the first end and the second end of the mirror group are connected correspondingly, the fifth end of the second input subunit is respectively connected with the first end and the second end of the fourth current mirror group, and the second input subunit
  • the sixth end is connected to the first end of the second output subunit;
  • Both the second terminal and the third terminal of the second output subunit are used to output the differential current, and the fourth terminal and the fifth terminal of the second output subunit are respectively connected to the first terminal of the third current mirror group.
  • the three terminals are correspondingly connected to the fourth terminal, and the sixth terminal and the seventh terminal of the second output subunit are correspondingly connected to the first terminal and the second terminal of the fourth current mirror group;
  • the fifth terminal of the third current mirror group is connected to the third terminal of the fourth current mirror group, the sixth terminal of the third current mirror group is connected to the power supply, and the seventh terminal of the third current mirror group is connected to the power supply.
  • the terminal is grounded; the fourth terminal of the fourth current mirror group is grounded.
  • the second input subunit includes a fifth filter bank and a sixth filter bank, and the fifth filter bank and the sixth filter bank respectively include several sets of filters connected in parallel;
  • the second output subunit includes a seventh filter bank and an eighth filter bank, and the seventh filter bank and the eighth filter bank respectively include several groups of filters connected in parallel;
  • the third current The mirror group includes a plurality of parallel-connected PMOS transistors;
  • the fourth current mirror group includes a plurality of parallel-connected NMOS transistors.
  • the second input subunit further includes a ninth switch controlled by a first clock signal and a tenth switch controlled by a second clock signal, the ninth switch is connected to the tenth switch, and the The ninth switch is also connected to the fifth filter bank, and the tenth switch is also connected to the sixth filter bank;
  • the third current mirror group further includes an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch controlled by a third clock signal, and the eleventh switch, the twelfth switch, the tenth switch
  • the three switches and the fourteenth switch are respectively connected to the four PMOS transistors in the third current mirror group
  • the fourth current mirror group also includes a fifteenth switch and a sixteenth switch controlled by a third clock signal, The fifteenth switch and the sixteenth switch are respectively correspondingly connected to two NMOS transistors in the fourth current mirror group.
  • a filter circuit provided by the present application includes a second-order filter, a filter signal source, and a common-mode voltage source; one end of the filter signal source is connected to the first input end of the second-order filter, One end of the common mode voltage source is connected to the second input end of the second-order filter; the second-order filter is used to obtain a filter signal through the first input end, and according to the second input end The obtained common-mode voltage performs filtering processing on the filter signal, and outputs a target filter signal.
  • the filter circuit of the present application reduces the output DC voltage bias change of the band-pass filter bank according to the band-pass filter bank based on the switched capacitor and passes through the time-divided current mirror technology, and obtains the target filter signal that meets the requirements, and reduces the While reducing power consumption and area, ensure that the analog filter bank can meet the signal filtering requirements in the system.
  • FIG. 1 is a schematic structural diagram of a filter circuit provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a first implementation of a second-order filter provided in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a second implementation of a second-order filter provided in an embodiment of the present application
  • Fig. 4 is a schematic structural diagram of a first implementation of a first transconductance unit provided in an embodiment of the present application
  • Fig. 5 is a schematic structural diagram of a second implementation of the first transconductance unit provided in the embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of a second transconductance unit provided by an embodiment of the present application.
  • this application introduces the application scenarios that this application can provide, such as providing a filter circuit that can reduce power consumption and area while ensuring that the analog filter bank can meet the signal filtering requirements in the system.
  • FIG. 1 is a schematic structural diagram of a filter circuit provided by an embodiment of the present application.
  • the filter circuit includes a second-order filter 1000, a filter signal source 1100, and a common-mode voltage source 1200; one end of the filter signal source 1100 is connected to the first input end of the second-order filter 1000, and one end of the common-mode voltage source 1200 is connected to The second input terminal of the second-order filter 1000; the second-order filter 1000 is used to obtain the filter signal through the first input terminal, and filter the filter signal according to the common mode voltage obtained by the second input terminal, and output the target filter the signal.
  • FIG. 2 is a schematic structural diagram of a first implementation of a second-order filter provided in an embodiment of the present application.
  • the second-order filter may specifically include a first span The conduction unit 1010 and the second transconductance unit 1020.
  • the first terminal of the first transconductance unit 1010 is used to input the filter signal
  • the first terminal of the second transconductance unit 1020 is used to input the common mode voltage
  • the second end of 1020 is connected to output the target filtered signal.
  • the second-order filter further includes a first integrating capacitor 1030 and a second integrating capacitor 1040 .
  • the first end of the first integration capacitor 1030 is connected with the second end of the first transconductance unit 1010 and the second end of the second transconductance unit 1020 respectively, and the second end of the first integration capacitor 1030 is grounded; the second integration capacitor 1040
  • the first terminal of the first terminal is connected to the third terminal and the fourth terminal of the first transconductance unit 1010 and the third terminal of the second transconductance unit 1020 respectively, and the second terminal of the second integrating capacitor 1040 is grounded.
  • FIG. 3 is a schematic structural diagram of a second implementation of the second-order filter provided by the embodiment of the present application, mainly including two transconductance units (Gm1, Gm2), and integrating capacitors C1 and C2. , the filter signal input terminal Vs, the filter signal output terminal BPF_OUT and the filter output DC voltage BPFOUT_DC.
  • OTA in Figure 3 operational transconductance amplifier, transconductance operational amplifier.
  • FIG. 4 is a schematic structural diagram of a first implementation manner of a first transconductance unit provided in an embodiment of the present application.
  • the first transconductance unit 1010 may specifically include a first input subunit 1011 , a first output subunit 1012 , a first current mirror group 1013 and a second current mirror group 1014 .
  • the first input subunit 1011 is used to convert the input differential signal into a differential current; the first output subunit 1012 is connected to the first input subunit 1011 and is used to guide the differential current to the first output subunit 1012 to output the target filtered signal.
  • the output terminals of the first output subunit 1012 are respectively connected to the first terminal of the first integrating capacitor 1030 and the second terminal of the second transconductance unit 1020 .
  • the first current mirror group 1013 is respectively connected to the first input subunit 1011 and the first output subunit 1012, and is used to provide bias current for the first input subunit 1011 and the first output subunit 1012; the second current mirror group 1014, respectively with the first current mirror group 1013, the first input subunit
  • the unit 1011 is connected to the first output subunit 1012 for providing bias current for the first input subunit 1011 and the first output subunit 1012 .
  • both the first terminal and the second terminal of the first input subunit 1011 are used to input the differential signal, and the third terminal and the fourth terminal of the first input subunit 1011 are connected to the first terminal respectively.
  • the first end and the second end of a current mirror group 1013 are connected correspondingly, the fifth end of the first input subunit 1011 is respectively connected with the first end and the second end of the second current mirror group 1014, the first input subunit 1011
  • the sixth end of is connected to the first end of the first output subunit 1012 .
  • the first terminal Vip of the first input subunit 1011 serves as the first terminal of the first transconductance unit 1010
  • the second terminal Vin of the first input subunit 1011 serves as the third terminal of the first transconductance unit 1010 .
  • the differential signal mentioned in the present invention is the filter signal.
  • Both the second terminal and the third terminal of the first output subunit 1012 are used to output differential current, the fourth terminal and the fifth terminal of the first output subunit 1012 are respectively connected with the third terminal and the fourth terminal of the first current mirror group 1013
  • the terminals are correspondingly connected, and the sixth terminal and the seventh terminal of the first output subunit 1012 are respectively connected to the first terminal and the second terminal of the second current mirror group 1014 correspondingly.
  • the second terminal Voutp of the first output subunit 1012 serves as the second terminal of the first transconductance unit 1010
  • the third terminal Voutn of the first output subunit 1012 serves as the fourth terminal of the first transconductance unit 1010 .
  • the fifth end of the first current mirror group 1013 is connected to the third end of the second current mirror group 1014, the sixth end of the first current mirror group 1013 is connected to the power supply, and the seventh end of the first current mirror group 1013 is grounded; The fourth terminal of the second current mirror group 1014 is grounded.
  • the first input subunit 1011 includes a first filter bank and a second filter bank, and the first filter bank and the second filter bank respectively include several groups of filters connected in parallel;
  • the first output subunit 1012 includes a third filter bank and a fourth filter bank, and the third filter bank and the fourth filter bank respectively include several groups of filters connected in parallel;
  • the first current mirror group 1013 includes a plurality of parallel connected PMOS transistors;
  • the second current mirror group 1014 includes a plurality of parallel connected NMOS transistors.
  • the first current mirror group 1013 is connected to the second current mirror group 1014 .
  • the first filter bank includes several sets of filters connected in parallel
  • the second filter bank includes several sets of filter banks connected in parallel.
  • the structures of the first filter bank and the second filter bank are the same, and both Or connected by two switches, the two switches are controlled by different clock signals system, the first filter bank and the second filter bank are respectively used to input corresponding differential signals.
  • the first input subunit 1011 may further include a first switch controlled by the first clock signal and a second switch controlled by the second clock signal, the first switch is connected to the second switch , the first switch is also connected to the first filter bank, and the second switch is also connected to the second filter bank.
  • the second current mirror group 1014 also includes a third switch, a fourth switch, a fifth switch and a sixth switch controlled by a third clock signal, and the third switch, the fourth switch, the fifth switch and the sixth switch are respectively connected to the first Four PMOS transistors in a current mirror group 1013; the second current mirror group 1014 also includes the seventh switch and the eighth switch controlled by the third clock signal, and the seventh switch and the eighth switch are respectively connected to the second current mirror group Two NMOS transistors in 1014.
  • the switch of the first filter bank in the first input subunit 1011 is controlled by the first clock signal
  • the second filter bank in the first input subunit 1011 is controlled by the second clock signal
  • the switches of the PMOS transistors of the first current mirror group 1013 and the switches of the NMOS transistors of the second current mirror group 1014 are controlled by the third clock signal.
  • the first current mirror group 1013 in this embodiment is a pulse-controlled P-tube current mirror group
  • the second current mirror group 014 is a pulse-controlled N-tube current mirror group.
  • FIG. 5 is a schematic structural diagram of a second implementation manner of the first transconductance unit provided in the embodiment of the present application.
  • the first transconductance unit is a folded operational amplifier architecture
  • Vip and Vin are differential signals
  • Voutp and Voutn are differential output terminals
  • PMOS transistors M3, M4, M5, M6, M7 are a group of mirror current groups
  • NMOS Transistors M10, M11, M12 are another set of mirrored current sets.
  • the switches are controlled by clock signals ⁇ 1, ⁇ 2 and ⁇ 3, and when the clock control signal is at a high level, the controlled current is turned on.
  • the first current mirror group can In order to pulse control the P tube current mirror group, the second current mirror group can be a pulse control N tube mirror group, and finally convert the input differential signal (Vip and Vin) into a differential current through the first input subunit, and pass the first output
  • the subunits steer differential currents to Vout (Voutp and Voutn), providing low-impedance electrical
  • Vbn in Figure 5 is used for input bias voltage.
  • the current mirror will generate a set of identical currents.
  • each transistor will produce different deviations, and the main deviations are changes in size, which are changes in width (W) and length (L) and threshold voltage Vth, respectively.
  • the current is ID, and Vgs is the voltage between the gate and source of the transistor.
  • the calculation formula is:
  • the deviation of the threshold voltage Vth is a Gaussian random distribution process.
  • the width and length are larger, the area of the transistor is larger, and the mismatch ratio is smaller.
  • the larger the current of the mirror current source the larger the gate-source Vgs of the transistor, and the smaller the influence of the change of the threshold voltage Vth.
  • the transconductance unit needs a larger mirror current to make Vgs larger, so as to reduce the influence of changes in the threshold voltage Vth.
  • the mismatch ratio of the mirror current decreases, the absolute value of the mismatch mirror current increases.
  • the mismatched ambient image current will cause the DC voltage at the filter output terminal BPF_OUT to deviate from the voltage value of BPFOUT_DC, reducing the linear range of the output signal.
  • the DC voltage at the output end deviates too much, the signal output by the filter will be severely distorted.
  • this application combines the working principle of the switched capacitor and proposes that a small pulse width controls the conduction state of the current mirror.
  • the specific implementation principle is as follows: In order to achieve a high matching degree of the current mirror, the current mirror of the transconductance unit adopts a large bias current; since the switched capacitor only needs to work at the time of ⁇ 1 and ⁇ 2, the conduction time of the current mirror is controlled by the pulse ⁇ 3, When the switched capacitor is guaranteed to work, the tubes of the first input subunit 1011 and the first output subunit 1012 work in the saturation region.
  • the matching degree of the current environment is only proportional to ID, the matching degree of the current mirror will not follow the change of Iabs. Therefore, this solution solves the contradiction between the matching degree of the current mirror and the absolute mismatch current value, so that the smaller size of the current mirror can also ensure that the DC voltage deviation of BPF_OUT is small.
  • the current mirror when the current mirror is turned off, the current mirror can be switched to other filtering channels, thereby further reducing the area of the current mirror.
  • FIG. 6 is a schematic structural diagram of a second transconductance unit provided in an embodiment of the present application.
  • the second transconductance unit 1020 may specifically include a second input subunit 1021 , a second output subunit 1022 , a third current mirror group 1023 and a fourth current mirror group 1024 .
  • the second input subunit 1021 is used to convert the input differential signal into a differential current; the second output subunit 1022 is connected to the second input subunit 1021 and is used to guide the differential current to the output of the second output subunit 1022 terminal to output the target filtered signal.
  • the third current mirror group 1023 is respectively connected to the second input subunit 1021 and the second output subunit 1022, and is used to provide bias current for the second input subunit 1021 and the second output subunit 1022;
  • Four current mirror groups 1024 are respectively connected to the third current mirror group 1023, the second input subunit 1021 and the second output subunit 1022 for providing bias currents for the second input subunit 1021 and the second output subunit 1022 .
  • both the first terminal and the second terminal of the second input subunit 1021 are used to input differential signals, and the third terminal and the fourth terminal of the second input subunit 1021 are respectively connected to the third current
  • the first terminal and the second terminal of the mirror group 1023 are connected correspondingly
  • the fifth terminal of the second input subunit 1021 is respectively connected with the first terminal and the second terminal of the fourth current mirror group 1024
  • the second terminal of the second input subunit 1021 The six terminals are connected to the first terminal of the second output subunit 1022 .
  • Both the second terminal and the third terminal of the second output subunit 1022 are used to output differential current, the fourth terminal and the fifth terminal of the second output subunit 1022 are respectively connected with the third terminal and the fourth terminal of the third current mirror group 1023 The terminals are correspondingly connected, and the sixth terminal and the seventh terminal of the second output subunit 1022 are respectively connected correspondingly to the first terminal and the second terminal of the fourth current mirror group 1024 .
  • the fifth end of the third current mirror group 1023 is connected to the third end of the fourth current mirror group 1024, the sixth end of the third current mirror group 1023 is connected to the power supply, and the seventh end of the third current mirror group 1023 is grounded; The fourth terminal of the four current mirror group 1024 is grounded.
  • the second input subunit 1021 may specifically include a fifth filter bank and a sixth filter bank, and the fifth filter bank and the sixth filter bank respectively include several sets of parallel-connected filtering
  • the second output subunit 1022 includes the seventh filter bank and the eighth filter bank, and the seventh filter bank and the eighth filter bank respectively include several groups of filters connected in parallel;
  • the third current mirror group 1023 includes multiple PMOS transistors connected in parallel;
  • the fourth current mirror group 1024 includes a plurality of NMOS transistors connected in parallel.
  • the second input subunit 1021 may further include a ninth switch controlled by the first clock signal and a tenth switch controlled by the second clock signal, the ninth switch is connected to the tenth switch , the ninth switch is also connected to the fifth filter bank, and the tenth switch is also connected to the sixth filter bank.
  • the third current mirror group 1023 also includes the eleventh switch, the twelfth switch, the thirteenth switch and the fourteenth switch controlled by the third clock signal, the eleventh switch, the twelfth switch, the thirteenth switch and the The fourteenth switch is respectively connected to the four PMOS transistors in the third current mirror group 1023; the fourth current mirror group 1024 also includes the fifteenth switch and the sixteenth switch controlled by the third clock signal, the fifteenth switch and The sixteenth switch is correspondingly connected to two NMOS transistors in the fourth current mirror group 1024 .
  • the second input subunit 1021 further includes a ninth switch controlled by the first clock signal and a tenth switch controlled by the second clock signal, the ninth switch is connected to the tenth switch, and the ninth switch is also connected to the fifth The filter bank is connected, and the tenth switch is also connected with the sixth filter bank.
  • the third current mirror group 1023 also includes the eleventh switch, the twelfth switch, the thirteenth switch and the fourteenth switch controlled by the third clock signal, the eleventh switch, the twelfth switch, the thirteenth switch and the The fourteenth switch is respectively connected to the four PMOS transistors in the third current mirror group 1023; the fourth current mirror group 1024 also includes the fifteenth switch and the sixteenth switch controlled by the third clock signal, the fifteenth switch and The sixteenth switch is correspondingly connected to two NMOS transistors in the fourth current mirror group 1024 .
  • the circuit principle and specific circuit composition of the first transconductance unit and the second transconductance unit in this embodiment are the same, so they will not be described in detail here. Detailed description. Since the circuit principle and specific circuit composition of the first transconductance unit and the second transconductance unit are the same, so, with reference to FIG. 5 , the input Vip The port of the first transconductance unit 1010 is connected to the Voutp terminal of the first transconductance unit 1010 and the first integration capacitor C1, the port of the input Vin in the second transconductance unit 1020 inputs the common mode voltage, and the Voutp terminal of the second transconductance unit 1020 is connected to the second integration capacitor C1 C2 connection.
  • a filter circuit provided by the embodiment of the present application includes a second-order filter, a filter signal source, and a common-mode voltage source; one end of the filter signal source is connected to the first input end of the second-order filter, and the common-mode One end of the voltage source is connected to the second input end of the second-order filter; the second-order filter is used to obtain the filter signal through the first input end, and filter the filter signal according to the common-mode voltage obtained at the second input end , output the target filtered signal.
  • the filter circuit of the present application reduces the output DC voltage bias change of the band-pass filter bank according to the band-pass filter bank based on the switched capacitor and passes through the time-divided current mirror technology, and obtains the target filter signal that meets the requirements, and reduces the While reducing power consumption and area, ensure that the analog filter bank can meet the signal filtering requirements in the system.

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Abstract

本申请提出了一种滤波电路，属于电子电路技术领域，包括二阶滤波器、滤波器信号源和共模电压源；所述滤波器信号源的一端连接所述二阶滤波器的第一输入端，所述共模电压源的一端连接所述二阶滤波器的第二输入端；所述二阶滤波器，用于通过所述第一输入端获取滤波器信号，并根据所述第二输入端获取的共模电压对所述滤波器信号进行滤波处理，输出目标滤波信号。本申请能够减小带通滤波器组的输出直流电压偏置变化，得到符合要求的目标滤波信号，在降低功耗与面积的同时，保证模拟滤波器组能够满足系统中的信号滤波要求。

Description

一种滤波电路
本申请要求于2022年02月09日提交中国专利局、申请号为202210122351.4、发明名称为“一种滤波电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于电子电路技术领域，具体涉及一种滤波电路。
背景技术
带通滤波器是信号频域处理中的关键模块，是对输入信号的频域特性分析的基础。其中，滤波器可以根据实现的方式的不同分为数字滤波器与模拟滤波器。模拟滤波器在低功耗需求强烈的应用场景比高速高精度模数转换器加数字滤波器的方案更有功耗与芯片面积优势。传统的模拟滤波器是基于晶体管的跨导与片上电容的容值实现带通滤波的作用。晶体管的跨导根据栅源电压的大小会工作在亚阈值区，线性区和饱和区，而不同的区域，晶体管的跨导会发生变化，限制滤波器的信号不失真下的输出幅度范围。然而，大信号幅度的输出可以降低连接在滤波器之后的信号链电路的其它模块的噪声、干扰等要求，简化其电路设计要求，并提高精度。而基于开关电容的滤波器的跨导是通过电容的容值与开关切换的频率，这些参数都与信号幅度的大小没有关系。因此，基于开关电容的带通滤波器可以实现大信号输出并保持较低的失真。
然而，虽然基于开关电容的带通滤波器可以实现大幅度的线性输出范围，但是传统的基于开关电容的带通滤波器的缺点是需要一个大偏置电流，保证晶体管的跨导变化不会影响滤波器的有效跨导。大偏置电流在同样匹配度的镜像电路中，会产生一个大的失调电流，最终导致很大的输出失调电压，影响滤波器的正常工作。传统解决输出失调电压的方法是通过加强电流镜的匹配度，然而，这需要很大尺寸的电流镜，增大芯片面积与生产成本。而在语音识别的物联网系统中，模拟滤波器虽然解决了使用高速高精度的模数转换器和数字滤波器的功耗问题。但是，这往往需要一组 多通道不同中心频率的带通滤波器对信号进行频域分析与特征提取，对面积的要求非常高。比如，蓝牙耳机，智能手表等，其印刷电路板面积非常小，限制其所使用芯片的尺寸，如何在降低功耗与面积的同时，保证模拟滤波器组能够满足系统中的信号滤波要求成为了一大技术难点。
发明内容
针对上述技术问题，本申请提供一种滤波电路，能够在降低功耗与面积的同时，保证模拟滤波器组能够满足系统中的信号滤波要求。
为实现所述目的，本发明提供了如下方案：
一种滤波电路，包括二阶滤波器、滤波器信号源和共模电压源；
所述滤波器信号源的一端连接所述二阶滤波器的第一输入端，所述共模电压源的一端连接所述二阶滤波器的第二输入端；
所述二阶滤波器，用于通过所述第一输入端获取滤波器信号，并根据所述第二输入端获取的共模电压对所述滤波器信号进行滤波处理，输出目标滤波信号。
可选地，所述二阶滤波器包括第一跨导单元和第二跨导单元；
所述第一跨导单元的第一端用于输入滤波器信号，所述第二跨导单元的第一端用于输入共模电压，所述第一跨导单元的第二端和所述第二跨导单元的第二端连接，以用于输出目标滤波信号。
可选地，所述二阶滤波器还包括第一积分电容和第二积分电容；
所述第一积分电容的第一端分别与所述第一跨导单元的第二端和所述第二跨导单元的第二端连接，所述第一积分电容的第二端接地；
所述第二积分电容的第一端分别与所述第一跨导单元的第三端和第四端以及所述第二跨导单元的第三端连接，所述第二积分电容的第二端接地。
可选地，所述第一跨导单元包括第一输入子单元、第一输出子单元、第一电流镜组和第二电流镜组；
所述第一输入子单元，用于将输入的差分信号转换成差分电流；
所述第一输出子单元，与所述第一输入子单元连接，用于将所述差分电流引导至所述第一输出子单元的输出端，以输出目标滤波信号；
所述第一电流镜组，分别与所述第一输入子单元和第一输出子单元连接，用于为所述第一输入子单元和第一输出子单元提供偏置电流；
所述第二电流镜组，分别与所述第一电流镜组、第一输入子单元和第一输出子单元连接，用于为所述第一输入子单元和第一输出子单元提供偏置电流。
可选地，所述第一输入子单元的第一端和第二端均用于输入所述差分信号，所述第一输入子单元的第三端和第四端分别与所述第一电流镜组的第一端和第二端对应连接，所述第一输入子单元的第五端分别与所述第二电流镜组的第一端和第二端连接，所述第一输入子单元的第六端与所述第一输出子单元的第一端连接；
所述第一输出子单元的第二端和第三端均用于输出所述差分电流，所述第一输出子单元的第四端和第五端分别与所述第一电流镜组的第三端和第四端对应连接，所述第一输出子单元的第六端和第七端分别与所述第二电流镜组的第一端和第二端对应连接；
所述第一电流镜组的第五端与所述第二电流镜组的第三端连接，所述第一电流镜组的第六端与电源连接，所述第一电流镜组的第七端接地；所述第二电流镜组的第四端接地。
可选地，所述第一输入子单元包括第一滤波器组和第二滤波器组，所述第一滤波器组和所述第二滤波器组分别包括若干组并联连接的滤波器；所述第一输出子单元包括第三滤波器组和第四滤波器组，所述第三滤波器组和所述第四滤波器组分别包括若干组并联连接的滤波器；所述第一电流镜组包括多个并联连接的PMOS晶体管；所述第二电流镜组包括多个并联连接的NMOS晶体管。
可选地，所述第一输入子单元还包括由第一时钟信号控制的第一开关和由第二时钟信号控制的第二开关，所述第一开关与所述第二开关连接，所述第一开关还与所述第一滤波器组连接，所述第二开关还与所述第二滤波器组连接；
所述第二电流镜组还包括由第三时钟信号控制的第三开关、第四开关、第五开关和第六开关，所述第三开关、第四开关、第五开关和第六开关分别对应连接所述第一电流镜组中的四个PMOS晶体管；所述第二电流镜组还包括由第三时钟信号控制的第七开关和第八开关，所述第七开关和第八开关分别对应连接所述第二电流镜组中的两个NMOS晶体管。
可选地，所述第二跨导单元包括第二输入子单元、第二输出子单元、第三电流镜组和第四电流镜组；
所述第二输入子单元，用于将输入的差分信号转换成差分电流；
所述第二输出子单元，与所述第二输入子单元连接，用于将所述差分电流引导至所述第二输出子单元的输出端，以输出目标滤波信号；
所述第三电流镜组，分别与所述第二输入子单元和第二输出子单元连接，用于为所述第二输入子单元和第二输出子单元提供偏置电流；
所述第四电流镜组，分别与所述第三电流镜组、第二输入子单元和第二输出子单元连接，用于为所述第二输入子单元和第二输出子单元提供偏置电流。
可选地，所述第二输入子单元的第一端和第二端均用于输入所述差分信号，所述第二输入子单元的第三端和第四端分别与所述第三电流镜组的第一端和第二端对应连接，所述第二输入子单元的第五端分别与所述第四电流镜组的第一端和第二端连接，所述第二输入子单元的第六端与所述第二输出子单元的第一端连接；
所述第二输出子单元的第二端和第三端均用于输出所述差分电流，所述第二输出子单元的第四端和第五端分别与所述第三电流镜组的第三端和第四端对应连接，所述第二输出子单元的第六端和第七端分别与所述第四电流镜组的第一端和第二端对应连接；
所述第三电流镜组的第五端与所述第四电流镜组的第三端连接，所述第三电流镜组的第六端与电源连接，所述第三电流镜组的第七端接地；所述第四电流镜组的第四端接地。
可选地，所述第二输入子单元包括第五滤波器组和第六滤波器组，所述第五滤波器组和所述第六滤波器组分别包括若干组并联连接的滤波器； 所述第二输出子单元包括第七滤波器组和第八滤波器组，所述第七滤波器组和所述第八滤波器组分别包括若干组并联连接的滤波器；所述第三电流镜组包括多个并联连接的PMOS晶体管；所述第四电流镜组包括多个并联连接的NMOS晶体管。
可选地，所述第二输入子单元还包括由第一时钟信号控制的第九开关和由第二时钟信号控制的第十开关，所述第九开关与所述第十开关连接，所述第九开关还与所述第五滤波器组连接，所述第十开关还与所述第六滤波器组连接；
所述第三电流镜组还包括由第三时钟信号控制的第十一开关、第十二开关、第十三开关和第十四开关，所述第十一开关、第十二开关、第十三开关和第十四开关分别对应连接所述第三电流镜组中的四个PMOS晶体管；所述第四电流镜组还包括由第三时钟信号控制的第十五开关和第十六开关，所述第十五开关和第十六开关分别对应连接所述第四电流镜组中的两个NMOS晶体管。
本发明的有益效果是：
如上所述，本申请提供的一种滤波电路，包括二阶滤波器、滤波器信号源和共模电压源；所述滤波器信号源的一端连接所述二阶滤波器的第一输入端，所述共模电压源的一端连接所述二阶滤波器的第二输入端；所述二阶滤波器，用于通过所述第一输入端获取滤波器信号，并根据所述第二输入端获取的共模电压对所述滤波器信号进行滤波处理，输出目标滤波信号。本申请的滤波电路，根据基于开关电容的带通滤波器组并通过时分的电流镜的技术，减小带通滤波器组的输出直流电压偏置变化，得到符合要求的目标滤波信号，在降低功耗与面积的同时，保证模拟滤波器组能够满足系统中的信号滤波要求。
说明书附图
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出 创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的滤波电路的结构示意图；
图2是本申请实施例提供的二阶滤波器的第一种实施方式的结构示意图；
图3是本申请实施例提供的二阶滤波器的第二种实施方式的结构示意图；
图4是本申请实施例提供的第一跨导单元的第一种实施方式的结构示意图；
图5是本申请实施例提供的第一跨导单元的第二种实施方式的结构示意图；
图6是本申请实施例提供的第二跨导单元的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为使本发明的所述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
首先介绍本申请可以提供的应用场景，如提供一种滤波电路，能够在降低功耗与面积的同时，保证模拟滤波器组能够满足系统中的信号滤波要求。
请参阅图1，图1是本申请实施例提供的滤波电路的结构示意图。该滤波电路包括二阶滤波器1000、滤波器信号源1100和共模电压源1200；该滤波器信号源1100的一端连接二阶滤波器1000的第一输入端，共模电压源1200的一端连接二阶滤波器1000的第二输入端；二阶滤波器1000，用于通过第一输入端获取滤波器信号，并根据第二输入端获取的共模电压对滤波器信号进行滤波处理，输出目标滤波信号。
可选地，在一些实施例中，请参阅图2，图2是本申请实施例提供的二阶滤波器的第一种实施方式的的结构示意图，该二阶滤波器具体可以包括第一跨导单元1010和第二跨导单元1020。第一跨导单元1010的第一端用于输入滤波器信号，第二跨导单元1020的第一端用于输入共模电压，第一跨导单元1010的第二端和第二跨导单元1020的第二端连接，以用于输出目标滤波信号。
可选地，在一些实施例中，如图2所示，二阶滤波器还包括第一积分电容1030和第二积分电容1040。第一积分电容1030的第一端分别与第一跨导单元1010的第二端和第二跨导单元1020的第二端连接，第一积分电容1030的第二端接地；第二积分电容1040的第一端分别与第一跨导单元1010的第三端和第四端以及第二跨导单元1020的第三端连接，第二积分电容1040的第二端接地。
具体的，请参阅图3，图3是本申请实施例提供的二阶滤波器的第二种实施方式的的结构示意图，主要包括两个跨导单元(Gm1,Gm2)，积分电容C1与C2，滤波器信号输入端Vs，滤波器信号输出端BPF_OUT与滤波器输出的直流电压BPFOUT_DC。图3中的OTA：operational transconductance amplifier，跨导运算放大器。
可选地，在一些实施例中，请参阅图4，图4是本申请实施例提供的第一跨导单元的第一种实施方式的结构示意图。第一跨导单元1010具体可以包括第一输入子单元1011、第一输出子单元1012、第一电流镜组1013和第二电流镜组1014。
第一输入子单元1011，用于将输入的差分信号转换成差分电流；第一输出子单元1012，与第一输入子单元1011连接，用于将差分电流引导至所述第一输出子单元1012的输出端，以输出目标滤波信号。第一输出子单元1012的输出端分别与第一积分电容1030的第一端和第二跨导单元1020的第二端连接。
第一电流镜组1013，分别与第一输入子单元1011和第一输出子单元1012连接，用于为第一输入子单元1011和第一输出子单元1012提供偏置电流；第二电流镜组1014，分别与第一电流镜组1013、第一输入子单 元1011和第一输出子单元1012连接，用于为第一输入子单元1011和第一输出子单元1012提供偏置电流。
可选地，在一些实施例中，第一输入子单元1011的第一端和第二端均用于输入所述差分信号，第一输入子单元1011的第三端和第四端分别与第一电流镜组1013的第一端和第二端对应连接，第一输入子单元1011的第五端分别与第二电流镜组1014的第一端和第二端连接，第一输入子单元1011的第六端与第一输出子单元1012的第一端连接。第一输入子单元1011的第一端Vip作为第一跨导单元1010的第一端，第一输入子单元1011的第二端Vin作为第一跨导单元1010的第三端。本发明中提到的差分信号即为滤波器信号。
第一输出子单元1012的第二端和第三端均用于输出差分电流，第一输出子单元1012的第四端和第五端分别与第一电流镜组1013的第三端和第四端对应连接，第一输出子单元1012的第六端和第七端分别与第二电流镜组1014的第一端和第二端对应连接。第一输出子单元1012的第二端Voutp作为第一跨导单元1010的第二端，第一输出子单元1012的第三端Voutn作为第一跨导单元1010的第四端。
第一电流镜组1013的第五端与第二电流镜组1014的第三端连接，第一电流镜组1013的第六端与电源连接，第一电流镜组1013的第七端接地；第二电流镜组1014的第四端接地。
可选地，在一些实施例中，第一输入子单元1011包括第一滤波器组和第二滤波器组，第一滤波器组和第二滤波器组分别包括若干组并联连接的滤波器；第一输出子单元1012包括第三滤波器组和第四滤波器组，第三滤波器组和第四滤波器组分别包括若干组并联连接的滤波器；第一电流镜组1013包括多个并联连接的PMOS晶体管；第二电流镜组1014包括多个并联连接的NMOS晶体管。第一电流镜组1013和第二电流镜组1014连接。
具体的，第一滤波器组包括若干组并联连接的滤波器，第二滤波器组包括若干组并联连接的滤波器组，第一滤波器组和第二滤波器组的结构是相同的，两者通过两个开关连接，两个开关分别由不同的时钟信号进行控 制，第一滤波器组和第二滤波器组分别用于输入对应的差分信号。
可选地，在一些实施例中，第一输入子单元1011具体还可以包括由第一时钟信号控制的第一开关和由第二时钟信号控制的第二开关，第一开关与第二开关连接，第一开关还与第一滤波器组连接，第二开关还与第二滤波器组连接。
第二电流镜组1014还包括由第三时钟信号控制的第三开关、第四开关、第五开关和第六开关，第三开关、第四开关、第五开关和第六开关分别对应连接第一电流镜组1013中的四个PMOS晶体管；第二电流镜组1014还包括由第三时钟信号控制的第七开关和第八开关，第七开关和第八开关分别对应连接第二电流镜组1014中的两个NMOS晶体管。
具体的，在本实施例中，通过第一时钟信号控制第一输入子单元1011中的第一滤波器组的开关，通过第二时钟信号控制第一输入子单元1011中的第二滤波器组的开关，通过第三时钟信号控制第一电流镜组1013的PMOS晶体管的开关，以及第二电流镜组1014的NMOS晶体管的开关。其中，本实施例中的第一电流镜组1013为脉冲控制P管电流镜组，第二电流镜组014为脉冲控制N管电流镜组。
在本实施例中，请参阅图5所示，图5是本申请实施例提供的第一跨导单元的第二种实施方式的结构示意图。第一跨导单元是一个折叠型的运算放大器架构，Vip与Vin为差分信号，Voutp与Voutn为差分输出端，PMOS晶体管(M3,M4,M5,M6,M7)是一组镜像电流组，NMOS晶体管(M10,M11,M12)是另一组镜像电流组。开关由时钟信号Φ1、Φ2和Φ3控制，当时钟控制信号为高电平时，被控制的一路电流导通。再输入差分信号至第一输入子单元的两个滤波器组，第一电流镜组和第二电流镜组均与第一输入子单元和第一输出子单元连接，第一输入子单元和第一输出子单元连接，通过第一电流镜组和第二电流镜组提供第一输入子单元和第二输出子单元的偏置电流，使其管子工作在饱和区，其中第一电流镜组可以为脉冲控制P管电流镜组，第二电流镜组可以为脉冲控制N管镜组，最终通过第一输入子单元将输入的差分信号(Vip和Vin)转换为差分电流，并通过第一输出子单元将差分电流引导至Vout(Voutp与Voutn)，提供低阻抗电 路，在经过滤波处理后得到目标滤波信号。图5中的Vbn用于输入偏置电压。
需要说明的是，在理想的工艺制造条件下，电流镜像会产生一组完全相同的电流。然而，由于芯片实际制造过程中的偏差，每一个晶体管都会产生不同的偏差，其中主要的偏差表现为尺寸大小的改变，分别为宽度(W)与长度(L)以及阈值电压Vth的变化，晶体管的电流为ID，Vgs是晶体管栅源间电压，该计算公式为：
由于晶体管的长度与宽度偏差，阈值电压Vth偏差是一个高斯随机分布的过程，当宽度与长度越大时，晶体管的面积越大，失配的比例就越小。此外，镜像电流源的电流越大，晶体管栅源Vgs越大，阈值电压Vth的变化影响就越小。在传统的基于开关电容的滤波器中，如果没有电流导通控制开关，电流会一直导通。为了达到更好的镜像电流匹配，跨导单元需要较大的镜像电流使Vgs变大，以减小阈值电压Vth的变化影响。然而，镜像电流的失配比例虽然减小了，但失配的镜像电流绝对值却增大了。失配的境像电流会导致滤波器输出端BPF_OUT的直流电压偏BPFOUT_DC的电压值，减小了输出信号的线性范围。当输出端的直流电压偏离过大时，滤波器输出的信号会严重失真。
为了解决镜像电流匹配度与镜像电流的大小的矛盾，本申请结合开关电容的工作原理，提出小脉冲宽度控制电流镜的导通状态。具体实现原理如下：为了达到高的电流镜匹配度，跨导单元的电流镜采用大偏置电流；由于开关电容只需在Φ1和Φ2的时间工作，通过脉冲Φ3控制电流镜的导通时间，保证开关电容工作的时候，第一输入子单元1011与第一输出子单元1012的管子工作在饱和区。
本方案通过降低电流镜的导通时间，从一直导通改变为只导通Φ3的时间。当时钟周期为T时，电流为ID，周期T时内累积电流的绝对值Iabs为：
由于电流境的匹配度只与ID成正比，电流镜的匹配度不会跟随Iabs变化。因此，本方案解决电流镜匹配度与绝对失配电流值的矛盾，使得较小的电流镜尺寸也可保证BPF_OUT的直流电压偏离值小。此外，当电流镜处于关闭阶段时，电流镜可切换到其它的滤波通道，从而进一步降小电流镜的面积。
可选地，在一些实施例中，请参阅图6，图6是本申请实施例提供的第二跨导单元的结构示意图。第二跨导单元1020具体可以包括第二输入子单元1021、第二输出子单元1022、第三电流镜组1023和第四电流镜组1024。
第二输入子单元1021，用于将输入的差分信号转换成差分电流；第二输出子单元1022，与第二输入子单元1021连接，用于将差分电流引导至第二输出子单元1022的输出端，以输出目标滤波信号。
第三电流镜组1023，分别与所述第二输入子单元1021和第二输出子单元1022连接，用于为所述第二输入子单元1021和第二输出子单元1022提供偏置电流；第四电流镜组1024，分别与第三电流镜组1023、第二输入子单元1021和第二输出子单元1022连接，用于为第二输入子单元1021和第二输出子单元1022提供偏置电流。
可选地，在一些实施例中，第二输入子单元1021的第一端和第二端均用于输入差分信号，第二输入子单元1021的第三端和第四端分别与第三电流镜组1023的第一端和第二端对应连接，第二输入子单元1021的第五端分别与第四电流镜组1024的第一端和第二端连接，第二输入子单元1021的第六端与第二输出子单元1022的第一端连接。
第二输出子单元1022的第二端和第三端均用于输出差分电流，第二输出子单元1022的第四端和第五端分别与第三电流镜组1023的第三端和第四端对应连接，第二输出子单元1022的第六端和第七端分别与第四电流镜组1024的第一端和第二端对应连接。
第三电流镜组1023的第五端与第四电流镜组1024的第三端连接，第三电流镜组1023的第六端与电源连接，第三电流镜组1023的第七端接地；第四电流镜组1024的第四端接地。
可选地，在一些实施例中，第二输入子单元1021具体可以包括第五滤波器组和第六滤波器组，第五滤波器组和第六滤波器组分别包括若干组并联连接的滤波器；第二输出子单元1022包括第七滤波器组和第八滤波器组，第七滤波器组和第八滤波器组分别包括若干组并联连接的滤波器；第三电流镜组1023包括多个并联连接的PMOS晶体管；第四电流镜组1024包括多个并联连接的NMOS晶体管。
可选地，在一些实施例中，第二输入子单元1021具体还可以包括由第一时钟信号控制的第九开关和由第二时钟信号控制的第十开关，第九开关与第十开关连接，第九开关还与第五滤波器组连接，第十开关还与第六滤波器组连接。
第三电流镜组1023还包括由第三时钟信号控制的第十一开关、第十二开关、第十三开关和第十四开关，第十一开关、第十二开关、第十三开关和第十四开关分别对应连接第三电流镜组1023中的四个PMOS晶体管；第四电流镜组1024还包括由第三时钟信号控制的第十五开关和第十六开关，第十五开关和第十六开关分别对应连接第四电流镜组1024中的两个NMOS晶体管。
可选地，第二输入子单元1021还包括由第一时钟信号控制的第九开关和由第二时钟信号控制的第十开关，第九开关与第十开关连接，第九开关还与第五滤波器组连接，第十开关还与第六滤波器组连接。
第三电流镜组1023还包括由第三时钟信号控制的第十一开关、第十二开关、第十三开关和第十四开关，第十一开关、第十二开关、第十三开关和第十四开关分别对应连接第三电流镜组1023中的四个PMOS晶体管；第四电流镜组1024还包括由第三时钟信号控制的第十五开关和第十六开关，第十五开关和第十六开关分别对应连接第四电流镜组1024中的两个NMOS晶体管。
需要说明的是，本实施例中的第一跨导单元和第二跨导单元的电路原理及具体电路组成是相同的，因此在此不再详细阐述，可参照上述对第一跨导单元的详细说明。由于第一跨导单元和第二跨导单元的电路原理及具体电路组成是相同的，所以，参照图5，第二跨导单元1020中输入Vip 的端口与第一跨导单元1010的Voutp端和第一积分电容C1连接，第二跨导单元1020中输入Vin的端口输入共模电压，第二跨导单元1020的Voutp端与第二积分电容C2连接。
由上可知，本申请实施例提供的一种滤波电路，包括二阶滤波器、滤波器信号源和共模电压源；滤波器信号源的一端连接二阶滤波器的第一输入端，共模电压源的一端连接二阶滤波器的第二输入端；二阶滤波器，用于通过第一输入端获取滤波器信号，并根据第二输入端获取的共模电压对滤波器信号进行滤波处理，输出目标滤波信号。本申请的滤波电路，根据基于开关电容的带通滤波器组并通过时分的电流镜的技术，减小带通滤波器组的输出直流电压偏置变化，得到符合要求的目标滤波信号，在降低功耗与面积的同时，保证模拟滤波器组能够满足系统中的信号滤波要求。
以上结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本发明的保护之内。

Claims (11)

  1. 一种滤波电路，其特征在于，包括二阶滤波器、滤波器信号源和共模电压源；
    所述滤波器信号源的一端连接所述二阶滤波器的第一输入端，所述共模电压源的一端连接所述二阶滤波器的第二输入端；
    所述二阶滤波器，用于通过所述第一输入端获取滤波器信号，并根据所述第二输入端获取的共模电压对所述滤波器信号进行滤波处理，输出目标滤波信号。
  2. 根据权利要求1所述的滤波电路，其特征在于，所述二阶滤波器包括第一跨导单元和第二跨导单元；
    所述第一跨导单元的第一端用于输入滤波器信号，所述第二跨导单元的第一端用于输入共模电压，所述第一跨导单元的第二端和所述第二跨导单元的第二端连接，以用于输出目标滤波信号。
  3. 根据权利要求2所述的滤波电路，其特征在于，所述二阶滤波器还包括第一积分电容和第二积分电容；
    所述第一积分电容的第一端分别与所述第一跨导单元的第二端和所述第二跨导单元的第二端连接，所述第一积分电容的第二端接地；
    所述第二积分电容的第一端分别与所述第一跨导单元的第三端和第四端以及所述第二跨导单元的第三端连接，所述第二积分电容的第二端接地。
  4. 根据权利要求2或3所述的滤波电路，其特征在于，所述第一跨导单元包括第一输入子单元、第一输出子单元、第一电流镜组和第二电流镜组；
    所述第一输入子单元，用于将输入的差分信号转换成差分电流；
    所述第一输出子单元，与所述第一输入子单元连接，用于将所述差分电流引导至所述第一输出子单元的输出端，以输出目标滤波信号；
    所述第一电流镜组，分别与所述第一输入子单元和第一输出子单元连接，用于为所述第一输入子单元和第一输出子单元提供偏置电流；
    所述第二电流镜组，分别与所述第一电流镜组、第一输入子单元和第一输出子单元连接，用于为所述第一输入子单元和第一输出子单元提供偏置电流。
  5. 根据权利要求4所述的滤波电路，其特征在于，所述第一输入子单元的第一端和第二端均用于输入所述差分信号，所述第一输入子单元的第三端和第四端分别与所述第一电流镜组的第一端和第二端对应连接，所述第一输入子单元的第五端分别与所述第二电流镜组的第一端和第二端连接，所述第一输入子单元的第六端与所述第一输出子单元的第一端连接；
    所述第一输出子单元的第二端和第三端均用于输出所述差分电流，所述第一输出子单元的第四端和第五端分别与所述第一电流镜组的第三端和第四端对应连接，所述第一输出子单元的第六端和第七端分别与所述第二电流镜组的第一端和第二端对应连接；
    所述第一电流镜组的第五端与所述第二电流镜组的第三端连接，所述第一电流镜组的第六端与电源连接，所述第一电流镜组的第七端接地；所述第二电流镜组的第四端接地。
  6. 根据权利要求5所述的滤波电路，其特征在于，所述第一输入子单元包括第一滤波器组和第二滤波器组，所述第一滤波器组和所述第二滤波器组分别包括若干组并联连接的滤波器；所述第一输出子单元包括第三滤波器组和第四滤波器组，所述第三滤波器组和所述第四滤波器组分别包括若干组并联连接的滤波器；所述第一电流镜组包括多个并联连接的PMOS晶体管；所述第二电流镜组包括多个并联连接的NMOS晶体管。
  7. 根据权利要求6所述的滤波电路，其特征在于，所述第一输入子单元还包括由第一时钟信号控制的第一开关和由第二时钟信号控制的第二开关，所述第一开关与所述第二开关连接，所述第一开关还与所述第一滤波器组连接，所述第二开关还与所述第二滤波器组连接；
    所述第二电流镜组还包括由第三时钟信号控制的第三开关、第四开关、第五开关和第六开关，所述第三开关、第四开关、第五开关和第六开关分别对应连接所述第一电流镜组中的四个PMOS晶体管；所述第二电 流镜组还包括由第三时钟信号控制的第七开关和第八开关，所述第七开关和第八开关分别对应连接所述第二电流镜组中的两个NMOS晶体管。
  8. 根据权利要求2或3所述的滤波电路，其特征在于，所述第二跨导单元包括第二输入子单元、第二输出子单元、第三电流镜组和第四电流镜组；
    所述第二输入子单元，用于将输入的差分信号转换成差分电流；
    所述第二输出子单元，与所述第二输入子单元连接，用于将所述差分电流引导至所述第二输出子单元的输出端，以输出目标滤波信号；
    所述第三电流镜组，分别与所述第二输入子单元和第二输出子单元连接，用于为所述第二输入子单元和第二输出子单元提供偏置电流；
    所述第四电流镜组，分别与所述第三电流镜组、第二输入子单元和第二输出子单元连接，用于为所述第二输入子单元和第二输出子单元提供偏置电流。
  9. 根据权利要求8所述的滤波电路，其特征在于，所述第二输入子单元的第一端和第二端均用于输入所述差分信号，所述第二输入子单元的第三端和第四端分别与所述第三电流镜组的第一端和第二端对应连接，所述第二输入子单元的第五端分别与所述第四电流镜组的第一端和第二端连接，所述第二输入子单元的第六端与所述第二输出子单元的第一端连接；
    所述第二输出子单元的第二端和第三端均用于输出所述差分电流，所述第二输出子单元的第四端和第五端分别与所述第三电流镜组的第三端和第四端对应连接，所述第二输出子单元的第六端和第七端分别与所述第四电流镜组的第一端和第二端对应连接；
    所述第三电流镜组的第五端与所述第四电流镜组的第三端连接，所述第三电流镜组的第六端与电源连接，所述第三电流镜组的第七端接地；所述第四电流镜组的第四端接地。
  10. 根据权利要求9所述的滤波电路，其特征在于，所述第二输入子单元包括第五滤波器组和第六滤波器组，所述第五滤波器组和所述第六滤波器组分别包括若干组并联连接的滤波器；所述第二输出子单元包括第七滤波器组和第八滤波器组，所述第七滤波器组和所述第八滤波器组分别包 括若干组并联连接的滤波器；所述第三电流镜组包括多个并联连接的PMOS晶体管；所述第四电流镜组包括多个并联连接的NMOS晶体管。
  11. 一种滤波电路，其特征在于，包括二阶滤波器；
    二阶滤波器中的每一个跨导单元均为基于开关电容的带通滤波器组；
    所述带通滤波器组中的电流镜组用于在所述带通滤波器组的开关电容工作的时候导通，使得开关电容工作的时候，所述带通滤波器组的晶体管工作在饱和区；
    所述带通滤波器组用于获取滤波器信号和共模电压，并根据所述共模电压对所述滤波器信号进行滤波处理，以输出目标滤波信号。
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