WO2023143488A1 - 低功耗晶振起振电路、芯片及电子设备 - Google Patents

低功耗晶振起振电路、芯片及电子设备 Download PDF

Info

Publication number
WO2023143488A1
WO2023143488A1 PCT/CN2023/073508 CN2023073508W WO2023143488A1 WO 2023143488 A1 WO2023143488 A1 WO 2023143488A1 CN 2023073508 W CN2023073508 W CN 2023073508W WO 2023143488 A1 WO2023143488 A1 WO 2023143488A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
circuit
crystal oscillator
clock signal
voltage
Prior art date
Application number
PCT/CN2023/073508
Other languages
English (en)
French (fr)
Inventor
江力
白瑞林
Original Assignee
深圳英集芯科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳英集芯科技股份有限公司 filed Critical 深圳英集芯科技股份有限公司
Publication of WO2023143488A1 publication Critical patent/WO2023143488A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L3/00—Starting of generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0082—Lowering the supply voltage and saving power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0094—Measures to ensure starting of oscillations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to a low-power crystal oscillator starting circuit, chip and electronic equipment.
  • Quartz crystal oscillators are electronic devices produced based on the piezoelectric effect of quartz crystals. They are widely used because they can provide clock signals with stable and reliable frequencies, especially for electronic products that require very high clock accuracy.
  • the power consumption of the start-up circuit of the crystal oscillator is positively correlated with the amplitude of the clock signal, and the larger the amplitude is, the greater the power consumption is. Therefore, the current power consumption of the start-up circuit of the crystal oscillator is relatively high.
  • the crystal oscillator start-up circuit is used to provide the clock for the chip system. Even if the electronic device enters the standby state, the start-up circuit cannot be turned off. Therefore, the high-power crystal oscillator start-up circuit will increase the standby power consumption of the electronic device.
  • Embodiments of the present application provide a low-power crystal oscillator starting circuit, chip and electronic equipment, which can reduce the power consumption of the crystal oscillator starting circuit, thereby reducing the standby power consumption of the electronic equipment and prolonging the standby time of the electronic equipment.
  • an embodiment of the present application provides a low-power crystal oscillator start-up circuit.
  • the low-power crystal oscillator start-up circuit includes a bias circuit, a drive circuit, and a crystal oscillator generation circuit.
  • the input terminal of the bias circuit is connected to VDD power supply, the output end of the bias circuit is connected to the first input end of the driving circuit, the second input end of the driving circuit is connected to the output end of the crystal generator circuit, and the output end of the driving circuit is connected to the The input terminal of the crystal oscillator generation circuit;
  • the bias circuit is used to provide an operating voltage to the driving circuit
  • the drive circuit is used to convert the first clock signal into a second clock signal, the first clock signal is the clock signal generated by the crystal oscillator generation circuit, and the second clock signal is the inverse of the first clock signal
  • the amplitude of the second clock signal is directly proportional to the value of the operating voltage.
  • an embodiment of the present application provides a chip, the chip including the low-power crystal oscillator start-up circuit described in the first aspect.
  • an embodiment of the present application provides an electronic device, the electronic device comprising the low-power crystal oscillator starting circuit described in the first aspect above or the chip described in the second aspect above.
  • the low-power crystal oscillator start-up circuit proposed by this application includes a bias circuit, a drive circuit and a crystal generator circuit, the input end of the bias circuit is connected to the VDD power supply, the output end of the bias circuit is connected to the first input end of the drive circuit, and the drive The second input end of the circuit is connected to the output end of the crystal oscillator generating circuit, and the output end of the driving circuit is connected to the input end of the crystal oscillator generating circuit; wherein the bias circuit is used to provide an operating voltage to the driving circuit; the driving circuit is used to convert the first clock signal is the second clock signal, the first clock signal is the clock signal generated by the crystal oscillator generating circuit, the second clock signal is the reverse clock signal of the first clock signal, and the amplitude of the second clock signal is proportional to the value of the working voltage.
  • the present application provides a small working voltage for the drive circuit through the bias circuit, thereby reducing the power consumption of the crystal oscillator circuit, thereby reducing the standby power consumption of the electronic
  • FIG. 1 is a schematic structural diagram of a low-power crystal oscillator start-up circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a bias circuit 100 provided in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a driving circuit 200 provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a crystal oscillator generating circuit 300 provided by an embodiment of the present application.
  • the crystal oscillator circuit generally adopts a Pierce (Pierce) structure, uses an inverter as a drive circuit, and directly drives the inverter by a fixed voltage power supply, in order to cover PVT (process, voltage, The impact of temperature (temperature) conditions on the crystal oscillator circuit, and in order to ensure the absolute safety of the crystal oscillator circuit, the power supply voltage will be set relatively high, generally 3.3v or 2.5v.
  • the amplitude of the clock signal output by the crystal oscillator circuit is consistent with the value of the power supply voltage, and the power consumption of the crystal oscillator circuit is also positively correlated with the amplitude of the clock signal. The greater the amplitude of the clock signal, the greater the power consumption.
  • the power consumption of the crystal oscillator starting circuit is relatively high.
  • the crystal oscillator circuit is used to provide the clock for the chip system of the electronic device, so even if the electronic device enters the standby state, the crystal oscillator circuit cannot be turned off, and in the entire standby power consumption in the standby state, the crystal oscillator circuit’s Power consumption often occupies a dominant position, so reducing the power consumption of the crystal oscillator start-up circuit needs to be solved urgently.
  • this application proposes a low-power crystal oscillator start-up circuit, in which a bias circuit is connected in series on the drive circuit, and a small operating voltage is provided for the drive circuit through the bias circuit to reduce the amplitude of the clock signal. Therefore, the power consumption of the crystal oscillator starting circuit is reduced, thereby reducing the standby power consumption of the electronic equipment and prolonging the standby time of the electronic equipment.
  • FIG. 1 is a schematic structural diagram of a low-power crystal oscillator start-up circuit provided by an embodiment of the present application.
  • the low-power crystal oscillator starting circuit includes a bias circuit 100, a drive circuit 200 and a crystal generator circuit 300, the input end of the bias circuit 100 is connected to the VDD power supply, and the output end of the bias circuit 100 is connected to the drive circuit 200, the second input terminal of the driving circuit 200 is connected to the output terminal of the crystal oscillator generation circuit 300, and the driving circuit 200 The output terminal is connected to the input terminal of the crystal oscillator generation circuit 300 .
  • the bias circuit 100 is used to provide an operating voltage to the driving circuit 200; the driving circuit 200 is used to convert the first clock signal into a second clock signal, and the first clock signal is generated by the crystal oscillator
  • the clock signal generated by the circuit 300, the second clock signal is an inverse clock signal of the first clock signal, and the amplitude of the second clock signal is proportional to the value of the operating voltage.
  • the crystal oscillator generating circuit 300 generates a first clock signal and inputs it to the driving circuit 200, and the driving circuit 200 converts the first clock signal into a second clock signal that is opposite to the first clock signal, and converts the second clock signal to The signal is fed back to the crystal oscillator generation circuit 300 to drive it to generate the next first clock signal.
  • the amplitude of the second clock signal is proportional to the input voltage (i.e., operating voltage) of the drive circuit 200, so the present application connects a bias circuit 100 in series with the drive circuit 200, and reduces the voltage provided by the VDD power supply through the bias circuit 100.
  • FIG. 2 is a schematic structural diagram of a bias circuit 100 provided in an embodiment of the present application.
  • the bias circuit 100 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a current source and a first resistor R1.
  • the first transistor Q1 , the second transistor Q2 , the third transistor Q3 and the seventh transistor Q7 are all P-channel MOS transistors.
  • the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6 and the eighth transistor Q8 are all N-channel MOS transistors.
  • the source of the first transistor Q1 is respectively connected to the input terminal of the bias circuit 100, the source of the second transistor Q2, and the source of the third transistor Q3, and the first transistor
  • the gate of Q1 is respectively connected to the drain of the first transistor Q1, the gate of the second transistor Q2 and the drain of the fourth transistor Q4, and the drain of the second transistor Q2 is respectively connected to the first
  • the gate of the third transistor Q3 and the drain of the sixth transistor Q6, the drain of the third transistor Q3 are respectively connected to the output terminal of the bias circuit 100 and the source of the seventh transistor Q7
  • the The gate of the fourth transistor Q4 is respectively connected to the gate of the fifth transistor Q5, the drain of the fifth transistor Q5, the current source and the gate of the sixth transistor Q6, and the fourth transistor Q4
  • the source of the fifth transistor Q5 is respectively connected to the source of the sixth transistor Q6, the source of the eighth transistor Q8 and the first The other end of the resistor R1 and the gate of the seventh transistor Q7 are respectively connected to the drain of the seventh transistor Q7,
  • the size of the first transistor Q1 is the same as that of the second transistor Q2
  • the size of the fifth transistor Q5 is the same as that of the sixth transistor Q6, and the size of the fourth transistor Q4 is smaller than the size of the sixth transistor Q6.
  • the size of the first transistor Q1 is the same as that of the second transistor Q2, and the source and gate of the first transistor Q1 are respectively connected to the source and gate of the second transistor Q2, so the second transistor Q2 A transistor Q1 and a second transistor Q2 form a mirror current source.
  • the size of the fifth transistor Q5 is the same as that of the sixth transistor Q6, and the source and gate of the fifth transistor Q5 are respectively connected to the source and gate of the sixth transistor Q6, so that the fifth transistor Q5 and the sixth transistor Q6 Six transistors Q6 form a mirror current source.
  • the size of the fourth transistor Q4 in this application is smaller than the size of the fifth transistor Q5 and/or the sixth transistor Q6.
  • the size of the fifth transistor Q5 and the sixth transistor Q6 both take a value of 4u/2u, and the size of the fourth transistor Q4 can take a value of 2u/2u.
  • the VDD power supply turns on all the transistors in the bias circuit 100, and then the current source provides a small bias current Ib, and the bias current Ib flows to the branch where the fifth transistor Q5 is located, and because the fifth transistor Q5 Q5 and the sixth transistor Q6 form a mirror current source, so that the currents flowing through the fifth transistor Q5 and the sixth transistor Q6 are completely equal.
  • the first transistor Q1 and the second transistor Q2 form a mirror current source, the current flowing through the fourth transistor Q4 is copied to the second transistor Q2, and the branch current of the second transistor Q2 only flows to the branch of the sixth transistor Q6. Therefore, the branch current of the second transistor Q2 is equal to the branch current of the sixth transistor Q6.
  • the current flowing through the first resistor R1 is Vr/R1, wherein the current flowing through the first resistor R1 includes the current flowing through the fifth transistor Q5 and the sixth transistor Q6, that is, the current flowing through the first resistor R1 includes 2 *Ib.
  • the branch current flowing through the seventh transistor Q7 and the eighth transistor Q8 Can be Vr/R1-2*Ib.
  • the working voltage is equal to the sum of the first voltage, the first threshold voltage, and the second threshold voltage
  • the first threshold voltage is the threshold voltage of the seventh transistor
  • the second threshold voltage is the The threshold voltage of the eighth transistor
  • the first voltage is the voltage across the first resistor.
  • the branch currents of the seventh transistor Q7 and the eighth transistor Q8 can be adjusted by adjusting the resistance value of the first resistor R1, so the branch current can be designed to a very small value, so that the seventh transistor
  • the voltage drop of Q7 and the eighth transistor Q8 can be equivalent to respective threshold voltages Vth7 and Vth8, so that the voltage value of the working voltage Vxtal provided by the output of the bias circuit 100 for the driving circuit 200 is equal to Vth7+Vth8+Vr.
  • the first voltage Vr is usually only tens of mv or lower, while vth7 and vth8 are usually on the order of hundreds of mv, so the working voltage Vxtal is approximately Vth7+Vth8.
  • the entire bias circuit 100 forms a stable static operating point, even if the driving circuit 200 draws current from the bias circuit 100 , the static operating point will not be changed.
  • the first voltage Vr will also decrease accordingly, and the voltage at the source of the sixth transistor Q6 will also decrease, but since the voltage at the gate of the sixth transistor Q6 does not Therefore, the current of the sixth transistor Q6 increases, and the current of the second transistor Q2 is equal to the current of the fourth transistor, so the current of the second transistor Q2 remains unchanged. In this way, the second transistor Q2 will pull down the Vg node voltage, so that the current of the third transistor Q3 will increase, and the voltage of the working voltage Vxtal will be pulled up again.
  • the currents of the fifth transistor Q5 and the sixth transistor are equal and both are Ib
  • the currents of the first transistor Q1 and the second transistor Q2 are equal and both are Ib
  • the currents of the fourth transistor Q4 and the sixth transistor Q6 are also equal and Both are Ib, so the first voltage can be calculated according to the currents at both ends of the fourth transistor Q4 and the sixth transistor Q6.
  • the branch current I1 of the eighth transistor Q8 can be preset, and then the value of the first resistor R1 can be calculated through the first voltage vr.
  • the application can use the eighth transistor The branch current I1 of Q8 is set to a smaller current value.
  • FIG. 3 is a schematic structural diagram of a driving circuit 200 provided in an embodiment of the present application.
  • the driving circuit 200 includes a ninth transistor Q9 and a tenth transistor Q10 .
  • the source of the ninth transistor Q9 is connected to the first input terminal of the driving circuit 200, and the gate of the ninth transistor Q9 is connected to the second input terminal of the driving circuit 200 and the tenth transistor Q10
  • the drain of the ninth transistor Q9 is respectively connected to the output terminal of the driving circuit 200 and the drain of the tenth transistor Q10, and the source of the tenth transistor Q10 is grounded.
  • the ninth transistor Q9 and the tenth transistor Q10 are connected in the form of diodes and connected in series to form an inverter structure, which converts the first clock signal output by the crystal oscillator generation circuit 300 into an inverted second clock signal, and The second clock signal is fed back to the crystal oscillator generating circuit 300 to drive the crystal oscillator components to work, wherein the amplitude of the output second clock signal is determined by the working voltage Vxtal output by the bias circuit 100 .
  • the size of the seventh transistor is the same as that of the ninth transistor, and the size of the eighth transistor is the same as that of the tenth transistor.
  • the present application sets the seventh transistor Q7 to completely match the ninth transistor Q9, and the eighth transistor Q8 to completely match the tenth transistor Q10, that is, the seventh transistor Q7
  • the size and threshold voltage Vth of the ninth transistor Q9 are the same, and the size of the eighth transistor Q8 and the tenth transistor Q10 are the same and the threshold voltage Vth is the same.
  • the threshold voltage Vth9 of the ninth transistor Q9 and the threshold voltage Vth7 of the seventh transistor Q7 is the same as the threshold voltage Vth8 of the eighth transistor Q8.
  • the working voltage Vxtal is related to the threshold voltage Vth7 of the seventh transistor Q7 and the threshold voltage Vth8 of the eighth transistor Q8, it is not affected by the VDD supply voltage.
  • the operating voltage Vxtal also changes accordingly.
  • the ninth transistor Q9 and the tenth transistor Q10 only work under these two threshold voltages, and then the amplitude of the second clock signal has only two threshold voltages, thereby greatly reducing the power consumption of the driving circuit 200 .
  • FIG. 4 is a schematic structural diagram of a crystal oscillator generating circuit 300 provided in an embodiment of the present application.
  • the crystal oscillator generating circuit 300 includes a second resistor R2 , a first capacitor C1 , a second capacitor C2 and passive crystal oscillator components.
  • one end of the second resistor R2 is respectively connected to the input end of the crystal oscillator generating circuit 300, the input end of the passive crystal oscillator component and one end of the first capacitor C1, and the other end of the first capacitor C1
  • One end is grounded
  • the other end of the second resistor R2 is respectively connected to the output end of the crystal oscillator generating circuit 300, the output end of the passive crystal oscillator component and one end of the second capacitor C2, and the second capacitor C2 The other end of the ground.
  • the above-mentioned second resistor R2 is a feedback resistor, which is used to feed back the output terminal signal of the driving circuit 200 to the second input terminal to form a negative feedback method circuit, and is used to make the driving circuit 200 work in a linear region with a large gain.
  • the above-mentioned first capacitor C1 and second capacitor C2 are both load capacitors, which are used to affect the load resonance frequency and equivalent load resonance resistance. Together with the passive crystal oscillator components, they determine the operating frequency of the crystal oscillator circuit. By adjusting the load capacitance, the crystal oscillator can be The operating frequency of the circuit is fine-tuned to the nominal value. Among them, increasing the load capacitance will decrease the oscillation frequency, while decreasing the load capacitance will increase the oscillation frequency.
  • the sum of the first threshold voltage and the second threshold voltage is greater than or equal to the driving voltage of the passive crystal oscillator component.
  • the voltage of Vth7+Vth8 needs to be greater than or equal to the minimum driving voltage value required by the passive crystal oscillator components.
  • this application can also be applied as needed At this time, passive crystal oscillator components with lower driving voltage requirements can be selected, thereby reducing the power consumption of the crystal oscillator start-up circuit.
  • the low-power crystal oscillator start-up circuit provided by the embodiment of the present application includes a bias circuit, a drive circuit and a crystal oscillator generation circuit, the input end of the bias circuit is connected to the VDD power supply, and the output end of the bias circuit is connected to the drive circuit.
  • the first input terminal, the second input terminal of the driving circuit is connected to the output terminal of the crystal oscillator generating circuit, and the output terminal of the driving circuit is connected to the input terminal of the crystal oscillator generating circuit; wherein the bias circuit is used to provide an operating voltage to the driving circuit; the driving circuit is used for Convert the first clock signal to the second clock signal, the first clock signal is the clock signal generated by the crystal oscillator generation circuit, the second clock signal is the reverse clock signal of the first clock signal, the amplitude of the second clock signal is related to the operating voltage
  • the values are proportional to each other.
  • the present application provides a small working voltage for the drive circuit through the bias circuit, thereby reducing the power consumption of the crystal oscillator circuit, thereby reducing the standby power consumption of the electronic equipment and prolonging the standby time of the electronic equipment.
  • the embodiment of the present application further provides a chip, the chip includes any low-power crystal oscillator start-up circuit described in the above-mentioned embodiments.
  • the embodiment of the present application also provides an electronic device, the electronic device includes any one of the chip or the low-power crystal oscillator starting circuit described in the above-mentioned embodiments.
  • the disclosed low-power crystal oscillator starting circuit can be implemented in other ways.
  • the embodiment of the low power consumption crystal oscillator circuit described above is only illustrative, for example, other components with the same function may be used for the components in the above circuit.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of circuits or components may be in electrical or other forms.
  • each circuit in each embodiment of the present application may be integrated into one circuit board, each circuit may exist separately, or two or more circuits may be integrated into one circuit board.

Landscapes

  • Oscillators With Electromechanical Resonators (AREA)

Abstract

本申请实施例公开了一种低功耗晶振起振电路、芯片及电子设备，该电路包括偏置电路、驱动电路和晶振生成电路，偏置电路的输出端连接驱动电路的第一输入端，驱动电路的第二输入端连接晶振生成电路的输出端，驱动电路的输出端连接晶振生成电路的输入端；偏置电路用于向驱动电路提供工作电压；驱动电路用于将第一时钟信号转变为第二时钟信号，第一时钟信号为晶振生成电路产生的时钟信号，第二时钟信号为第一时钟信号的反向时钟信号，第二时钟信号的振幅与工作电压的值成正比例关系。本申请通过偏置电路为驱动电路提供一个较小的工作电压，降低时钟信号的振幅，从而降低了晶振起振电路的功耗，减少电子设备的待机功耗，延长电子设备的待机时间。

Description

低功耗晶振起振电路、芯片及电子设备
本申请要求于2022年01月29日提交中国专利局、申请号为202210110859.2、申请名称为“低功耗晶振起振电路、芯片及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种低功耗晶振起振电路、芯片及电子设备。
背景技术
石英晶体振荡器是根据石英晶体的压电效应生产的电子器件，由于其可以提供频率稳定可靠的时钟信号而得到广泛应用，尤其是对时钟精度要求非常高的电子产品。
晶体振荡器的起振电路的功耗与时钟信号的幅度呈正相关，其幅度越大功耗也越大，因此目前的晶振起振电路的功耗都比较高。而晶振起振电路是用于为芯片系统提供时钟，即使电子设备进入待机状态，起振电路也依然不能关闭，因此高功耗的晶振起振电路会提高电子设备待机功耗。
发明内容
本申请实施例提供了一种低功耗晶振起振电路、芯片及电子设备，能够降低晶振起振电路的功耗，进而减少电子设备的待机功耗，延长电子设备的待机时间。
第一方面，本申请实施例提供的一种低功耗晶振起振电路，所述低功耗晶振起振电路包括偏置电路、驱动电路和晶振生成电路，所述偏置电路的输入端连接VDD电源，所述偏置电路的输出端连接所述驱动电路的第一输入端，所述驱动电路的第二输入端连接所述晶振生成电路的输出端，所述驱动电路的输出端连接所述晶振生成电路的输入端；其中，
所述偏置电路用于向所述驱动电路提供工作电压；
所述驱动电路用于将第一时钟信号转变为第二时钟信号，所述第一时钟信号为所述晶振生成电路产生的时钟信号，所述第二时钟信号为所述第一时钟信号的反向时钟信号，所述第二时钟信号的振幅与所述工作电压的值成正比例关系。
第二方面，本申请实施例提供一种芯片，所述芯片包括上述第一方面所述的低功耗晶振起振电路。
第三方面，本申请实施例提供一种电子设备，所述电子设备包括上述第一方面所述的低功耗晶振起振电路或上述第二方面所述的芯片。
本申请提出的低功耗晶振起振电路，包括偏置电路、驱动电路和晶振生成电路，偏置电路的输入端连接VDD电源，偏置电路的输出端连接驱动电路的第一输入端，驱动电路的第二输入端连接晶振生成电路的输出端，驱动电路的输出端连接晶振生成电路的输入端；其中偏置电路用于向驱动电路提供工作电压；驱动电路用于将第一时钟信号转变为第二时钟信号，第一时钟信号为晶振生成电路产生的时钟信号，第二时钟信号为第一时钟信号的反向时钟信号，第二时钟信号的振幅与工作电压的值成正比例关系。本申请通过偏置电路为驱动电路提供一个较小的工作电压，从而降低了晶振起振电路的功耗，进而减少电子设备的待机功耗，延长电子设备的待机时间。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种低功耗晶振起振电路的结构示意图；
图2是本申请实施例提供的一种偏置电路100的结构示意图；
图3是本申请实施例提供的一种驱动电路200的结构示意图；
图4是本申请实施例提供的一种晶振生成电路300的结构示意图。
具体实施方式
为了本技术领域人员更好理解本申请的技术方案，下面结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的部分实施例，而并非全部的实施例。基于本申请实施例的描述，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请所保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如，包含了一系列步骤或单元的过程、方法、软件、产品或设备没有限定于已列出的步骤或单元，而是还包括没有列出的步骤或单元，或还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
目前，晶振起振电路一般采用皮尔斯(Pierce)结构，使用反相器作为驱动电路，并且直接由一个固定电压的电源来驱动反相器，为了覆盖PVT(工艺(process)、电压(voltage)、温度(temperature))条件变化对晶振起振电路的影响，同时也为了保证晶振起振电路的绝对安全，会将电源电压设置的比较高，一般为3.3v或2.5v。其中晶振起振电路输出时钟信号的振幅与电源电压的数值一致，而晶振起振电路的功耗也与时钟信号的振幅呈正相关，其时钟信号的振幅越大其功耗也越大，因此目前的晶振起振电路的功耗都比较高。而晶振起振电路是用于为电子设备的芯片系统提供时钟，因此即使电子设备进入待机状态，晶振起振电路也依然不能关闭，并且待机状态时的整个待机功耗中，晶振起振电路的功耗往往占据主导地位，因此，降低晶振起振电路的功耗正亟待解决。
为了解决上述问题，本申请提出了一种低功耗晶振起振电路，在驱动电路上串联一个偏置电路，通过偏置电路为驱动电路提供一个较小的工作电压，降低时钟信号的振幅，从而降低晶振起振电路的功耗，进而减少电子设备的待机功耗，延长电子设备的待机时间。
下面结合附图对本申请实施例进行介绍，附图中相交导线的交叉处有圆点表示导线相接，交叉处无圆点表示导线不相接。
请参阅图1，图1是本申请实施例提供的一种低功耗晶振起振电路的结构示意图。该低功耗晶振起振电路包括偏置电路100、驱动电路200和晶振生成电路300，所述偏置电路100的输入端连接VDD电源，所述偏置电路100的输出端连接所述驱动电路200的第一输入端，所述驱动电路200的第二输入端连接所述晶振生成电路300的输出端，所述驱动电路200的 输出端连接所述晶振生成电路300的输入端。
其中，所述偏置电路100用于向所述驱动电路200提供工作电压；所述驱动电路200用于将第一时钟信号转变为第二时钟信号，所述第一时钟信号为所述晶振生成电路300产生的时钟信号，所述第二时钟信号为所述第一时钟信号的反向时钟信号，所述第二时钟信号的振幅与所述工作电压的值成正比例关系。
在具体实现中，晶振生成电路300生成第一时钟信号输入至驱动电路200，驱动电路200将第一时钟信号转变成与该第一时钟信号反相的第二时钟信号，并将该第二时钟信号反馈给晶振生成电路300以驱动其生成下一第一时钟信号。其中第二时钟信号的振幅与驱动电路200的输入电压(即工作电压)呈比例关系，因此本申请在驱动电路200上串联一个偏置电路100，通过偏置电路100降低VDD电源所提供的电压，使得提供给驱动电路200的工作电压较小，从而减小了时钟信号的振幅，进而降低了晶振起振电路的功耗，减少电子设备的待机功耗，延长电子设备的待机时间。
示例的，请参阅图2，图2是本申请实施例提供的一种偏置电路100的结构示意图。如图2所示，该偏置电路100包括第一晶体管Q1、第二晶体管Q2、第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第六晶体管Q6、第七晶体管Q7、第八晶体管Q8、电流源和第一电阻R1。
其中，上述第一晶体管Q1、第二晶体管Q2、第三晶体管Q3和第七晶体管Q7均为P沟道的MOS晶体管。上述第四晶体管Q4、第五晶体管Q5、第六晶体管Q6和第八晶体管Q8均为N沟道的MOS晶体管。
可选的，所述第一晶体管Q1的源极分别连接所述偏置电路100的输入端、所述第二晶体管Q2的源极以及所述第三晶体管Q3的源极，所述第一晶体管Q1的栅极分别连接所述第一晶体管Q1的漏极、所述第二晶体管Q2的栅极以及所述第四晶体管Q4的漏极，所述第二晶体管Q2的漏极分别连接所述第三晶体管Q3的栅极和所述第六晶体管Q6的漏极，所述第三晶体管Q3的漏极分别连接所述偏置电路100的输出端和所述第七晶体管Q7的源极，所述第四晶体管Q4的栅极分别连接所述第五晶体管Q5的栅极、所述第五晶体管Q5的漏极、所述电流源以及所述第六晶体管Q6的栅极，所述第四晶体管Q4的源极连接所述第一电阻R1的一端并接地，所述第五晶体管Q5的源极分别连接所述第六晶体管Q6的源极、所述第八晶体管Q8的源极以及所述第一电阻R1的另一端，所述第七晶体管Q7的栅极分别连接所述第七晶体管Q7的漏极、所述第八晶体管Q8的栅极以及所述第八晶体管Q8的漏极。
可选的，所述第一晶体管Q1的尺寸与所述第二晶体管Q2的尺寸相同，所述第五晶体管Q5的尺寸与所述第六晶体管Q6的尺寸相同，所述第四晶体管Q4的尺寸小于所述第六晶体管Q6的尺寸。
在本申请实施例中，该第一晶体管Q1的尺寸与第二晶体管Q2的尺寸相同，且第一晶体管Q1的源极和栅极分别与第二晶体管Q2的源极和栅极连接，因此第一晶体管Q1和第二晶体管Q2组成一个镜像电流源。
同理，第五晶体管Q5的尺寸与第六晶体管Q6的尺寸相同，且第五晶体管Q5的源极和栅极分别与第六晶体管Q6的源极和栅极连接，使得第五晶体管Q5和第六晶体管Q6组成一个镜像电流源。
进一步地，本申请中的第四晶体管Q4的尺寸小于第五晶体管Q5和/或第六晶体管Q6的尺寸。例如，第五晶体管Q5和第六晶体管Q6尺寸均取值为4u/2u，则第四晶体管Q4的尺寸可取值为2u/2u。
其中，VDD电源将偏置电路100中的所有晶体管均导通，然后电流源提供一个很小的偏置电流Ib，该偏置电流Ib流向第五晶体管Q5所在的支路，而由于第五晶体管Q5与第六晶体管Q6组成了镜像电流源，使得流经第五晶体管Q5和流经第六晶体管Q6的电流完全相等。同时，由于第一晶体管Q1和第二晶体管Q2组成了镜像电流源，从而将流经第四晶体管Q4电流复制给第二晶体管Q2，而第二晶体管Q2支路电流又只流向第六晶体管Q6支路，所以第二晶体管Q2的支路电流与第六晶体管Q6的支路电流相等。这样迫使第四晶体管Q4的电流与第六晶体管Q6的电流相同，而由于第六晶体管Q6的尺寸大于第四晶体管的尺寸，为了保持电流相等，第六晶体管Q6源端的电压会升高至一定数值Vr。此时流过第一电阻R1的电流为Vr/R1，其中流过第一电阻R1的电流包括流过第五晶体管Q5和第六晶体管Q6的电流，即流过第一电阻R1的电流包括2*Ib。由于流过第一电阻R1的电流包括第五晶体管Q5的电流、第六晶体管Q6、第七晶体管Q7或第八晶体管Q8的电流，因此流过第七晶体管Q7与第八晶体管Q8的支路电流可以为Vr/R1-2*Ib。
可选的，所述工作电压等于第一电压、第一阈值电压、第二阈值电压的和，所述第一阈值电压为所述第七晶体管的阈值电压，所述第二阈值电压为所述第八晶体管的阈值电压，所述第一电压为所述第一电阻两端的电压。
在本申请中，通过调整第一电阻R1的阻值可以调节第七晶体管Q7与第八晶体管Q8的支路电流，因此可以将该支路电流设计成一个很小的数值，进而使得第七晶体管Q7和第八晶体管Q8的压降可以分别等效成各自的阈值电压Vth7和Vth8，从而使得偏置电路100的输出的为驱动电路200提供的工作电压Vxtal的电压值等于Vth7+Vth8+Vr。
示例的，第一电压Vr通常只有几十mv或者更低，而vth7和vth8通常为几百mv量级，所以工作电压Vxtal就近似为Vth7+Vth8。此时整个偏置电路100形成一个稳定的静态工作点，即使驱动电路200从偏置电路100中抽取电流，也不会改变该静态工作点。比如，假设工作电压Vxtal电压因驱动电路200抽取电流而降低，那么第一电压Vr也会随之降低，第六晶体管Q6源极的电压也会降低，但由于第六晶体管Q6栅极的电压没变，因此第六晶体管Q6的电流就会增大，而第二晶体管Q2的电流与第四晶体管的电流相等，因此第二晶体管Q2的电流不变。这样第二晶体管Q2就会把Vg节点电压拉低，从而第三晶体管Q3的电流就会变大，重新将工作电压Vxtal的电压拉升回去。
其中，由于第五晶体管Q5与第六晶体管的电流相等且均为Ib，第一晶体管Q1与第二晶体管Q2的电流相等且均为Ib，第四晶体管Q4与第六晶体管Q6的电流也相等且均为Ib，因此根据第四晶体管Q4和第六晶体管Q6两端的电流可计算出第一电压。
具体地，MOS晶体管的电流计算公式可表示为：I＝1/2*μ*Cox*(W/L)*(Vgs-Vth)2，其中μ为载流子迁移率，是常数，Cox是绝缘层介电常数，W为MOS管沟道宽度，L为MOS管沟道长度，Vgs为栅源电压，Vth为mos管阈值电压。其中第四晶体管的电流I4＝1/2*μ*Cox*(W4/L)*(Vgs4-Vth)2＝Ib，第六晶体管Q6的电流I6＝1/2*μ*Cox*(W6/L)*(Vgs6-Vth)2＝Ib。由于第四晶体管Q4的源极接地，第六晶体管Q6的源极的电压为vr，因此vgs4＝vgs2+vr，进而根据I4＝I6，可以推倒出(W4/L)*(Vgs4-Vth)2＝(W6/L)*(Vgs6-Vth)，把Vgs4用vgs6+vr代替，则得到(W4/L)*(Vgs6+vr-Vth)2＝(W6/L)*(Vgs6-Vth)2。将第四晶体管Q4和第六晶体管Q6的尺寸代入进去，可以计算得到第一电压vr。
进一步地，第一电阻R1的计算公式可以表示为：R1＝vr/(Ib+Ib+I1)，其中I1是第八晶体管Q8的支路电流。本申请可预先设置第八晶体管Q8的支路电流I1，进而通过第一电压vr可以计算得到第一电阻R1的数值。其中为了达到低功耗的目的，本申请可将第八晶体管 Q8的支路电流I1设置成较小电流值。
示例的，请参阅图3，图3为本申请实施例提供的一种驱动电路200的结构示意图。如图3所示，该驱动电路200包括第九晶体管Q9和第十晶体管Q10。
其中，所述第九晶体管Q9的源极连接所述驱动电路200的第一输入端，所述第九晶体管Q9的栅极连接所述驱动电路200的第二输入端和所述第十晶体管Q10的栅极，所述第九晶体管Q9的漏极分别连接所述驱动电路200的输出端和所述第十晶体管Q10的漏极，所述第十晶体管Q10的源极接地。
其中，第九晶体管Q9和第十晶体管Q10连接成二极管的形式并串联起来形成一个反相器的结构，将晶振生成电路300输出的第一时钟信号转变成反向的第二时钟信号，并将该第二时钟信号反馈给晶振生成电路300以驱动晶振元器件进行工作，其中输出的第二时钟信号的振幅由偏置电路100输出的工作电压Vxtal所决定。
可选的，所述第七晶体管的尺寸与所述第九晶体管的尺寸相同，所述第八晶体管的尺寸与所述第十晶体管的尺寸相同。
其中，为了是驱动电路200的工作电压较小以降低其功耗，本申请设置第七晶体管Q7与第九晶体管Q9完全匹配、第八晶体管Q8与第十晶体管Q10完全匹配，即第七晶体管Q7与第九晶体管Q9的尺寸和阈值电压Vth均相同，第八晶体管Q8与第十晶体管Q10的尺寸相同和阈值电压Vth均相同。
在本申请实施例中，由于第七晶体管Q7与第九晶体管Q9完全匹配、第八晶体管Q8与第十晶体管Q10完全匹配，因此第九晶体管Q9的阈值电压Vth9与第七晶体管Q7的阈值电压Vth7相同、第十晶体管Q10的阈值电压Vth10与第八晶体管Q8的阈值电压Vth8相同。而由于工作电压Vxtal与第七晶体管Q7的阈值电压Vth7以及第八晶体管Q8的阈值电压Vth8有关，不受VDD电源电压的影响。因此在工艺偏差或温度变化使得的第七晶体管Q7的阈值电压Vth7以及第八晶体管Q8的阈值电压Vth8产生变化时，工作电压Vxtal也随之变化。这样使得第九晶体管Q9和第十晶体管Q10仅工作在这两个阈值电压下，进而使得第二时钟信号的振幅就只有两个阈值电压，从而大幅降低了驱动电路200的功耗。
示例的，请参阅图4，图4是本申请实施例提供的一种晶振生成电路300的结构示意图。如图4所示，该晶振生成电路300包括第二电阻R2、第一电容C1、第二电容C2和无源晶振元器件。
其中，所述第二电阻R2的一端分别连接所述晶振生成电路300的输入端、所述无源晶振元器件的输入端以及所述第一电容C1的一端，所述第一电容C1的另一端接地，所述第二电阻R2的另一端分别连接所述晶振生成电路300的输出端、所述无源晶振元器件的输出端以及所述第二电容C2的一端，所述第二电容C2的另一端接地。
其中，上述第二电阻R2为反馈电阻，用于将驱动电路200的输出端信号反馈给第二输入端，构成负反馈方法电路，用于让驱动电路200工作在增益较大的线性区。上述第一电容C1和第二电容C2均为负载电容，用于影响负载谐振频率和等效负载谐振电阻，与无源晶振元器件一起决定晶振电路的工作频率，通过调整负载电容，可以将晶振电路的工作频率微调到标称值。其中增大负载电容会使振荡频率下降，而减小负载电容会使振荡频率升高。
可选的，所述第一阈值电压和所述第二阈值电压的和大于或等于所述无源晶振元器件的驱动电压。
在本申请实施例中，为了使得无源晶振元器件能够正常工作，需要Vth7+Vth8的电压大于或等于无源晶振元器件所要求的最低驱动电压值。示例的，本申请也可以根据需要在应用 时可以选择驱动电压要求较低的无源晶振元器件，进而减小晶振起振电路的功耗。
可以看出，本申请实施例提供的低功耗晶振起振电路，包括偏置电路、驱动电路和晶振生成电路，偏置电路的输入端连接VDD电源，偏置电路的输出端连接驱动电路的第一输入端，驱动电路的第二输入端连接晶振生成电路的输出端，驱动电路的输出端连接晶振生成电路的输入端；其中偏置电路用于向驱动电路提供工作电压；驱动电路用于将第一时钟信号转变为第二时钟信号，第一时钟信号为晶振生成电路产生的时钟信号，第二时钟信号为第一时钟信号的反向时钟信号，第二时钟信号的振幅与工作电压的值成正比例关系。本申请通过偏置电路为驱动电路提供一个较小的工作电压，从而降低了晶振起振电路的功耗，进而减少电子设备的待机功耗，延长电子设备的待机时间。
本申请实施例还提供一种芯片，所述芯片包括上述实施例记载的任一低功耗晶振起振电路。
本申请实施例还提供一种电子设备，所述电子设备包括上述实施例记载的任一所述的芯片或低功耗晶振起振电路。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的低功耗晶振起振电路，可通过其它的方式实现。例如，以上所描述的低功耗晶振起振电路实施例仅仅是示意性的，例如上述电路中的元器件也可以采用其他相同功能的元器件。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，电路或元器件的间接耦合或通信连接，可以是电性或其它的形式。
另外，在本申请各个实施例中的各电路可以集成在一个电路板中，也可以是各个电路单独物存在，也可以两个或两个以上电路集成在一个电路板中。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上上述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种低功耗晶振起振电路，其特征在于，所述低功耗晶振起振电路包括偏置电路、驱动电路和晶振生成电路，所述偏置电路的输入端连接VDD电源，所述偏置电路的输出端连接所述驱动电路的第一输入端，所述驱动电路的第二输入端连接所述晶振生成电路的输出端，所述驱动电路的输出端连接所述晶振生成电路的输入端；其中，
    所述偏置电路用于向所述驱动电路提供工作电压；
    所述驱动电路用于将第一时钟信号转变为第二时钟信号，所述第一时钟信号为所述晶振生成电路产生的时钟信号，所述第二时钟信号为所述第一时钟信号的反向时钟信号，所述第二时钟信号的振幅与所述工作电压的值成正比例关系。
  2. 根据权利要求1所述的电路，其特征在于，所述偏置电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、电流源和第一电阻；
    所述第一晶体管的源极分别连接所述偏置电路的输入端、所述第二晶体管的源极以及所述第三晶体管的源极，所述第一晶体管的栅极分别连接所述第一晶体管的漏极、所述第二晶体管的栅极以及所述第四晶体管的漏极，所述第二晶体管的漏极分别连接所述第三晶体管的栅极和所述第六晶体管的漏极，所述第三晶体管的漏极分别连接所述偏置电路的输出端和所述第七晶体管的源极，所述第四晶体管的栅极分别连接所述第五晶体管的栅极、所述第五晶体管的漏极、所述电流源以及所述第六晶体管的栅极，所述第四晶体管的源极连接所述第一电阻的一端并接地，所述第五晶体管的源极分别连接所述第六晶体管的源极、所述第八晶体管的源极以及所述第一电阻的另一端，所述第七晶体管的栅极分别连接所述第七晶体管的漏极、所述第八晶体管的栅极以及所述第八晶体管的漏极。
  3. 根据权利要求2所述的电路，其特征在于，所述第一晶体管的尺寸与所述第二晶体管的尺寸相同，所述第五晶体管的尺寸与所述第六晶体管的尺寸相同，所述第四晶体管的尺寸小于所述第六晶体管的尺寸。
  4. 根据权利要求3所述的电路，其特征在于，所述驱动电路包括第九晶体管和第十晶体管；
    所述第九晶体管的源极连接所述驱动电路的第一输入端，所述第九晶体管的栅极连接所述驱动电路的第二输入端和所述第十晶体管的栅极，所述第九晶体管的漏极分别连接所述驱动电路的输出端和所述第十晶体管的漏极，所述第十晶体管的源极接地。
  5. 根据权利要求4所述的电路，其特征在于，所述第七晶体管的尺寸与所述第九晶体管的尺寸相同，所述第八晶体管的尺寸与所述第十晶体管的尺寸相同。
  6. 根据权利要求5所述的电路，其特征在于，所述晶振生成电路包括：第二电阻、第一电容、第二电容和无源晶振元器件；
    所述第二电阻的一端分别连接所述晶振生成电路的输入端、所述无源晶振元器件的输入端以及所述第一电容的一端，所述第一电容的另一端接地，所述第二电阻的另一端分别连接所述晶振生成电路的输出端、所述无源晶振元器件的输出端以及所述第二电容的一端，所述第二电容的另一端接地。
  7. 根据权利要求6所述的电路，其特征在于，所述工作电压等于第一电压、第一阈值电压、第二阈值电压的和，所述第一阈值电压为所述第七晶体管的阈值电压，所述第二阈值电压为所述第八晶体管的阈值电压，所述第一电压为所述第一电阻两端的电压。
  8. 根据权利要求7所述的电路，其特征在于，所述第一阈值电压和所述第二阈值电压的和大于或等于所述无源晶振元器件的驱动电压。
  9. 一种芯片，其特征在于，所述芯片包括如权利要求1-8任一项所述的低功耗晶振起振电路。
  10. 一种电子设备，其特征在于，所述电子设备包括如权利要求1-8任一项所述的低功耗晶振起振电路或如权利要求9所述的芯片。
PCT/CN2023/073508 2022-01-29 2023-01-28 低功耗晶振起振电路、芯片及电子设备 WO2023143488A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210110859.2A CN114138045B (zh) 2022-01-29 2022-01-29 低功耗晶振起振电路、芯片及电子设备
CN202210110859.2 2022-01-29

Publications (1)

Publication Number Publication Date
WO2023143488A1 true WO2023143488A1 (zh) 2023-08-03

Family

ID=80381839

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/073508 WO2023143488A1 (zh) 2022-01-29 2023-01-28 低功耗晶振起振电路、芯片及电子设备

Country Status (2)

Country Link
CN (2) CN116566326A (zh)
WO (1) WO2023143488A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116566326A (zh) * 2022-01-29 2023-08-08 深圳英集芯科技股份有限公司 一种低功耗晶振起振电路和相关芯片及相关电子设备
CN116248046B (zh) * 2023-05-08 2023-08-22 深圳市中科蓝讯科技股份有限公司 晶振起振电路、集成芯片封装方法、集成芯片及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103078631A (zh) * 2012-12-18 2013-05-01 上海集成电路研发中心有限公司 晶体振荡器
CN108123683A (zh) * 2017-12-08 2018-06-05 上海玮舟微电子科技有限公司 一种晶振电路
US20190006990A1 (en) * 2017-06-30 2019-01-03 Silicon Laboratories Inc. Crystal driver circuit with external oscillation signal amplitude control
CN110224689A (zh) * 2018-03-01 2019-09-10 比亚迪股份有限公司 起振电路
CN112511155A (zh) * 2020-11-06 2021-03-16 深圳市国微电子有限公司 电源电压自适应晶振驱动电路和振荡器
CN114138045A (zh) * 2022-01-29 2022-03-04 深圳英集芯科技股份有限公司 低功耗晶振起振电路、芯片及电子设备

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998032218A1 (fr) * 1997-01-22 1998-07-23 Seiko Epson Corporation Circuit oscillant, circuit electronique, dispositif a semi-conducteur, installation electronique et horloge
JP2001308642A (ja) * 2001-03-13 2001-11-02 Seiko Epson Corp 発振回路、半導体装置及びこれらを具備した携帯用電子機器および時計

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103078631A (zh) * 2012-12-18 2013-05-01 上海集成电路研发中心有限公司 晶体振荡器
US20190006990A1 (en) * 2017-06-30 2019-01-03 Silicon Laboratories Inc. Crystal driver circuit with external oscillation signal amplitude control
CN108123683A (zh) * 2017-12-08 2018-06-05 上海玮舟微电子科技有限公司 一种晶振电路
CN110224689A (zh) * 2018-03-01 2019-09-10 比亚迪股份有限公司 起振电路
CN112511155A (zh) * 2020-11-06 2021-03-16 深圳市国微电子有限公司 电源电压自适应晶振驱动电路和振荡器
CN114138045A (zh) * 2022-01-29 2022-03-04 深圳英集芯科技股份有限公司 低功耗晶振起振电路、芯片及电子设备

Also Published As

Publication number Publication date
CN116566326A (zh) 2023-08-08
CN114138045A (zh) 2022-03-04
CN114138045B (zh) 2022-05-06

Similar Documents

Publication Publication Date Title
WO2023143488A1 (zh) 低功耗晶振起振电路、芯片及电子设备
JP4043683B2 (ja) プロセスに対して寛容性のある集積回路の設計手法
US20090085545A1 (en) Voltage regulator
JPH09246946A (ja) ３ｖのｃｍｏｓプロセスにおける５ｖドライバ
CN110058632A (zh) 低压差放大器
WO2020156588A1 (zh) 电压基准源电路及低功耗电源系统
JPH03296991A (ja) 入力回路
US11139801B2 (en) Power-on reset circuit
US9964975B1 (en) Semiconductor devices for sensing voltages
US5686824A (en) Voltage regulator with virtually zero power dissipation
US5216291A (en) Buffer circuit having high stability and low quiescent current consumption
CN103078631A (zh) 晶体振荡器
CN114337609A (zh) 环形振荡器系统
JP2011134347A (ja) 低消費電力回路
JP3357689B2 (ja) 定電圧出力回路
US6380792B1 (en) Semiconductor integrated circuit
KR100460458B1 (ko) 외부 전압 글리치에 안정적인 내부 전압 발생 회로
US5457434A (en) Integrated circuit oscillator with high voltage feedback network
US20040084696A1 (en) Voltage level shifter implemented by essentially PMOS transistors
CN113885639B (zh) 基准电路、集成电路及电子设备
CN114637367A (zh) 一种芯片内部低压电源产生电路
US5212460A (en) Crystal oscillation circuit with voltage regulating circuit
CN110719070B (zh) 一种基于动态阈值技术的低功耗压控振荡器
CN114337548A (zh) 晶体振荡电路、集成电路及电子设备
KR100434432B1 (ko) Ｐｖｔ 변화에 둔감한 저전압 고속용 셀프-오실레이터

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23746366

Country of ref document: EP

Kind code of ref document: A1