WO2023137927A1 - 场效应晶体管、存算一体芯片、电路及设备 - Google Patents

场效应晶体管、存算一体芯片、电路及设备 Download PDF

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WO2023137927A1
WO2023137927A1 PCT/CN2022/091334 CN2022091334W WO2023137927A1 WO 2023137927 A1 WO2023137927 A1 WO 2023137927A1 CN 2022091334 W CN2022091334 W CN 2022091334W WO 2023137927 A1 WO2023137927 A1 WO 2023137927A1
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effect transistor
storage
field effect
logic
positively charged
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PCT/CN2022/091334
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English (en)
French (fr)
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刘欢
玉虓
韩根全
刘艳
金成吉
陈佳佳
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之江实验室
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Priority to JP2022577533A priority Critical patent/JP7514334B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention belongs to the technical field of microelectronics, and in particular relates to a field-effect transistor, a memory-computing integrated chip, a circuit and equipment with the mutual conversion function of logic characteristics and storage characteristics.
  • Monolithic 3D integrated circuits combine high-performance gate-all-around logic transistors (GAA MOSFETs) and ferroelectric memory based on back-end process Back-End-Of-Line (BEOL), which can achieve low power consumption and high-bandwidth signal transmission, and have the advantages of low manufacturing cost, small circuit area and high-bandwidth interconnection.
  • GAA MOSFETs gate-all-around logic transistors
  • BEOL Back-End-Of-Line
  • the performance of transistors and 3D integrated circuits based on back-end process technology is limited by low thermal budget fabrication technology.
  • the object of the present invention is to provide a field effect transistor with a mutual conversion function of logic characteristics and storage characteristics to address the above-mentioned deficiencies in the prior art.
  • the first aspect of the embodiments of the present invention provides a field effect transistor with a mutual conversion function between a logic device and a storage device, including: a substrate, an insulating interface layer, a gate dielectric layer, positively charged oxygen vacancies, a gate electrode, a source electrode, and a drain electrode; wherein, the insulating interface layer, the gate dielectric layer, and the gate electrode are vertically distributed on the upper surface of the substrate from bottom to top; the source electrode and the drain electrode are respectively arranged on both sides of the upper surface of the substrate, and the insulating interface layer is arranged between the source electrode and the drain electrode;
  • the gate dielectric layer has the positively charged oxygen vacancies, and the positively charged oxygen vacancies are mobile ions, wherein the positively charged oxygen vacancies can be switched between the first state and the second state, so that the field effect transistor is correspondingly switched between a function used as a logic device and a function used as a storage device;
  • the first state is: the positively charged oxygen vacancies are trapped and neutralized by the interface of the insulating interface layer and/or the interface of the gate electrode;
  • the second state is: the positively charged oxygen vacancies are in an untrapped state.
  • the field effect transistor when a high-frequency pulse is applied to the gate electrode, the positively charged oxygen vacancies are in the first state, so that the field effect transistor has logic characteristics and can be used as a logic device;
  • the field effect transistor When a low-frequency pulse is applied to the gate electrode, the positively charged oxygen vacancies are in the second state, so that the field effect transistor has storage characteristics and can be used as a storage device.
  • the frequency of the high-frequency pulse is greater than or equal to 1 kHz; and/or
  • the frequency of the low-frequency pulse is less than or equal to 10 Hz.
  • the substrate is a semiconductor material
  • the semiconductor material includes one of silicon Si, germanium Ge, silicon germanium SiGe, silicon-on-insulator SOI, or germanium-on-insulator GOI.
  • the insulating interface layer includes one of silicon oxide material SiO 2 , silicon nitride material Si 3 N 4 , silicon oxynitride material SiON, germanium oxide material GeO 2 and aluminum oxide material Al 2 O 3 .
  • the gate dielectric layer is an insulating oxide
  • the insulating oxide includes one of hafnium oxide HfO 2 , zirconium oxide ZrO 2 , aluminum oxide Al 2 O 3 , lanthanum oxide La 2 O 3 , yttrium oxide Y 2 O 3 , titanium oxide TiO 2 , silicon oxide SiO 2 and germanium oxide GeO 2 .
  • the gate electrode is metal nitride
  • the metal nitride includes one of tantalum nitride TaN, titanium nitride TiN, molybdenum nitride MoN and tungsten nitride WN.
  • the second aspect of the embodiments of the present invention provides an integrated storage and calculation chip, including a chip body and the field effect transistor having the function of converting logic devices and storage devices according to the first aspect, wherein the field effect transistor is arranged on the chip body.
  • a third aspect of the embodiments of the present invention provides an integrated storage and calculation circuit, including a circuit board main body and the integrated storage and calculation chip described in the second aspect, wherein the integrated storage and calculation chip is arranged on the circuit board main body.
  • a fourth aspect of the embodiments of the present invention provides an integrated storage and calculation device, including a housing and the integrated storage and calculation circuit described in the third aspect, wherein the integrated storage and calculation circuit is arranged on the housing.
  • the present invention provides a field effect transistor, which has the function of mutual conversion between a logic device and a storage device, and can realize the integration of storage and calculation of a single transistor.
  • the preparation process of the transistor is compatible with the silicon-based CMOS process, and the lower thermal budget can greatly reduce leakage current and power consumption, thereby realizing a high-density storage and calculation integrated three-dimensional heterogeneous integrated chip.
  • Fig. 1 is the cross-sectional schematic diagram of the field effect transistor that the present invention has logic characteristic and memory characteristic conversion function
  • Fig. 2 is a schematic diagram of the production process of the first example of the present invention.
  • Fig. 3 is the transfer curve diagram of the storage characteristic in the initial state of the field effect transistor with logic characteristic and storage characteristic conversion function
  • Fig. 4 is a transfer curve diagram of a field effect transistor having a mutual conversion function of a logic characteristic and a storage characteristic from a storage characteristic to a logic characteristic;
  • FIG. 5 is a transfer curve diagram of a field effect transistor having a function of mutual conversion between logic characteristics and storage characteristics from logic characteristics to storage characteristics.
  • first, second, third, etc. may be used in the present invention to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present invention, first information may also be called second information, and similarly, second information may also be called first information. Depending on the context, the word “if” as used herein may be interpreted as “at” or “when” or “in response to a determination.”
  • the example of the present invention provides a field effect transistor with a function of mutual conversion between logic characteristics and storage characteristics
  • the field effect transistor may include a substrate 1, an insulating interface layer 2, a gate dielectric layer 3, positively charged oxygen vacancies 4, a gate electrode 5, a source electrode 6 and a drain electrode 7.
  • the insulating interface layer 2, the gate dielectric layer 3 and the gate electrode 5 are distributed on the upper surface of the substrate 1 from bottom to top; the source electrode 6 and the drain electrode 7 are arranged on both sides of the upper surface of the substrate 1, and the insulating interface layer 2 is arranged between the source electrode 6 and the drain electrode 7.
  • the positively charged oxygen vacancies 4 can be switched between the first state and the second state, so that the field effect transistor can be switched between the function of being used as a logic device and the function of being used as a storage device.
  • the first state is: the positively charged oxygen vacancies 4 are trapped and neutralized by the interface of the insulating interface layer 2 and/or the interface of the gate electrode 5.
  • the second state is: the positively charged oxygen vacancies 4 are in an untrapped state.
  • the field effect transistor of the embodiment of the present invention by setting positively charged oxygen vacancies 4 with movable ions in the gate dielectric layer 3 , and by regulating the movable ions, the field effect transistor has the function of interconversion between logic characteristics and storage characteristics, and can realize the integration of memory and computing characteristics of a single transistor.
  • the preparation process of the transistor is compatible with the silicon-based CMOS process.
  • the amorphous gate dielectric avoids high-temperature annealing, and the low thermal budget can greatly reduce leakage current and power consumption, thereby realizing a high-density memory-computing integrated three-dimensional heterogeneous integrated chip.
  • the positively charged oxygen vacancies 4 when the positively charged oxygen vacancies 4 are in the first state, the positively charged oxygen vacancies 4 are completely neutralized by the interface capture of the insulating interface layer 2; in some embodiments, when the positively charged oxygen vacancies 4 are in the first state, the positively charged oxygen vacancies 4 are completely neutralized by the interface capture of the gate electrode 5; The other part is neutralized by the interface trapping of the gate electrode 5 .
  • the positively charged oxygen vacancies 4 are controlled to switch between the first state and the second state by changing the frequency of the pulse applied to the gate electrode 5.
  • the positively charged oxygen vacancies 4 are in the first state, so that the field effect transistor has logic characteristics and can be used as a logic device.
  • the positively charged oxygen vacancies 4 are in the second state, so that the field effect transistor has storage characteristics and can be used as a storage device.
  • the frequency of the high-frequency pulse is greater than or equal to 1 kHz, and/or the frequency of the low-frequency pulse is less than or equal to 10 Hz.
  • the frequency of the high-frequency pulse can be selected as 1 kHz, 2 kHz, 3 kHz, 4 kHz, 5 kHz, 6 kHz, 7 kHz, 8 kHz, 9 kHz, 10 kHz or other values greater than 1 kHz
  • the frequency of the low-frequency pulse can be selected as 1 Hz, 2 Hz, 3 Hz, 4 Hz, 5 Hz, 6 Hz, 7 Hz, 8 Hz, 9 Hz, 10 Hz or other values smaller than 10 Hz.
  • the materials of the substrate 1 , the insulating interface layer 2 , the gate dielectric layer 3 and the gate electrode 5 can be set as required.
  • the substrate 1 can be a semiconductor material, for example, the material of the substrate 1 can include silicon Si, germanium Ge, silicon germanium SiGe, silicon-on-insulator SOI or germanium-on-insulator GOI; of course, the material of the substrate 1 can also be other types of semiconductor materials.
  • the insulating interface layer 2 may include at least one of silicon oxide material SiO 2 , silicon nitride material Si 3 N 4 , silicon oxynitride material SiON, germanium oxide material GeO 2 and aluminum oxide material Al 2 O 3 ; of course, the material of the insulating interface layer 2 may also be other types of materials.
  • the gate dielectric layer 3 may include an insulating oxide, and the insulating oxide includes one of hafnium oxide HfO 2 , zirconium oxide ZrO 2 , aluminum oxide Al 2 O 3 , lanthanum oxide La 2 O 3 , yttrium oxide Y 2 O 3 , titanium oxide TiO 2 , silicon oxide SiO 2 and germanium oxide GeO 2 ; of course, the material of the gate dielectric layer 3 can also be other types of materials.
  • the gate electrode 5 may include metal nitride, and the nitride metal includes one of tantalum nitride TaN, titanium nitride TiN, molybdenum nitride MoN and tungsten nitride WN; of course, the material of the gate electrode 5 may also be other types of materials.
  • Transistors based on amorphous ZrO2 gate dielectrics with positively charged oxygen vacancies have the function of switching between logic devices and storage devices. Referring to Figure 2, the transistor manufacturing steps are as follows;
  • Step 1 select the substrate and clean it.
  • an n-type germanium sheet Ge is selected as the substrate 1, and the substrate is routinely cleaned.
  • Step 2 depositing an amorphous zirconia ZrO 2 film, as shown in (a) in FIG. 2 .
  • the deposition process conditions are: use zirconium tetradimethylamino as the precursor zirconium source, water as the precursor oxygen source, and the deposition temperature is 250 degrees. Among them, the pulse time of the zirconium source and the water source is controlled to regulate the content of oxygen vacancies, so that the zirconium oxide ZrO2 film contains positively charged oxygen vacancies4. At the same time, GeO2 will be formed as an insulating interfacial layer 2 during the growth process.
  • Step 3 using radio frequency reactive magnetron sputtering equipment to deposit 100nm tantalum nitride TaN on the zirconia ZrO 2 gate dielectric 2 as the gate metal, as shown in (b) in FIG. 2 .
  • Step 4 define gate pattern and source and drain regions.
  • Photolithography was first performed on the TaN surface to define the gate electrode pattern, and then etched to form the gate electrode 5 and source and drain regions, and then BF 2 + ion implantation was performed with an implantation energy of 30KeV and an implantation dose of 1 ⁇ 10 15 cm -2 .
  • Step 5 perform photolithography on the surface of the structure shown in (c) in Figure 2, define the area where nickel metal needs to be deposited, deposit Ni with a thickness of 20nm, put it into an acetone solution for stripping treatment, and form the source electrode 6 and the drain electrode 7, as shown in (d) in Figure 2.
  • Step 6 annealing and activating the entire fabricated device at 400° C. for 30 s to prepare a field effect transistor.
  • the transistor based on the amorphous Al 2 O 3 gate dielectric with positively charged oxygen vacancies has the function of switching between logic devices and storage devices, and the fabrication steps of the transistor are as follows;
  • Step 1 select the substrate and clean it.
  • an n-type germanium sheet Ge is selected as the substrate 1, and the substrate is routinely cleaned.
  • Step 2 depositing an amorphous Al 2 O 3 film.
  • a plasma-enhanced atomic layer deposition PEALD equipment was used to deposit 5nm aluminum oxide Al 2 O 3 on the substrate 1 as the gate dielectric layer 3.
  • the deposition process conditions were: trimethylaluminum was used as the precursor aluminum source, water was used as the precursor oxygen source, and the deposition temperature was 300 degrees. Among them, the pulse time of the aluminum source and the water source is controlled to regulate the content of oxygen vacancies, so that the aluminum oxide Al 2 O film contains positively charged oxygen vacancies. At the same time, GeO2 will be formed as an insulating interfacial layer 2 during the growth process.
  • Step 3 using radio frequency reactive magnetron sputtering equipment to deposit 100nm titanium nitride TiN on the aluminum oxide Al 2 O 3 gate dielectric 3 as the gate metal.
  • Step 4 defining the gate electrode pattern and the source and drain regions.
  • the gate electrode pattern is first defined by photolithography, and then the gate electrode 5 and the source and drain regions are formed by etching, and then BF 2 + ion implantation is performed, the implantation energy is 30KeV, and the implantation dose is 1 ⁇ 10 15 cm -2 .
  • Step 5 use photolithography to define the area where metal nickel needs to be deposited, deposit nickel Ni with a thickness of 20nm, put it into an acetone solution for lift-off treatment, and form the source electrode 6 and the drain electrode 7 .
  • Step 6 annealing and activating the entire manufactured device at 400° C. for 30 s to prepare a field effect transistor.
  • the transistor based on the amorphous La 2 O 3 gate dielectric with positively charged oxygen vacancies has the function of switching logic devices and storage devices, and the fabrication steps of the transistor are as follows;
  • Step 1 select the substrate and clean it.
  • an n-type silicon wafer Si is selected as the substrate 1, and the substrate is cleaned conventionally.
  • Step 2 define the source and drain regions by photolithography, and perform ion implantation.
  • P ions were implanted into the source and drain regions with a dose of 1 ⁇ 10 15 cm -2 , and the activation condition was 1000°C for 1 minute.
  • Step 2 depositing an amorphous lanthanum oxide La 2 O 3 thin film.
  • 15nm lanthanum oxide La 2 O 3 was deposited on the substrate 1 as the gate dielectric layer 3 by plasma-enhanced atomic layer deposition PEALD equipment.
  • the deposition process conditions were: use La(iPrCp) 3 as the precursor lanthanum source, water as the precursor oxygen source, and the deposition temperature was 150°C.
  • the pulse time of the lanthanum source and the water source is controlled to control the oxygen vacancy content, so that the lanthanum oxide La 2 O 3 film contains positively charged oxygen vacancies.
  • SiO2 will be formed as an insulating interfacial layer 2 during the growth process.
  • Step 3 using radio frequency reactive magnetron sputtering equipment to deposit 100nm titanium nitride TiN on the La 2 O 3 gate dielectric 2 as the gate metal. Then implement post-metallization annealing treatment at 400° C. for 30 s.
  • Step 4 define the gate electrode pattern.
  • the gate electrode pattern is defined by photolithography on the surface of titanium nitride TiN.
  • Step 5 use photolithography to define the area where metal Al needs to be deposited, deposit Al with a thickness of 20nm, put it into acetone solution for lift-off treatment, and form source 6 and drain 7 .
  • Step 6 annealing and activating the entire manufactured device at 400° C. for 30 s to prepare a field effect transistor.
  • the field effect transistor when the positively charged oxygen vacancies are in the trapped state, the field effect transistor exhibits logic characteristics. After a certain low-frequency pulse (frequency of 1 Hz-100 Hz) is applied to the gate electrode 5, the oxygen vacancies are in the de-captured state, and the device exhibiting logic characteristics can be transformed into a memory device.
  • a certain low-frequency pulse frequency of 1 Hz-100 Hz
  • the field effect transistor when the positively charged oxygen vacancies are in the decaptured state, the field effect transistor exhibits storage characteristics. After a certain high-frequency pulse (frequency above 1 kHz) is applied to the gate electrode 5, the oxygen vacancies are in the trapped state, and the device exhibiting storage characteristics can be transformed into a logic device. Therefore, the field effect transistor can realize the function of mutual conversion between logic characteristics and storage characteristics.
  • Embodiment 4 Test the interchangeability of logic characteristics and storage characteristics of field effect transistors
  • Example 1 The transistor prepared in Example 1 was tested. When the field effect transistor with positively charged oxygen vacancies showed storage characteristics, its transfer characteristics were shown in Figure 3. After a 1kHz high-frequency pulse was applied to the gate electrode, its transfer characteristics were shown in Figure 4. Since the positively charged oxygen vacancies were captured and neutralized by the interface, the device showed almost zero hysteresis and had logic characteristics. On the basis of this device exhibiting logic characteristics, a 10Hz low-frequency pulse is applied to the gate electrode, and its transfer characteristics are shown in Figure 5. Since the positively charged oxygen vacancies are in a decaptured state, the device exhibits a ferroelectric-like hysteresis upwards and has storage characteristics. Both logic characteristics and memory characteristics of the device remain stable.
  • the embodiment of the present invention also provides an integrated storage and calculation chip, which may include a chip main body and the field effect transistor with the function of mutual conversion between logic devices and storage devices in the above embodiments, wherein the field effect transistor is arranged on the chip main body.
  • the storage-computing integrated chip in the embodiment of the present invention may be a storage-computing integrated three-dimensional heterogeneous integrated chip, or other types of storage-computing integrated chips.
  • the embodiment of the present invention also provides an integrated storage and calculation circuit, which may include a circuit board main body and the integrated storage and calculation chip in the above embodiment, wherein the integrated storage and calculation chip is arranged on the circuit board main body.
  • An embodiment of the present invention also provides an integrated storage and calculation device, which may include a housing and the integrated storage and calculation circuit in the above embodiment, wherein the integrated storage and calculation circuit is arranged on the housing.

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Abstract

本发明公开了一种具有逻辑特性与存储特性相互转换功能的场效应晶体管、存算一体芯片、电路及设备。其自下而上包括衬底、绝缘界面层、栅介质层、栅电极；所述衬底两边分别设有源极和漏极，所述栅介质层具有带正电荷氧空位的可移动离子。当栅电极施加有高频脉冲时，所述带正电荷氧空位处于被俘获状态，使得所述场效应晶体管具备逻辑特性而能够作为逻辑器件使用；当栅电极施加有低频脉冲时，所述带正电荷氧空位处于去俘获状态，使得所述场效应晶体管具备存储特性而能够作为存储器件使用。本发明可以实现逻辑特性与存储特性感相互转换并保持高性能器件状态稳定，这可用于存算一体的三维异质集成芯片。

Description

场效应晶体管、存算一体芯片、电路及设备 技术领域
本发明属于微电子技术领域，特别涉及一种具有逻辑特性与存储特性相互转换功能的场效应晶体管、存算一体芯片、电路及设备。
技术背景
随着摩尔定律的进一步发展，特征尺寸不断缩小，集成度和性能不断提高，由此产生的功耗问题变得日益严重。传统冯诺依曼结构存在延迟时间长，带宽有限，内存总线上大寄生负载和大数据访问的高功耗问题。单片三维集成电路结合了基于后端工艺Back-End-Of-Line(BEOL)的高性能全环栅逻辑晶体管(GAA MOSFET)和铁电存储器，可实现低功耗和高带宽信号传输，具有低制造成本，小电路面积和高带宽互连的优势，然而，基于后端工艺的晶体管和三维集成电路的性能受到低热预算制备技术的限制。
发明内容
本发明的目的在于针对上述现有技术的不足，提供一种具有逻辑特性与存储特性相互转换功能的场效应晶体管。
为实现上述发明目的，本发明的技术方案为：
本发明实施例的第一方面提供一种具有逻辑器件与存储器件相互转换功能的场效应晶体管，包括：衬底、绝缘界面层、栅介质层、带正电荷氧空位、栅电极、源极和漏极；其中，所述绝缘界面层、所述栅介质层和所述栅电极自下向上竖直分布于所述衬底的上表面；所述源极和所述漏极分别设置于所述衬底的上表面两侧，所述绝缘界面层设置于所述源极和所述漏极之间；
所述栅介质层内具有所述带正电荷氧空位，所述带正电荷氧空位为可移动离子，其中，所述带正电荷氧空位能够在第一状态和第二状态之间切换，使得所述场效应晶体管对应在作为逻辑器件使用的功能和作为存储器件的使用功能之间切换；
所述第一状态为：所述带正电荷氧空位被所述绝缘界面层的界面和/或所述栅电极的界面俘获中和；
所述第二状态为：所述带正电荷氧空位处于去俘获状态。
可选地，当所述栅电极施加有高频脉冲时，所述带正电荷氧空位处于所述第一状态，使得所述场效应晶体管具备逻辑特性而能够作为逻辑器件使用；
当所述栅电极施加有低频脉冲时，所述带正电荷氧空位处于所述第二状态，使得所述场效应晶体管具备存储特性而能够作为存储器件使用。
可选地，所述高频脉冲的频率大于或等于1kHz；和/或
所述低频脉冲的频率小于或等于10Hz。
可选地，所述衬底为半导体材料，所述半导体材料包括硅Si，锗Ge，硅锗SiGe，绝缘体上硅SOI或绝缘体上锗GOI中的一种。
可选地，所述绝缘界面层包括氧化硅材料SiO 2、氮化硅材料Si 3N 4、氮氧化硅材料SiON、氧化锗材料GeO 2和氧化铝材料Al 2O 3中的一种。
可选地，所述栅介质层为绝缘氧化物，所述绝缘氧化物包括氧化铪HfO 2、氧化锆ZrO 2、氧化铝Al 2O 3、氧化镧La 2O 3、氧化钇Y 2O 3、氧化钛TiO 2、氧化硅SiO 2和氧化锗GeO 2中的一种。
可选地，所述栅电极为氮化物金属，所述氮化物金属包括氮化钽TaN，氮化钛TiN，氮化钼MoN和氮化钨WN中的一种。
本发明实施例的第二方面提供一种存算一体芯片，包括芯片主体和第一方面所述的具有逻辑器件与存储器件相互转换功能的场效应晶体管，其中，所述场效应晶体管设置于所述芯片主体上。
本发明实施例的第三方面提供一种存算一体电路，包括电路板主体和第二方面所述的存算一体芯片，其中，所述存算一体芯片设置于所述电路板主体上。
本发明实施例的第四方面提供一种存算一体设备，包括外壳和第三方面所述的存算一体电路，其中，所述存算一体电路设置于所述外壳上。
本发明的有益效果为：本发明提供了一种场效应晶体管，具有逻辑器件与存储器件相互转换的功能，可实现单个晶体管的存算一体特性，同时，晶体管的制备工艺与硅基CMOS工艺兼容，较低热预算能较大幅度减小泄漏电流，降低功耗，从而实现高密度的存算一体三维异质集成芯片。
附图说明
下面结合附图和具体实施例对本发明做进一步详细说明。
图1为本发明具有逻辑特性与存储特性相互转换功能的场效应晶体管的截面示意图；
图2为本发明第一实例的制作流程示意图；
图3为具有逻辑特性与存储特性相互转换功能的场效应晶体管在初始状态为存储特性的转移曲线图；
图4为具有逻辑特性与存储特性相互转换功能的场效应晶体管由存储特性转为逻辑特性的转移曲线图；
图5为具有逻辑特性与存储特性相互转换功能的场效应晶体管由逻辑特性转为存储特性的转移曲线图。
以上图中：1、衬底；2、绝缘界面层；3、栅介质层；4、带正电荷氧空位；5、栅电极；6、源极；7、漏极。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本发明的一些方面相一致的装置和方法的例子。
在本发明使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本发明可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本发明范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
下面结合实例对本发明的具有逻辑特性与存储特性相互转换功能的场效应晶体管进行详细说明。在不冲突的情况下，下述的实施例及实施方式中的特征可以相互组合。
参照图1，本发明实例提供了具有逻辑特性与存储特性相互转换功能的场效应晶体管，该场效应晶体管可包括衬底1、绝缘界面层2、栅介质层3、带正电荷氧空位4、栅电极5、源极6和漏极7。其中，绝缘界面层2、栅介质层3和栅电极5自下而上分布于所述衬底1的上表面；所述源极6和漏极7设置在衬底1的上表面两侧，绝缘界面层2设置于源极6和漏极7之间。
在本发明实施例中，栅介质层2内具有带正电荷氧空位4的可移动离子，具体地，栅介质层3内具有带正电荷氧空位4，带正电荷氧空位4为可移动离子。其中，带正电荷氧空位4能够在第一状态和第二状态之间切换，使得场效应晶体管对应在作为逻辑器件使用的功能和作为存储器件的使用功能之间切换。第一状态为：所述带正电荷氧空位4被所述绝缘界面层 2的界面和/或所述栅电极5的界面俘获中和。第二状态为：所述带正电荷氧空位4处于去俘获状态。
本发明实施例的场效应晶体管，通过在栅介质层3内设置具有可移动离子的带正电荷氧空位4，通过对可移动离子的调控，使得该场效应晶体管具有逻辑特性与存储特性相互转换的功能，可实现单个晶体管的存算一体特性，同时，晶体管的制备工艺与硅基CMOS工艺兼容，无定性栅介质避免高温退火，较低热预算能较大幅度减小泄漏电流，降低功耗，从而实现高密度的存算一体三维异质集成芯片。
需要说明的是，在一些实施例中，当带正电荷氧空位4处于第一状态，带正电荷氧空位4完全被所述绝缘界面层2的界面俘获中和；在一些实施例中，当带正电荷氧空位4处于第一状态，带正电荷氧空位4完全被栅电极5的界面俘获中和；在一些实施例中，当带正电荷氧空位4处于第一状态，带正电荷氧空位4中的一部分被绝缘界面层2的界面俘获中和，另一部分则被栅电极5的界面俘获中和。
其中，控制带正电荷氧空位4在第一状态和第二状态之间切换的方式可包括多种，例如，在一些实施例中，通过改变施加在栅电极5的脉冲的频率大小的方式来控制带正电荷氧空位4在第一状态和第二状态之间切换，具体而言，当所述栅电极5施加有高频脉冲时，所述带正电荷氧空位4处于所述第一状态，使得所述场效应晶体管具备逻辑特性而能够作为逻辑器件使用。当所述栅电极5施加有低频脉冲时，所述带正电荷氧空位4处于所述第二状态，使得所述场效应晶体管具备存储特性而能够作为存储器件使用。本实施例中，高频脉冲的频率大于或等于1kHz，和/或低频脉冲的频率小于或等于10Hz。示例性地，高频脉冲的频率可以选择为1kHz、2kHz、3kHz、4kHz、5kHz、6kHz、7kHz、8kHz、9kHz、10kHz或其他大于1kHz的数值，和/或低频脉冲的频率可以选择为1Hz、2Hz、3Hz、4Hz、5Hz、6Hz、7Hz、8Hz、9Hz、10Hz或其他小于10Hz的数值。
衬底1、绝缘界面层2、栅介质层3及栅电极5的材质可根据需要设置。
其中，衬底1可为半导体材料，例如，衬底1的材质可包括硅Si，锗Ge，硅锗SiGe，绝缘体上硅SOI或绝缘体上锗GOI中的一种；当然，衬底1的材质也可为其他类型的半导体材料。
绝缘界面层2可包括氧化硅材料SiO 2、氮化硅材料Si 3N 4、氮氧化硅材料SiON、氧化锗材料GeO 2和氧化铝材料Al 2O 3中至少一种；当然，绝缘界面层2的材质也可为其他类型材质。
栅介质层3可包括绝缘氧化物，所述绝缘氧化物包括氧化铪HfO 2、氧化锆ZrO 2、氧化铝Al 2O 3、氧化镧La 2O 3、氧化钇Y 2O 3、氧化钛TiO 2、氧化硅SiO 2和氧化锗GeO 2中的一种；当 然，栅介质层3的材质也可为其他类型材质。
栅电极5可包括氮化物金属，所述氮化物金属包括氮化钽TaN，氮化钛TiN，氮化钼MoN和氮化钨WN中的一种；当然，栅电极5的材质也可为其他类型材质。
下面，介绍几种形成具有逻辑特性与存储特性相互转换功能的场效应晶体管的结构的过程。
实施例1
基于带有正电荷氧空位的无定形ZrO 2栅介质的晶体管具有逻辑器件与存储器件相互转换功能，参照图2，晶体管制作步骤如下；
步骤1，选择衬底并进行清洗。
本实施例中选择n型锗片Ge作为衬底1，将衬底进行常规清洗。
步骤2，沉积无定型氧化锆ZrO 2薄膜，如图2中的(a)所示。
用等离子体增强型原子层沉积PEALD设备在衬底1上沉积3.5nm氧化锆ZrO 2作为栅介质层3，沉积的工艺条件为：使用四二甲氨基锆作为前驱体锆源，水为前驱体氧源，沉积温度为250度。其中，控制锆源和水源的脉冲时间来调控氧空位含量，使氧化锆ZrO 2薄膜中含有带正电荷氧空位4。同时生长过程中会形成GeO 2作为绝缘界面层2。
步骤3，采用射频反应磁控溅射设备在氧化锆ZrO 2栅介质2上沉积100nm氮化钽TaN，作为栅金属，如图2中的(b)所示。
步骤4，定义栅极图形和源漏区域。
在TaN表面先进行光刻，定义出栅电极图形，再刻蚀形成栅电极5和源漏区域，然后进行BF 2 +离子注入，注入能量为30KeV，注入剂量为1×10 15cm -2。
步骤5，在图2中的(c)所示的结构表面进行光刻，定义出需要沉积金属镍的区域，沉积20nm厚的Ni，放入丙酮溶液中进行剥离处理，形成源极6和漏极7，如图2中的(d)所示。
步骤6，将整个制备完的器件在400℃，30s条件下进行退火激活，制备得到场效应晶体管。
实施例2
基于带有正电荷氧空位的无定形Al 2O 3栅介质的晶体管具有逻辑器件与存储器件相互转换功能，晶体管制作步骤如下；
步骤1，选择衬底并进行清洗。
本实施例中选择n型锗片Ge作为衬底1，将衬底进行常规清洗。
步骤2，沉积无定型Al 2O 3薄膜。
用等离子体增强型原子层沉积PEALD设备在衬底1上沉积5nm氧化铝Al 2O 3作为栅介 质层3，沉积的工艺条件为：使用三甲基铝作为前驱体铝源，水为前驱体氧源，沉积温度为300度。其中，控制铝源和水源的脉冲时间来调控氧空位含量，使氧化铝Al 2O薄膜中含有带正电荷氧空位。同时生长过程中会形成GeO 2作为绝缘界面层2。
步骤3，采用射频反应磁控溅射设备在氧化铝Al 2O 3栅介质3上沉积100nm氮化钛TiN，作为栅金属。
步骤4，定义栅电极图形及源漏区域。
在氮化钛TiN表面先进行光刻定义栅电极图形，再刻蚀形成栅电极5和源漏区域，然后进行BF 2 +离子注入，注入能量为30KeV，注入剂量为1×10 15cm -2。
步骤5，利用光刻定义出需要沉积金属镍的区域，沉积20nm厚的镍Ni，放入丙酮溶液中进行剥离处理，形成源极6和漏极7。
步骤6，将整个制作完的器件在400℃，30s条件下退火激活，制备得到场效应晶体管。
实施例3
基于带有正电荷氧空位的无定形La 2O 3栅介质的晶体管具有逻辑器件与存储器件相互转换功能，晶体管制作步骤如下；
步骤1，选择衬底并进行清洗。
本实施例中选择n型硅片Si作为衬底1，将衬底进行常规清洗。
步骤2，光刻定义源漏区域，并进行离子注入。
源漏区域注入P离子，剂量为1×10 15cm -2，激活条件为1000℃，1分钟。
步骤2，沉积无定型氧化镧La 2O 3薄膜。
用等离子体增强型原子层沉积PEALD设备在衬底1上沉积15nm氧化镧La 2O 3作为栅介质层3，沉积的工艺条件为：使用La(iPrCp) 3作为前驱体镧源，水为前驱体氧源，沉积温度为150℃。其中，控制镧源和水源的脉冲时间来调控氧空位含量，使氧化镧La 2O 3薄膜中含有带正电荷氧空位。同时生长过程中会形成SiO 2作为绝缘界面层2。
步骤3，采用射频反应磁控溅射设备在La 2O 3栅介质2上沉积100nm氮化钛TiN，作为栅金属。然后在400℃，30s条件下实施金属化后退火处理。
步骤4，定义栅电极图形。
在氮化钛TiN表面进行光刻定义栅电极图形。
步骤5，利用光刻定义出需要沉积金属Al的区域，沉积20nm厚的Al，放入丙酮溶液中进行剥离处理，形成源极6和漏极7。
步骤6，将整个制作完的器件在400℃，30s条件下退火激活，制备得到场效应晶体管。
本发明实施例在带正电荷氧空位处于被俘获状态时，场效应晶体管表现出逻辑特性，在 栅电极5上施加一定的低频脉冲(频率在1Hz-100Hz)后，氧空位处于去俘获状态，表现为逻辑特性的器件可转变成存储器件。
本发明实施例在带正电荷氧空位处于去俘获状态时，场效应晶体管表现出存储特性，在栅电极5上施加一定的高频脉冲(频率在1kHz以上)后，氧空位处于被俘获状态，表现为存储特性的器件可转变成逻辑器件。由此场效应晶体管可以实现逻辑特性与存储特性相互转换的功能。
实施例4：测试场效应晶体管的逻辑特性与存储特性的互换性能
对实施例1制得的晶体管进行测试，带有正电荷氧空位的场效应晶体管表现为存储特性时，其转移特性如图3所示，在对栅电极施加一个1kHz高频脉冲后，其转移特性如图4所示，由于带正电荷氧空位被界面俘获中和，器件表现出几乎为零的回滞，具有逻辑特性。在此表现为逻辑特性的器件基础上，对栅电极施加一个10Hz低频脉冲，其转移特性如图5所示，由于带正电荷氧空位处于去俘获状态，器件表现出向上回的类铁电回滞，具有存储特性。器件的逻辑特性和存储特新两个状态均可保持稳定。
值得一提的是，本发明实施例还提供一种存算一体芯片，该存算一体芯片可包括芯片主体和上述实施例中的具有逻辑器件与存储器件相互转换功能的场效应晶体管，其中，所述场效应晶体管设置于芯片主体上。
本发明实施例的存算一体芯片可为存算一体三维异质集成芯片，也可为其他类型的存算一体芯片。
本发明实施例还提供一种存算一体电路，该存算一体电路可包括电路板主体和上述实施例中的存算一体芯片，其中，所述存算一体芯片设置于所述电路板主体上。
本发明实施例还提供一种存算一体设备，该存算一体设备可包括外壳和上述实施例中的存算一体电路，其中，所述存算一体电路设置于所述外壳上。
以上描述仅是本发明的两个具体实例，并未构成对本发明的任何限制，显然对于本领域的专业人员来说，在了解了本发明内容和原理后，都可能在不背离本发明原理、结构的情况下，进行形式和细节上的各种修改和改变，但是这些基于本发明思想的修正和改变仍在本发明的权利要求保护范围之内。

Claims (10)

  1. 一种具有逻辑特性与存储特性相互转换功能的场效应晶体管，其特征在于，包括：衬底(1)、绝缘界面层(2)、栅介质层(3)、带正电荷氧空位(4)、栅电极(5)、源极(6)和漏极(7)；其中，所述绝缘界面层(2)、所述栅介质层(3)和所述栅电极(5)自下向上竖直分布于所述衬底(1)的上表面；所述源极(6)和所述漏极(7)分别设置于所述衬底(1)的上表面两侧，所述绝缘界面层(2)设置于所述源极(6)和所述漏极(7)之间；
    所述栅介质层(3)内具有所述带正电荷氧空位(4)，所述带正电荷氧空位(4)为可移动离子，其中，所述带正电荷氧空位(4)能够在第一状态和第二状态之间切换，使得所述场效应晶体管对应在作为逻辑器件使用的功能和作为存储器件的使用功能之间切换；
    所述第一状态为：所述带正电荷氧空位(4)被所述绝缘界面层(2)的界面和/或所述栅电极(5)的界面俘获中和；
    所述第二状态为：所述带正电荷氧空位(4)处于去俘获状态。
  2. 根据权利要求1所述的具有逻辑特性与存储特性相互转换功能的场效应晶体管，其特征在于，当所述栅电极(5)施加有高频脉冲时，所述带正电荷氧空位(4)处于所述第一状态，使得所述场效应晶体管具备逻辑特性而能够作为逻辑器件使用；
    当所述栅电极(5)施加有低频脉冲时，所述带正电荷氧空位(4)处于所述第二状态，使得所述场效应晶体管具备存储特性而能够作为存储器件使用。
  3. 根据权利要求2所述的具有逻辑特性与存储特性相互转换功能的场效应晶体管，其特征在于，所述高频脉冲的频率大于或等于1kHz；和/或
    所述低频脉冲的频率小于或等于10Hz。
  4. 根据权利要求1所述的具有逻辑特性与存储特性相互转换功能的场效应晶体管，其特征在于，所述绝缘界面层(2)包括氧化硅材料SiO 2、氮化硅材料Si 3N 4、氮氧化硅材料SiON、氧化锗材料GeO 2和氧化铝材料Al 2O 3中的一种。
  5. 根据权利要求1所述的具有逻辑特性与存储特性相互转换功能的场效应晶体管，其特征在于，所述衬底(1)为半导体材料；所述栅介质层(3)为绝缘氧化物；所述栅电极(5)为氮化物金属。
  6. 根据权利要求5所述的具有逻辑特性与存储特性相互转换功能的场效应晶体管，其特征在于，所述半导体材料包括硅Si，锗Ge，硅锗SiGe，绝缘体上硅SOI或绝缘体上锗GOI 中的一种。
  7. 根据权利要求5所述的具有逻辑特性与存储特性相互转换功能的场效应晶体管，其特征在于，所述绝缘氧化物包括氧化铪HfO 2、氧化锆ZrO 2、氧化铝Al 2O 3、氧化镧La 2O 3、氧化钇Y 2O 3、氧化钛TiO 2、氧化硅SiO 2和氧化锗GeO 2中的一种；所述氮化物金属包括氮化钽TaN，氮化钛TiN，氮化钼MoN和氮化钨WN中的一种。
  8. 一种存算一体芯片，其特征在于，包括芯片主体和如权利要求1至7任一项所述的具有逻辑特性与存储特性相互转换功能的场效应晶体管，其中，所述场效应晶体管设置于所述芯片主体上。
  9. 一种存算一体电路，其特征在于，包括电路板主体和如权利要求8所述的存算一体芯片，其中，所述存算一体芯片设置于所述电路板主体上。
  10. 一种存算一体设备，其特征在于，包括外壳和权利要求9所述的存算一体电路，其中，所述存算一体电路设置于所述外壳上。
PCT/CN2022/091334 2022-01-20 2022-05-07 场效应晶体管、存算一体芯片、电路及设备 WO2023137927A1 (zh)

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CN114639729B (zh) * 2022-05-17 2022-10-11 之江实验室 场效应晶体管、低功耗cmos集成芯片、电路及设备
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