WO2022156120A1 - 电容结构的制备方法、电容结构及存储器 - Google Patents

电容结构的制备方法、电容结构及存储器 Download PDF

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Publication number
WO2022156120A1
WO2022156120A1 PCT/CN2021/098877 CN2021098877W WO2022156120A1 WO 2022156120 A1 WO2022156120 A1 WO 2022156120A1 CN 2021098877 W CN2021098877 W CN 2021098877W WO 2022156120 A1 WO2022156120 A1 WO 2022156120A1
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layer
dielectric constant
amorphous
electrode
capacitor structure
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PCT/CN2021/098877
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English (en)
French (fr)
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苏星松
白卫平
郁梦康
王连红
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长鑫存储技术有限公司
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Priority to EP21783125.4A priority Critical patent/EP4060718B1/en
Priority to US17/444,690 priority patent/US20220230876A1/en
Publication of WO2022156120A1 publication Critical patent/WO2022156120A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Definitions

  • the present application relates to the technical field of semiconductor technology, and in particular, to a method for preparing a capacitor structure, a capacitor structure and a memory.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM for short) is widely used in various electronic devices because of its high density and fast read and write speed. Dynamic random access memory is generally composed of a plurality of memory cells, each memory cell usually includes a transistor and a capacitor structure. The capacitor structure stores data information, and the transistor controls the reading and writing of the data information in the capacitor structure.
  • the capacitive structure generally includes two electrodes disposed opposite to each other, and a dielectric layer located between the two electrodes.
  • the material of the dielectric layer is usually hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) or a perovskite structure material, such as calcium titanate (CaTiO 3 ) or barium titanate (BaTiO 3 ).
  • the above-mentioned materials usually have higher dielectric constants, so that the dielectric layer can have better insulating properties. However, when the above materials are in contact with the metal electrodes, a large leakage current will be generated.
  • the present application provides a method for fabricating a capacitor structure, a capacitor structure and a memory to solve the technical problem of large leakage current of the capacitor structure.
  • the present application provides a method for preparing a capacitor structure, including: forming a dielectric layer on a first electrode; wherein the dielectric layer includes a first amorphous layer and a high dielectric constant layer that are stacked and arranged , the first amorphous layer maintains an amorphous structure after annealing, the high dielectric constant layer is formed by crystallization after annealing the initial dielectric constant layer; a second electrode is formed on the dielectric layer.
  • a dielectric layer is first formed on the first electrode; wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer that are stacked and arranged.
  • the high dielectric constant layer is formed by crystallizing the initial dielectric constant layer after annealing; and then forming a second electrode on the dielectric layer. Since the first amorphous layer still has an amorphous structure after annealing, electron migration is not easy to occur in the amorphous structure, so that the first amorphous layer can suppress electron transfer, reduce the leakage current of the capacitor structure, and improve the performance of the capacitor structure.
  • the step of forming a dielectric layer on the first electrode includes: forming a first amorphous layer on the first electrode; forming an initial dielectric constant on the first amorphous layer annealing the first amorphous layer and the initial dielectric constant layer; wherein, the first amorphous layer maintains an amorphous structure after annealing, and the initial dielectric constant layer is annealed to form a high dielectric constant a dielectric constant layer; forming a second amorphous layer on the high dielectric constant layer.
  • the material of the second amorphous layer includes silicon oxide, aluminum oxide, hafnium silicate with a mass concentration of 10%-50% of silicon, or a mass concentration of aluminum with a mass concentration of 10%-50%.
  • 50% aluminum titanate, the thickness of the second amorphous layer is 0.5nm-5nm.
  • the step of forming a dielectric layer on the first electrode includes: forming a first amorphous layer on the first electrode; forming an initial dielectric constant on the first amorphous layer layer; forming a second amorphous layer on the initial dielectric constant layer; annealing the first amorphous layer, the initial dielectric constant layer and the second amorphous layer; wherein the Both the first amorphous layer and the second amorphous layer maintain an amorphous structure after annealing, and a high dielectric constant layer is formed after the initial dielectric constant layer is annealed.
  • the material of the second amorphous layer includes hafnium silicate with a mass concentration of silicon of 10%-50% or aluminum titanate with a mass concentration of aluminum of 10%-50% , the thickness of the second amorphous layer is 0.5nm-5nm.
  • the material of the first amorphous layer includes hafnium silicate or aluminum titanate.
  • the mass concentration of silicon in the hafnium silicate is 10%-50%
  • the mass concentration of aluminum in the aluminum titanate is 10%-50%
  • the thickness of the first amorphous layer is 0.5nm-5nm.
  • the material of the initial dielectric constant layer includes hafnium oxide doped with silicon, zirconium oxide doped with silicon or strontium titanate.
  • the mass concentration of silicon in the silicon-doped hafnium oxide and the silicon-doped zirconia is both less than or equal to 10%.
  • the thickness of the initial dielectric constant layer is 1 nm-10 nm.
  • the temperature of the annealing treatment is 200°C-600°C, and the time of the annealing treatment is 10s-600s.
  • the dielectric constant of the first amorphous layer and the second amorphous layer is 20-50, and the dielectric constant of the high dielectric constant layer is 40-300 .
  • the present application provides a capacitor structure, comprising a first electrode, a dielectric layer and a second electrode; the first electrode and the second electrode are disposed opposite to each other, and the dielectric layer is located on the first electrode between the electrode and the second electrode, and in contact with the first electrode and the second electrode; the dielectric layer includes a first amorphous layer, a high dielectric constant layer and a second amorphous layer; The first amorphous layer is in contact with the first electrode, the second amorphous layer is in contact with the second electrode, and the high dielectric constant layer is located between the first amorphous layer and the second electrode.
  • the first amorphous layer maintains an amorphous structure after annealing, and the high dielectric constant layer is composed of Crystallization is formed after the initial dielectric constant layer is annealed.
  • the capacitor structure provided by the present application includes a first electrode and a second electrode disposed opposite to each other, and a dielectric layer located between the first electrode and the second electrode and in contact with the first electrode and the second electrode, wherein the dielectric layer including a first amorphous layer in contact with the first electrode, a second amorphous layer in contact with the second electrode, and a high dielectric constant layer between the first amorphous layer and the second amorphous layer, the high dielectric constant The dielectric constant layer is in contact with the first amorphous layer and the second amorphous layer.
  • the first amorphous layer maintains an amorphous structure after annealing, and electron migration is not easy to occur in the amorphous structure, so that the first amorphous layer can suppress electron transfer, reduce the leakage current of the capacitor structure, and improve the performance of the capacitor structure.
  • the high dielectric constant layer is formed by crystallizing the initial dielectric constant layer after annealing, and its dielectric constant is relatively high, which can improve the dielectric properties of the capacitor structure.
  • the material of the first amorphous layer includes hafnium silicate with a mass concentration of silicon of 10%-50% or aluminum titanate with a mass concentration of aluminum of 10%-50%;
  • the material of the initial dielectric constant layer includes hafnium oxide doped with silicon, zirconium oxide doped with silicon or strontium titanate;
  • the material of the second amorphous layer includes silicon oxide, aluminum oxide, and the mass concentration of silicon is 10%- The mass concentration of 50% hafnium silicate or aluminum is 10%-50% aluminum titanate.
  • the present application provides a memory including a transistor and the above-mentioned capacitor structure.
  • the memory provided by the present application has the advantages of small leakage current and high dielectric constant because it includes the above-mentioned capacitor structure.
  • the specific effects can be referred to the above, and will not be repeated here.
  • FIG. 1 is a flowchart of a method for preparing a capacitor structure in an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a first electrode in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram after forming a first amorphous layer in an embodiment of the present application
  • FIG. 4 is a schematic structural diagram after forming an initial dielectric constant layer in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of the first amorphous layer and the initial dielectric constant layer after annealing in an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of forming a second electrode on a high dielectric constant layer according to an embodiment of the present application
  • FIG. 7 is a flowchart of a method for preparing a dielectric layer according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of forming a second amorphous layer on a high dielectric constant layer according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of forming a second electrode on the second amorphous layer in an embodiment of the present application.
  • FIG. 10 is a flowchart of another method for preparing a dielectric layer in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram after forming a second amorphous layer on the initial dielectric constant layer according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of the first amorphous layer, the initial dielectric constant layer and the second amorphous layer after annealing in an embodiment of the present application;
  • FIG. 13 is a schematic diagram of a capacitor structure in an embodiment of the present application.
  • the capacitive structure generally includes two electrodes disposed opposite to each other, and a dielectric layer located between the two electrodes.
  • the material of the dielectric layer is usually hafnium oxide, zirconium oxide or perovskite structure material, and the above materials usually have a relatively high dielectric constant.
  • the above materials are in contact with the metal electrodes, a large leakage current will be generated, resulting in a large leakage current of the capacitor structure.
  • the embodiment of the present application provides a method for preparing a capacitor structure.
  • a dielectric layer with a first amorphous layer By forming a dielectric layer with a first amorphous layer, and the first amorphous layer still maintains the amorphous structure after annealing, electron migration is not easy to occur in the amorphous structure, thereby As a result, the first amorphous layer can suppress electron transmission, reduce the leakage current of the capacitor structure, and improve the performance of the capacitor structure.
  • FIG. 1 is a flowchart of a method for fabricating a capacitor structure in an embodiment of the present application
  • FIGS. 2 to 6 are schematic structural diagrams of a capacitor structure at each stage of the fabrication process.
  • the following describes the preparation method of the capacitor structure with reference to FIG. 1 to FIG. 6 .
  • the preparation method may include the following steps:
  • Step S101 forming a dielectric layer on the first electrode; wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer, the first amorphous layer maintains an amorphous structure after annealing, and the high dielectric constant layer is initially Crystallization is formed after the dielectric constant layer is annealed.
  • a first electrode 10 is provided, and the first electrode 10 may be one or more of a metal electrode, a metal oxide electrode, a metal nitride electrode or a metal silicide electrode.
  • the material of the first electrode 10 may be aluminum (Al), copper (Cu), silver (Ag), gold (Au), molybdenum (Mo), nickel (Ni), cobalt (Co), titanium (Ti) ) or one or more of tungsten (W), or one or more of its oxides, nitrides or silicides.
  • the first electrode 10 can be formed by a deposition process, for example, by a chemical vapor deposition (Chemical Vapor Deposition, CVD for short) process, a Physical Vapor Deposition (Physical Vapor Deposition, PVD for short) process or Atomic Layer Deposition (Atomic Layer Deposition, ALD for short) process etc. to form the first electrode 10 .
  • a chemical vapor deposition Chemical Vapor Deposition, CVD for short
  • Physical Vapor Deposition Physical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the embodiment of the present application is not limited thereto, and the first electrode 10 in the embodiment of the present application may also be formed by other processes, such as an electroplating process.
  • the dielectric layer in the embodiment of the present application may be a multi-layer structure.
  • the dielectric layer includes a first amorphous layer 20 and a high dielectric constant layer 30 that are stacked.
  • the first amorphous layer 20 may be located on a side of the high dielectric constant layer 30 close to the first electrode 10 .
  • the first amorphous layer 20 may also be located on the side of the high dielectric constant layer 30 away from the first electrode 10 , which is not limited to this embodiment of the present application.
  • the material of the first amorphous layer 20 can be an amorphous structure material (amorphous material), and the amorphous structure can still be maintained after annealing, and no or less crystallization occurs. That is, under the condition of higher temperature (200°C-600°C), the first amorphous layer 20 does not or less undergoes crystal phase transformation. In this way, the atoms or molecules inside the amorphous structure material are arranged in a disorderly state, and electrons are not easy to migrate in the amorphous structure material, so that the electron transmission can still be suppressed after the first amorphous layer 20 is annealed, thereby reducing the capacitance of the capacitance structure. leakage current, improving the performance of the capacitor structure.
  • amorphous structure material amorphous material
  • the material of the first amorphous layer 20 includes hafnium silicate or aluminum titanate, wherein the mass concentration of silicon in the hafnium silicate may be 10%-50%, and the mass concentration of aluminum in the aluminum titanate may be 10%. %-50%.
  • the thickness of the first amorphous layer 20 may be 0.5 nm-5 nm, so as to prevent the first amorphous layer 20 from being too thick and affecting the overall dielectric performance of the capacitor structure.
  • the dielectric constant of the first amorphous layer 20 may be 20-50.
  • the high dielectric constant layer 30 may have a higher dielectric constant, for example, its value may be 40-300, so as to improve the overall dielectric constant of the capacitor structure, so that the capacitor structure has better dielectric properties.
  • the high dielectric constant layer 30 may be formed by crystallization when the initial dielectric constant layer 31 is annealed, that is, the high dielectric constant layer 30 has a higher degree of crystallinity.
  • forming the dielectric layer on the first electrode 10 may include the following steps:
  • the first amorphous layer 20 is formed on the first electrode 10 .
  • the first amorphous layer 20 may be formed on the first electrode 10 by a deposition process, for example, by a plasma enhanced chemical vapor deposition process (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD) formed on the first electrode 10.
  • PECVD plasma enhanced chemical vapor deposition
  • the first amorphous layer 20 may also be formed on the first electrode 10 by a process such as sputtering, which is not limited in this embodiment of the present application.
  • an initial dielectric constant layer 31 is formed on the first amorphous layer 20 .
  • an initial dielectric constant layer 31 is deposited on the first amorphous layer 20 .
  • the thickness of the initial dielectric constant layer 31 may be 1 nm-10 nm.
  • the material of the initial dielectric constant layer 31 may be silicon-doped hafnium oxide, silicon-doped zirconia or strontium titanate (SrTiO 3 ), wherein the mass concentration of silicon in the hafnium oxide may be less than or equal to 10%, and the zirconia The mass concentration of silicon in the medium can be less than or equal to 10%; in this way, the initial dielectric constant layer 31 can undergo crystal phase transition under higher temperature conditions, such as 200°C-600°C.
  • the transformed crystal phase has a higher
  • the dielectric constant increases the dielectric constant of the capacitor structure.
  • the first amorphous layer 20 and the initial dielectric constant layer 31 are annealed.
  • the first amorphous layer 20 maintains an amorphous structure after annealing;
  • the initial dielectric constant layer 31 is crystallized after annealing to form a high dielectric constant layer 30 having a higher dielectric constant.
  • the temperature of the annealing treatment may be 200°C-600°C, and the time of the annealing treatment may be 10s-600s.
  • the first amorphous layer 20 and the high dielectric constant layer 30 form a dielectric layer.
  • Step S102 forming a second electrode on the dielectric layer.
  • the second electrode 50 is formed on the dielectric layer.
  • the second electrode 50 is deposited and formed on the high-k layer 30 in the dielectric layer.
  • the second electrode 50 may be one or more of a metal electrode, a metal oxide electrode, a metal nitride electrode or a metal silicide electrode.
  • the material and preparation of the second electrode 50 can be referred to the first electrode 10 , which will not be repeated here.
  • the material of the second electrode 50 may be the same as or different from that of the first electrode 10 .
  • the first electrode 10 , the first amorphous layer 20 , the high dielectric constant layer 30 and the second electrode 50 are sequentially stacked from bottom to top to form the capacitor structure in the embodiment of the present application.
  • a dielectric layer is firstly formed on the first electrode 10; wherein, the dielectric layer includes a stacked first amorphous layer 20 and a high dielectric constant layer 30, the first The amorphous layer 20 maintains an amorphous structure after annealing, and the high dielectric constant layer 30 is formed by crystallizing the initial dielectric constant layer 31 after annealing; and then the second electrode 50 is formed on the dielectric layer.
  • the first amorphous layer 20 still has an amorphous structure after annealing, electron migration is not easy to occur in the amorphous structure, so that the first amorphous layer 20 can suppress electron transfer, reduce the leakage current of the capacitor structure, and improve the performance of the capacitor structure.
  • the high dielectric constant layer 30 can have a higher dielectric constant, which can improve the dielectric constant of the capacitor structure, so that the capacitor structure has better dielectric properties.
  • forming the dielectric layer on the first electrode may also include the following steps:
  • Step S201 forming a first amorphous layer on the first electrode.
  • the first amorphous layer may be formed on the first electrode through a deposition process.
  • the material of the first amorphous layer may include hafnium silicate with a mass concentration of silicon of 10%-50% or aluminum titanate with a mass concentration of aluminum of 10%-50%.
  • Step S202 forming an initial dielectric constant layer on the first amorphous layer.
  • an initial dielectric constant layer is deposited on the first amorphous layer.
  • the material of the initial dielectric constant layer may include silicon-doped hafnium oxide, silicon-doped zirconia or strontium titanate, wherein the mass concentration of silicon in the hafnium oxide may be less than or equal to 10%, and the mass concentration of silicon in the zirconia It may be less than or equal to 10%, and the thickness of the initial dielectric constant layer 31 may be 1 nm-10 nm.
  • Step S203 annealing the first amorphous layer and the initial dielectric constant layer; wherein, the first amorphous layer maintains an amorphous structure after annealing, and a high dielectric constant layer is formed after the initial dielectric constant layer is annealed. That is, the initial dielectric constant layer 31 is crystallized after annealing to form a high dielectric constant layer 30 with a higher dielectric constant, thereby increasing the dielectric constant of the capacitor structure.
  • the first amorphous layer 20 maintains the amorphous structure after annealing, so as to suppress electron transport and reduce the leakage current of the capacitor structure.
  • the temperature of the annealing treatment may be 200°C-600°C, and the time of the annealing treatment may be 10s-600s.
  • Step S204 forming a second amorphous layer on the high dielectric constant layer.
  • the thickness of the second amorphous layer 40 may be 0.5 nm-5 nm, and the dielectric constant may be 20-50.
  • the material of the second amorphous layer 40 may be an amorphous material.
  • the material of the second amorphous layer 40 may include silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ); it may also include hafnium silicate or aluminum with a mass concentration of 10%-50% of silicon.
  • Amorphous materials such as aluminum titanate with a mass concentration of 10%-50%.
  • the second amorphous layer 40 in the embodiment of the present application does not need to be annealed, so it is not limited whether the crystal phase transition occurs when the second amorphous layer 40 is annealed.
  • the first amorphous layer 20 , the high dielectric constant layer 30 and the second amorphous layer 40 form the dielectric layers in the embodiments of the present application.
  • forming the dielectric layer on the first electrode may further include the following steps:
  • Step S301 forming a first amorphous layer on the first electrode.
  • the first amorphous layer may be formed on the first electrode through a deposition process.
  • the material of the first amorphous layer may include hafnium silicate with a mass concentration of silicon of 10%-50% or aluminum titanate with a mass concentration of aluminum of 10%-50%.
  • Step S302 forming an initial dielectric constant layer on the first amorphous layer.
  • an initial dielectric constant layer may be formed on the first amorphous layer through a deposition process.
  • the material of the initial dielectric constant layer may include silicon-doped hafnium oxide, silicon-doped zirconia or strontium titanate, wherein the mass concentration of silicon in the hafnium oxide may be less than or equal to 10%, and the mass concentration of silicon in the zirconia It may be less than or equal to 10%, and the thickness of the initial dielectric constant layer 31 may be 1 nm-10 nm.
  • Step S303 forming a second amorphous layer on the initial dielectric constant layer.
  • the thickness of the second amorphous layer 40 may be 0.5 nm-5 nm, and the dielectric constant may be 20-50.
  • the material of the second amorphous layer 40 may be an amorphous material.
  • the material of the second amorphous layer 40 may include hafnium silicate with a mass concentration of 10%-50% of silicon, or aluminum titanate with a mass concentration of aluminum of 10%-50%, which is not generated or relatively high during annealing. Amorphous material with little crystallization. In this way, during the subsequent annealing process, the second amorphous layer 40 can maintain an amorphous structure without or less crystallization, so that the second amorphous layer 40 can also suppress electron transport and further reduce the leakage of the capacitor structure. current.
  • Step S304 annealing the first amorphous layer, the initial dielectric constant layer, and the second amorphous layer; wherein, the first amorphous layer and the second amorphous layer maintain an amorphous structure after annealing, and the initial dielectric constant
  • a high dielectric constant layer is formed after layer annealing.
  • the temperature of the annealing treatment may be 200°C-600°C
  • the time of the annealing treatment may be 10s-600s.
  • the initial dielectric constant layer 31 is crystallized after annealing to form a high dielectric constant layer 30 with a higher dielectric constant, which improves the dielectric constant of the capacitor structure.
  • the amorphous structure of the first amorphous layer 20 is maintained after annealing, which can suppress electron transfer and reduce the leakage current of the capacitor structure.
  • the second amorphous layer 40 maintains the amorphous structure after annealing, which can also suppress the electron transfer and further reduce the leakage current of the capacitor structure.
  • the first amorphous layer 20 , the high dielectric constant layer 30 and the second amorphous layer 40 form the dielectric layers in the embodiments of the present application.
  • the preparation method of the capacitor structure in the embodiment of the present application can be applied to the columnar capacitor structure.
  • the first electrode 10 is roughly U-shaped, and the inner portion of the U-shape and the outer portion of the U-shape are provided with a dielectric layer and a second electrode 50 to form a stacked double-sided structure.
  • the dielectric layer includes a first amorphous layer 20 , a high dielectric constant layer 30 and a second amorphous layer 40 .
  • the first amorphous layer 20 maintains an amorphous structure after annealing, so as to suppress electron transfer, reduce the leakage current of the capacitor structure, and improve the performance of the capacitor structure.
  • the first electrode 10 is formed on the support pad 60 , and the support pad 60 may be formed at the middle and top of the capacitor to ensure stable support for the capacitor.
  • an embodiment of the present application provides a capacitor structure including a first electrode 10 , a dielectric layer and a second electrode 50 .
  • the first electrode 10 and the second electrode 50 are disposed opposite to each other, a dielectric layer is disposed between the first electrode 10 and the second electrode 50 , and the dielectric layer is in contact with the first electrode 10 and the second electrode 50 .
  • the first electrode 10 and the second electrode 50 may be one or more of a metal electrode, a metal oxide electrode, a metal nitride electrode or a metal silicide electrode, that is, the capacitor structure in the embodiment of the present application may be a metal-insulator -Metal-Insulator-Metal (MIM for short) capacitor structure, of course, the embodiment of the present application is not limited to this. Insulator-Semiconductor, referred to as MIS) capacitors, etc.
  • MIM metal-insulator -Metal-Insulator-Metal
  • the dielectric layer includes a first amorphous layer 20, a high dielectric constant layer 30 and a second amorphous layer 40, wherein the first amorphous layer 20 is in contact with the first electrode 10, and the second amorphous layer 40 is in contact with the second electrode 50 contacts, the high dielectric constant layer 30 is located between the first amorphous layer 20 and the second amorphous layer 40 and is in contact with the first amorphous layer 20 and the second amorphous layer 40 .
  • the first electrode 10 , the first amorphous layer 20 , the high dielectric constant layer 30 , the second amorphous layer 40 and the second electrode 50 are sequentially stacked from bottom to top.
  • the first amorphous layer 20 After the first amorphous layer 20 is annealed, no or less crystal phase transformation occurs, and the amorphous structure can still be maintained. Compared with the crystalline structure, electron migration is less likely to occur in the amorphous structure, so that the first amorphous layer 20 can suppress electron transport and reduce the leakage current of the capacitor structure.
  • the material of the first amorphous layer 20 can be an amorphous structure material, for example, hafnium silicate or aluminum titanate, wherein the concentration of silicon in the hafnium silicate is 10%-50%, and the concentration of aluminum in the aluminum titanate is 10%. %-50%, its dielectric constant can be 20-50, and its thickness can be 0.5nm-5nm.
  • the high dielectric constant layer 30 is formed by crystallization after the initial dielectric constant layer 31 is annealed, that is, the crystal phase of the initial dielectric constant layer 31 changes after annealing, from a low dielectric constant crystal phase to a high dielectric constant crystal phase,
  • the high dielectric constant layer 30 with higher dielectric constant is formed to improve the dielectric constant of the capacitor structure.
  • the dielectric constant of the high dielectric constant layer 30 may be 40-300, and the thickness thereof may be 1 nm-10 nm.
  • the temperature of the annealing treatment may be 200°C-600°C, and the time of the annealing treatment may be 10s-600s.
  • the material of the initial dielectric constant layer 31 may be silicon-doped hafnium oxide, silicon-doped zirconia or strontium titanate, wherein the mass concentration of silicon in the hafnium oxide is less than or equal to 10%, and the mass concentration of silicon in the zirconia less than or equal to 10%.
  • the material of the second amorphous layer 40 can be an amorphous structural material.
  • the material of the second amorphous layer 40 can include silicon oxide, aluminum oxide, etc.; it can also include amorphous materials such as hafnium silicate or aluminum titanate. material, wherein the concentration of silicon in hafnium silicate is 10%-50%, the concentration of aluminum in aluminum titanate is 10%-50%, its dielectric constant can be 20-50, and its thickness can be 0.5nm-5nm .
  • the material of the second amorphous layer 40 may be an amorphous material such as hafnium silicate or aluminum titanate that does not produce or less crystallizes during annealing , so that the second amorphous layer 40 after annealing can still maintain the amorphous structure, so as to suppress the electron transfer and reduce the leakage current of the capacitor structure.
  • the material of the second amorphous layer 40 may be an amorphous structural material.
  • the capacitor structure in the embodiments of the present application may be applicable to the columnar capacitor structure.
  • the first electrode 10 is roughly U-shaped, and the inner portion of the U-shape and the outer portion of the U-shape are provided with a dielectric layer and a second electrode 50 to form a stacked double-sided structure.
  • the dielectric layer includes a first amorphous layer 20 , a high dielectric constant layer 30 and a second amorphous layer 40 .
  • the first amorphous layer 20 maintains an amorphous structure after annealing, so as to suppress electron transfer, reduce the leakage current of the capacitor structure, and improve the performance of the capacitor structure.
  • the first electrode 10 is formed on the support pad 60 , and the support pad 60 may be formed at the middle and top of the capacitor to ensure stable support for the capacitor.
  • the capacitor structure in the embodiment of the present application includes a first electrode 10 and a second electrode 50 disposed opposite to each other, and an intermediate electrode located between the first electrode 10 and the second electrode 50 and in contact with the first electrode 10 and the second electrode 50
  • the electrical layer, wherein the dielectric layer includes a first amorphous layer 20 in contact with the first electrode 10, a second amorphous layer 40 in contact with the second electrode 50, and the first amorphous layer 20 and the second amorphous layer 40
  • the high dielectric constant layer 30 between the amorphous layers 40 is in contact with the first amorphous layer 20 and the second amorphous layer 40 .
  • the first amorphous layer 20 maintains an amorphous structure after annealing, and electron migration is not easily generated in the amorphous structure, thereby reducing the leakage current of the capacitor structure and improving the performance of the capacitor structure.
  • the high dielectric constant layer 30 is formed by crystallizing the initial dielectric constant layer 31 after annealing, and its dielectric constant is relatively high, which can improve the dielectric properties of the capacitor structure.
  • An embodiment of the present application further provides a memory, including a transistor and a capacitor structure, the capacitor structure stores data information, and the transistor controls the reading and writing of the data information in the capacitor structure.
  • the gate of the transistor is electrically connected to the Word Line (WL) structure of the memory, one of the source and drain of the transistor is electrically connected to the Bit Line (BL) structure, and the source and drain are electrically connected to the Bit Line (BL) structure.
  • the other pole is electrically connected with the capacitive structure.
  • the capacitor structure includes a first electrode, a dielectric layer and a second electrode, the first electrode and the second electrode are arranged oppositely, and the dielectric layer is located between the first electrode and the second electrode and is in contact with the first electrode and the second electrode.
  • the dielectric layer includes a first amorphous layer, a high dielectric constant layer, and a second amorphous layer arranged in a stack. The first amorphous layer may be located on a side of the dielectric layer close to the first electrode.
  • the first electrode and the second electrode can be one or more of a metal electrode, a metal oxide electrode, a metal nitride electrode or a metal silicide electrode; the material of the first amorphous layer and the second amorphous layer can be amorphous Shaped structure material, its dielectric constant can be 20-50, and its thickness can be 0.5nm-5nm, wherein, the amorphous structure can still be maintained after the first amorphous layer is annealed; the dielectric constant of the high dielectric constant layer can be 40-300, and its thickness can be 1nm-10nm, which is formed by crystallization after annealing the initial dielectric constant layer.
  • the material of the first amorphous layer includes hafnium silicate with a mass concentration of silicon of 10%-50% or aluminum titanate with a mass concentration of aluminum of 10%-50%;
  • the material of the initial dielectric constant layer includes Silicon-doped hafnium oxide, silicon-doped zirconium oxide or strontium titanate;
  • the material of the second amorphous layer includes silicon oxide, aluminum oxide, hafnium silicate with a mass concentration of 10%-50% of silicon, or the mass of aluminum Aluminum titanate at a concentration of 10%-50%.
  • the memory in the embodiment of the present application includes a transistor and a capacitor structure. Since the memory has the capacitor structure in the above-mentioned embodiment, it has the advantage of small leakage current. The specific effect can be referred to the above-mentioned embodiment, which will not be repeated here.
  • references to the terms “one embodiment,” “some embodiments,” “illustrative embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments A particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

本申请属于半导体工艺技术领域，具体涉及一种电容结构的制备方法、电容结构及存储器，用于解决电容结构漏电流较大的技术问题。该电容结构的制备方法包括：在第一电极上形成介电层；其中，介电层包括堆叠设置的第一无定形层和高介电常数层，第一无定形层退火后保持无定形结构，高介电常数层由初始介电常数层退火后结晶形成；在介电层上形成第二电极。由于第一无定形层退火后仍为无定形结构，可以抑制电子传输，从而降低了电容结构的漏电流。

Description

电容结构的制备方法、电容结构及存储器
本申请要求于2021年01月20日提交中国专利局、申请号为202110075635.8、申请名称为“电容结构的制备方法、电容结构及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体工艺技术领域，尤其涉及一种电容结构的制备方法、电容结构及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)因具有较高的密度以及较快的读写速度广泛地应用在各种电子设备中。动态随机存取存储器一般由多个存储单元组成，每个存储单元通常包括晶体管和电容结构。电容结构中存储数据信息，晶体管控制电容结构中的数据信息的读写。
电容结构一般包括相对设置的两个电极，以及位于两个电极之间的介电层。介电层的材质通常为氧化铪(HfO 2)、氧化锆(ZrO 2)或者钙钛矿结构材质，例如钛酸钙(CaTiO 3)或者钛酸钡(BaTiO 3)。上述材质通常具有较高的介电常数，使得介电层可以具有较好的绝缘性能。然而，上述材质与金属电极接触时会产生较大的漏电流。
发明内容
有鉴于此，本申请提供一种电容结构的制备方法、电容结构及存储器，以解决电容结构的漏电流较大的技术问题。
第一方面，本申请提供了一种电容结构的制备方法，包括：在第一电极上形成介电层；其中，所述介电层包括堆叠设置的第一无定形层和高介电常数层，所述第一无定形层退火后保持无定形结构，所述高介电常数层由初始介电常数层退火后结晶形成；在所述介电层上形成第二电极。
本申请提供的电容结构的制备方法具有如下优点：
本申请提供的电容结构的制备方法中，先在第一电极上形成介电层；其中，介电层包括堆叠设置的第一无定形层和高介电常数层，第一无定形层退火后保持无定形结构，高介电常数层由初始介电常数层退火后结晶形成；然后在介电层上形成第二电极。由于第一无定形层退火后仍为无定形结构，无定形结构中不易发生电子迁移，从而使得第一无定形层可以抑制电子传输，减小电容结构的漏电流，提高电容结构的性能。
如上所述的电容结构的制备方法中，在第一电极上形成介电层的步骤包括：在第一电极上形成第一无定形层；在所述第一无定形层上形成初始介电常数层；对所述第一无定形层和所述初始介电常数层进行退火处理；其中，所述第一无定形层退火后保持无定形结构，所述初始介电常数层退火后形成高介电常数层；在所述高介电常数层上形成第二无定形层。
如上所述的电容结构的制备方法中，所述第二无定形层的材质包括氧化硅、氧化铝、硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝，所述第二无定形层的厚度为0.5nm-5nm。
如上所述的电容结构的制备方法中，在第一电极上形成介电层的步骤包括：在第一电极上形成第一无定形层；在所述第一无定形层上形成初始介电常数层；在所述初始介电常数层上形成第二无定形层；对所述第一无定形层、所述初始介电常数层和所述第二无定形层进行退火处理；其中，所述第一无定形层和所述第二无定形层退火后均保持无定形结构，所述初始介电常数层退火后形成高介电常数层。
如上所述的电容结构的制备方法中，所述第二无定形层的材质包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝，所述第二无定形层的厚度为0.5nm-5nm。
如上所述的电容结构的制备方法中，所述第一无定形层的材质包括硅酸铪或者钛酸铝。
如上所述的电容结构的制备方法中，所述硅酸铪中硅的质量浓度为10％-50％，所述钛酸铝中铝的质量浓度为10％-50％。
如上所述的电容结构的制备方法中，所述第一无定形层的厚度为0.5nm-5nm。
如上所述的电容结构的制备方法中，所述初始介电常数层的材质包括 掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶。
如上所述的电容结构的制备方法中，所述掺杂硅的氧化铪和所述掺杂硅的氧化锆中硅的质量浓度均小于或者等于10％。
如上所述的电容结构的制备方法中，所述初始介电常数层的厚度为1nm-10nm。
如上所述的电容结构的制备方法中，所述退火处理的温度为200℃-600℃，所述退火处理的时间为10s-600s。
如上所述的电容结构的制备方法中，所述第一无定形层和所述第二无定形层的介电常数为20-50，所述高介电常数层的介电常数为40-300。
第二方面，本申请提供了一种电容结构，包括第一电极，介电层和第二电极；所述第一电极和所述第二电极相对设置，所述介电层位于所述第一电极和所述第二电极之间，且与所述第一电极和所述第二电极相接触；所述介电层包括第一无定形层，高介电常数层和第二无定形层；其中，所述第一无定形层与所述第一电极接触，所述第二无定形层与所述第二电极接触，所述高介电常数层位于所述第一无定形层与所述第二无定形层之间，且与所述第一无定形层和所述第二无定形层相接触；所述第一无定形层退火后保持无定形结构，所述高介电常数层由初始介电常数层退火后结晶形成。
本申请提供的电容结构包括相对设置的第一电极和第二电极，以及位于第一电极和第二电极之间且与第一电极和第二电极相接触的介电层，其中，介电层包括与第一电极相接触的第一无定形层、与第二电极相接触的第二无定形层，以及位于第一无定形层和第二无定形层之间的高介电常数层，高介电常数层与第一无定形层和第二无定形层相接触。第一无定形层退火后保持无定形结构，无定形结构中不易发生电子迁移，从而使得第一无定形层可以抑制电子传输，减小电容结构的漏电流，提高电容结构的性能。此外，高介电常数层由初始介电常数层退火后结晶形成，其介电常数较高，可以提高电容结构的介电性能。
如上所述的电容结构中，所述第一无定形层的材质包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝；所述初始介电常数层的材质包括掺杂硅的氧化铪，掺杂硅的氧化锆或者钛酸锶；所述第二无定形层的材质包括氧化硅、氧化铝、硅的质量浓度为10％-50％的硅 酸铪或者铝的质量浓度为10％-50％的钛酸铝。
第三方面，本申请提供了一种存储器，包括晶体管和上述电容结构。
本申请提供的存储器由于包括上述电容结构，因而具有漏电流小和介电常数高的优点，具体效果参照上文所述，在此不再赘述。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的电容结构的制备方法、电容结构及存储器所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
图1为本申请实施例中的一种电容结构的制备方法的流程图；
图2为本申请实施例中的第一电极的结构示意图；
图3为本申请实施例中的形成第一无定形层后的结构示意图；
图4为本申请实施例中的形成初始介电常数层后的结构示意图；
图5为本申请实施例中的对第一无定形层和初始介电常数层退火后的结构示意图；
图6为本申请实施例中的在高介电常数层上形成第二电极后的结构示意图；
图7为本申请实施例中的一种介电层的制备方法的流程图；
图8为本申请实施例中的在高介电常数层上形成第二无定形层后的结构示意图；
图9为本申请实施例中的在第二无定形层上形成第二电极后的结构示意图；
图10为本申请实施例中的另一种介电层的制备方法的流程图；
图11为本申请实施例中的在初始介电常数层上形成第二无定形层后的结构示意图；
图12为本申请实施例中的对第一无定形层、初始介电常数层和第二无定形层退火后的结构示意图；
图13为本申请实施例中的电容结构的示意图。
具体实施方式
电容结构通常包括相对设置的两个电极，以及位于两个电极之间的介电层。相关技术中，介电层的材质通常为氧化铪、氧化锆或者钙钛矿结构材质，上述材质通常具有较高的介电常数。然而，上述材质与金属电极接触时会产生较大的漏电流，导致电容结构的漏电流较大。
本申请实施例提供一种电容结构的制备方法，通过形成具有第一无定形层的介电层，且第一无定形层退火后仍保持无定形结构，无定形结构中不易发生电子迁移，从而使得第一无定形层可以抑制电子传输，减小电容结构的漏电流，提高电容结构的性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
实施例一
参照图1至图6，图1为本申请实施例中的电容结构的制备方法的流程图，图2至图6为电容结构在制备过程的各阶段的结构示意图。下面结合图1至图6对电容结构的制备方法进行介绍，该制备方法可以包括以下步骤：
步骤S101、在第一电极上形成介电层；其中，介电层包括第一无定形层和高介电常数层，第一无定形层退火后保持无定形结构，高介电常数层由初始介电常数层退火后结晶形成。
参照图2，提供第一电极10，第一电极10可以为金属电极，金属氧化物电极，金属氮化物电极或者金属硅化物电极中的一种或者多种。示例性的，第一电极10的材质可以为铝(Al)、铜(Cu)、银(Ag)、金(Au)、钼(Mo)、镍(Ni)、钴(Co)、钛(Ti)或者钨(W)中的一种或者多种，或其氧化物，氮化物或者硅化物中的一种或者多种。
第一电极10可以通过沉积工艺形成，例如，通过化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺、物理气相沉积(Physical Vapor Deposition，简称PVD)工艺或者原子层沉积(Atomic Layer Deposition， 简称ALD)工艺等形成第一电极10。当然本申请实施例并不以此为限，本申请实施例中的第一电极10还可以通过其他工艺形成，例如电镀(Electroplating)工艺。
提供第一电极10后，在第一电极10上形成介电层。本申请实施例中的介电层可以为多层结构，例如，介电层包括堆叠设置的第一无定形层20和高介电常数层30。示例性的，第一无定形层20可以位于高介电常数层30靠近第一电极10的一侧。第一无定形层20也可以位于高介电常数层30远离第一电极10的一侧，本申请实施例不以此为限。
第一无定形层20的材质可以为无定形结构材质(非晶体材料)，且其在退火后仍可以保持无定形结构，不产生或者较少产生结晶现象。即在较高温度(200℃-600℃)条件下，第一无定形层20不发生或者较少发生晶相转变。如此设置，无定形结构材质内部原子或分子呈杂乱无章的排布状态，电子不易在无定形结构材质中迁移，从而使得第一无定形层20退火后仍可以抑制电子传输，从而减小电容结构的漏电流，提高电容结构的性能。
示例性的，第一无定形层20的材质包括硅酸铪或者钛酸铝，其中，硅酸铪中硅的质量浓度可以为10％-50％，钛酸铝中铝的质量浓度可以为10％-50％。第一无定形层20的厚度可以为0.5nm-5nm，以避免第一无定形层20过厚，影响电容结构整体的介电性能。本申请实施例中，第一无定形层20的介电常数可以为20-50。
高介电常数层30可以具有较高的介电常数，例如，其值可以为40-300，以提高电容结构整体的介电常数，使得电容结构具有较好的介电性能。本申请实施例中，高介电常数层30可以由初始介电常数层31退火时结晶形成，也就是说，高介电常数层30的结晶程度较高。
本申请实施例中，在第一电极10上形成介电层可以包括以下步骤：
首先，在第一电极10上形成第一无定形层20。参照图3，第一无定形层20可以通过沉积工艺形成在第一电极10上，例如，通过等离子体增强化学气相沉积工艺(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)形成在第一电极10上。当然第一无定形层20也可以采用溅镀等工艺形成在第一电极10上，本申请实施例对此不作限定。
其次，在第一无定形层20上形成初始介电常数层31。参照图4，在第一无定形层20上沉积形成初始介电常数层31。初始介电常数层31的厚度 可以为1nm-10nm。
初始介电常数层31的材质可以为掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶(SrTiO 3)，其中，氧化铪中硅的质量浓度可以小于或者等于10％，氧化锆中硅的质量浓度可以小于或者等于10％；如此设置，初始介电常数层31可以在较高温度条件下，例如200℃-600℃条件下，发生晶相转变。示例性的，由低介电常数的晶相(例如单斜，斜方晶系等)向高介电常数的晶相(例如四方，立方晶系等)转变，转变后的晶相具有较高的介电常数，提高了电容结构的介电常数。
然后，对第一无定形层20和初始介电常数层31进行退火处理。参照图5，第一无定形层20退火后保持无定形结构；初始介电常数层31退火后结晶，形成具有较高介电常数的高介电常数层30。示例性的，退火处理的温度可以为200℃-600℃，退火处理的时间可以为10s-600s。第一无定形层20和高介电常数层30形成介电层。
步骤S102、在介电层上形成第二电极。
参照图6，第二电极50形成在介电层上，示例性的，第二电极50沉积形成在介电层中的高介电常数层30上。第二电极50可以为金属电极，金属氧化物电极，金属氮化物电极或者金属硅化物电极中的一种或者多种，其材质和制备可以参照第一电极10，在此不再赘述。第二电极50的材质可以与第一电极10的材质相同，也可以不同。如图6所示，第一电极10、第一无定形层20、高介电常数层30以及第二电极50由下至上依次堆叠设置，形成本申请实施例中的电容结构。
本申请实施例提供的电容结构的制备方法中，先在第一电极10上形成介电层；其中，介电层包括堆叠设置的第一无定形层20和高介电常数层30，第一无定形层20退火后保持无定形结构，高介电常数层30由初始介电常数层31退火后结晶形成；然后在介电层上形成第二电极50。由于第一无定形层20退火后仍为无定形结构，无定形结构中不易发生电子迁移，从而使得第一无定形层20可以抑制电子传输，降低电容结构的漏电流，提高电容结构的性能。此外，高介电常数层30可以具有较高的介电常数，可以提高电容结构的介电常数，使得电容结构具有较好的介电性能。
需要说明的是，参照图7，本申请实施例中，在第一电极上形成介电层也可以包括以下步骤：
步骤S201、在第一电极上形成第一无定形层。第一无定形层可以通过沉积工艺形成在第一电极上。第一无定形层的材质可以包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝。
步骤S202、在第一无定形层上形成初始介电常数层。例如，初始介电常数层沉积形成在第一无定形层上。初始介电常数层的材质可以包括掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶，其中，氧化铪中硅的质量浓度可以小于或者等于10％，氧化锆中硅的质量浓度可以小于或者等于10％，初始介电常数层31的厚度可以为1nm-10nm。
步骤S203、对第一无定形层和初始介电常数层进行退火处理；其中，第一无定形层退火后保持无定形结构，初始介电常数层退火后形成高介电常数层。即初始介电常数层31退火后结晶，形成具有较高介电常数的高介电常数层30，提高了电容结构的介电常数。第一无定形层20退火后保持无定形结构，以抑制电子传输，减小电容结构的漏电流。退火处理的温度可以为200℃-600℃，退火处理的时间可以为10s-600s。
步骤S204、在高介电常数层上形成第二无定形层。参照图8，第二无定形层40的厚度可以为0.5nm-5nm，介电常数可以为20-50。第二无定形层40的材质可以为无定形体材质。
示例性的，第二无定形层40的材质可以包括氧化硅(SiO 2)、氧化铝(Al 2O 3)；也可以包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝等无定形体材质。
本申请实施例中的第二无定形层40无需进行退火处理，因此对第二无定形层40退火时是否发生晶相转变不作限定。第一无定形层20、高介电常数层30和第二无定形层40形成本申请实施例中的介电层。
需要说明的是，本申请实施例中，参照图10，在第一电极上形成介电层还可以包括以下步骤：
步骤S301、在第一电极上形成第一无定形层。第一无定形层可以通过沉积工艺形成在第一电极上。第一无定形层的材质可以包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝。
步骤S302、在第一无定形层上形成初始介电常数层。例如，可以通过沉积工艺在第一无定形层上形成初始介电常数层。初始介电常数层的材质可以包括掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶，其中，氧化铪中 硅的质量浓度可以小于或者等于10％，氧化锆中硅的质量浓度可以小于或者等于10％，初始介电常数层31的厚度可以为1nm-10nm。
步骤S303、在初始介电常数层上形成第二无定形层。参照图11，第二无定形层40的厚度可以为0.5nm-5nm，介电常数可以为20-50。第二无定形层40的材质可以为无定形体材质。
示例性的，第二无定形层40的材质可以包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝等退火时不产生或者较少产生结晶现象的无定形体材质。如此设置，后续退火处理时，第二无定形层40可以保持无定形结构，不产生或者较少产生结晶现象，从而使得第二无定形层40也可以抑制电子传输，进一步减小电容结构的漏电流。
步骤S304、对第一无定形层、初始介电常数层和第二无定形层进行退火处理；其中，第一无定形层和第二无定形层退火后均保持无定形结构，初始介电常数层退火后形成高介电常数层。示例性的，退火处理的温度可以为200℃-600℃，退火处理的时间可以为10s-600s。
本步骤中，参照图12，初始介电常数层31退火后结晶，形成具有较高介电常数的高介电常数层30，提高了电容结构的介电常数。第一无定形层20退火后保持无定形结构，可以抑制电子传输，减小电容结构的漏电流。第二无定形层40退火后保持无定形结构，也可以抑制电子传输，进一步减小电容结构的漏电流。第一无定形层20、高介电常数层30和第二无定形层40形成本申请实施例中的介电层。
需要说明的是，本申请实施例中的电容结构的制备方法可以适用于柱状电容结构。示例性的，如图13所示的柱状电容结构中，第一电极10大致呈U形，U形的内部及U形的外部均设置有介电层及第二电极50，形成堆叠式双面柱状电容结构。
参照图13，沿第一电极10至第二电极50的方向，介电层包括第一无定形层20、高介电常数层30和第二无定形层40。第一无定形层20退火后保持无定形结构，以抑制电子传输，降低电容结构的漏电流，提高电容结构的性能。如图13所示的柱状电容结构中，第一电极10形成于支撑垫60上，支撑垫60可以形成在电容器的中部和顶部，以保证提供电容器的稳定支撑。
实施例二
参照图9，本申请实施例提供一种电容结构，包括第一电极10、介电层和第二电极50。其中，第一电极10和第二电极50相对设置，第一电极10与第二电极50之间设置有介电层，介电层与第一电极10和第二电极50相接触。
第一电极10和第二电极50可以为金属电极，金属氧化物电极，金属氮化物电极或者金属硅化物电极中的一种或者多种，即本申请实施例中的电容结构可以为金属-绝缘体-金属型(Metal-Insulator-Metal，简称MIM)电容结构，当然本申请实施例并不以此为限，例如，本申请实施例中的电容结构也可以为金属-绝缘体-半导体型(Metal-Insulator-Semiconductor，简称MIS)电容等。
介电层包括第一无定形层20，高介电常数层30和第二无定形层40，其中，第一无定形层20与第一电极10接触，第二无定形层40与第二电极50接触，高介电常数层30位于第一无定形层20和第二无定形层40之间，且与第一无定形层20和第二无定形层40接触。示例性的，如图9所示，第一电极10、第一无定形层20、高介电常数层30、第二无定形层40和第二电极50由下至上依次堆叠设置。
第一无定形层20退火后不产生或者较少产生晶相转变，仍可以保持无定形结构。相较于晶体结构，无定形结构中不易发生电子迁移，从而使得第一无定形层20可以抑制电子传输，减少电容结构的漏电流。
第一无定形层20的材质可以为无定形结构材质，例如，硅酸铪或者钛酸铝，其中，硅酸铪中硅的浓度为10％-50％，钛酸铝中铝的浓度为10％-50％，其介电常数可以为20-50，其厚度可以为0.5nm-5nm。
高介电常数层30由初始介电常数层31退火后结晶形成，即初始介电常数层31退火后晶相发生变化，由低介电常数的晶相转变为高介电常数的晶相，形成介电常数较高的高介电常数层30，提高了电容结构的介电常数。高介电常数层30的介电常数可以为40-300，其厚度可以为1nm-10nm。退火处理的温度可以为200℃-600℃，退火处理的时间可以为10s-600s。
初始介电常数层31的材质可以为掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶，其中，氧化铪中硅的质量浓度小于或者等于10％，氧化锆中硅的质量浓度小于或者等于10％。
第二无定形层40的材质可以为无定形结构材质，示例性的，第二无定形层40的材质可以包括氧化硅、氧化铝等；也可以包括硅酸铪或者钛酸铝等无定形体材质，其中，硅酸铪中硅的浓度为10％-50％，钛酸铝中铝的浓度为10％-50％，其介电常数可以为20-50，其厚度可以为0.5nm-5nm。
需要说明的是，当第二无定形层40需要进行退火处理时，第二无定形层40的材质可以为硅酸铪或者钛酸铝等退火时不产生或者较少产生结晶的无定形体材质，以使退火后的第二无定形层40仍可以保持无定形结构，以抑制电子传输，减小电容结构的漏电流。当第二无定形层40不需要进行退火处理时，无需对第二无定形层40退火后是否发生结晶进行限定，第二无定形层40的材质为无定形结构材质即可。
需要说明的是，本申请实施例中的电容结构可以适用于柱状电容结构。示例性的，如图13所示的柱状电容结构中，第一电极10大致呈U形，U形的内部及U形的外部均设置有介电层及第二电极50，形成堆叠式双面柱状电容结构。
参照图13，沿第一电极10至第二电极50的方向，介电层包括第一无定形层20、高介电常数层30和第二无定形层40。第一无定形层20退火后保持无定形结构，以抑制电子传输，降低电容结构的漏电流，提高电容结构的性能。如图13所示的柱状电容结构中，第一电极10形成于支撑垫60上，支撑垫60可以形成在电容器的中部和顶部，以保证提供电容器的稳定支撑。
本申请实施例中的电容结构包括相对设置的第一电极10和第二电极50，以及位于第一电极10和第二电极50之间且与第一电极10和第二电极50相接触的介电层，其中，介电层包括与第一电极10相接触的第一无定形层20、与第二电极50相接触的第二无定形层40，以及位于第一无定形层20和第二无定形层40之间的高介电常数层30，高介电常数层30与第一无定形层20和第二无定形层40相接触。第一无定形层20退火后保持无定形结构，无定形结构中不易产生电子迁移，从而降低电容结构的漏电流，提高电容结构的性能。此外，高介电常数层30由初始介电常数层31退火后结晶形成，其介电常数较高，可以提高电容结构的介电性能。
实施例三
本申请实施例还提供一种存储器，包括晶体管和电容结构，电容结构存储数据信息，晶体管控制电容结构中的数据信息的读写。晶体管的栅极与存储器的字线(Word Line，简称WL)结构电连接，晶体管的源极和漏极中的一极与位线(Bit Line，简称BL)结构电连接，源极和漏极中的另一极与电容结构电连接。
电容结构包括第一电极、介电层和第二电极，第一电极和第二电极相对设置，介电层位于第一电极和第二电极之间且与第一电极和第二电极相接触。介电层包括堆叠设置的第一无定形层、高介电常数层和第二无定形层。第一无定形层可以位于介电层中靠近第一电极的一侧。
第一电极和第二电极可以为金属电极，金属氧化物电极，金属氮化物电极或者金属硅化物电极中的一种或者多种；第一无定形层和第二无定形层的材质可以为无定形结构材质，其介电常数可以为20-50，其厚度可以为0.5nm-5nm，其中，第一无定形层退火后仍可以保持无定形结构；高介电常数层的介电常数可以为40-300，其厚度可以为1nm-10nm，其由初始介电常数层退火后结晶形成。
示例性的，第一无定形层的材质包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝；初始介电常数层的材质包括掺杂硅的氧化铪，掺杂硅的氧化锆或者钛酸锶；第二无定形层的材质包括氧化硅、氧化铝、硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝。
本申请实施例中的存储器包括晶体管和电容结构，由于存储器具有上述实施例中的电容结构，因而具有漏电流较小的优点，具体效果参照上述实施例，在此不再赘述。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
本领域技术人员应理解的是，在本申请的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的系统或元件必须具有特定的方位、以特定的方位构造和操作，因此上述 术语不能理解为对本申请的限制。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种电容结构的制备方法，其特征在于，包括：
    在第一电极上形成介电层；
    其中，所述介电层包括堆叠设置的第一无定形层和高介电常数层，所述第一无定形层退火后保持无定形结构，所述高介电常数层由初始介电常数层退火后结晶形成；
    在所述介电层上形成第二电极。
  2. 根据权利要求1所述的电容结构的制备方法，其特征在于，在第一电极上形成介电层的步骤包括：
    在所述第一电极上形成第一无定形层；
    在所述第一无定形层上形成初始介电常数层；
    对所述第一无定形层和所述初始介电常数层进行退火处理；其中，所述第一无定形层退火后保持无定形结构，所述初始介电常数层退火后形成高介电常数层；
    在所述高介电常数层上形成第二无定形层。
  3. 根据权利要求2所述的电容结构的制备方法，其特征在于，所述第二无定形层的材质包括氧化硅、氧化铝、硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝，所述第二无定形层的厚度为0.5nm-5nm。
  4. 根据权利要求1所述的电容结构的制备方法，其特征在于，在第一电极上形成介电层的步骤包括：
    在所述第一电极上形成第一无定形层；
    在所述第一无定形层上形成初始介电常数层；
    在所述初始介电常数层上形成第二无定形层；
    对所述第一无定形层、所述初始介电常数层和所述第二无定形层进行退火处理；其中，所述第一无定形层和所述第二无定形层退火后均保持无定形结构，所述初始介电常数层退火后形成高介电常数层。
  5. 根据权利要求4所述的电容结构的制备方法，其特征在于，所述第二无定形层的材质包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝，所述第二无定形层的厚度为0.5nm-5nm。
  6. 根据权利要求1所述的电容结构的制备方法，其特征在于，所述第一无定形层的材质包括硅酸铪或者钛酸铝。
  7. 根据权利要求6所述的电容结构的制备方法，其特征在于，所述硅酸铪中硅的质量浓度为10％-50％，所述钛酸铝中铝的质量浓度为10％-50％。
  8. 根据权利要求7所述的电容结构的制备方法，其特征在于，所述第一无定形层的厚度为0.5nm-5nm。
  9. 根据权利要求1所述的电容结构的制备方法，其特征在于，所述初始介电常数层的材质包括掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶。
  10. 根据权利要求2所述的电容结构的制备方法，其特征在于，所述初始介电常数层的材质包括掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶。
  11. 根据权利要求3所述的电容结构的制备方法，其特征在于，所述初始介电常数层的材质包括掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶。
  12. 根据权利要求4所述的电容结构的制备方法，其特征在于，所述初始介电常数层的材质包括掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶。
  13. 根据权利要求5所述的电容结构的制备方法，其特征在于，所述初始介电常数层的材质包括掺杂硅的氧化铪、掺杂硅的氧化锆或者钛酸锶。
  14. 根据权利要求9所述的电容结构的制备方法，其特征在于，所述掺杂硅的氧化铪和所述掺杂硅的氧化锆中硅的质量浓度均小于或者等于10％。
  15. 根据权利要求1所述的电容结构的制备方法，其特征在于，所述初始介电常数层的厚度为1nm-10nm。
  16. 根据权利要求1所述的电容结构的制备方法，其特征在于，所述退火处理的温度为200℃-600℃，所述退火处理的时间为10s-600s。
  17. 根据权利要求2所述的电容结构的制备方法，其特征在于，所述第一无定形层和所述第二无定形层的介电常数为20-50，所述高介电常数层的介电常数为40-300。
  18. 一种电容结构，其特征在于，包括：
    第一电极，介电层和第二电极；
    所述第一电极和所述第二电极相对设置，所述介电层位于所述第一电极和所述第二电极之间，且与所述第一电极和所述第二电极相接触；
    所述介电层包括第一无定形层，高介电常数层和第二无定形层；
    所述第一无定形层与所述第一电极接触，所述第二无定形层与所述第二电极接触，所述高介电常数层位于所述第一无定形层与所述第二无定形层之间，且与所述第一无定形层和所述第二无定形层相接触；
    所述第一无定形层退火后保持无定形结构，所述高介电常数层由初始介电常数层退火后结晶形成。
  19. 根据权利要求18所述的电容结构，其特征在于，所述第一无定形层的材质包括硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝；
    所述初始介电常数层的材质包括掺杂硅的氧化铪，掺杂硅的氧化锆或者钛酸锶；
    所述第二无定形层的材质包括氧化硅、氧化铝、硅的质量浓度为10％-50％的硅酸铪或者铝的质量浓度为10％-50％的钛酸铝。
  20. 一种存储器，其特征在于，包括晶体管和如权利要求18所述的电容结构。
PCT/CN2021/098877 2021-01-20 2021-06-08 电容结构的制备方法、电容结构及存储器 WO2022156120A1 (zh)

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US20100014212A1 (en) * 2005-11-10 2010-01-21 Deok-Sin Kil Capacitor and method for fabricating the same
CN102187440A (zh) * 2008-10-15 2011-09-14 美光科技公司 电容器、电介质结构和形成电介质结构的方法

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CN1655362A (zh) * 2004-01-29 2005-08-17 三星电子株式会社 用于半导体器件的电介质层及其制造方法
CN1934685A (zh) * 2004-05-21 2007-03-21 应用材料股份有限公司 高介电常数介电材料的稳定化方法
US20100014212A1 (en) * 2005-11-10 2010-01-21 Deok-Sin Kil Capacitor and method for fabricating the same
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CN102187440A (zh) * 2008-10-15 2011-09-14 美光科技公司 电容器、电介质结构和形成电介质结构的方法

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