WO2023137831A1 - 一种半导体器件及其制备方法 - Google Patents

一种半导体器件及其制备方法 Download PDF

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WO2023137831A1
WO2023137831A1 PCT/CN2022/078648 CN2022078648W WO2023137831A1 WO 2023137831 A1 WO2023137831 A1 WO 2023137831A1 CN 2022078648 W CN2022078648 W CN 2022078648W WO 2023137831 A1 WO2023137831 A1 WO 2023137831A1
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layer
drain
source
conduction
conduction layer
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PCT/CN2022/078648
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English (en)
French (fr)
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陈涛
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长鑫存储技术有限公司
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Priority to US17/746,452 priority Critical patent/US20230238235A1/en
Publication of WO2023137831A1 publication Critical patent/WO2023137831A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor device and a manufacturing method thereof.
  • DRAM dynamic random access memory
  • embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.
  • a semiconductor device including:
  • a gate layer located on the substrate
  • the first conduction layer and the second conduction layer are located on the gate layer; the materials of the first conduction layer and the second conduction layer include perovskite;
  • first source and the first drain are spaced apart from each other and respectively connected to both ends of the first conduction layer;
  • a second source and a second drain, the second source and the second drain are spaced apart from each other and are respectively connected to two ends of the second conduction layer.
  • the perovskite includes an inorganic perovskite.
  • the first source, the first drain, the first conduction layer and part of the gate layer constitute a transistor of the first conductivity type
  • the second source, the second drain, the second conduction layer and part of the gate layer form a second conductivity type transistor
  • the first drain is in contact with the second drain, so that the transistor of the first conductivity type and the transistor of the second conductivity type constitute an inverter.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the material of the first source and the first drain includes a low work function material; the material of the second source and the second drain includes a high work function material.
  • the material of the gate layer includes graphene.
  • a dielectric layer located on the gate layer and covering part of the gate layer
  • the area of the gate layer not covered by the dielectric layer is formed with a stacked first metal layer and a second metal layer; the material of the first metal layer is the same as that of the first source and the first drain; the material of the second metal layer is the same as that of the second source and the second drain.
  • a passivation layer covering exposed surfaces of the first source, the first drain, the first conduction layer, the second source, the second drain, the second conduction layer and the second metal layer.
  • a method for manufacturing a semiconductor device including:
  • first conduction layer and a second conduction layer on the gate layer; materials of the first conduction layer and the second conduction layer include perovskite;
  • a first source and a first drain spaced apart from each other are formed at both ends of the first conduction layer; the first source and the first drain are respectively connected to both ends of the first conduction layer;
  • a second source and a second drain spaced apart from each other are formed at both ends of the second conduction layer; the second source and the second drain are respectively connected to both ends of the second conduction layer.
  • the perovskite includes an inorganic perovskite.
  • the first source, the first drain, the first conduction layer and part of the gate layer constitute a transistor of the first conductivity type
  • the second source, the second drain, the second conduction layer and part of the gate layer form a second conductivity type transistor
  • the first drain is in contact with the second drain, so that the transistor of the first conductivity type and the transistor of the second conductivity type constitute an inverter.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the material of the first source and the first drain includes a low work function material; the material of the second source and the second drain includes a high work function material.
  • the material of the gate layer includes graphene.
  • a first metal layer is formed in a region of the gate layer not covered by the dielectric layer; the material of the first metal layer is the same as that of the first source and the first drain;
  • a second metal layer is formed on the first metal layer; the material of the second metal layer is the same as that of the second source and the second drain.
  • a passivation layer is formed; the passivation layer covers the exposed surfaces of the first source, the first drain, the first conduction layer, the second source, the second drain, the second conduction layer and the second metal layer.
  • the perovskite can form different types of Schottky junctions by contacting with different metals, which can save the step of ion implantation, reduce the use of photomasks, reduce process steps, and reduce costs; at the same time, the use of perovskite materials can suppress the SCE effect without additional doping, which can reduce the threshold voltage and improve the saturation current and reliability of the device.
  • FIG. 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 3a is a circuit diagram of an inverter in an embodiment of the present disclosure.
  • Fig. 3b is a schematic structural diagram corresponding to an inverter in an embodiment of the present disclosure
  • FIG. 4 is a schematic flow diagram of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
  • 5a to 5h are schematic structural diagrams of the semiconductor device provided by the embodiments of the present disclosure during the manufacturing process.
  • halo and lightly doped drain (LDD) doping techniques are mainly used to reduce SCE.
  • the depth of the halo ion implantation is greater than the depth of the lightly doped drain ion implantation, thereby effectively reducing the lateral expansion of the depletion region of the source region and the drain region and preventing the source-drain punch-through phenomenon.
  • a variety of doping techniques not only require high manufacturing costs, but also increase device reliability problems, such as the instantaneous enhanced diffusion of boron, PN junction leakage and negative bias temperature instability (NBTI), etc.
  • Ultra-thin-body (UTB) is used as a means to effectively reduce SCE, so that the gate can better adjust the device.
  • the thickness of the channel generally needs to be controlled at 1/3 of the gate length.
  • the inhomogeneity of the thickness of the atomic size will increase the change of the surface potential, resulting in enhanced Coulomb scattering of carriers, reducing the carrier mobility, and then reducing the saturation current.
  • FIG. 1 is a schematic structural diagram of the semiconductor device provided by the embodiment of the present disclosure
  • FIG. 2 is a top view of the semiconductor device provided by the embodiment of the present disclosure. It should be noted that the top view in FIG. 2 is a top view obtained after the passivation layer 90 is removed.
  • described semiconductor device comprises: substrate 10; Gate layer 30, is positioned on described substrate 10; First conduction layer 51 and second conduction layer 52, are positioned on described gate layer 30; The material of described first conduction layer 51 and described second conduction layer 52 comprises perovskite; The drain 72 , the second source 71 and the second drain 72 are spaced apart from each other and connected to both ends of the second conduction layer 52 respectively.
  • the perovskite can form different types of Schottky junctions by contacting with different metals, which can save the step of ion implantation, reduce the use of photomasks, reduce process steps, and reduce costs; at the same time, the use of perovskite materials can suppress the SCE effect without additional doping, which can reduce the threshold voltage and improve the saturation current and reliability of the device.
  • the substrate 10 may be a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a quartz, sapphire substrate, etc.
  • a single semiconductor material substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.
  • a compound semiconductor material substrate such as a silicon germanium (SiGe) substrate, etc.
  • SOI silicon-on-insulator
  • GeOI germanium-on-insulator
  • the semiconductor device further includes: an oxide layer 20 located on the substrate 10 .
  • the material of the oxide layer 20 includes but not limited to silicon dioxide.
  • the oxide layer 20 can be a gate oxide layer, and the oxide layer is located between the gate layer 30 and the substrate 10 , and can provide sufficient electrical insulation for the gate layer 30 and the substrate 10 below it, so as to prevent short circuit between the gate layer 30 and the substrate 10 .
  • the gate layer 30 is located on the substrate 10 . Specifically, the gate layer 30 is located on the oxide layer 20 .
  • the material of the gate layer 30 may include graphene. Using graphene as the material of the gate layer 30 can reduce the pollution of the dielectric layer caused by the metal electrode and avoid the electrical degradation of the device caused by high temperature annealing.
  • the gate layer 30 may also use conventional metal electrode materials, but it needs to be ensured that the conventional metal electrode materials will not damage the perovskite material during the annealing process.
  • the semiconductor device further includes: a dielectric layer 40 located on the gate layer 30 and partially covering the gate layer 30 .
  • the dielectric layer 40 is located between the gate layer and the first conduction layer above it, the second conduction layer and the first source, the first drain, the second source and the second drain, and can play the role of insulation and isolation to prevent short circuits between the gate layer and the conduction layer and the source/drain.
  • the dielectric layer 40 is a high-K dielectric layer.
  • the material of the dielectric layer 40 includes at least one of dielectric materials such as hafnium dioxide, silicon dioxide or aluminum oxide.
  • the first conduction layer 51 and the second conduction layer 52 are located on the gate layer 30 ; specifically, the first conduction layer 51 and the second conduction layer 52 are located on the dielectric layer 40 .
  • the perovskite includes inorganic perovskite.
  • Inorganic perovskite materials have the advantages of high carrier mobility, strong stability, and simple preparation methods.
  • inorganic perovskite materials can form P-type or N-type field effect transistors (Field Effect Transistors, FETs) by contacting metals with different work functions without ion implantation.
  • FETs Field Effect Transistors
  • their valence bands match with high work function metals to form P-type FETs
  • their conduction bands match with low work function metals to form N-type FETs, showing that they can be used as perfect components of MOS devices in DRAM.
  • the use of inorganic perovskite materials to make the conduction layer can better reduce the threshold voltage, increase the saturation current, and then improve the reliability of the device, and because the ion implantation step is omitted, the process steps are reduced and the cost is reduced.
  • the inorganic perovskite includes CsPbBr x I 3-x , where 0 ⁇ x ⁇ 3.
  • CsPbBr x I 3-x (0 ⁇ x ⁇ 3) as an ultra-thin channel (channel) with a size less than 1nm can suppress the SCE effect of silicon-based MOS devices caused by size reduction, and without additional doping, it can reduce the threshold voltage, improve the saturation current and the reliability of the device.
  • Cs can be replaced by Rb or Fr
  • Pb can be replaced by Sn
  • Br and I can be replaced by Cl.
  • an inversion layer (not shown in the figure) is formed on the side of the first conduction layer 51 and the second conduction layer 52 close to the dielectric layer 40, and the inversion layer constitutes a conductive channel, which is the reason for the conduction of the device.
  • the semiconductor device further includes: a first source 61 and a first drain 62, the first source 61 and the first drain 62 are spaced apart from each other and are respectively connected to both ends of the first conduction layer 51; a second source 71 and a second drain 72, the second source 71 and the second drain 72 are spaced apart from each other and are respectively connected to both ends of the second conduction layer 52.
  • the first source 61 , the first drain 62 , the second source 71 and the second drain 72 are all located on the dielectric layer 40 .
  • the first source 61 and the first drain 62 are respectively located at two ends of the first conduction layer 51 , wrap around the sidewall of the first conduction layer 51 and are partially located on the first conduction layer 51 .
  • the second source 71 and the second drain 72 are respectively located at both ends of the second conduction layer 52, wrapping the sidewall of the second conduction layer 52 and partly located on the second conduction layer 52.
  • the second drain 72 is in contact with the first drain 62 , wraps around the sidewall of the first drain 62 and is partially located on the first drain 62 .
  • the first drain 62 surrounds the sidewall of the second drain 72 and is partially located on the second drain 72 . It should be explained that whether the first drain 62 wraps the sidewall of the second drain 72 or the second drain 72 wraps the sidewall of the first drain 62 , good contact between the first drain 62 and the second drain 72 needs to be ensured.
  • the first source 61, the first drain 62, the first conduction layer 51 and part of the gate layer 30 constitute a transistor of the first conductivity type;
  • the second source 71, the second drain 72, the second conduction layer 52 and part of the gate layer 30 constitute a transistor of the second conduction type;
  • the first drain 62 is in contact with the second drain 72, so that the transistor of the first conduction type and the transistor of the second conduction type form an inverter.
  • FIG. 3a is a circuit diagram of an inverter in an embodiment of the present disclosure
  • FIG. 3b is a schematic structural diagram corresponding to an inverter in an embodiment of the present disclosure.
  • the transistor of the first conductivity type is connected to the gate of the transistor of the second conductivity type and used as an input terminal Vin
  • the source of the transistor of the second conductivity type that is, the second source is connected to the power supply voltage VDD
  • the source of the transistor of the first conductivity type that is, the first source is grounded to VSS
  • the transistor of the first conductivity type is connected to the drain of the transistor of the second conductivity type.
  • the poles are connected and used as the output terminal Vout. Specifically, the output terminal is drawn out through the second drain 72.
  • This connection method only occupies a small area and is more conducive to large-scale integration.
  • the transistors of the first conductivity type and the transistors of the second conductivity type share a gate, the integration degree is higher, and because only one gate needs to be fabricated, the required cost is lower.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the transistors of the first conductivity type are NMOS transistors
  • the transistors of the second conductivity type are PMOS transistors.
  • the material of the first source 61 and the first drain 62 includes a low work function material; the material of the second source 71 and the second drain 72 includes a high work function material.
  • the work function of the low work function material is low, the first conduction layer 51 is matched with the low work function material to form an NMOS transistor; the work function of the high work function material is high, and the second conduction layer 52 is matched with the high work function material to form a PMOS transistor.
  • Both the low work function material and the high work function material are electrode materials.
  • the low work function material includes materials such as Ti, Al, Ag, and Zn
  • the high work function material includes materials such as Au, Pt, C, W, Co, and Ni.
  • the low work function material may be Ti
  • the high work function material may be Au.
  • the region of the gate layer 30 not covered by the dielectric layer 40 is formed with a laminated first metal layer 81 and a second metal layer 82; the material of the first metal layer 81 is the same as that of the first source 61 and the first drain 62; the material of the second metal layer 82 is the same as that of the second source 71 and the second drain 72.
  • the gate layer 30 is connected to the first metal layer 81 and the second metal layer 82 , so that the PMOS transistor and the NMOS transistor share one gate layer.
  • the thickness of the first metal layer 81 is equal to the thickness of the first source 61 and the first drain 62
  • the thickness of the second metal layer 82 is equal to the thickness of the second source 71 . If the thicknesses are equal, the first metal layer and the first source and the first drain, or the second metal layer and the second source can be formed in the same deposition step.
  • the thickness of the first metal layer 81 may not be equal to the thicknesses of the first source 61 and the first drain 62
  • the thickness of the second metal layer 82 may not be equal to the thickness of the second source 71 .
  • the semiconductor device further includes: a passivation layer 90 covering exposed surfaces of the first source 61, the first drain 62, the first conduction layer 51, the second source 71, the second drain 72, the second conduction layer 52 and the second metal layer 82.
  • the passivation layer 90 can protect the channel material and prevent the channel material from being oxidized.
  • the passivation layer 90 is a high-K dielectric layer, and the material of the passivation layer 90 includes at least one of dielectric materials such as hafnium dioxide, silicon dioxide or aluminum oxide.
  • the embodiment of the present disclosure also provides a method for manufacturing a semiconductor device, please refer to accompanying drawing 4 for details, as shown in the figure, the method includes the following steps:
  • Step 401 providing a substrate
  • Step 402 forming a gate layer on the substrate
  • Step 403 forming a first conduction layer and a second conduction layer on the gate layer; materials of the first conduction layer and the second conduction layer include perovskite;
  • Step 404 forming a first source and a first drain spaced apart from each other at both ends of the first conduction layer; the first source and the first drain are respectively connected to both ends of the first conduction layer;
  • Step 405 Forming a second source and a second drain spaced apart from each other at both ends of the second conduction layer; the second source and the second drain are respectively connected to both ends of the second conduction layer.
  • 5a to 5h are schematic structural diagrams of the semiconductor device provided by the embodiments of the present disclosure during the manufacturing process.
  • step 401 is executed.
  • a substrate 10 is provided.
  • the substrate 10 may be a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a quartz, sapphire substrate, etc.
  • a single semiconductor material substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.
  • a compound semiconductor material substrate such as a silicon germanium (SiGe) substrate, etc.
  • SOI silicon-on-insulator
  • GeOI germanium-on-insulator
  • an oxide layer 20 is formed on the substrate 10 .
  • the material of the oxide layer 20 includes but not limited to silicon dioxide.
  • the oxide layer 20 can be a gate oxide layer, and the oxide layer is located between the gate layer 30 and the substrate 10, and can provide sufficient electrical insulation for the gate layer 30 and the substrate 10 below it, so as to prevent short circuit between the gate layer 30 and the substrate 10.
  • step 402 is executed.
  • a gate layer 30 is formed on the substrate 10 .
  • a gate layer 30 is formed on the oxide layer 20 .
  • the gate layer 30 may be formed using wet transfer or other deposition processes, including but not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the material of the gate layer 30 may include graphene. Using graphene as the material of the gate layer 30 can reduce the pollution of the dielectric layer caused by the metal electrode and avoid the electrical degradation of the device caused by high temperature annealing.
  • the gate layer 30 may also use conventional metal electrode materials, but it needs to be ensured that the conventional metal electrodes will not damage the perovskite during the annealing process.
  • the method further includes: after forming the gate layer 30 , forming a dielectric layer 40 covering part of the gate layer 30 on the gate layer 30 .
  • the dielectric layer 40 is located between the gate layer and the first conduction layer above it, the second conduction layer and the first source, the first drain, the second source and the second drain, and can play the role of insulation and isolation to prevent short circuits between the gate layer and the conduction layer and the source/drain.
  • the dielectric layer 40 can be formed by one or more thin film deposition processes; specifically, the deposition processes include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the dielectric layer 40 is a high-K dielectric layer.
  • the material of the dielectric layer 40 includes at least one of dielectric materials such as hafnium dioxide, silicon dioxide or aluminum oxide.
  • step 403 is executed.
  • a first conduction layer 51 and a second conduction layer 52 are formed on the gate layer 30 ; materials of the first conduction layer 51 and the second conduction layer 52 include perovskite. Specifically, a first conduction layer 51 and a second conduction layer 52 are formed on the dielectric layer 40.
  • a conductive layer pre-layer 50 covering the dielectric layer 40 is formed on the dielectric layer 40 .
  • the conduction layer pre-layer 50 can be deposited by electron beam evaporation or scrape coating, and can also be formed by one or more thin film deposition processes; specifically, the deposition process includes but is not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the conduction layer pre-layer 50 is etched to form a first conduction layer 51 and a second conduction layer 52 .
  • a mask layer can be grown on the upper surface of the dielectric layer 40 first, and then the mask layer can be patterned to display patterns to be etched away on the mask layer except for the first conduction layer and the second conduction layer, and the mask layer can be patterned by a photolithography process.
  • the mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer is patterned through steps such as exposure, development, and stripping.
  • the conduction layer pre-layer to be removed is etched according to the pattern to be etched to form a first conduction layer and a second conduction layer.
  • the etching process may be dry etching or wet etching, specifically, the etching process may be a reactive ion etching (RIE) process or a plasma etching (Plasma Etching) process or the like.
  • RIE reactive ion etching
  • Pasma Etching plasma etching
  • the perovskite includes inorganic perovskite.
  • Inorganic perovskite materials have the advantages of high carrier mobility, strong stability, and simple preparation methods.
  • inorganic perovskite materials do not require ion implantation, and can form P-type or N-type field effect transistors (Field Effect Transistors, FETs) by contacting metals with different work functions.
  • FETs Field Effect Transistors
  • their valence bands match with high work function metals to form P-type FETs
  • their conduction bands match with low work function metals to form N-type FETs, showing that they can be used as perfect components of MOS devices in DRAM.
  • the use of inorganic perovskite materials to make the conduction layer can better reduce the threshold voltage, increase the saturation current, and then improve the reliability of the device, and because the ion implantation step is omitted, the process steps are reduced and the cost is reduced.
  • the inorganic perovskite includes CsPbBr x I 3-x , where 0 ⁇ x ⁇ 3.
  • CsPbBr x I 3-x (0 ⁇ x ⁇ 3) as an ultra-thin channel (channel) with a size less than 1nm can suppress the SCE effect of silicon-based MOS devices caused by size reduction, and without additional doping, it can reduce the threshold voltage, improve the saturation current and the reliability of the device.
  • Cs can be replaced by Rb or Fr
  • Pb can be replaced by Sn
  • Br and I can be replaced by Cl.
  • an inversion layer (not shown in the figure) is formed on the side of the first conduction layer 51 and the second conduction layer 52 close to the dielectric layer 40, and the inversion layer constitutes a conductive channel, which is the reason for the conduction of the device.
  • step 404 is performed.
  • a first source 61 and a first drain 62 spaced apart from each other are formed at both ends of the first conduction layer 51 ; the first source 61 and the first drain 62 are respectively connected to both ends of the first conduction layer 51 .
  • a first photoresist layer 601 is formed on the part of the dielectric layer 40 where the first source electrode and the first drain electrode do not need to be formed and on the second conduction layer; then the first source electrode 61 and the first drain electrode 62 are respectively formed on both sides of the first conduction layer 51, and the first source electrode 61 and the first drain electrode 62 wrap the sidewall of the first conduction layer 51 and are partially located on the first conduction layer 51; after the first source electrode 61 and the first drain electrode 62 are formed, the first photoresist layer 601 is removed .
  • a first metal layer 81 is formed in the region of the gate layer 30 not covered by the dielectric layer 40; the material of the first metal layer 81 is the same as that of the first source 61 and the first drain 62.
  • step 405 is performed.
  • a second source 71 and a second drain 72 spaced apart from each other are formed at both ends of the second conduction layer 52 ; the second source 71 and the second drain 72 are respectively connected to both ends of the second conduction layer 52 .
  • the dielectric layer 40 does not need to form the second source electrode and the second drain electrode part and the second photoresist layer 701 is formed on the first conduction layer, the first source electrode and a part of the first drain electrode; then the second source electrode 71 and the second drain electrode 72 are respectively formed on both sides of the second conduction layer 52, and the second source electrode 71 and the second drain electrode 72 wrap the sidewall of the second conduction layer 52 and are partially located on the second conduction layer 52; after forming the second source electrode 71 and the second drain electrode 72, remove the second Photoresist layer 701 .
  • the second drain 72 is in contact with the first drain 62 , wraps around the sidewall of the first drain 62 and is partially located on the first drain 62 .
  • the first drain 62 surrounds the sidewall of the second drain 72 and is partially located on the second drain 72 . It should be explained that whether the first drain 62 wraps the sidewall of the second drain 72 or the second drain 72 wraps the sidewall of the first drain 62 , good contact between the first drain 62 and the second drain 72 needs to be ensured.
  • a second metal layer 82 is formed on the first metal layer 81; the material of the second metal layer 82 is the same as that of the second source 71 and the second drain 72.
  • the thickness of the first metal layer 81 is equal to the thickness of the first source 61 and the first drain 62
  • the thickness of the second metal layer 82 is equal to the thickness of the second source 71 . If the thicknesses are equal, the first metal layer and the first source and the first drain, or the second metal layer and the second source can be formed in the same deposition step.
  • the thickness of the first metal layer 81 may not be equal to the thicknesses of the first source 61 and the first drain 62
  • the thickness of the second metal layer 82 may not be equal to the thickness of the second source 71 .
  • the first source 61, the first drain 62, the first conduction layer 51 and part of the gate layer 30 constitute a transistor of the first conductivity type;
  • the second source 71, the second drain 72, the second conduction layer 52 and part of the gate layer 30 constitute a transistor of the second conduction type;
  • the first drain 62 is in contact with the second drain 72, so that the transistor of the first conduction type and the transistor of the second conduction type form an inverter.
  • the gate layer 30 is connected to the first metal layer 81 and the second metal layer 82 , so that the transistors of the first conductivity type and the transistors of the second conductivity type share one gate layer.
  • FIG. 3a is a circuit diagram of an inverter in an embodiment of the present disclosure
  • FIG. 3b is a schematic structural diagram corresponding to an inverter in an embodiment of the present disclosure.
  • the transistor of the first conductivity type is connected to the gate of the transistor of the second conductivity type and used as an input terminal Vin
  • the source of the transistor of the second conductivity type that is, the second source is connected to the power supply voltage VDD
  • the source of the transistor of the first conductivity type that is, the first source is grounded to VSS
  • the transistor of the first conductivity type is connected to the drain of the transistor of the second conductivity type.
  • the poles are connected and used as the output terminal Vout. Specifically, the output terminal is drawn out through the second drain 72.
  • This connection method only occupies a small area and is more conducive to large-scale integration.
  • the transistors of the first conductivity type and the transistors of the second conductivity type share a gate, the integration degree is higher, and because only one gate needs to be fabricated, the required cost is lower.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the transistors of the first conductivity type are NMOS transistors
  • the transistors of the second conductivity type are PMOS transistors.
  • the material of the first source 61 and the first drain 62 includes a low work function material; the material of the second source 71 and the second drain 72 includes a high work function material.
  • the work function of the low work function material is low, and the first conduction layer is matched with the low work function material to form an NMOS transistor; the work function of the high work function material is relatively high, and the second conduction layer is matched with the high work function material to form a PMOS transistor.
  • Both the low work function material and the high work function material are electrode materials.
  • the low work function material includes materials such as Ti, Al, Ag, and Zn
  • the high work function material includes materials such as Au, Pt, C, W, Co, and Ni.
  • the low work function material may be Ti
  • the high work function material may be Au.
  • the method further includes: after forming the second source 71 and the second drain 72, forming a passivation layer 90; the passivation layer 90 covers the exposed surfaces of the first source 61, the first drain 62, the first conduction layer 51, the second source 71, the second drain 72, the second conduction layer 52 and the second metal layer 82.
  • the passivation layer can protect the channel material and prevent the channel material from being oxidized.
  • the passivation layer 90 is a high-K dielectric layer, and the material of the passivation layer 90 includes at least one of dielectric materials such as hafnium dioxide, silicon dioxide or aluminum oxide.
  • the passivation layer 90 can be formed by one or more thin film deposition processes; specifically, the deposition processes include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition

Abstract

本公开实施例公开了一种半导体器件及其制备方法，其中，所述半导体器件，包括：衬底；栅极层，位于所述衬底上；第一导通层和第二导通层，位于所述栅极层上；所述第一导通层和所述第二导通层的材料包括钙钛矿；第一源极和第一漏极，所述第一源极和所述第一漏极相互间隔并分别与所述第一导通层的两端连接；第二源极和第二漏极，所述第二源极和所述第二漏极相互间隔并分别与所述第二导通层的两端连接。

Description

一种半导体器件及其制备方法
相关申请的交叉引用
本申请基于申请号为202210072561.7、申请日为2022年01月21日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及但不限于一种半导体器件及其制备方法。
背景技术
在动态随机存取存储器(DRAM)的制造领域中，随着先进制程技术(10nm节点及以下)的快速发展，并在更快的开关速度和低能耗的需求下，控制硅基MOS器件的短沟道效应(short channel effect，SCE)成为一大难点。
发明内容
有鉴于此，本公开实施例提供一种半导体器件及其制备方法。
根据本公开实施例的第一方面，提供了一种半导体器件，包括：
衬底；
栅极层，位于所述衬底上；
第一导通层和第二导通层，位于所述栅极层上；所述第一导通层和所述第二导通层的材料包括钙钛矿；
第一源极和第一漏极，所述第一源极和所述第一漏极相互间隔并分别与所述第一导通层的两端连接；
第二源极和第二漏极，所述第二源极和所述第二漏极相互间隔并分别与所述第二导通层的两端连接。
在一些实施例中，所述钙钛矿包括无机钙钛矿。
在一些实施例中，所述第一源极、所述第一漏极、所述第一导通层和部分所述栅极层构成第一导电类型的晶体管；
所述第二源极、所述第二漏极、所述第二导通层和部分所述栅极层构成第二导电类型的晶体管；
所述第一漏极与所述第二漏极接触，以使所述第一导电类型的晶体管和所述第二导电类型的晶体管构成反相器。
在一些实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
在一些实施例中，所述第一源极和所述第一漏极的材料包括低功函数材料；所述第二源极和所述第二漏极的材料包括高功函数材料。
在一些实施例中，所述栅极层的材料包括石墨烯。
在一些实施例中，还包括：
介质层，位于所述栅极层上且覆盖部分所述栅极层；
所述栅极层未被所述介质层覆盖的区域形成有层叠的第一金属层和第二金属层；所述第一金属层的材料与所述第一源极和所述第一漏极的材料相同；所述第二金属层的材料与所述第二源极和所述第二漏极的材料相同。
在一些实施例中，还包括：
钝化层，覆盖所述第一源极、所述第一漏极、所述第一导通层、所述第二源极、所述第二漏极、所述第二导通层和所述第二金属层裸露的表面。
根据本公开实施例的第二方面，提供一种半导体器件的制备方法，包括：
提供衬底；
在所述衬底上形成栅极层；
在所述栅极层上形成第一导通层和第二导通层；所述第一导通层和所述第二导通层的材料包括钙钛矿；
在所述第一导通层的两端形成相互间隔的第一源极和第一漏极；所述第一源极和所述第一漏极分别与所述第一导通层的两端连接；
在所述第二导通层的两端形成相互间隔的第二源极和第二漏极；所述第二源极和所述第二漏极分别与所述第二导通层的两端连接。
在一些实施例中，所述钙钛矿包括无机钙钛矿。
在一些实施例中，所述第一源极、所述第一漏极、所述第一导通层和部分所述栅极层构成第一导电类型的晶体管；
所述第二源极、所述第二漏极、所述第二导通层和部分所述栅极层构成第二导电类型的晶体管；
所述第一漏极与所述第二漏极接触，以使所述第一导电类型的晶体管和所述第二导电类型的晶体管构成反相器。
在一些实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
在一些实施例中，所述第一源极和所述第一漏极的材料包括低功函数材料；所述第二源极和所述第二漏极的材料包括高功函数材料。
在一些实施例中，所述栅极层的材料包括石墨烯。
在一些实施例中，还包括：
在形成栅极层后，在所述栅极层上形成覆盖部分所述栅极层的介质层；
在形成所述第一源极和所述第一漏极的同一步骤中，在所述栅极层未被所述介质层覆盖的区域形成第一金属层；所述第一金属层的材料与所述第一源极和所述第一漏极的材料相同；
在形成所述第二源极和所述第二漏极的同一步骤中，在所述第一金属 层上形成第二金属层；所述第二金属层的材料与所述第二源极和所述第二漏极的材料相同。
在一些实施例中，还包括：
在形成第二源极和第二漏极后，形成钝化层；所述钝化层覆盖所述第一源极、所述第一漏极、所述第一导通层、所述第二源极、所述第二漏极、所述第二导通层和所述第二金属层裸露的表面。
本公开实施例中，通过采用钙钛矿材料形成导通层，钙钛矿通过与不同金属接触形成不同型的肖特基结可以省去离子注入的步骤，减少光罩使用，减少工艺步骤，降低成本；同时使用钙钛矿材料，可以抑制SCE效应，且无需额外掺杂，可降低阈值电压，提高饱和电流及器件的可靠性。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体器件的结构示意图；
图2为本公开实施例提供的半导体器件的俯视图；
图3a为本公开实施例中的反相器的电路图；
图3b为与本公开实施例中的反相器相对应的结构示意图；
图4为本公开实施例提供的半导体器件的制备方法的流程示意图；
图5a至5h为本公开实施例提供的半导体器件在制备过程中的结构示意图。
附图标记说明：
10-衬底；20-氧化层；30-栅极层；40-介质层；
51-第一导通层；52-第二导通层；
61-第一源极；62-第一漏极；601-第一光刻胶层；
71-第二源极；72-第二漏极；701-第二光刻胶层；
81-第一金属层；82-第二金属层；
90-钝化层。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或 部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
在一些实施例中，主要采用晕环(Halo)与轻掺杂漏(LDD)掺杂技术降低SCE。晕环离子注入的深度大于轻掺杂漏离子注入的深度，从而有 效降低源区和漏区的耗尽区往横向扩展，防止源漏穿通现象。然而多种掺杂技术不仅需要高的制造成本，更增加了器件可靠性的问题，如硼的瞬间增强扩散，PN结漏电和负偏置温度不稳定性(NBTI)等。超薄体(Ultra-thin-body，UTB)作为一种有效减少SCE的手段，使栅极能更好的进行器件的调节。在UTB器件中，沟道的厚度一般需要控制在栅极长度的1/3。然而在10nm节点以下，原子尺寸的厚度的不均匀性会增大表面势的变化，导致载流子库伦散射增强，降低了载流子迁移率，进而降低饱和电流。
基于此，本公开实施例提供了一种半导体器件，图1为本公开实施例提供的半导体器件的结构示意图，图2为本公开实施例提供的半导体器件的俯视图。需要说明的是，图2中的俯视图是在去除钝化层90后得到的俯视图。
参见图1和图2，所述半导体器件，包括：衬底10；栅极层30，位于所述衬底10上；第一导通层51和第二导通层52，位于所述栅极层30上；所述第一导通层51和所述第二导通层52的材料包括钙钛矿；第一源极61和第一漏极62，所述第一源极61和所述第一漏极62相互间隔并分别与所述第一导通层51的两端连接；第二源极71和第二漏极72，所述第二源极71和所述第二漏极72相互间隔并分别与所述第二导通层52的两端连接。
在本公开实施例中，通过采用钙钛矿材料形成导通层，钙钛矿通过与不同金属接触形成不同型的肖特基结可以省去离子注入的步骤，减少光罩使用，减少工艺步骤，降低成本；同时使用钙钛矿材料，可以抑制SCE效应，且无需额外掺杂，可降低阈值电压，提高饱和电流及器件的可靠性。
在一实施例中，所述衬底10可以为单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底，或石英、蓝 宝石衬底等。
所述半导体器件还包括：氧化层20，位于所述衬底10上。所述氧化层20的材料包括但不限于二氧化硅。
所述氧化层20可以为栅极氧化层，氧化层位于栅极层30和衬底10之间，可以为栅极层30和位于其下方的衬底10提供足够的电学绝缘，以防栅极层30与衬底10发生短路。
在一实施例中，所述栅极层30，位于所述衬底10上。具体地，所述栅极层30位于所述氧化层20上。
在一些实施例中，所述栅极层30的材料可以包括石墨烯。使用石墨烯作为栅极层30的材料，可降低金属电极造成的电介质层污染以及避免高温退火时造成的器件电性退化。
在其他一些实施例中，所述栅极层30也可使用常规金属电极材料，但需要保证该常规金属电极材料在退火的工艺中不会对钙钛矿材料产生损伤。
所述半导体器件还包括：介质层40，位于所述栅极层30上且覆盖部分所述栅极层30。
所述介质层40位于栅极层和位于其上方的第一导通层、第二导通层以及第一源极、第一漏极、第二源极和第二漏极之间，可以起到绝缘隔离的作用，以防栅极层和导通层以及源/漏极之间发生短路。
所述介质层40为高K介质层。所述介质层40的材料包括二氧化铪、二氧化硅或氧化铝等介电材料中的至少一种。
第一导通层51和第二导通层52，位于所述栅极层30上；具体地，所述第一导通层51和所述第二导通层52，位于所述介质层40上。
在一实施例中，所述钙钛矿包括无机钙钛矿。无机钙钛矿材料具有高载流子迁移率、稳定性强、制备方法简单等优点。此外，无机钙钛矿材料 无需进行离子注入，可通过与不同功函数的金属接触即可形成P型或N型场效应管(Field Effect Transistor，FET)。例如，无机钙钛矿材料与不同金属接触时，其价带与高功函数金属匹配形成P型FET，其导带与低功函数金属匹配形成N型FET，显示出其可以作为DRAM中MOS器件的完美组成部分。因此，使用无机钙钛矿材料制作导通层，能更好的降低阈值电压，提高饱和电流，进而提高器件的可靠性，且因为省去了离子注入的步骤，因此减少了工艺步骤，降低了成本。
在一些实施例中，所述无机钙钛矿包括CsPbBr xI 3-x，其中，0<x<3。CsPbBr xI 3-x(0<x<3)作为尺寸小于1nm的超薄沟道(channel)，可以抑制尺寸缩小导致的硅基MOS器件的SCE效应，且无需额外掺杂，可降低阈值电压，提高饱和电流及器件的可靠性。
在其他一些实施例中，Cs可替换成Rb或Fr，Pb可替换成Sn，Br和I可替换成Cl。
在一实施例中，所述第一导通层51和所述第二导通层52的靠近所述介质层40的一面上形成有反型层(图中未示出)，所述反型层构成导电沟道，是器件导通的原因。
在一实施例中，所述半导体器件还包括：第一源极61和第一漏极62，所述第一源极61和所述第一漏极62相互间隔并分别与所述第一导通层51的两端连接；第二源极71和第二漏极72，所述第二源极71和所述第二漏极72相互间隔并分别与所述第二导通层52的两端连接。
所述第一源极61、所述第一漏极62、所述第二源极71和所述第二漏极72均位于所述介质层40上。
所述第一源极61和所述第一漏极62分别位于所述第一导通层51的两端，包裹所述第一导通层51的侧壁且部分位于所述第一导通层51上。
所述第二源极71和所述第二漏极72分别位于所述第二导通层52的两 端，包裹所述第二导通层52的侧壁且部分位于所述第二导通层52上。
在一些实施例中，所述第二漏极72与所述第一漏极62接触，包裹所述第一漏极62的侧壁且部分位于所述第一漏极62上。
在其他一些实施例中，所述第一漏极62包裹所述第二漏极72的侧壁且部分位于所述第二漏极72上。需要解释的是，无论是所述第一漏极62包裹所述第二漏极72的侧壁，还是所述第二漏极72包裹所述第一漏极62的侧壁，都需要保证第一漏极62与第二漏极72之间的良好接触。
在一实施例中，所述第一源极61、所述第一漏极62、所述第一导通层51和部分所述栅极层30构成第一导电类型的晶体管；所述第二源极71、所述第二漏极72、所述第二导通层52和部分所述栅极层30构成第二导电类型的晶体管；所述第一漏极62与所述第二漏极72接触，以使所述第一导电类型的晶体管和所述第二导电类型的晶体管构成反相器。
图3a为本公开实施例中的反相器的电路图，图3b为与本公开实施例中的反相器相对应的结构示意图，如图3a和图3b所示，所述第一导电类型的晶体管和所述第二导电类型的晶体管的栅极相连并作为输入端Vin，所述第二导电类型的晶体管的源极，即第二源极接电源电压VDD，所述第一导电类型的晶体管的源极，即第一源极接地VSS，所述第一导电类型的晶体管与所述第二导电类型的晶体管的漏极相连并作为输出端Vout，具体地，输出端通过第二漏极72引出，这样的连接方式仅占用很小的面积，更有利于大规模集成。
本实施例中，所述第一导电类型的晶体管和所述第二导电类型的晶体管共用一个栅极，集成度更高，且因只需要制作一个栅极，所需花费的成本更低。
在一实施例中，所述第一导电类型为N型，所述第二导电类型为P型。即所述第一导电类型的晶体管为NMOS晶体管，第二导电类型的晶体管为 PMOS晶体管。
在一实施例中，所述第一源极61和所述第一漏极62的材料包括低功函数材料；所述第二源极71和所述第二漏极72的材料包括高功函数材料。低功函数材料的功函数较低，第一导通层51与低功函数材料匹配形成NMOS晶体管；高功函数材料的功函数较高，第二导通层52与高功函数材料匹配形成PMOS晶体管。所述低功函数材料和所述高功函数材料均为电极材料。
具体地，所述低功函数材料包括Ti、Al、Ag和Zn等材料，所述高功函数材料包括Au、Pt、C、W、Co和Ni等材料。在本公开实施例中，所述低功函数材料可以为Ti，所述高功函数材料可以为Au。
在一实施例中，所述栅极层30未被所述介质层40覆盖的区域形成有层叠的第一金属层81和第二金属层82；所述第一金属层81的材料与所述第一源极61和所述第一漏极62的材料相同；所述第二金属层82的材料与所述第二源极71和所述第二漏极72的材料相同。栅极层30通过与第一金属层81和第二金属层82连接，使得PMOS晶体管和NMOS晶体管共用一个栅极层。
在一些实施例中，所述第一金属层81的厚度与所述第一源极61和所述第一漏极62的厚度相等，所述第二金属层82的厚度与所述第二源极71的厚度相等。所述厚度相等，则可以在同一沉积步骤中形成第一金属层和第一源极以及第一漏极，或者第二金属层和第二源极。
在其他一些实施例中，所述第一金属层81的厚度与所述第一源极61和所述第一漏极62的厚度可以不相等，所述第二金属层82的厚度与所述第二源极71的厚度也可以不相等。
在一实施例中，所述半导体器件还包括：钝化层90，覆盖所述第一源极61、所述第一漏极62、所述第一导通层51、所述第二源极71、所述第 二漏极72、所述第二导通层52和所述第二金属层82裸露的表面。钝化层90可对沟道材料进行保护，防止沟道材料氧化。
所述钝化层90为高K介质层，所述钝化层90的材料包括二氧化铪、二氧化硅或氧化铝等介电材料中的至少一种。
本公开实施例还提供了一种半导体器件的制备方法，具体请参见附图4，如图所示，所述方法包括以下步骤：
步骤401：提供衬底；
步骤402：在所述衬底上形成栅极层；
步骤403：在所述栅极层上形成第一导通层和第二导通层；所述第一导通层和所述第二导通层的材料包括钙钛矿；
步骤404：在所述第一导通层的两端形成相互间隔的第一源极和第一漏极；所述第一源极和所述第一漏极分别与所述第一导通层的两端连接；
步骤405：在所述第二导通层的两端形成相互间隔的第二源极和第二漏极；所述第二源极和所述第二漏极分别与所述第二导通层的两端连接。
下面结合具体实施例对本公开实施例提供的半导体器件的制备方法再作进一步详细的说明。
图5a至5h为本公开实施例提供的半导体器件在制备过程中的结构示意图。
首先，参见图5a，执行步骤401。提供衬底10。
所述衬底10可以为单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底，或石英、蓝宝石衬底等。
继续参见图5a，在所述衬底10上形成氧化层20。所述氧化层20的材料包括但不限于二氧化硅。
所述氧化层20可以为栅极氧化层，氧化层位于栅极层30和衬底10之 间，可以为栅极层30和位于其下方的衬底10提供足够的电学绝缘，以防栅极层30与衬底10发生短路。
接着，参见图5b，执行步骤402。在所述衬底10上形成栅极层30。具体地，在所述氧化层20上形成栅极层30。
在实际操作中，可以使用湿法转移或其他沉积工艺形成栅极层30，所述沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
在一些实施例中，所述栅极层30的材料可以包括石墨烯。使用石墨烯作为栅极层30的材料，可降低金属电极造成的电介质层污染以及避免高温退火时造成的器件电性退化。
在其他一些实施例中，所述栅极层30也可使用常规金属电极材料，但需要保证该常规金属电极在退火的工艺中不会对钙钛矿产生损伤。
接着，参见图5c，所述方法还包括：在形成栅极层30后，在所述栅极层30上形成覆盖部分所述栅极层30的介质层40。
所述介质层40位于栅极层和位于其上方的第一导通层、第二导通层以及第一源极、第一漏极、第二源极和第二漏极之间，可以起到绝缘隔离的作用，以防栅极层和导通层以及源/漏极之间发生短路。
在实际操作中，所述介质层40可以通过一种或多种薄膜沉积工艺形成；具体地，所述沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
所述介质层40为高K介质层。所述介质层40的材料包括二氧化铪、二氧化硅或氧化铝等介电材料中的至少一种。
接着，参见图5d和图5e，执行步骤403。在所述栅极层30上形成第一导通层51和第二导通层52；所述第一导通层51和所述第二导通层52的材料包括钙钛矿。具体地，在所述介质层40上形成第一导通层51和第二 导通层52。
在实际操作中，先参见图5d，在所述介质层40上形成一层覆盖所述介质层40的导通层预层50。
所述导通层预层50可以通过电子束蒸发或刮涂等工艺沉积形成，也可以通过一种或多种薄膜沉积工艺形成；具体地，所述沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
接着，参见图5e，将所述导通层预层50刻蚀形成第一导通层51和第二导通层52。
具体地，可以先在介质层40的上表面生长一层掩模层，接着对该掩模层进行图案化，以在掩模层上显示出要刻蚀掉的除第一导通层和第二导通层以外的图形，可以通过光刻工艺对该掩模层进行图案化。该掩模层可以是光致抗蚀剂掩模或者基于光刻掩模进行图案化的硬掩模；当该掩模层是光致抗蚀剂掩模时，具体通过曝光、显影和去胶等步骤对该掩模层进行图案化。接着按照要刻蚀的图形刻蚀掉要去除的导通层预层，形成第一导通层和第二导通层。
所述刻蚀工艺可以为干法刻蚀或湿法刻蚀，具体地，所述刻蚀工艺可以为反应离子刻蚀(RIE)工艺或等离子刻蚀(Plasma Etching)工艺等。
在一实施例中，所述钙钛矿包括无机钙钛矿。无机钙钛矿材料具有高载流子迁移率、稳定性强、制备方法简单等优点。此外，无机钙钛矿材料无需进行离子注入，可通过与不同功函数的金属接触即可形成P型或N型场效应管(Field Effect Transistor，FET)。例如，无机钙钛矿材料与不同金属接触时，其价带与高功函数金属匹配形成P型FET，其导带与低功函数金属匹配形成N型FET，显示出其可以作为DRAM中MOS器件的完美组成部分。因此，使用无机钙钛矿材料制作导通层，能更好的降低阈值电压， 提高饱和电流，进而提高器件的可靠性，且因为省去了离子注入的步骤，因此减少了工艺步骤，降低了成本。
在一些实施例中，所述无机钙钛矿包括CsPbBr xI 3-x，其中，0<x<3。CsPbBr xI 3-x(0<x<3)作为尺寸小于1nm的超薄沟道(channel)，可以抑制尺寸缩小导致的硅基MOS器件的SCE效应，且无需额外掺杂，可降低阈值电压，提高饱和电流及器件的可靠性。
在其他一些实施例中，Cs可替换成Rb或Fr，Pb可替换成Sn，Br和I可替换成Cl。
在一实施例中，所述第一导通层51和所述第二导通层52的靠近所述介质层40的一面上形成有反型层(图中未示出)，所述反型层构成导电沟道，是器件导通的原因。
接着，参见图5f，执行步骤404。在所述第一导通层51的两端形成相互间隔的第一源极61和第一漏极62；所述第一源极61和所述第一漏极62分别与所述第一导通层51的两端连接。
具体地，在所述介质层40无需形成第一源极和第一漏极的部分以及第二导通层上形成第一光刻胶层601；接着在所述第一导通层51的两侧分别形成第一源极61和第一漏极62，所述第一源极61和所述第一漏极62包裹所述第一导通层51的侧壁且部分位于所述第一导通层51上；在形成第一源极61和第一漏极62后，去除所述第一光刻胶层601。
继续参见图5f，在形成所述第一源极61和所述第一漏极62的同一步骤中，在所述栅极层30未被所述介质层40覆盖的区域形成第一金属层81；所述第一金属层81的材料与所述第一源极61和所述第一漏极62的材料相同。
接着，参见图5g，执行步骤405。在所述第二导通层52的两端形成相互间隔的第二源极71和第二漏极72；所述第二源极71和所述第二漏极72 分别与所述第二导通层52的两端连接。
具体地，所述介质层40无需形成第二源极和第二漏极的部分以及第一导通层、第一源极和部分第一漏极上形成第二光刻胶层701；接着在所述第二导通层52的两侧分别形成第二源极71和第二漏极72，所述第二源极71和所述第二漏极72包裹所述第二导通层52的侧壁且部分位于所述第二导通层52上；在形成第二源极71和第二漏极72后，去除第二光刻胶层701。
在一些实施例中，所述第二漏极72与所述第一漏极62接触，包裹所述第一漏极62的侧壁且部分位于所述第一漏极62上。
在其他一些实施例中，所述第一漏极62包裹所述第二漏极72的侧壁且部分位于所述第二漏极72上。需要解释的是，无论是所述第一漏极62包裹所述第二漏极72的侧壁，还是所述第二漏极72包裹所述第一漏极62的侧壁，都需要保证第一漏极62与第二漏极72之间的良好接触。
继续参见图5g，在形成所述第二源极71和所述第二漏极72的同一步骤中，在所述第一金属层81上形成第二金属层82；所述第二金属层82的材料与所述第二源极71和所述第二漏极72的材料相同。
在一些实施例中，所述第一金属层81的厚度与所述第一源极61和所述第一漏极62的厚度相等，所述第二金属层82的厚度与所述第二源极71的厚度相等。所述厚度相等，则可以在同一沉积步骤中形成第一金属层和第一源极以及第一漏极，或者第二金属层和第二源极。
在其他一些实施例中，所述第一金属层81的厚度与所述第一源极61和所述第一漏极62的厚度可以不相等，所述第二金属层82的厚度与所述第二源极71的厚度也可以不相等。
在一实施例中，所述第一源极61、所述第一漏极62、所述第一导通层51和部分所述栅极层30构成第一导电类型的晶体管；所述第二源极71、所述第二漏极72、所述第二导通层52和部分所述栅极层30构成第二导电 类型的晶体管；所述第一漏极62与所述第二漏极72接触，以使所述第一导电类型的晶体管和所述第二导电类型的晶体管构成反相器。在本公开实施例中，所述栅极层30通过与第一金属层81和第二金属层82连接，使得第一导电类型的晶体管和第二导电类型的晶体管共用一个栅极层。
图3a为本公开实施例中的反相器的电路图，图3b为与本公开实施例中的反相器相对应的结构示意图，如图3a和图3b所示，所述第一导电类型的晶体管和所述第二导电类型的晶体管的栅极相连并作为输入端Vin，所述第二导电类型的晶体管的源极，即第二源极接电源电压VDD，所述第一导电类型的晶体管的源极，即第一源极接地VSS，所述第一导电类型的晶体管与所述第二导电类型的晶体管的漏极相连并作为输出端Vout，具体地，输出端通过第二漏极72引出，这样的连接方式仅占用很小的面积，更有利于大规模集成。
本实施例中，所述第一导电类型的晶体管和所述第二导电类型的晶体管共用一个栅极，集成度更高，且因只需要制作一个栅极，所需花费的成本更低。
在一实施例中，所述第一导电类型为N型，所述第二导电类型为P型。即所述第一导电类型的晶体管为NMOS晶体管，第二导电类型的晶体管为PMOS晶体管。
在一实施例中，所述第一源极61和所述第一漏极62的材料包括低功函数材料；所述第二源极71和所述第二漏极72的材料包括高功函数材料。低功函数材料的功函数较低，第一导通层与低功函数材料匹配形成NMOS晶体管；高功函数材料的功函数较高，第二导通层与高功函数材料匹配形成PMOS晶体管。所述低功函数材料和所述高功函数材料均为电极材料。
具体地，所述低功函数材料包括Ti、Al、Ag和Zn等材料，所述高功函数材料包括Au、Pt、C、W、Co和Ni等材料。在本公开实施例中，所述 低功函数材料可以为Ti，所述高功函数材料可以为Au。
接着，参见图5h，所述方法还包括：在形成第二源极71和第二漏极72后，形成钝化层90；所述钝化层90覆盖所述第一源极61、所述第一漏极62、所述第一导通层51、所述第二源极71、所述第二漏极72、所述第二导通层52和所述第二金属层82裸露的表面。钝化层可对沟道材料进行保护，防止沟道材料氧化。
所述钝化层90为高K介质层，所述钝化层90的材料包括二氧化铪、二氧化硅或氧化铝等介电材料中的至少一种。
在实际操作中，所述钝化层90可以通过一种或多种薄膜沉积工艺形成；具体地，所述沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种半导体器件，包括：
    衬底；
    栅极层，位于所述衬底上；
    第一导通层和第二导通层，位于所述栅极层上；所述第一导通层和所述第二导通层的材料包括钙钛矿；
    第一源极和第一漏极，所述第一源极和所述第一漏极相互间隔并分别与所述第一导通层的两端连接；
    第二源极和第二漏极，所述第二源极和所述第二漏极相互间隔并分别与所述第二导通层的两端连接。
  2. 根据权利要求1所述的半导体器件，其中，
    所述钙钛矿包括无机钙钛矿。
  3. 根据权利要求1所述的半导体器件，其中，
    所述第一源极、所述第一漏极、所述第一导通层和部分所述栅极层构成第一导电类型的晶体管；
    所述第二源极、所述第二漏极、所述第二导通层和部分所述栅极层构成第二导电类型的晶体管；
    所述第一漏极与所述第二漏极接触，以使所述第一导电类型的晶体管和所述第二导电类型的晶体管构成反相器。
  4. 根据权利要求3所述的半导体器件，其中，
    所述第一导电类型为N型，所述第二导电类型为P型。
  5. 根据权利要求4所述的半导体器件，其中，
    所述第一源极和所述第一漏极的材料包括低功函数材料；
    所述第二源极和所述第二漏极的材料包括高功函数材料。
  6. 根据权利要求1所述的半导体器件，其中，
    所述栅极层的材料包括石墨烯。
  7. 根据权利要求1所述的半导体器件，还包括：
    介质层，位于所述栅极层上且覆盖部分所述栅极层；
    所述栅极层未被所述介质层覆盖的区域形成有层叠的第一金属层和第二金属层；所述第一金属层的材料与所述第一源极和所述第一漏极的材料相同；所述第二金属层的材料与所述第二源极和所述第二漏极的材料相同。
  8. 根据权利要求7所述的半导体器件，还包括：
    钝化层，覆盖所述第一源极、所述第一漏极、所述第一导通层、所述第二源极、所述第二漏极、所述第二导通层和所述第二金属层裸露的表面。
  9. 一种半导体器件的制备方法，包括：
    提供衬底；
    在所述衬底上形成栅极层；
    在所述栅极层上形成第一导通层和第二导通层；所述第一导通层和所述第二导通层的材料包括钙钛矿；
    在所述第一导通层的两端形成相互间隔的第一源极和第一漏极；所述第一源极和所述第一漏极分别与所述第一导通层的两端连接；
    在所述第二导通层的两端形成相互间隔的第二源极和第二漏极；所述第二源极和所述第二漏极分别与所述第二导通层的两端连接。
  10. 根据权利要求9所述的方法，其中，
    所述钙钛矿包括无机钙钛矿。
  11. 根据权利要求9所述的方法，其中，
    所述第一源极、所述第一漏极、所述第一导通层和部分所述栅极层构成第一导电类型的晶体管；
    所述第二源极、所述第二漏极、所述第二导通层和部分所述栅极层构 成第二导电类型的晶体管；
    所述第一漏极与所述第二漏极接触，以使所述第一导电类型的晶体管和所述第二导电类型的晶体管构成反相器。
  12. 根据权利要求11所述的方法，其中，
    所述第一导电类型为N型，所述第二导电类型为P型。
  13. 根据权利要求12所述的方法，其中，
    所述第一源极和所述第一漏极的材料包括低功函数材料；
    所述第二源极和所述第二漏极的材料包括高功函数材料。
  14. 根据权利要求9所述的方法，其中，
    所述栅极层的材料包括石墨烯。
  15. 根据权利要求9所述的方法，还包括：
    在形成栅极层后，在所述栅极层上形成覆盖部分所述栅极层的介质层；
    在形成所述第一源极和所述第一漏极的同一步骤中，在所述栅极层未被所述介质层覆盖的区域形成第一金属层；所述第一金属层的材料与所述第一源极和所述第一漏极的材料相同；
    在形成所述第二源极和所述第二漏极的同一步骤中，在所述第一金属层上形成第二金属层；所述第二金属层的材料与所述第二源极和所述第二漏极的材料相同。
  16. 根据权利要求15所述的方法，还包括：
    在形成第二源极和第二漏极后，形成钝化层；所述钝化层覆盖所述第一源极、所述第一漏极、所述第一导通层、所述第二源极、所述第二漏极、所述第二导通层和所述第二金属层裸露的表面。
PCT/CN2022/078648 2022-01-21 2022-03-01 一种半导体器件及其制备方法 WO2023137831A1 (zh)

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