WO2023135931A1 - 多層基板 - Google Patents

多層基板 Download PDF

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Publication number
WO2023135931A1
WO2023135931A1 PCT/JP2022/042723 JP2022042723W WO2023135931A1 WO 2023135931 A1 WO2023135931 A1 WO 2023135931A1 JP 2022042723 W JP2022042723 W JP 2022042723W WO 2023135931 A1 WO2023135931 A1 WO 2023135931A1
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WO
WIPO (PCT)
Prior art keywords
insulator layer
conductor
interlayer connection
region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/042723
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English (en)
French (fr)
Japanese (ja)
Inventor
恒亮 西尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to CN202290000759.8U priority Critical patent/CN221807328U/zh
Priority to JP2023573870A priority patent/JP7626252B2/ja
Publication of WO2023135931A1 publication Critical patent/WO2023135931A1/ja
Priority to US18/651,724 priority patent/US20240292535A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0141—Liquid crystal polymer [LCP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias

Definitions

  • the present invention relates to a multilayer substrate provided with interlayer connection conductors.
  • the flex board described in Patent Document 1 As an invention related to conventional multilayer boards, for example, the flex board described in Patent Document 1 is known.
  • the flex board has a rigid portion and a flex portion.
  • the number of laminations of the rigid portion is greater than the number of laminations of the flex portion.
  • the thickness of the rigid portion is greater than the thickness of the flex.
  • the rigid section is less likely to deform than the flex section.
  • an object of the present invention is to provide a multilayer substrate that can suppress the occurrence of disconnection in the laminate.
  • a multilayer substrate according to one aspect of the present invention comprises One of the vertical directions is the first direction, the other of the vertical directions is the second direction, and the first insulator layer, the second insulator layer, and the third insulator layer are laminated in this order in the second direction.
  • a laminate having a structure which includes a first region in which the first insulator layer, the second insulator layer, and the third insulator layer are present when viewed in the vertical direction, and a laminate having a second region in which the first insulator layer and the third insulator layer are present and the second insulator layer is not present, each of the first insulator layer to the third insulator layer has a first main surface positioned in the first direction and a second main surface positioned in the second direction; a plurality of interlayer connection conductors provided in the laminate; a conductor provided on the first insulator layer; a second conductor layer located on the second main surface of the third insulator layer; and The plurality of interlayer connection conductors are located in the first region and have at least one conductor vertically penetrating through any one of the first insulator layer, the second insulator layer, and the third insulator layer.
  • first interlayer connection conductor and a second interlayer connection conductor positioned in the second region and vertically penetrating the third insulator layer, the second interlayer connection conductor is joined to the conductor and joined to the second conductor layer,
  • the area of the second interlayer connection conductor viewed in the vertical direction is larger than the minimum value among the areas of the one or more first interlayer connection conductors viewed in the vertical direction.
  • the multilayer substrate of the present invention it is possible to suppress the occurrence of disconnection in the laminate.
  • FIG. 1 is a cross-sectional view of a multilayer substrate 10.
  • FIG. FIG. 2 is a cross-sectional view of the multilayer substrate 10 before thermocompression bonding.
  • FIG. 3 is a cross-sectional view of the multilayer substrate 10a.
  • FIG. 4 is a cross-sectional view of the multilayer substrate 10a before thermocompression bonding.
  • FIG. 5 is a cross-sectional view of the multilayer substrate 10b.
  • FIG. 6 is a cross-sectional view of the multilayer substrate 10b before thermocompression bonding.
  • FIG. 7 is a cross-sectional view of the multilayer substrate 10c.
  • FIG. 8 is a cross-sectional view of the multilayer substrate 10c before thermocompression bonding.
  • FIG. 1 is a cross-sectional view of a multilayer substrate 10.
  • FIG. 2 is a cross-sectional view of the multilayer substrate 10 before thermocompression bonding.
  • FIG. 3 is a cross-sectional view of the multilayer substrate
  • FIG. 9 is a sectional view when the multilayer substrate 10c is folded.
  • FIG. 10 is a cross-sectional view of the multilayer substrate 10d.
  • FIG. 11 is a cross-sectional view of the multilayer substrate 10e and a top view of the insulator layer 16e and the conductor layer 18e.
  • FIG. 1 is a cross-sectional view of a multilayer substrate 10.
  • FIG. 2 is a cross-sectional view of the multilayer substrate 10 before thermocompression bonding.
  • the stacking direction of the laminate 12 of the multilayer substrate 10 is the vertical direction.
  • One of the vertical directions (upward direction) is the first direction.
  • the other of the vertical directions (downward direction) is the second direction.
  • the direction in which the first area A1 and the second area A2 are arranged is defined as the horizontal direction.
  • a direction orthogonal to the up-down direction and the left-right direction is defined as the front-rear direction.
  • the up-down direction, the front-rear direction, and the left-right direction are orthogonal to each other.
  • the vertical direction, the front-rear direction, and the left-right direction in this specification do not have to correspond to the vertical direction, the front-rear direction, and the left-right direction when the multilayer substrate 10 is actually used.
  • the multilayer board 10 is a flexible board used for electrically connecting two circuit boards in an electronic device such as a smart phone.
  • the multilayer substrate 10 includes a laminate 12, conductor layers 18a to 18e, and a plurality of interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, ve2.
  • the laminate 12 has a plate shape, as shown in FIG. Therefore, the laminated body 12 has an upper principal surface and a lower principal surface which are aligned in the vertical direction.
  • the laminate 12 has flexibility.
  • the laminate 12 includes insulator layers 16a to 16e (insulator layer 16c is the first insulator layer, insulator layer 16d is the second insulator layer, insulator layer 16e is the third insulator layer). Insulator layers) are laminated in this order downward (second direction).
  • Each of the insulator layers 16a to 16e (the insulator layer 16c is the first insulator layer, the insulator layer 16d is the second insulator layer, and the insulator layer 16e is the third insulator layer) extends upward (first direction). ) and a lower main surface (second main surface) positioned downward (second direction).
  • the laminate 12 has a first area A1 and a second area A2.
  • the first region A1 includes an insulator layer 16c (first insulator layer), an insulator layer 16d (second insulator layer), and an insulator layer 16e (third insulator layer) when viewed in the vertical direction. It is an area where The second region A2 includes an insulator layer 16c (first insulator layer) and an insulator layer 16e (third insulator layer) when viewed in the vertical direction, and an insulator layer 16d (second insulator layer). Insulator layer) is not present.
  • the first area A1 is positioned to the left of the second area A2.
  • the first area A1 and the second area A2 are in contact with each other.
  • the insulator layer 16d exists in the first area A1, and the insulator layer 16d does not exist in the second area A2. Therefore, the vertical thickness T1 of the laminate 12 in the first area A1 is greater than the vertical thickness T2 of the laminate 12 in the second area A2. Furthermore, the laminate 12 has a boundary area B1 including a boundary B between the first area A1 and the second area A2. The vertical thickness of the laminate 12 in the boundary region B1 decreases in the direction (rightward direction) from the first region A1 toward the second region A2. The vertical thickness of the laminate 12 in the boundary region B1 varies continuously.
  • the insulator layers 16a to 16e are dielectric sheets having flexibility.
  • the material of the insulator layers 16a to 16e is resin.
  • the material of the insulator layers 16a to 16e is thermoplastic resin. Therefore, the material of the insulator layer 16c (first insulator layer), the material of the insulator layer 16d (second insulator layer), and the material of the insulator layer 16e (third insulator layer) are the same thermoplastic resin. is.
  • the thermoplastic resin is, for example, liquid crystal polymer, PTFE (polytetrafluoroethylene), or the like.
  • the material of the insulator layers 16a to 16e may be polyimide.
  • the insulator layers 16a to 16e are welded together vertically adjacent to each other.
  • the conductor layers 18 a to 18 e are provided (in/on) on the laminate 12 .
  • the conductor layers 18a to 18e (first conductor layer and second conductor layer) have an upper major surface (third major surface) located upward (first direction) and located downward (second direction). It has a lower main surface (fourth main surface). More specifically, the conductor layer 18a is located on the upper major surface of the insulator layer 16a. The surface roughness of the lower main surface of the conductor layer 18a is greater than the surface roughness of the upper main surface of the conductor layer 18a. Thereby, the conductor layer 18a is fixed to the insulator layer 16a.
  • the conductor layer 18b is located on the lower main surface of the insulator layer 16b.
  • the surface roughness of the upper main surface of the conductor layer 18b is greater than the surface roughness of the lower main surface of the conductor layer 18b. Thereby, the conductor layer 18b is fixed to the insulator layer 16b. The conductor layer 18b is also adhered to the insulator layer 16c. However, the strength with which the conductor layer 18b adheres to the insulator layer 16b is greater than the strength with which the conductor layer 18b adheres to the insulator layer 16c.
  • the conductor layer 18c (conductor) is provided on the insulator layer 16c (first insulator layer). More specifically, the conductor layer 18c (second conductor layer) is located on the lower main surface (second main surface) of the insulator layer 16c (first insulator layer).
  • the surface roughness of the upper main surface (third main surface) of the conductor layer 18c (second conductor layer) is greater than the surface roughness of the lower main surface (fourth main surface) of the conductor layer 18c (second conductor layer).
  • the conductor layer 18c is fixed to the insulator layer 16c.
  • the conductor layer 18c also adheres to the insulator layers 16d and 16e.
  • the strength with which the conductor layer 18c adheres to the insulator layer 16c is greater than the strength with which the conductor layer 18c adheres to the insulator layers 16d and 16e.
  • the conductor layer 18d is located on the lower main surface of the insulator layer 16d.
  • the surface roughness of the upper main surface of the conductor layer 18d is greater than the surface roughness of the lower main surface of the conductor layer 18d. Thereby, the conductor layer 18d is fixed to the insulator layer 16d. The conductor layer 18d also adheres to the insulator layer 16e. However, the strength with which the conductor layer 18d adheres to the insulator layer 16d is greater than the strength with which the conductor layer 18d adheres to the insulator layer 16e.
  • the conductor layer 18e (first conductor layer) is located on the lower main surface (fourth main surface) of the insulator layer 16e (third insulator layer).
  • the surface roughness of the upper main surface (third main surface) of the conductor layer 18e (first conductor layer) is greater than the surface roughness of the lower main surface (fourth main surface) of the conductor layer 18e (first conductor layer). Thereby, the conductor layer 18e is fixed to the insulator layer 16e.
  • the conductor layers 18a to 18c, 18e as described above are located in both the first area A1 and the second area A2.
  • the conductor layer 18d is located in the first area A1 and not located in the second area A2.
  • the conductor layers 18a to 18e are signal lines, ground lines, ground conductors, power lines, floating conductors, signal electrodes, ground electrodes, and the like.
  • the material of the conductor layers 18a to 18e as described above is metal.
  • the material of the conductor layers 18a-18e is, for example, copper.
  • a plurality of interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, ve2 are provided in the laminate 12.
  • the interlayer connection conductor va1 is located in the first region A1 and vertically penetrates the insulator layer 16a.
  • the two interlayer connection conductors va2 are located in the second region A2 and penetrate the insulator layer 16a in the vertical direction.
  • the interlayer connection conductor vb1 is located in the first region A1 and vertically penetrates the insulator layer 16b.
  • the two interlayer connection conductors vb2 are located in the second region A2 and penetrate the insulator layer 16b in the vertical direction.
  • the interlayer connection conductor vc1 (first interlayer connection conductor) is located in the first region A1 and vertically penetrates the insulator layer 16c (first insulator layer).
  • the two interlayer connection conductors vc2 (fourth interlayer connection conductors) are located in the second region A2 and vertically penetrate the insulator layer 16c (first insulator layer).
  • the two interlayer connection conductors vd1 (first interlayer connection conductors) are located in the first region A1 and vertically penetrate the insulator layer 16d (second insulator layer).
  • the interlayer connection conductor ve1 (first interlayer connection conductor/third interlayer connection conductor) is located in the first region A1 and vertically penetrates the insulator layer 16e (third insulator layer).
  • the interlayer connection conductor ve2 (second interlayer connection conductor) is located in the second region A2 and vertically penetrates the insulator layer 16e (third insulator layer).
  • the interlayer connection conductor va1 is joined to the conductor layer 18a and the interlayer connection conductor vb1.
  • the interlayer connection conductor va2 is joined to the conductor layer 18a and the interlayer connection conductor vb2.
  • the interlayer connection conductor vb1 is joined to the conductor layer 18b and the interlayer connection conductor va1.
  • the interlayer connection conductor vb2 is joined to the conductor layer 18b and the interlayer connection conductor va2.
  • the interlayer connection conductor vc1 is joined to the conductor layers 18b and 18c.
  • the interlayer connection conductor vc2 (fourth interlayer connection conductor) is joined to the conductor layer 18b and the conductor layer 18c (second conductor layer).
  • the interlayer connection conductor vd1 is joined to the conductor layers 18c and 18d.
  • the interlayer connection conductor ve1 (third interlayer connection conductor) is joined to the conductor layers 18d and 18e.
  • the interlayer connection conductor ve2 (second interlayer connection conductor) is joined to the conductor layer 18c (conductor/second conductor layer) and the conductor layer 18e (first conductor layer).
  • the through holes penetrating vertically through the insulating layers 16a to 16e are filled with a conductive paste. It is formed by solidifying the conductive paste by heating and pressurizing.
  • a conductive paste is a mixture of resin and metal.
  • metal is contained in the plurality of interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, and ve2 after solidification, and resin remains.
  • the plurality of interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, ve2 are made of the same material. Therefore, the material of the interlayer connection conductor ve2 (second interlayer connection conductor) is the same as the material of the interlayer connection conductors va1, vb1, vc1, vd1, ve1 (first interlayer connection conductor).
  • the plurality of interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, ve2 have a truncated cone shape.
  • the plurality of interlayer connection conductors va1 and va2 become thicker from top to bottom.
  • a plurality of interlayer connection conductors vb1, vb2, vc1, vc2, vd1, ve1, and ve2 become thicker from bottom to top.
  • the thicker interlayer connection conductor means that the cross-sectional area of the interlayer connection conductor in the direction perpendicular to the vertical direction is increased.
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) viewed in the vertical direction is the area of the interlayer connection conductors va1, vb1, vc1, vd1, and ve1 (first interlayer connection conductor) viewed in the vertical direction. greater than the minimum value in The interlayer connection conductors va1, vb1, vc1, vd1 and ve1 are interlayer connection conductors located in the first region A1.
  • the area of the interlayer connection conductor in this specification will be described below.
  • the interlayer connection conductor ve2 will be taken as an example below. As described above, the interlayer connection conductor ve2 has a truncated cone shape.
  • the area of the interlayer connection conductor ve2 viewed in the vertical direction means the area of the thinner end t between the upper end and the lower end of the interlayer connection conductor ve2 viewed in the vertical direction.
  • the thin end t of the upper end and the lower end of the interlayer connection conductor ve2 is in contact with the conductor layer 18e.
  • the material of the interlayer connection conductor ve2 is different from the material of the conductor layer 18e. Therefore, it is relatively easy to identify the boundary between the interlayer connection conductor ve2 and the conductor layer 18e.
  • the boundary between the interlayer connection conductor ve2 and the conductor layer 18e corresponds to the thinner end t between the upper end and the lower end of the interlayer connection conductor ve2.
  • an alloy layer G of the material of the conductor layer 18e and the interlayer connection conductor ve2 is formed at the boundary between the conductor layer 18e and the interlayer connection conductor ve2. Therefore, the end t is a portion of the alloy layer G that is flush with the upper main surface of the conductor layer 18e.
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) viewed in the vertical direction is larger than the area of the interlayer connection conductor ve1 (third interlayer connection conductor) viewed in the vertical direction.
  • the interlayer connection conductor ve1 is an interlayer connection conductor provided on the same insulator layer 16e as the insulator layer on which the interlayer connection conductor ve2 is provided.
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) seen in the vertical direction is ) is larger than the maximum area. Furthermore, in the multilayer substrate 10, the area of the interlayer connection conductor ve2 (second interlayer connection conductor) viewed in the vertical direction is larger than the area of the interlayer connection conductor vc2 (fourth interlayer connection conductor) viewed in the vertical direction.
  • the multilayer substrate 10 it is possible to suppress the occurrence of disconnection in the laminate 12 . More specifically, as shown in FIG. 2, the insulator layer 16d exists in the first area A1 and the insulator layer 16d does not exist in the second area A2. As a result, before the step of thermally compressing the laminated body 12, a cavity Sp1 is formed between the insulator layer 16c and the insulator layer 16e in the first region A1. The upper end of the interlayer connection conductor ve2 is exposed to the cavity Sp1. Then, in the thermocompression bonding process of the laminate 12, the insulator layer 16c and the insulator layer 16e are welded together in the first region A1, and the cavity Sp1 disappears.
  • the interlayer connection conductor ve2 (second interlayer connection conductor) is joined to the conductor layer 18c (conductor/second conductor layer). Since the cavity Sp1 exists before the thermocompression bonding step, disconnection may occur between the interlayer connection conductor ve2 (second interlayer connection conductor) and the conductor layer 18c (conductor/second conductor layer). .
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) seen in the vertical direction is the area of the interlayer connection conductors va1, vb1, vc1, vd1, and ve1 (first interlayer connection conductor) seen in the vertical direction. greater than the minimum value of For example, when the area of the interlayer connection conductor va1 seen in the vertical direction is the smallest among the areas of the interlayer connection conductors va1, vb1, vc1, vd1, and ve1 seen in the vertical direction, the interlayer connection conductor The area of ve2 (second interlayer connection conductor) is larger than the area of interlayer connection conductor va1 when viewed in the vertical direction.
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) when viewed in the vertical direction is increased, so that the interlayer connection conductor ve2 (second interlayer connection conductor) and the conductor layer 18c (conductor/second conductor layer ) are in contact with each other.
  • the possibility of disconnection occurring between the interlayer connection conductor ve2 (second interlayer connection conductor) and the conductor layer 18c (conductor/second conductor layer) is reduced.
  • the multilayer substrate 10 it is possible to suppress the occurrence of disconnection in the laminate 12 .
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) viewed in the vertical direction is larger than the area of the interlayer connection conductor ve1 (third interlayer connection conductor) viewed in the vertical direction.
  • This further increases the contact area between the interlayer connection conductor ve2 (second interlayer connection conductor) and the conductor layer 18c (second conductor layer).
  • the possibility of disconnection occurring between the interlayer connection conductor ve2 (second interlayer connection conductor) and the conductor layer 18c (second conductor layer) is further reduced.
  • the interlayer connection conductors can be formed at required locations with a narrow pitch, the degree of freedom in designing the multilayer substrate 10 is enhanced.
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) viewed in the vertical direction is equal to that of the interlayer connection conductors va1, vb1, vc1, vd1, ve1 (first interlayer connection conductor) viewed in the vertical direction. Greater than the largest of the areas. For example, when the area of the interlayer connection conductor vb1 seen in the vertical direction is the largest among the areas of the interlayer connection conductors va1, vb1, vc1, vd1, and ve1 seen in the vertical direction, the interlayer connection conductor The area of ve2 (second interlayer connection conductor) is larger than the area of interlayer connection conductor vb1 when viewed in the vertical direction.
  • each area of the interlayer connection conductor ve2 (second interlayer connection conductor) seen in the vertical direction is larger than the area of the interlayer connection conductor vc2 (fourth interlayer connection conductor) seen in the vertical direction.
  • This further increases the contact area between the interlayer connection conductor ve2 (second interlayer connection conductor) and the conductor layer 18c (second conductor layer).
  • the possibility of disconnection occurring between the interlayer connection conductor ve2 (second interlayer connection conductor) and the conductor layer 18c (second conductor layer) is further reduced.
  • the interlayer connection conductor ve2 is joined to the conductor layer 18c.
  • the interlayer connection conductor ve2 is joined to the planar conductor layer 18c.
  • occurrence of disconnection in the multilayer substrate 10 is suppressed.
  • the interlayer connection conductor vc2 is joined to the conductor layer 18c. Also, the area of the interlayer connection conductor ve2 seen in the vertical direction is larger than the area of the interlayer connection conductor vc2 seen in the vertical direction. As a result, the interlayer connection conductors can be arranged at a narrow pitch even in the second area A2 as required.
  • FIG. 3 is a cross-sectional view of the multilayer substrate 10a.
  • FIG. 4 is a cross-sectional view of the multilayer substrate 10a before thermocompression bonding.
  • the multilayer substrate 10a has the structure of the present invention at two locations. Specifically, in the lower half of the multilayer substrate 10a, the interlayer connection conductor ve2 is the second interlayer connection conductor. In the upper half of the multilayer substrate 10a, the interlayer connection conductor va2 is the second interlayer connection conductor. It is explained below.
  • the multilayer substrate 10a differs from the multilayer substrate 10 in the following first difference.
  • a first difference relates to the structure of the lower half of the multilayer substrate 10a.
  • Insulator layers 16a to 16e (insulator layer 16c is the first insulator layer, insulator layer 16d is the second insulator layer, insulator layer 16e is the third insulator layer, insulator layer 16b is the fourth insulator layer) It has a structure in which layers, the insulator layer 16a and the fifth insulator layer) are stacked downward (second direction) in this order.
  • the insulator layer 16a (fifth insulator layer) is provided in the first region A1 and the second region A2.
  • the insulator layer 16b (fourth insulator layer) is provided in the first region A1 and is not in contact with the boundary B between the first region A1 and the second region A2. That is, the insulator layer 16b is not provided in the second region A2.
  • the distance between the insulator layer 16b and the boundary B is, for example, equal to or greater than the vertical thickness of the insulator layer 16b.
  • the insulator layer 16a and the insulator layer 16c are welded together in part of the first region A1 and in the second region A2.
  • the multilayer substrate 10a differs from the multilayer substrate 10 in the following second difference.
  • a second difference relates to the structure of the upper half of the multilayer substrate 10a.
  • the laminated body 12 has 1st area
  • the first region A11 includes an insulator layer 16c (first insulator layer), an insulator layer 16b (second insulator layer), and an insulator layer 16a (third insulator layer) when viewed in the vertical direction. It is an area where
  • the second region A12 includes an insulator layer 16c (first insulator layer) and an insulator layer 16a (third insulator layer) when viewed in the vertical direction, and an insulator layer 16b (second insulator layer).
  • the two interlayer connection conductors va2 (second interlayer connection conductors) are located in the second region A12 and penetrate the insulator layer 16a (third insulator layer) in the vertical direction.
  • the two interlayer connection conductors vc2 (fourth interlayer connection conductor/conductor) are provided on the insulator layer 16c (first insulator layer). More specifically, the two interlayer connection conductors vc2 (fourth interlayer connection conductors) are located in the second region A12 and vertically penetrate the insulator layer 16c (first insulator layer).
  • the interlayer connection conductor va2 (second interlayer connection conductor) is joined to the interlayer connection conductor vc2 (conductor/fourth interlayer connection conductor). -
  • the area of the two interlayer connection conductors va2 (second interlayer connection conductor) seen in the vertical direction is larger than the area of the interlayer connection conductor vc2 (fourth interlayer connection conductor) seen in the vertical direction.
  • the multilayer substrate 10a satisfies the following conditions.
  • the vertical thickness b2 of the insulator layer 16e (third insulator layer) at the boundary B between the first area A1 and the second area A2 is equal to the thickness b2 of the insulator layer 16e (third insulator layer) in the first area A1 is greater than the thickness b1 in the vertical direction.
  • the vertical thickness of the insulator layer 16d (second insulator layer) decreases as it approaches the boundary B between the first area A1 and the second area A2.
  • the multilayer substrate 10a satisfies the following conditions.
  • the vertical thickness a12 of the insulator layer 16a at the boundary BB between the first area A11 and the second area A12 is greater than the vertical thickness a11 of the insulator layer 16a in the first area A11.
  • the vertical thickness b12 of the insulator layer 16c at the boundary BB between the first area A11 and the second area A12 is greater than the vertical thickness b11 of the insulator layer 16c in the first area A11.
  • the thickness of the insulator layer 16b in the vertical direction decreases as it approaches the boundary BB between the first area A11 and the second area A12.
  • Other structures of the multilayer substrate 10 a are the same as those of the multilayer substrate 10 .
  • the insulator layer 16b (fourth insulator layer) is provided in the first area A1 and is not in contact with the boundary B between the first area A1 and the second area A2. Therefore, the right end of the insulator layer 16b is not vertically aligned with the right end of the insulator layer 16d. This suppresses a large change in the vertical thickness of the laminate 12 in the vicinity of the boundary B between the first area A1 and the second area A2. As a result, separation of the insulator layer 16a from the insulator layer 16b is suppressed.
  • the area of the two interlayer connection conductors va2 (second interlayer connection conductors) seen in the vertical direction is ) and larger than the area of the interlayer connection conductor vc2 (fourth interlayer connection conductor) when viewed in the vertical direction.
  • the area of the two interlayer connection conductors va2 (second interlayer connection conductor) when viewed in the vertical direction is increased, and the interlayer connection conductor va2 (second interlayer connection conductor) and the interlayer connection conductor vc2 (fourth interlayer connection conductor) are increased. ) are in contact with each other.
  • the possibility of disconnection occurring between the interlayer connection conductor ve2 (second interlayer connection conductor) and the interlayer connection conductor vc2 (fourth interlayer connection conductor) is reduced.
  • the area of the interlayer connection conductor vc2 (second interlayer connection conductor) seen in the vertical direction is the area of the interlayer connection conductors va1, vb1, vc1, vd1, and ve1 (first interlayer connection conductor) seen in the vertical direction. and larger than the area of the interlayer connection conductor vc2 (fourth interlayer connection conductor) when viewed in the vertical direction.
  • the structure of the multilayer substrate 10 may be applied to the multilayer substrate 10a.
  • FIG. 5 is a cross-sectional view of the multilayer substrate 10b.
  • FIG. 6 is a cross-sectional view of the multilayer substrate 10b before thermocompression bonding.
  • the area of the two interlayer connection conductors va2 (second interlayer connection conductors) viewed in the vertical direction is the same as the area of the two interlayer connection conductors vc2 (fourth interlayer connection conductors) viewed in the vertical direction. It differs from the multilayer substrate 10a in the same respect.
  • the rest of the structure of the multilayer substrate 10b is the same as that of the multilayer substrate 10a, so the description is omitted.
  • the contact area between the interlayer connection conductor va2 (second interlayer connection conductor) and the interlayer connection conductor vc2 (fourth interlayer connection conductor) is further increased. As a result, the possibility of disconnection occurring between the interlayer connection conductor ve2 (second interlayer connection conductor) and the interlayer connection conductor vc2 (fourth interlayer connection conductor) is further reduced.
  • FIG. 7 is a cross-sectional view of the multilayer substrate 10c.
  • FIG. 8 is a cross-sectional view of the multilayer substrate 10c before thermocompression bonding.
  • FIG. 9 is a sectional view when the multilayer substrate 10c is folded.
  • the multilayer substrate 10c differs from the multilayer substrate 10 in the following points.
  • Insulator layers 16a to 16e (insulator layer 16c is the first insulator layer, insulator layer 16d is the second insulator layer, insulator layer 16e is the third insulator layer, insulator layer 16a is the fourth insulator layer) layers) are laminated in this order downward (second direction).
  • the insulator layer 16a (fourth insulator layer) is provided in the first region A1 and is not in contact with the boundary B between the first region A1 and the second region A2. That is, the insulator layer 16a is not provided in the second region A2.
  • the distance between the insulator layer 16a and the boundary B is, for example, equal to or greater than the vertical thickness of the insulator layer 16a.
  • the insulator layer 16a (fourth insulator layer) is provided in the first area A1 and is not in contact with the boundary B between the first area A1 and the second area A2. Accordingly, the right end of the insulator layer 16a is not vertically aligned with the right end of the insulator layer 16d. A large change in the vertical thickness of the laminate 12 in the vicinity of the boundary B between the first area A1 and the second area A2 is suppressed. As a result, separation of the insulator layer 16a from the insulator layer 16b is suppressed.
  • the insulator layer 16a (fourth insulator layer) is provided in the first area A1 and does not touch the boundary B between the first area A1 and the second area A2. Even if the multilayer substrate 10b is bent as shown in FIG. 9, the insulator layer 16a is less likely to deform. Therefore, the insulator layer 16a is less likely to separate from the insulator layer 16b.
  • FIG. 10 is a cross-sectional view of the multilayer substrate 10d.
  • the multilayer substrate 10d differs from the multilayer substrate 10 in that the conductor layer 18c does not exist near the boundary B.
  • FIG. Moreover, the multilayer substrate 10d may satisfy the following conditions.
  • the vertical thickness a2 of the insulator layer 16c (first insulator layer) at the boundary B between the first area A1 and the second area A2 is equal to the insulator layer 16c (first insulator layer) in the first area A1 is greater than the thickness a1 in the vertical direction.
  • the vertical thickness b2 of the insulator layer 16e (third insulator layer) at the boundary B between the first area A1 and the second area A2 is equal to the thickness b2 of the insulator layer 16e (third insulator layer) in the first area A1 is greater than the thickness b1 in the vertical direction.
  • the vertical thickness of the insulator layer 16d (second insulator layer) decreases as it approaches the boundary B between the first area A1 and the second area A2.
  • Other structures of the multilayer substrate 10 d are the same as those of the multilayer substrate 10 .
  • the multilayer substrate 10d has the insulator layer 16c and the insulator layer 16e strongly welded together at the boundary B between the first area A1 and the second area A2. As a result, the insulating layers 16c, 16d, and 16e are prevented from being peeled off.
  • FIG. 11 is a cross-sectional view of the multilayer substrate 10e and a top view of the insulator layer 16e and the conductor layer 18e.
  • the multilayer substrate 10e differs from the multilayer substrate 10a in the following points.
  • the conductor layer 18e (first conductor layer) has a linear shape when viewed in the vertical direction. That is, the conductor layer 18e is a signal conductor layer used for transmitting high frequency signals.
  • the laminate 12 further includes an insulator layer 16f laminated below the insulator layer 16e.
  • the multilayer substrate 10e further includes a conductor layer 18f located on the lower main surface of the insulator layer 16f.
  • the multilayer substrate 10e further includes a conductor layer 18g positioned on the lower main surface of the insulator layer 16c.
  • the multilayer substrate 10e does not include the conductor layer 18d.
  • the conductor layers 18c and 18f are ground conductor layers connected to a ground potential.
  • the conductor layer 18g is a signal conductor layer.
  • the interlayer connection conductor ve2 is joined to the conductor layer 18e and the conductor layer 18g.
  • the line width w1 of the conductor layer 18e (first conductor layer) in the first region A1 viewed in the vertical direction is greater than the line width w2 of the conductor layer 18e (first conductor layer) in the second region A2 viewed in the vertical direction. thick.
  • the conductor layer 18e (first conductor layer) in the boundary area B1 seen in the vertical direction is tapered in the direction (rightward) from the first area A1 toward the second area A2.
  • the rest of the structure of the multilayer substrate 10e is the same as that of the multilayer substrate 10a, so the description is omitted.
  • the multilayer substrate 10e it is possible to suppress deviation of the characteristic impedance generated in the conductor layer 18e from a predetermined characteristic impedance (for example, 50 ⁇ ). More specifically, the distance between the conductor layer 18c, which is the ground conductor layer, and the conductor layer 18e, which is the signal conductor layer, in the first area A1 is the distance between the conductor layer 18c, which is the ground conductor layer in the second area A2, and the signal conductor layer. It is larger than the distance to a certain conductor layer 18e.
  • the capacitance generated between the conductor layers 18c and 18e in the first region A1 tends to be smaller than the capacitance generated between the conductor layers 18c and 18e in the second region A2. Therefore, the characteristic impedance generated in the conductor layer 18e in the first area A1 tends to be larger than the characteristic impedance generated in the conductor layer 18e in the second area A2.
  • the line width w1 of the conductor layer 18e (first conductor layer) in the first region A1 viewed in the vertical direction is equal to the line width w1 of the conductor layer 18e (first conductor layer) in the second region A2 viewed in the vertical direction. ) is thicker than the line width w2. Accordingly, the magnitude of the capacitance generated between the conductor layer 18c and the conductor layer 18e in the first region A1 is the magnitude of the capacitance generated between the conductor layer 18c and the conductor layer 18e in the second region A2. get closer to Therefore, the characteristic impedance generated in the conductor layer 18e in the first area A1 approaches the characteristic impedance generated in the conductor layer 18e in the second area A2. As described above, according to the multilayer substrate 10e, it is possible to suppress deviation of the characteristic impedance generated in the conductor layer 18e from a predetermined characteristic impedance (for example, 50 ⁇ ).
  • a predetermined characteristic impedance for example, 50 ⁇
  • the distance between the conductor layer 18c and the conductor layer 18e decreases in the direction (rightward direction) from the first area A1 toward the second area A2. Therefore, the conductor layer 18e (first conductor layer) in the boundary area B1 seen in the vertical direction becomes thinner in the direction (rightward) from the first area A1 toward the second area A2. This suppresses a change in the characteristic impedance generated in the conductor layer 18e in the boundary region B1.
  • a predetermined characteristic impedance for example, 50 ⁇ .
  • the multilayer substrate according to the present invention is not limited to the multilayer substrates 10, 10a to 10e, and can be modified within the scope of the gist thereof. Also, the structures of the multilayer substrates 10, 10a to 10e may be combined arbitrarily.
  • the number of each of the interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, vd2, ve1, and ve2 should be 1 or more.
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) viewed in the vertical direction may be less than or equal to the area of the interlayer connection conductor ve1 (third interlayer connection conductor) viewed in the vertical direction.
  • the area of the interlayer connection conductor ve2 (second interlayer connection conductor) seen in the vertical direction is the maximum area of the interlayer connection conductors va1, vb1, vc1, vd1, ve1 (first interlayer connection conductor) seen in the vertical direction. value or less.
  • the areas of the interlayer connection conductors va1, vb1, vc1, vd1, and ve1 (first interlayer connection conductors) when viewed in the vertical direction may not be uniform.
  • conductor layer 18c is not an essential component.
  • insulator layers 16a and 16b are not essential constituent elements.
  • the laminate 12 may further include new interlayer connection conductors.
  • the material of the new interlayer connection conductors may not be the same as the material of the interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, ve2.
  • the new interlayer connection conductor may be formed, for example, by metal plating the inner peripheral surface of the through hole provided in the insulator layer.
  • interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, and ve2 have, for example, metal-plated portions on the inner peripheral surfaces of through holes provided in the insulator layer. may be
  • the shapes of the plurality of interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, and ve2 are not limited to truncated cone shapes.
  • the shape of the interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, ve2 may be a truncated pyramid shape or a plate shape.
  • the vertical size of the plurality of interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2, vd1, ve1, ve2 is, for example, the plurality of interlayer connection conductors va1, va2, vb1, vb2, vc1, vc2 , vd1, ve1, and ve2.
  • the laminated body 12 is a protective layer that covers the conductor layer positioned on the upper main surface of the uppermost insulator layer, or covers the conductor layer positioned on the lower main surface of the lowermost insulator layer. At least one of the protective layers may be included.
  • the protective layer prevents the conductor layers from being exposed from the laminate 12 . However, part of the conductor may be exposed from the protective layer.
  • the material of the protective layer is an insulating material different from the material of the insulator layers 16a-16f.
  • the other of the vertical directions (downward direction) may be the first direction, and one of the vertical directions (upward direction) may be the second direction.

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PCT/JP2022/042723 2022-01-13 2022-11-17 多層基板 Ceased WO2023135931A1 (ja)

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US18/651,724 US20240292535A1 (en) 2022-01-13 2024-05-01 Multilayer board

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WO2025228331A1 (zh) * 2024-04-30 2025-11-06 株式会社村田制作所 多层基板和多层基板的制造方法

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WO2011058938A1 (ja) * 2009-11-10 2011-05-19 株式会社村田製作所 多層基板およびその製造方法
WO2015015975A1 (ja) * 2013-07-30 2015-02-05 株式会社村田製作所 多層基板および多層基板の製造方法
JP2016054313A (ja) * 2011-04-26 2016-04-14 株式会社村田製作所 リジッドフレキシブル基板およびその製造方法
WO2017199824A1 (ja) * 2016-05-18 2017-11-23 株式会社村田製作所 多層基板、および、電子機器

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JP5800301B2 (ja) * 2009-09-14 2015-10-28 日本碍子株式会社 銅合金箔、それを用いたフレキシブルプリント基板

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WO2011058938A1 (ja) * 2009-11-10 2011-05-19 株式会社村田製作所 多層基板およびその製造方法
JP2016054313A (ja) * 2011-04-26 2016-04-14 株式会社村田製作所 リジッドフレキシブル基板およびその製造方法
WO2015015975A1 (ja) * 2013-07-30 2015-02-05 株式会社村田製作所 多層基板および多層基板の製造方法
WO2017199824A1 (ja) * 2016-05-18 2017-11-23 株式会社村田製作所 多層基板、および、電子機器

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