WO2023133974A1 - 本地放大电路、数据读出方法和存储器 - Google Patents

本地放大电路、数据读出方法和存储器 Download PDF

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Publication number
WO2023133974A1
WO2023133974A1 PCT/CN2022/078106 CN2022078106W WO2023133974A1 WO 2023133974 A1 WO2023133974 A1 WO 2023133974A1 CN 2022078106 W CN2022078106 W CN 2022078106W WO 2023133974 A1 WO2023133974 A1 WO 2023133974A1
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Prior art keywords
data line
complementary
local
read
transistor
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PCT/CN2022/078106
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English (en)
French (fr)
Inventor
汪瑛
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长鑫存储技术有限公司
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Priority to US17/854,153 priority Critical patent/US20230230632A1/en
Publication of WO2023133974A1 publication Critical patent/WO2023133974A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the disclosure relates to the field of semiconductor circuit design, in particular to a local amplifier circuit, a data readout method and a memory.
  • the data is sequentially transmitted from the bit line/complementary bit line to the local data line/complementary local data line, and then transmitted to the global data line/complementary global data line, and the data is transferred from the local data line/complementary local data line
  • the transmission of the data line to the global data line/complementary global data line is realized based on a local amplification circuit.
  • the local amplification circuit When the local amplification circuit performs a read operation, it needs to wait for the data to be transmitted from the bit line/complementary bit line to the local data line/complementary local data line, and then provide a read enable signal to further read the data to the global data line/complementary global Data line; if the data is not completely transmitted to the local data line/complementary local data line and a read enable signal is provided, at this time, the local data line/complementary local data line are both high, and the local data line/complementary local data line will be are discharged at the same time, causing reading errors of the local amplifying circuit or causing unnecessary power consumption loss, and the time interval between providing the column selection signal and providing the read enable signal will affect the performance of the memory.
  • An embodiment of the present disclosure provides a local amplification circuit, including: a write control transistor configured to, based on a write enable signal, connect a global data line to a local data line, and connect a complementary global data line to a complementary local data line ;
  • the column selection transistor is configured to, based on the column selection signal, connect the bit line to the local data line, and connect the complementary bit line to the complementary local data line;
  • the first control NMOS transistor the gate is connected to the local data line, and the source is One end of the drain or drain is connected to the global data line, and the other end is connected to the read control transistor;
  • the second control NMOS transistor the gate is connected to the complementary local data line, one end of the source or the drain is connected to the complementary global data line, and the other end is connected to the read Control transistor;
  • a pre-charging module connected to the local data line and the complementary local data line, for pre-charging the local data line and the complementary local data line to a first preset level, and the first preset
  • the first preset level is 0.
  • the pre-charging module includes a pre-charging MOS transistor, the gate of the pre-charging MOS transistor is used to receive the pre-charging signal, one end of the source or the drain is connected to the local data line and the complementary local data line, and the other end is grounded.
  • the precharge level of the global data line and the complementary global data line before data readout is low level, and the second preset level is high level.
  • the precharge level of the global data line and the complementary global data line before data readout is high level, and the second preset level is low level.
  • the write control transistor includes: the first write MOS transistor, the gate is used to receive the write enable signal, the source is connected to the global data line, and the drain is connected to the local data line; the second write MOS transistor, the gate is used to receive the write enable signal Enable signal, the source is connected to the complementary global data line, and the drain is connected to the complementary local data line.
  • the first write MOS transistor and the second write MOS transistor are PMOS. Since the pull-up capability of the PMOS transistor is stronger than that of the NMOS transistor, the first write MOS transistor and the second write MOS transistor are PMOS transistors, which can accelerate the pull-up of the local data line or the complementary local data line to a high voltage after the read enable signal is provided. flat.
  • the column selection transistor includes: the first column selection MOS transistor, the gate is used to receive the column selection signal, the source is connected to the local data line, and the drain is connected to the bit line; the second column selection MOS transistor, the gate is used to receive the column selection signal, the source is connected to the complementary local data line, and the drain is connected to the complementary bit line.
  • the first column selects the MOS transistor and the second column selects the MOS transistor as PMOS. Since the pull-up capability of the PMOS transistor is stronger than that of the NMOS transistor, the first column selection transistor and the second column selection transistor are PMOS transistors, which can accelerate the pull-up of the local data line or the complementary local data line to a high level after the column selection signal is provided. .
  • the read control transistor includes: a first read MOS transistor, the gate is used to receive the read enable signal, the source is connected to the first control NMOS transistor, and the drain is used to receive the first preset level; the second read MOS transistor, The gate is used to receive the read enable signal, the source is connected to the second control NMOS transistor, and the drain is used to receive the first preset level.
  • An embodiment of the present disclosure also provides a data readout method, which is applied to the above-mentioned local amplifying circuit, including: before the readout stage, precharging the local data line and the complementary local data line to a first preset level, and storing the global data line and the complementary global data line are precharged to the precharge level; in the read phase, a read enable signal is provided, and when the first control NMOS transistor is turned on, the global data line is pulled high/low to the second preset level , when the second control NMOS transistor is turned on, the complementary global data line is pulled up/down to the second preset level; a column selection signal is provided to synchronize the bit line level to the local data line, and the complementary bit line level is level synchronization to the complementary local data line; wherein, the read enable signal is provided no later than the global data line or the time when the potential of the complementary global data line changes based on the column selection signal.
  • the supply timing of the read enable signal is not later than the supply timing of the column selection signal.
  • a read enable signal and a column select signal are simultaneously provided.
  • An embodiment of the present disclosure also provides a memory, which uses the above-mentioned local amplifier circuit to write and read data.
  • the memory includes: DRAM, SDRAM, DDR-SDRAM, DDR2-SDRAM, DDR3-SDRAM, DDR4-SDRAM, LPDDR4-SDRAM, DDR5-SDRAM, LPDDR5-SDRAM, GDDR5-SDRAM and GDDR6-SDRAM.
  • FIG. 1 is a schematic structural diagram of a local amplification circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a timing sequence for providing a read enable signal and a column selection signal according to an embodiment of the present disclosure
  • FIG. 3 and FIG. 4 are timing diagrams of signal provision when reading data on a local data line/complementary local data line to a global data line/complementary global data line according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a pre-charging module provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another local amplification circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic flowchart of a data readout method provided by another embodiment of the present disclosure.
  • the data is sequentially transmitted from the bit line/complementary bit line to the local data line/complementary local data line, and then transmitted to the global data line/complementary global data line, and the data is transferred from the local data line/complementary local data line
  • the transmission of the data line to the global data line/complementary global data line is realized based on a local amplification circuit.
  • the local amplification circuit When the local amplification circuit performs a read operation, it needs to wait for the data to be transmitted from the bit line/complementary bit line to the local data line/complementary local data line, and then provide a read enable signal to further read the data to the global data line/complementary global Data line; if the data is not completely transmitted to the local data line/complementary local data line and a read enable signal is provided, at this time, the local data line/complementary local data line are both high, and the local data line/complementary local data line will be are discharged at the same time, causing reading errors of the local amplifying circuit or causing unnecessary power consumption loss, and the time interval between providing the column selection signal and providing the read enable signal will affect the performance of the memory.
  • An embodiment of the present disclosure provides a local amplifier circuit, which shortens the time interval between a column selection signal and a read enable signal during a data readout phase, and speeds up data readout from a memory.
  • Figure 1 is a schematic structural diagram of a local amplifier circuit provided by this embodiment
  • Figure 2 is a schematic diagram of the timing sequence of the read enable signal and column selection signal provided by this embodiment
  • Figure 3 and Figure 4 are the local data provided by this embodiment Line/complementary local data line data read out to the global data line/complementary global data line signal timing diagram
  • Figure 5 is a schematic structural diagram of the pre-charging module provided in this embodiment
  • Figure 6 is a schematic diagram of the pre-charging module provided in this embodiment
  • the local amplifying circuit provided in this embodiment will be further described in detail below in conjunction with the accompanying drawings, specifically as follows:
  • the local amplifier circuit includes:
  • the write control transistor 101 is configured to connect the global data line YIO to the local data line LIO and to connect the complementary global data line YIO- to the complementary local data line LIO- based on the write enable signal WrEn.
  • the write enable signal WrEn is used to turn on the write control transistor 101; the global data line YIO and the complementary global data line YIO- are used to transmit inverted data, that is, the global data line YIO transmits high-level data, and the complementary global data line YIO-transmits Low-level data; the global data line YIO transmits low-level data, and the complementary global data line YIO- transmits high-level data; in addition, the local data line LIO and the complementary local data line LIO- are also used to transmit inverted data.
  • the column selection transistor 102 is configured to connect the bit line BL to the local data line LIO and the complementary bit line BLB to the complementary local data line based on the column selection signal CSL.
  • the column selection signal CSL is used to turn on the column selection transistor 102; the bit line BL and the complementary bit line BLB are used to transmit inverted data, and the bit line BL and the complementary bit line BLB are connected with memory cells, when the data is transmitted by the local data line LIO When the data is transmitted to the bit line BL, or the data is transmitted from the complementary local data line LIO- to the complementary bit line BLB, that is, the data storage stage of the memory; when the data is transmitted from the bit line BL to the local data line LIO, or the data is transmitted from the complementary bit line BLB When transmitting to the complementary local data line LIO-, that is, the data reading phase of the memory.
  • the gate of the first control NMOS transistor 110 is connected to the local data line LIO, one end of the source or the drain is connected to the global data line YIO, and the other end is connected to the read control transistor 103 .
  • the gate of the second control NMOS transistor 120 is connected to the complementary local data line LIO-, one end of the source or the drain is connected to the complementary global data line YIO-, and the other end is connected to the read control transistor 103 .
  • the first control NMOS transistor 110 is controlled by the level of the local data line LIO.
  • the first control NMOS transistor 110 is turned on, and one of the terminals of the source and drain in the read control transistor 103 is connected to the global data line.
  • the second control NMOS transistor 120 is controlled by the level of the complementary local data line LIO-, when the complementary local data line LIO- is high Normally, the second control NMOS transistor 120 is turned on, and one of the terminals of the source and drain of the read control transistor 103 is connected to the complementary global data line YIO-; when the complementary local data line LIO- is at a low level, the second control NMOS transistor 120 is turned off. open.
  • the pre-charging module 104 is connected to the local data line LIO and the complementary local data line LIO-, and is used to pre-charge the local data line LIO and the complementary local data line LIO- to a first preset level V1, the first preset level V1 It is smaller than the threshold voltage of the first control NMOS transistor and smaller than the threshold voltage of the second control NMOS transistor.
  • the read control transistor 103 is configured to, based on the read enable signal RdEn, pull up/pull down the terminals of the first control NMOS transistor and the second control NMOS transistor connected to the read control transistor 103 to a second preset level V2, and the second The preset level V2 is opposite to the precharge level of the global data line YIO and the complementary global data line YIO ⁇ .
  • the read enable signal RdEn is used to turn on the read control transistor 103.
  • the read control transistor 103 and the first control NMOS transistor 110 are turned on, the read control transistor 103 pulls up/pulls the global data line YIO to a second preset level V2, when the read control transistor 103 and the second control NMOS transistor 120 are turned on, the read control transistor 103 pulls up/pulls the complementary global data line YIO- to the second preset level V2, wherein the second preset level V2 is opposite to the precharge level of the global data line YIO and the complementary global data line YIO ⁇ .
  • the local data line LIO and the complementary local data line LIO- are precharged to the first preset level V1 through the precharging module 104, and the first preset level V1 is not enough to turn on the second
  • the first control NMOS transistor 110 and the second control NMOS transistor 120 provide a write enable signal WrEn during the data writing phase, and the data on the global data line YIO and the complementary global data line YIO- are transmitted to the local data line LIO and the complementary local data line Line LIO-, since the read control transistor 103 cannot be turned on, the conduction of the first control NMOS transistor 110 and the second control NMOS transistor 120 does not affect the data writing of the memory; in the data read phase, the read enable can be provided in advance Signal RdEn, at this time, because the first control NMOS transistor 110 and the second control NMOS transistor 120 cannot be turned on, it does not affect the data readout of the memory.
  • the first control NMOS transistor 110 or the second control NMOS transistor 120 is turned on, thereby turning on the corresponding readout path, and the local data line LIO and the complementary local data line
  • the data on LIO- is transmitted to the global data line YIO and the complementary global data line YIO-; thus, in the data readout stage, the time interval between the column selection signal CSL and the read enable signal RdEn is shortened, and the data readout of the memory is accelerated .
  • the read enable signal RdEn is provided before the change of the local data line LIO and the complementary local data line LIO ⁇ is completed, which can also speed up the data reading of the memory, that is, in some embodiments, the read enable signal can be provided within the time period t1.
  • the global data line YIO and the complementary global data line YIO-the precharge level precharged before data readout is a low level, and the second preset level V2 is a high level ;
  • the read control transistor 103 and the first control NMOS transistor 110 are turned on, the global data line YIO is pulled up to a high level, and when the read control transistor 103 and the second control NMOS transistor 120 are turned on, the complementary global data line Line YIO- is pulled high.
  • the global data line YIO and the complementary global data line YIO-the precharge level precharged before data readout is a high level, and the second preset level V2 is a low level ;
  • the read control transistor 103 and the first control NMOS transistor 110 are turned on, the global data line YIO is pulled down to a low level, and when the read control transistor 103 and the second control NMOS transistor 120 are turned on, the complementary global data line Line YIO- is pulled low.
  • the first preset level is 0, that is, the local data line LIO and the complementary local data line LIO ⁇ are discharged before the data read or data write phase.
  • the pre-charging module 104 includes a pre-charging MOS transistor 105, the gate of the pre-charging MOS transistor 105 is used to receive the pre-charging signal PRE, and one end of the source or the drain is connected to the local data line LIO and the complementary local The other end of the data line LIO- is grounded to GND, so that the discharge of the local data line LIO and the complementary local data line LIO- can be controlled by the precharge signal PRE.
  • the write control transistor 101 includes:
  • the first write MOS transistor ⁇ 11> has a gate for receiving the write enable signal WrEn, a source connected to the global data line YIO, and a drain connected to the local data line LIO.
  • the second write MOS transistor ⁇ 12> has a gate for receiving the write enable signal WrEn, a source connected to the complementary global data line YIO-, and a drain connected to the complementary local data line LIO-.
  • the first write MOS transistor ⁇ 11> and the second write MOS transistor ⁇ 12> are NMOS transistors; since the pull-up capability of the PMOS transistor is stronger than that of the NMOS transistor, in some embodiments, the first write MOS transistor ⁇ 11> and the second write MOS transistor ⁇ 12> are PMOS transistors, which can accelerate the pull-up of the local data line LIO or the complementary local data line LIO- to a high level after the write enable signal WrEn is provided.
  • column select transistor 102 includes:
  • the first column selection transistor ⁇ 21> has a gate for receiving the column selection signal CSL, a source connected to the local data line LIO, and a drain connected to the bit line BL.
  • the second column selection transistor ⁇ 22> has a gate for receiving the column selection signal CSL, a source connected to the complementary local data line LIO-, and a drain connected to the complementary bit line BLB.
  • the first column selection transistor ⁇ 21> and the second column selection transistor ⁇ 22> are NMOS transistors; since the pull-up capability of the PMOS transistor is stronger than that of the NMOS transistor, in some embodiments, the first column selection transistor ⁇ 21> and the second column selection transistor ⁇ 22> are PMOS transistors, which can accelerate the pull-up of the local data line LIO or the complementary local data line LIO- to a high level after the column selection signal CSL is provided.
  • the corresponding circuit diagram refers to Figure 6.
  • the read control transistor 103 includes:
  • the first read MOS transistor ⁇ 31> has a gate for receiving the read enable signal RdEn, a source connected to the first control NMOS transistor 110, and a drain for receiving the first preset level V1.
  • the second read MOS transistor ⁇ 32> has a gate for receiving the read enable signal RdEn, a source connected to the second control NMOS transistor 120, and a drain for receiving the first preset level V1.
  • the first read MOS transistor ⁇ 31> and the second read MOS transistor ⁇ 32> are NMOS transistors; since the pull-up capability of the PMOS transistor is stronger than that of the NMOS transistor, the pull-down capability of the NMOS transistor is stronger than that of the PMOS transistor.
  • the types of the first read MOS transistor ⁇ 31> and the second read MOS transistor ⁇ 32> can be flexibly set according to the size of the first preset level V1; for example, when the first preset level V1 is high Level, the first read MOS tube ⁇ 31> and the second read MOS tube ⁇ 32> are NMOS tubes, when the first preset level V1 is low, the first read MOS tube ⁇ 31> and the second read MOS tube Tube ⁇ 32> is a PMOS tube.
  • the local data line LIO and the complementary local data line LIO- are precharged to the first preset level V1 through the precharging module 104, and the first preset level V1 is not enough to turn on the second
  • the first control NMOS transistor 110 and the second control NMOS transistor 120 provide a write enable signal WrEn during the data writing phase, and the data on the global data line YIO and the complementary global data line YIO- are transmitted to the local data line LIO and the complementary local data line Line LIO-, since the read control transistor 103 cannot be turned on, the conduction of the first control NMOS transistor 110 and the second control NMOS transistor 120 does not affect the data writing of the memory; in the data read phase, the read enable can be provided in advance Signal RdEn, at this time, because the first control NMOS transistor 110 and the second control NMOS transistor 120 cannot be turned on, it does not affect the data readout of the memory.
  • the first control NMOS transistor 110 or the second control NMOS transistor 120 is turned on, thereby turning on the corresponding readout path, and the local data line LIO and the complementary local data line
  • the data on LIO- is transmitted to the global data line YIO and the complementary global data line YIO-; thus, in the data readout stage, the time interval between the column selection signal CSL and the read enable signal RdEn is shortened, and the data readout of the memory is accelerated .
  • Another embodiment of the present disclosure provides a data readout method. Based on the local amplifier circuit provided in this embodiment, in the data readout stage, the time interval between the column selection signal and the read enable signal is shortened, and the data readout of the memory is accelerated. out.
  • FIG. 7 is a schematic flow chart of the data readout method provided by this embodiment.
  • the data readout method provided by this embodiment will be further described in detail below in conjunction with the accompanying drawings, specifically as follows:
  • the data readout method includes:
  • Step 201 precharge the local data line and the complementary local data line to a first preset level, and precharge the global data line and the complementary global data line to a precharge level.
  • the local sum data line and the complementary local sum data line are precharged to a first preset level, and the global data line and the complementary global data line are precharged to a precharge level.
  • Step 202 providing a read enable signal and a column selection signal.
  • the read enable signal is provided no later than the moment when the potential of the global data line or the complementary global data line changes based on the column selection signal.
  • a read enable signal is provided, and when the first control NMOS transistor is turned on, the global data line is pulled up/lower to the second preset level, and when the second control NMOS transistor is turned on, the The complementary global data line is pulled high/low to the second preset level, providing a column selection signal, synchronizing the level of the bit line to the local data line, and synchronizing the level of the complementary bit line to the complementary local data line, wherein, the read The enabling signal is provided no later than the moment when the potential of the global data line or the complementary global data line changes based on the column selection signal.
  • the local data line and the complementary local data line are precharged to the first preset level by the precharging module, and the first preset level is not enough to turn on the first control NMOS transistor and the second control NMOS transistor, in the data writing stage , to provide a write enable signal, and the data on the global data line and the complementary global data line are transmitted to the local data line and the complementary local data line.
  • the read control transistor cannot be turned on, the conduction of the first control NMOS transistor and the second control NMOS transistor It does not affect the data writing of the memory; in the data read stage, the read enable signal can be provided in advance, at this time, because the first control NMOS transistor and the second control NMOS transistor cannot be turned on, it does not affect the data read of the memory , when the column selection signal is provided, the data of the bit line and the complementary bit line are synchronized to the local data line and the complementary local data line, and the first control NMOS transistor or the second control NMOS transistor is turned on, thereby turning on the corresponding readout path , and transmit the data on the local data line and the complementary local data line to the global data line and the complementary global data line; thereby shortening the time interval between the column selection signal and the read enable signal in the data readout stage, and speeding up the storage of the memory Data readout.
  • the column selection signal CSL is provided to the local data line LIO and the complementary local data line LIO-there is a delay of t1 time after the change is completed, it is only necessary to ensure that the read enable signal RdEn is on the local data line LIO and the complementary local data line Provided before the LIO-change is completed, the data reading of the memory can also be accelerated, that is, in some embodiments, the read enable signal can be provided within the t1 time period; in some embodiments, the time of the read enable signal is no later than The timing of providing the column selection signal; in some embodiments, the read enable signal and the column selection signal are provided at the same time.
  • Another embodiment of the present disclosure provides a memory, which uses the local amplification circuit provided by the above embodiments to write and read data, so as to shorten the time interval between the column selection signal and the read enable signal, and speed up the data reading of the memory. out.
  • the memory is a dynamic random access memory (DRAM) chip.
  • DRAM dynamic random access memory
  • the memory is a dynamic random access memory SRAM chip.
  • the memory is a dynamic random access memory SDRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR memory specification.
  • the memory is a dynamic random access memory SDRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR2 memory specification.
  • the memory is a dynamic random access memory SDRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR3 memory specification.
  • the memory is a dynamic random access memory SDRAM chip, wherein the memory of the dynamic random access memory DRAM chip complies with DDR4 or LPDDR4 memory specifications.
  • the memory is a dynamic random access memory SDRAM chip, wherein the memory of the dynamic random access memory DRAM chip complies with DDR5 or LPDDR5 memory specifications.
  • the memory is a dynamic random access memory SDRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the GDDR5 or GDDR6 memory specification.

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Abstract

本公开涉及半导体电路设计领域，特别涉及一种本地放大电路、数据读出方法和存储器，包括：写控制晶体管（101）基于写使能信号，将全局数据线连接至本地数据线；列选择晶体管（102）基于列选择信号，将位线连接至本地数据线；第一控制NMOS管（110），栅极连接本地数据线，源极或漏极的其中一端连接全局数据线，另一端连接读控制晶体管（103）；第二控制NMOS管（120），栅极连接互补本地数据线，源极或漏极的其中一端连接互补全局数据线，另一端连接读控制晶体管（103）；读控制晶体管基于读使能信号，将第一控制NMOS管（110）和第二控制NMOS管（120）与读控制晶体管（103）相连的端子上拉/下拉至第二预设电平，以缩短列选择信号和读使能信号之间的时间间隔。

Description

本地放大电路、数据读出方法和存储器
交叉引用
本公开要求于2022年01月14日递交的名称为“本地放大电路、数据读出方法和存储器”、申请号为202210044996.0的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开涉及半导体电路设计领域，特别涉及一种本地放大电路、数据读出方法和存储器。
背景技术
存储器在进行数据读出的过程中，数据依次由位线/互补位线传输至本地数据线/互补本地数据线，再传输至全局数据线/互补全局数据线，数据由本地数据线/互补本地数据线传输至全局数据线/互补全局数据线基于本地放大电路实现。
本地放大电路在进行读操作时，需要等待数据从位线/互补位线传输至本地数据线/互补本地数据线，之后在提供读使能信号，将数据进一步读出至全局数据线/互补全局数据线；若数据未完全传递到本地数据线/互补本地数据线而提供读使能信号，此时，本地数据线/互补本地数据线均为高电平，本地数据线/互补本地数据线会被同时放电，造成本地放大电路的读取错误或造成不必要的功耗损失，而列选择信号提供至读使能信号提供的时间间隔会影响存储器的性能。
因此，当下亟待设计一种信号的读出电路，以缩短列选择信号提供至读使能信号提供的时间间隔，从而优化存储器的性能。
发明内容
本公开实施例提供了一种本地放大电路，包括：写控制晶体管，被配置为，基于写使能信号，将全局数据线连接至本地数据线，并将互补全局数据线连接至互补本地数据线；列选择晶体管，被配置为，基于列选择信号，将位线连接至本地数据线，并将互补位线连接至互补本地数据线；第一控制NMOS管，栅极连接本地数据线，源极或漏极的其中一端连接全局数据线，另一端连接读 控制晶体管；第二控制NMOS管，栅极连接互补本地数据线，源极或漏极的其中一端连接互补全局数据线，另一端连接读控制晶体管；预充电模块，连接本地数据线和互补本地数据线，用于将本地数据线和互补本地数据线预充电至第一预设电平，第一预设电平小于第一控制NMOS管的阈值电压，且小于第二控制NMOS管的阈值电压；读控制晶体管被配置为，基于读使能信号，将第一控制NMOS管和第二控制NMOS管与读控制晶体管相连的端子上拉/下拉至第二预设电平；第二预设电平与全局数据线和互补全局数据线的预充电电平相反。
另外，第一预设电平为0。
另外，预充电模块包括预充电MOS管，预充电MOS管的栅极用于接收预充电信号，源极或漏极的其中一端连接本地数据线和互补本地数据线，另一端接地。
另外，全局数据线和互补全局数据线在数据读出前被预充的预充电电平为低电平，第二预设电平为高电平。
另外，全局数据线和互补全局数据线在数据读出前被预充的预充电电平为高电平，第二预设电平为低电平。
另外，写控制晶体管包括：第一写MOS管，栅极用于接收写使能信号，源极连接全局数据线，漏极连接本地数据线；第二写MOS管，栅极用于接收写使能信号，源极连接互补全局数据线，漏极连接互补本地数据线。
另外，第一写MOS管和第二写MOS管为PMOS。由于PMOS管比NMOS管的上拉能力强，第一写MOS管和第二写MOS管为PMOS管，能加速在提供读使能信号后，将本地数据线或互补本地数据线上拉至高电平。
另外，列选择晶体管包括：第一列选择MOS管，栅极用于接收列选择信号，源极连接本地数据线，漏极连接位线；第二列选择MOS管，栅极用于接收列选择信号，源极连接互补本地数据线，漏极连接互补位线。
另外，第一列选择MOS管和第二列选择MOS管为PMOS。由于PMOS管比NMOS管的上拉能力强，第一列选择晶体管和第二列选择晶体管为PMOS管，能加速在提供列选择信后，将本地数据线或互补本地数据线上拉至高电平。
另外，读控制晶体管包括：第一读MOS管，栅极用于接收读使能信号， 源极连接第一控制NMOS管，漏极用于接收第一预设电平；第二读MOS管，栅极用于接收读使能信号，源极连接第二控制NMOS管，漏极用于接收第一预设电平。
本公开实施例还提供一种数据读出方法，应用于上述本地放大电路，包括：在读出阶段之前，将本地数据线和互补本地数据线预充电至第一预设电平，将全局数据线和互补全局数据线预充电至预充电电平；在读出阶段，提供读使能信号，当第一控制NMOS管导通，将全局数据线拉高/拉低至第二预设电平，当第二控制NMOS管导通，将互补全局数据线拉高/拉低至第二预设电平；提供列选择信号，将位线电平同步至本地数据线，并将互补位线电平同步至互补本地数据线；其中，读使能信号的提供时刻不迟于全局数据线或所述互补全局数据线基于列选择信号发生电位变化的时刻。
另外，读使能信号的提供时刻不迟于优先于列选择信号的提供时刻。
另外，读使能信号和列选择信号同时提供。
本公开实施例还提供一种存储器，应用上述本地放大电路进行数据的写入和读出。
另外，存储器包括：DRAM、SDRAM、DDR-SDRAM、DDR2-SDRAM、DDR3-SDRAM、DDR4-SDRAM、LPDDR4-SDRAM、DDR5-SDRAM、LPDDR5-SDRAM、GDDR5-SDRAM和GDDR6-SDRAM。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领缺普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的本地放大电路的结构示意图；
图2为本公开一实施例提供的读使能信号和列选择信号的提供时序示意图；
图3和图4为本公开一实施例提供的将本地数据线/互补本地数据线上的数据读出至全局数据线/互补全局数据线时的信号提供时序示意图；
图5为本公开一实施例提供的预充电模块的结构示意图；
图6为本公开一实施例提供的另一种本地放大电路的结构示意图；
图7为本公开另一实施例提供的数据读出方法的流程示意图。
具体实施方式
存储器在进行数据读出的过程中，数据依次由位线/互补位线传输至本地数据线/互补本地数据线，再传输至全局数据线/互补全局数据线，数据由本地数据线/互补本地数据线传输至全局数据线/互补全局数据线基于本地放大电路实现。
本地放大电路在进行读操作时，需要等待数据从位线/互补位线传输至本地数据线/互补本地数据线，之后在提供读使能信号，将数据进一步读出至全局数据线/互补全局数据线；若数据未完全传递到本地数据线/互补本地数据线而提供读使能信号，此时，本地数据线/互补本地数据线均为高电平，本地数据线/互补本地数据线会被同时放电，造成本地放大电路的读取错误或造成不必要的功耗损失，而列选择信号提供至读使能信号提供的时间间隔会影响存储器的性能。
本公开实施例提供了一种本地放大电路，在数据读出阶段，缩短列选择信号和读使能信号之间的时间间隔，加快存储器的数据读出。
本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例提供的本地放大电路的结构示意图，图2为本实施例提供的读使能信号和列选择信号的提供时序示意图，图3和图4为本实施例提供的将本地数据线/互补本地数据线上的数据读出至全局数据线/互补全局数据线时的信号提供时序示意图，图5为本实施例提供的预充电模块的结构示意图，图6为本实施例提供的另一种本地放大电路的结构示意图，以下结合附图对本 实施例提供的本地放大电路作进一步详细说明，具体如下：
参考图1，本地放大电路，包括：
写控制晶体管101，被配置为，基于写使能信号WrEn，将全局数据线YIO连接至本地数据线LIO，并将互补全局数据线YIO-连接至互补本地数据线LIO-。
写使能信号WrEn用于导通写控制晶体管101；全局数据线YIO和互补全局数据线YIO-用于传输反相数据，即全局数据线YIO传输高电平数据，互补全局数据线YIO-传输低电平数据；全局数据线YIO传输低电平数据，互补全局数据线YIO-传输高电平数据；另外，本地数据线LIO和互补本地数据线LIO-也用于传输反相数据。
列选择晶体管102，被配置为，基于列选择信号CSL，将位线BL连接至本地数据线LIO，并将互补位线BLB连接至互补本地数据线。
列选择信号CSL用于导通列选择晶体管102；位线BL和互补位线BLB用于传输反相数据，且位线BL和互补位线BLB上连接有存储单元，当数据由本地数据线LIO向位线BL传输，或数据由互补本地数据线LIO-向互补位线BLB传输时，即存储器的数据存储阶段；当数据由位线BL向本地数据线LIO传输，或数由互补位线BLB向互补本地数据线LIO-传输时，即存储器的数据读取阶段。
第一控制NMOS管110，栅极连接本地数据线LIO，源极或漏极的其中一端连接全局数据线YIO，另一端连接读控制晶体管103。
第二控制NMOS管120，栅极连接互补本地数据线LIO-，源极或漏极的其中一端连接互补全局数据线YIO-，另一端连接读控制晶体管103。
第一控制NMOS管110通过本地数据线LIO的电平控制，当本地数据线LIO为高电平时，第一控制NMOS管110导通，读控制晶体管103中源漏的其中一个端子与全局数据线YIO连接；当本地数据线LIO为低电平时，第一控制NMOS管110断开；第二控制NMOS管120通过互补本地数据线LIO-的电平控制，当互补本地数据线LIO-为高电平时，第二控制NMOS管120导通，读控制晶体管103中源漏的其中一个端子与互补全局数据线YIO-连接；当互补本地数据线LIO-为低电平时，第二控制NMOS管120断开。
预充电模块104，连接本地数据线LIO和互补本地数据线LIO-，用于将 本地数据线LIO和互补本地数据线LIO-预充电至第一预设电平V1，第一预设电平V1小于第一控制NMOS管的阈值电压，且小于第二控制NMOS管的阈值电压。
读控制晶体管103被配置为，基于读使能信号RdEn，将第一控制NMOS管和第二控制NMOS管与读控制晶体管103相连的端子上拉/下拉至第二预设电平V2，第二预设电平V2与全局数据线YIO和互补全局数据线YIO-的预充电电平相反。
读使能信号RdEn用于导通读控制晶体管103，当读控制晶体管103和第一控制NMOS管110导通时，读控制晶体管103将全局数据线YIO上拉/下拉至第二预设电平V2，当读控制晶体管103和第二控制NMOS管120导通时，读控制晶体管103将互补全局数据线YIO-上拉/下拉至第二预设电平V2，其中，第二预设电平V2与全局数据线YIO和互补全局数据线YIO-的预充电电平相反。
基于本实施例提供的本地放大电路，通过预充电模块104将本地数据线LIO和互补本地数据线LIO-预充电至第一预设电平V1，且第一预设电平V1不足以开启第一控制NMOS管110和第二控制NMOS管120，在数据写入阶段，提供写使能信号WrEn，全局数据线YIO和互补全局数据线YIO-上的数据传输至本地数据线LIO和互补本地数据线LIO-，由于读控制晶体管103无法导通，第一控制NMOS管110和第二控制NMOS管120的导通并不影响存储器的数据写入；在数据读出阶段，可以提前提供读使能信号RdEn，此时由于第一控制NMOS管110和第二控制NMOS管120无法导通，并不影响存储器的数据读出，当提供列选择信号CSL后，位线BL和互补位线BLB的数据被同步至本地数据线LIO和互补本地数据线LIO-，第一控制NMOS管110或第二控制NMOS管120导通，从而导通相应的读出通路，将本地数据线LIO和互补本地数据线LIO-上的数据传输至全局数据线YIO和互补全局数据线YIO-；从而实现在数据读出阶段，缩短列选择信号CSL和读使能信号RdEn之间的时间间隔，加快存储器的数据读出。
需要说明的是，参考图2，基于本实施例提供的本地放大电路，由于列选择信号CSL的提供至本地数据线LIO和互补本地数据线LIO-变化完毕存在t1时间的延时，仅需保证读使能信号RdEn在本地数据线LIO和互补本地数据线LIO-变化完毕前提供，同样可以加快存储器的数据读出，即在一些实施例中， 读使能信号可以在t1时间段内提供。
在一些实施例中，参考图3，全局数据线YIO和互补全局数据线YIO-在数据读出前被预充的预充电电平为低电平，第二预设电平V2为高电平；此时，当读控制晶体管103和第一控制NMOS管110导通时，全局数据线YIO被上拉至高电平，当读控制晶体管103和第二控制NMOS管120导通时，互补全局数据线YIO-被上拉至高电平。
在一些实施例中，参考图4，全局数据线YIO和互补全局数据线YIO-在数据读出前被预充的预充电电平为高电平，第二预设电平V2为低电平；此时，当读控制晶体管103和第一控制NMOS管110导通时，全局数据线YIO被下拉至低电平，当读控制晶体管103和第二控制NMOS管120导通时，互补全局数据线YIO-被下拉至低电平。
在一些实施例中，第一预设电平为0，即在数据读出或数据写入阶段之前，对本地数据线LIO和互补本地数据线LIO-进行放电。
具体地，参考图5，预充电模块104包括预充电MOS管105，预充电MOS管105的栅极用于接收预充电信号PRE，源极或漏极的其中一端连接本地数据线LIO和互补本地数据线LIO-，另一端接地GND，从而实现通过预充电信号PRE控制对本地数据线LIO和互补本地数据线LIO-的放电。
在一些实施例中，继续参考图1，写控制晶体管101包括：
第一写MOS管<11>，栅极用于接收写使能信号WrEn，源极连接全局数据线YIO，漏极连接本地数据线LIO。
第二写MOS管<12>，栅极用于接收写使能信号WrEn，源极连接互补全局数据线YIO-，漏极连接互补本地数据线LIO-。
在本实施例中，第一写MOS管<11>和第二写MOS管<12>为NMOS管；由于PMOS管比NMOS管的上拉能力强，在一些实施例中，第一写MOS管<11>和第二写MOS管<12>为PMOS管，能加速在提供写使能信号WrEn后，将本地数据线LIO或互补本地数据线LIO-上拉至高电平。
在一些实施例中，继续参考图1，列选择晶体管102包括：
第一列选择晶体管<21>，栅极用于接收列选择信号CSL，源极连接本地 数据线LIO，漏极连接位线BL。
第二列选择晶体管<22>，栅极用于接收列选择信号CSL，源极连接互补本地数据线LIO-，漏极连接互补位线BLB。
在本实施例中，第一列选择晶体管<21>和第二列选择晶体管<22>为NMOS管；由于PMOS管比NMOS管的上拉能力强，在一些实施例中，第一列选择晶体管<21>和第二列选择晶体管<22>为PMOS管，能加速在提供列选择信号CSL后，将本地数据线LIO或互补本地数据线LIO-上拉至高电平。
具体地，当第一写MOS管<11>和第二写MOS管<12>为PMOS管，第一列选择晶体管<21>和第二列选择晶体管<22>为PMOS管，对应的电路图参考图6。
在一些实施例中，继续参考图1，读控制晶体管103包括：
第一读MOS管<31>，栅极用于接收读使能信号RdEn，源极连接第一控制NMOS管110，漏极用于接收第一预设电平V1。
第二读MOS管<32>，栅极用于接收读使能信号RdEn，源极连接第二控制NMOS管120，漏极用于接收第一预设电平V1。
在本实施例中，第一读MOS管<31>和第二读MOS管<32>为NMOS管；由于PMOS管比NMOS管的上拉能力强，NMOS管子比PMOS管的下拉能力强，在一些实施例中，可以根据第一预设电平V1的大小灵活设置第一读MOS管<31>和第二读MOS管<32>的类型；例如，当第一预设电平V1为高电平，第一读MOS管<31>和第二读MOS管<32>为NMOS管，当第一预设电平V1为低电平，第一读MOS管<31>和第二读MOS管<32>为PMOS管。
需要说明的是，对于上述提到的各类MOS管，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
需要说明的是，上述实施例所提供的监测电路中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的电路实施例。
基于本实施例提供的本地放大电路，通过预充电模块104将本地数据线LIO和互补本地数据线LIO-预充电至第一预设电平V1，且第一预设电平V1不 足以开启第一控制NMOS管110和第二控制NMOS管120，在数据写入阶段，提供写使能信号WrEn，全局数据线YIO和互补全局数据线YIO-上的数据传输至本地数据线LIO和互补本地数据线LIO-，由于读控制晶体管103无法导通，第一控制NMOS管110和第二控制NMOS管120的导通并不影响存储器的数据写入；在数据读出阶段，可以提前提供读使能信号RdEn，此时由于第一控制NMOS管110和第二控制NMOS管120无法导通，并不影响存储器的数据读出，当提供列选择信号CSL后，位线BL和互补位线BLB的数据被同步至本地数据线LIO和互补本地数据线LIO-，第一控制NMOS管110或第二控制NMOS管120导通，从而导通相应的读出通路，将本地数据线LIO和互补本地数据线LIO-上的数据传输至全局数据线YIO和互补全局数据线YIO-；从而实现在数据读出阶段，缩短列选择信号CSL和读使能信号RdEn之间的时间间隔，加快存储器的数据读出。
本公开另一实施例提供一种数据读出方法，基于本实施例提供的本地放大电路，在数据读出阶段，缩短列选择信号和读使能信号之间的时间间隔，加快存储器的数据读出。
图7为本实施例提供的数据读出方法的流程示意图，以下结合附图对本实施例提供的数据读出方法作进一步详细说明，具体如下：
参考图7，数据读出方法，包括：
步骤201，将本地数据线和互补本地数据线预充电至第一预设电平，将全局数据线和互补全局数据线预充电至预充电电平。
具体地，在读出阶段之前，将本地和数据线和互补本地和数据线预充电至第一预设电平，将全局数据线和互补全局数据线预充电至预充电电平。
步骤202，提供读使能信号和列选择信号，读使能信号的提供时刻不迟于全局数据线或互补全局数据线基于列选择信号发生电位变化的时刻。
具体地，在读出阶段，提供读使能信号，当第一控制NMOS管导通，将全局数据线拉高/拉低至第二预设电平，当第二控制NMOS管导通，将互补全局数据线拉高/拉低至第二预设电平，提供列选择信号，将位线电平同步至本地数据线，并将互补位线电平同步至互补本地数据线，其中，读使能信号的提供时刻不迟于全局数据线或互补全局数据线基于列选择信号发生电位变化的时刻。
通过预充电模块将本地数据线和互补本地数据线预充电至第一预设电平，且第一预设电平不足以开启第一控制NMOS管和第二控制NMOS管，在数据写入阶段，提供写使能信号，全局数据线和互补全局数据线上的数据传输至本地数据线和互补本地数据线，由于读控制晶体管无法导通，第一控制NMOS管和第二控制NMOS管的导通并不影响存储器的数据写入；在数据读出阶段，可以提前提供读使能信号，此时由于第一控制NMOS管和第二控制NMOS管无法导通，并不影响存储器的数据读出，当提供列选择信号后，位线和互补位线的数据被同步至本地数据线和互补本地数据线，第一控制NMOS管或第二控制NMOS管导通，从而导通相应的读出通路，将本地数据线和互补本地数据线上的数据传输至全局数据线和互补全局数据线；从而实现在数据读出阶段，缩短列选择信号和读使能信号之间的时间间隔，加快存储器的数据读出。
结合图2，由于列选择信号CSL的提供至本地数据线LIO和互补本地数据线LIO-变化完毕存在t1时间的延时，仅需保证读使能信号RdEn在本地数据线LIO和互补本地数据线LIO-变化完毕前提供，同样可以加快存储器的数据读出，即在一些实施例中，读使能信号可以在t1时间段内提供；在一些实施例中，读使能信号的时刻不迟于列选择信号的提供时刻；在一些实施例中，读使能信号和列选择信号同时提供。
需要说明的是，以上数据读出方法的描述，与上述本地放大电路实施例的描述是类似的，具有同本地放大电路实施例相似的有益效果，因此不做赘述。对于本公开实施例数据读出方法中未披露的技术细节，请参照本公开实施例中本地放大电路的描述而理解。
本公开又一实施例提供一种存储器，应用上述实施例提供的本地放大电路进行数据的写入和读出，以缩短列选择信号和读使能信号之间的时间间隔，加快存储器的数据读出。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片。
在一些实施例中，存储器为动态随机存取存储器SRAM芯片。
在一些实施例中，存储器为动态随机存取存储器SDRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR内存规格。
在一些实施例中，存储器为动态随机存取存储器SDRAM芯片，其中， 动态随机存取存储器DRAM芯片的内存符合DDR2内存规格。
在一些实施例中，存储器为动态随机存取存储器SDRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR3内存规格。
在一些实施例中，存储器为动态随机存取存储器SDRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR4或LPDDR4内存规格。
在一些实施例中，存储器为动态随机存取存储器SDRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR5或LPDDR5内存规格。
在一些实施例中，存储器为动态随机存取存储器SDRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合GDDR5或GDDR6内存规格。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (15)

  1. 一种本地放大电路，包括：
    写控制晶体管，被配置为，基于写使能信号，将全局数据线连接至本地数据线，并将互补全局数据线连接至互补本地数据线；
    列选择晶体管，被配置为，基于列选择信号，将位线连接至所述本地数据线，并将互补位线连接至所述互补本地数据线；
    第一控制NMOS管，栅极连接所述本地数据线，源极或漏极的其中一端连接所述全局数据线，另一端连接读控制晶体管；
    第二控制NMOS管，栅极连接所述互补本地数据线，源极或漏极的其中一端连接所述互补全局数据线，另一端连接所述读控制晶体管；
    预充电模块，连接所述本地数据线和所述互补本地数据线，用于将所述本地数据线和所述互补本地数据线预充电至第一预设电平，所述第一预设电平小于所述第一控制NMOS管的阈值电压，且小于所述第二控制NMOS管的阈值电压；
    所述读控制晶体管被配置为，基于读使能信号，将所述第一控制NMOS管和所述第二控制NMOS管与所述读控制晶体管相连的端子上拉/下拉至第二预设电平；
    所述第二预设电平与所述全局数据线和所述互补全局数据线的预充电电平相反。
  2. 根据权利要求1所述的本地放大电路，其中，所述第一预设电平为0。
  3. 根据权利要求2所述的本地放大电路，其中，所述预充电模块包括预充电MOS管，所述预充电MOS管的栅极用于接收预充电信号，源极或漏极的其中一端连接所述本地数据线和所述互补本地数据线，另一端接地。
  4. 根据权利要求1所述的本地放大电路，其中，所述全局数据线和所述互补全局数据线在数据读出前被预充的预充电电平为低电平，所述第二预设电平为高电平。
  5. 根据权利要求1所述的本地放大电路，其中，所述全局数据线和所述互补全 局数据线在数据读出前被预充的预充电电平为高电平，所述第二预设电平为低电平。
  6. 根据权利要求1所述的本地放大电路，其中，所述写控制晶体管包括：
    第一写MOS管，栅极用于接收所述写使能信号，源极连接所述全局数据线，漏极连接所述本地数据线；
    第二写MOS管，栅极用于接收所述写使能信号，源极连接所述互补全局数据线，漏极连接所述互补本地数据线。
  7. 根据权利要求6所述的本地放大电路，其中，所述第一写MOS管和所述第二写MOS管为PMOS。
  8. 根据权利要求1所述的本地放大电路，其中，所述列选择晶体管包括：
    第一列选择MOS管，栅极用于接收所述列选择信号，源极连接所述本地数据线，漏极连接所述位线；
    第二列选择MOS管，栅极用于接收所述列选择信号，源极连接所述互补本地数据线，漏极连接所述互补位线。
  9. 根据权利要求8所述的本地放大电路，其中，所述第一列选择MOS管和所述第二列选择MOS管为PMOS。
  10. 根据权利要求1所述的本地放大电路，其中，所述读控制晶体管包括：
    第一读MOS管，栅极用于接收所述读使能信号，源极连接所述第一控制NMOS管，漏极用于接收所述第一预设电平；
    第二读MOS管，栅极用于接收所述读使能信号，源极连接所述第二控制NMOS管，漏极用于接收所述第一预设电平。
  11. 一种数据读出方法，应用于权利要求1～10任一项所述的本地放大电路，包括：
    在读出阶段之前，将本地数据线和互补本地数据线预充电至第一预设电平，将全局数据线和互补全局数据线预充电至预充电电平；
    在读出阶段，提供读使能信号，当第一控制NMOS管导通，将所述全局数据线拉高/拉低至第二预设电平，当第二控制NMOS管导通，将所述互补全局数 据线拉高/拉低至第二预设电平；
    提供列选择信号，将位线电平同步至所述本地数据线，并将互补位线电平同步至所述互补本地数据线；
    其中，所述读使能信号的提供时刻不迟于所述全局数据线或所述互补全局数据线基于列选择信号发生电位变化的时刻。
  12. 根据权利要求11所述的数据读出方法，其中，所述读使能信号的提供时刻不迟于所述列选择信号的提供时刻。
  13. 根据权利要求12所述的数据读出方法，其中，所述读使能信号和所述列选择信号同时提供。
  14. 一种存储器，应用权利要求1～10任一项所述的本地放大电路进行数据的写入和读出。
  15. 根据权利要求14所述的存储器，其中，所述存储器包括：DRAM、SDRAM、DDR-SDRAM、DDR2-SDRAM、DDR3-SDRAM、DDR4-SDRAM、LPDDR4-SDRAM、DDR5-SDRAM、LPDDR5-SDRAM、GDDR5-SDRAM和GDDR6-SDRAM。
PCT/CN2022/078106 2022-01-14 2022-02-25 本地放大电路、数据读出方法和存储器 WO2023133974A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040037123A1 (en) * 2002-08-10 2004-02-26 Chang-Man Khang Integrated circuit devices including equalization/precharge circuits for improving signal transmission
CN113517882A (zh) * 2021-07-21 2021-10-19 北京百瑞互联技术有限公司 一种高速低功耗比较电路、转换器和电子设备
CN113760173A (zh) * 2020-06-05 2021-12-07 长鑫存储技术(上海)有限公司 读写转换电路以及存储器
CN113823342A (zh) * 2020-06-19 2021-12-21 长鑫存储技术(上海)有限公司 半导体集成电路以及存储器
CN113870911A (zh) * 2020-06-30 2021-12-31 长鑫存储技术(上海)有限公司 灵敏放大器、存储装置及读写方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040037123A1 (en) * 2002-08-10 2004-02-26 Chang-Man Khang Integrated circuit devices including equalization/precharge circuits for improving signal transmission
CN113760173A (zh) * 2020-06-05 2021-12-07 长鑫存储技术(上海)有限公司 读写转换电路以及存储器
CN113823342A (zh) * 2020-06-19 2021-12-21 长鑫存储技术(上海)有限公司 半导体集成电路以及存储器
CN113870911A (zh) * 2020-06-30 2021-12-31 长鑫存储技术(上海)有限公司 灵敏放大器、存储装置及读写方法
CN113517882A (zh) * 2021-07-21 2021-10-19 北京百瑞互联技术有限公司 一种高速低功耗比较电路、转换器和电子设备

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