WO2023133954A1 - 阵列基板、液晶显示面板及显示装置 - Google Patents

阵列基板、液晶显示面板及显示装置 Download PDF

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Publication number
WO2023133954A1
WO2023133954A1 PCT/CN2022/075867 CN2022075867W WO2023133954A1 WO 2023133954 A1 WO2023133954 A1 WO 2023133954A1 CN 2022075867 W CN2022075867 W CN 2022075867W WO 2023133954 A1 WO2023133954 A1 WO 2023133954A1
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WIPO (PCT)
Prior art keywords
side wall
electrode
wall
array substrate
away
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PCT/CN2022/075867
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English (en)
French (fr)
Inventor
吴云飞
李永凯
谭聪
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武汉华星光电技术有限公司
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Priority to US17/635,839 priority Critical patent/US20240036403A1/en
Publication of WO2023133954A1 publication Critical patent/WO2023133954A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to the field of virtual reality technology, and in particular to an array substrate, a liquid crystal display panel and a display device.
  • VR virtual reality
  • the display panel of VR display device has higher response speed and higher resolution (generally around 1000PPI).
  • VR display The electrodes of the display panel of the device are comb-shaped, which can obtain a better response time, but the transmittance of the comb-shaped electrodes is relatively low.
  • the transmittance of comb electrodes is relatively low.
  • the present application provides an array substrate with better response time and higher transmittance.
  • the present application also provides a liquid crystal display panel comprising the above electrodes.
  • the present application also provides a real display device comprising the above-mentioned liquid crystal display panel.
  • the present application provides an array substrate, including a driving circuit layer and a first electrode located on the driving circuit layer.
  • the driving circuit layer includes a plurality of scanning lines and a plurality of data lines; the extension direction of the scanning lines is defined as The first direction, the extension direction of the data line is the second direction, the second direction is perpendicular to the first direction;
  • the first electrode further includes a solid part; the solid part includes:
  • first side wall a first side wall, a second side wall, and a first bottom wall; one end of the first side wall and the second side wall is connected through the first bottom wall;
  • the line connecting the end of the first side wall far away from the second side wall to the end of the third side wall far away from the fourth side wall and the second side wall far away from the first side wall A line connecting one end of the fourth side wall to the end of the fourth side wall away from the third side wall extends along the first direction;
  • the shortest distance from the first bottom wall to the second bottom wall is defined as d1, from the end of the first side wall away from the second side wall to the third side wall away from the fourth side
  • the distance between one end of the wall is d2
  • the distance from one end of the second side wall away from the first side wall to the end of the fourth side wall away from the third side wall is d3, then d1 ⁇ d2 and d1 ⁇ d3.
  • the first electrode further includes a cavity located in the solid part, the first side wall, the second side wall, the third side wall, the first side wall
  • the four side walls, the first bottom wall and the second bottom wall are inner walls of the cavity.
  • the solid part further includes an outer wall, and the outer wall surrounds the first side wall, the second side wall, the third side wall and the fourth side A wall is provided, and the outer wall is the outer wall of the solid part.
  • the first electrode is a common electrode.
  • the first electrode is a pixel electrode.
  • a line connecting the end of the first side wall connected to the first bottom wall and the end of the third side wall connected to the second bottom wall is connected to the first side wall.
  • the included angle in one direction is greater than 0°.
  • the included angle between the first side wall and the second direction is defined as a first inclination angle ⁇ 1, and the included angle between the second side wall and the second direction
  • the angle is the second inclination angle ⁇ 2
  • the included angle between the third side wall and the second direction is the third inclination angle ⁇ 3
  • the included angle between the fourth side wall and the second direction is the fourth
  • the value ranges of the ⁇ 1, the ⁇ 2, the ⁇ 3 and the ⁇ 4 are all 3°-35°.
  • the value ranges of the ⁇ 1, the ⁇ 2, the ⁇ 3 and the ⁇ 4 are all 5°-15°.
  • the first side wall is parallel to the fourth side wall, and the second side wall is parallel to the third side wall;
  • the ⁇ 1 is equal to or not equal to the ⁇ 2, and the ⁇ 3 is equal to or not equal to the ⁇ 4.
  • the entity part further includes:
  • first bottom wall a first bottom wall, the two ends of the first bottom wall are respectively connected to the first side wall and the second side wall;
  • the second bottom wall, the two ends of the second bottom wall are respectively connected with the third side wall and the fourth side wall.
  • both the first bottom wall and the second bottom wall are planes parallel to the second direction or not parallel to the second direction.
  • both the first bottom wall and the second bottom wall are curved surfaces.
  • the entity part further includes:
  • the included angle between the fifth side wall and the second direction as the fifth inclination angle ⁇ 1
  • the included angle between the sixth side wall and the second direction as the sixth inclination angle ⁇ 2
  • the ⁇ 1 and the value range of ⁇ 2 are both 0°-90°.
  • the value ranges of the ⁇ 1 and the ⁇ 2 are both 45°-60°.
  • the entity part further includes:
  • the eighth side wall and the seventh side wall are located at two ends of the solid part.
  • the array substrate further includes a substrate and a second electrode disposed opposite to the first electrode, and the second electrode is located in the driving circuit layer or located in the driving circuit layer.
  • the driving circuit layer is located on the substrate, and the second electrode is located between the substrate and the first electrode.
  • the present application also provides a liquid crystal display panel, which includes a liquid crystal and a color filter substrate.
  • the liquid crystal display panel also includes the above-mentioned array substrate, and the liquid crystal is located between the color filter substrate and the array substrate.
  • the present application also provides a display device, which includes the above-mentioned liquid crystal display panel.
  • the shape of the first electrode is designed to have a first waist (consisting of a first side wall, a second side wall and a first bottom wall) and a second waist (consisting of the third side wall, the fourth side wall and the second bottom wall), and the shortest distance from the first waist to the second waist is smaller than the distance between the first side wall and the second side wall
  • the distance from one end to the end of the third side wall away from the fourth side wall is less than the distance from the end of the second side wall away from the first side wall to the fourth side wall away from the third side wall
  • the angle between the end of the first side wall close to the second side wall and the end of the third side wall close to the fourth side wall and the first direction is greater than 0° , making the first waist part and the second waist part asymmetrical, not only can increase the selectable range of the inclination angle of the first electrode, but also can avoid the mutual interference region of liquid crystal rotation disorder, reduce dark domains, and improve transmittance ; 3) Since the response time decreases with the increase of the electrode inclination angle and the penetration rate increases first and then decreases with the increase of the electrode inclination angle, therefore, the value of the inclination angle of the first electrode is set at 3°-35° In between, the transmittance of the display panel can be improved, and at the same time, it can have a better response time to meet the needs of the VR display device. 4) Since the first electrode provided by the application is a pixel electrode, the waist of the electrode shrinks, Therefore, the distance between two adjacent electrodes is increased, thereby reducing the risk of crosslinking of adjacent electrodes during
  • FIG. 1 is a block diagram of a virtual reality display device provided by a preferred embodiment of the present application.
  • FIG. 2 is a cross-sectional view of a liquid crystal display panel provided by a preferred embodiment of the present application.
  • FIG. 3 is a simplified layout diagram of a driving circuit of an array substrate shown.
  • FIG. 4 is a top view of a first electrode (pixel electrode) provided in the first embodiment of the present application.
  • FIG. 5 is a real topography diagram of the first electrode shown in FIG. 4 .
  • Fig. 6 is a simulated light effect diagram of comb electrodes in the prior art.
  • FIG. 7 is a simulated light effect diagram of the electrodes shown in FIG. 4 .
  • FIG. 8 is a top view of a first electrode (pixel electrode) provided in the second embodiment of the present application.
  • FIG. 9 is a top view of a first electrode (pixel electrode) provided by the third embodiment of the present application.
  • FIG. 10 is a top view of a first electrode (pixel electrode) provided by the fourth embodiment of the present application.
  • FIG. 11 is a top view of a first electrode (pixel electrode) provided in the fifth embodiment of the present application.
  • FIG. 12 is a top view of a first electrode (pixel electrode) provided in the sixth embodiment of the present application.
  • FIG. 13 is a top view of a first electrode (common electrode) provided by the seventh embodiment of the present application.
  • FIG. 14 is a top view of a first electrode (common electrode) provided in the eighth embodiment of the present application.
  • the present application also provides a display device 1000 , the display device 1000 includes the liquid crystal display panel 1200 and a main body 1100 , and the liquid crystal display panel 1200 is disposed on/in the main body 1100 .
  • the display device 1000 is a virtual reality (VR) display device.
  • VR virtual reality
  • the type of the display device 1000 is not limited to a VR display device.
  • the liquid crystal display panel 1200 includes an array substrate, a color filter substrate and a liquid crystal, and the liquid crystal is located between the array substrate and the color filter substrate.
  • the display mode of the liquid crystal display panel 1200 may be one of FFS mode, IPS mode and VA mode.
  • the display mode of the liquid crystal display panel 1200 is an FFS mode.
  • the array substrate includes a substrate, a driving circuit layer located above the substrate, and a first electrode and a second electrode formed on the driving circuit layer, and the second electrode is located on the driving circuit layer.
  • the position of the first electrode is opposite to the second electrode, and the first electrode and the second electrode are separated by an insulating layer.
  • the first electrode is located above the second electrode, that is, the first electrode is a top electrode (top electrode), and the second electrode is a bottom electrode (bottom electrode).
  • the first electrode When the first electrode is a common electrode, the second electrode is electrically connected to the driving circuit layer. When the first electrode is a pixel electrode, the first electrode is electrically connected to the driving circuit layer.
  • the second electrode when the first electrode is a pixel electrode, the second electrode is a common electrode, and the second electrode may also be disposed in the driving circuit layer.
  • the display mode of the liquid crystal display panel 1200 is an IPS mode
  • the first electrode and the second electrode of the array substrate are both arranged on the driving circuit layer and Located on the same floor.
  • the display mode of the liquid crystal display panel is VA mode
  • the first electrode of the array substrate is a pixel electrode and is formed on the driving circuit layer
  • the second electrode is located on the Inside the color filter substrate.
  • the structure of the liquid crystal display panel 1200 and the array substrate 1210 will be briefly described below by taking the structure of the liquid crystal display panel 1200 shown in FIG. 2 as an example.
  • the liquid crystal display panel 1200 includes an array substrate 1210 , a color filter substrate 1220 and a liquid crystal 1230 , and the liquid crystal 1230 is located between the array substrate 1210 and the color filter substrate 1220 .
  • the display mode of the liquid crystal display panel 1200 is the FFS mode
  • the array substrate 1210 includes a substrate 110, a driving circuit layer located above the substrate 110, and a first driving circuit layer formed on the driving circuit layer.
  • the first electrode 100 is a pixel electrode.
  • the driving circuit layer includes a plurality of driving transistors, and each driving transistor includes a gate 120 formed on the substrate 110, a gate formed on the substrate 110 and covering the gate 120.
  • the second electrode 130 is formed on the substrate 110 and covered by the gate insulating layer 140
  • the first electrode 100 is formed on the planar layer 180 and is opposite to the second electrode 130 .
  • the array substrate 1210 further includes a plurality of scanning lines 121 and a plurality of data lines 161.
  • the scanning lines 121 are arranged on the same layer as the gate 120 and 120
  • the data line 161 is provided on the same layer as the source and drain electrodes 160 and is electrically connected to the source and drain electrodes 160 .
  • the scan line 121 is used to provide a scan signal to the drive transistor
  • the data line 161 is used to provide a data signal to the drive transistor.
  • a plurality of scanning lines 151 and a plurality of data lines 161 are arranged in an array, a plurality of scanning lines 151 are arranged along rows, a plurality of data lines 161 are arranged along columns, a plurality of scanning lines 151 and a plurality of data lines 161 constitute a plurality of pixel units, one
  • the pixel unit has at least one driving transistor, one first electrode 100 and one second electrode 130 , the first electrode 100 is a pixel electrode, and the second electrode 130 is a common electrode.
  • the first electrode 100 is opposite to the second electrode 130 to form an electric field for driving the liquid crystal 1230 to deflect.
  • the structure of the array substrate 1210 is not limited to the structure described above.
  • the first electrode 100 is fish-like
  • the second electrode 130 is a sheet electrode
  • one common electrode may correspond to one or more pixel electrodes.
  • the extending direction of the scan lines 121 is defined as a first direction Y1, and the extending direction of the data lines 161 is defined as a second direction Y2.
  • the first electrode 100 includes a solid part 10 .
  • the first electrode 100 is a pixel electrode, that is, the first electrode 100 only includes the solid portion 10 .
  • the solid portion 10 includes a first surface 1001 and a second surface (not shown) opposite to the first surface 1001 , and the second surface is in contact with the planar layer 180 .
  • the distance between the first surface 1001 and the second surface is the thickness of the solid part 10 (the first electrode 100 ).
  • the solid part 10 also includes a first side wall 11, a second side wall 12, a third side wall 13, a fourth side wall 14, a first bottom wall 31 and a second bottom wall 32.
  • the first side wall 11, the second side wall 12, the third side wall 13 and the fourth side wall 14 are respectively connected to the first surface 1001 and are at different positions from the first surface 1001. face.
  • One end of the first side wall 11 and the second side wall 12 is connected through the first bottom wall 31 to form a first waist 101 of the first electrode 100, and the third side wall 13 and the The fourth side wall 14 is connected by the second bottom wall 32 to form the second waist 102 of the first electrode 100 .
  • the line connecting the end of the first side wall 11 away from the second side wall 12 to the end of the third side wall 13 away from the fourth side wall 14 extends along the first direction Y1, so A line connecting the end of the second side wall 12 away from the first side wall 11 to the end of the fourth side wall 14 away from the third side wall 13 extends along the first direction Y1.
  • the shortest distance defining the first waist 101 to the second waist 102 is d1
  • the distance between one end of the fourth side wall 14 is d2
  • the distance from one end of the second side wall 12 away from the first side wall 11 to the end of the fourth side wall 14 away from the third side wall 13 is d3, then d1 ⁇ d2 and d1 ⁇ d3.
  • the d2 may be equal to or not equal to the d3.
  • the d2 is equal to the d3.
  • first bottom wall 31 and the second bottom wall 32 are planes parallel to each other.
  • the first bottom wall 31 and the second bottom wall 32 respectively extend along the second direction Y2.
  • the shortest distance d1 from the first waist portion 101 to the second waist portion 102 is the vertical distance between the first bottom wall 31 and the second bottom wall 32 .
  • first bottom wall 31 and the second bottom wall 32 are parallel, and the first bottom wall 31 and the second bottom wall 32 are not along the The second direction Y2 extends.
  • the first side wall 11 and the third side wall 13 are bilaterally symmetrical.
  • the second side wall 12 and the fourth side wall 14 are bilaterally symmetrical.
  • connection between the first side wall 11 and the second side wall 12 and the first bottom wall 31 and the connection between the third side wall 13 and the fourth side wall 14 and the The connection of the second bottom wall 32 is a smooth connection, that is, the intersection of the first side wall 11 and the second side wall 12 with the first bottom wall 31 and the third side wall 13 respectively And the joints between the fourth side wall 14 and the second bottom wall 32 do not form a sharp corner.
  • the joints between the first side wall 11 and the second side wall 12 and the first bottom wall 31 and the third side wall 13 and the The joints between the fourth side wall 14 and the second bottom wall 32 may also form a sharp angle, that is, the connection may not be smooth.
  • first sidewall 11 , the second sidewall 12 , the third sidewall 13 and the fourth sidewall 14 are all vertically connected to the first surface 1001 .
  • the angle between the first side wall 11 and the second direction Y2 is defined as the first inclination angle ⁇ 1
  • the angle between the second side wall 12 and the second direction Y2 is defined as the second angle ⁇ 1.
  • Inclination angle ⁇ 2 the included angle between the third side wall 13 and the second direction Y2 is a third inclination angle ⁇ 3, and the included angle between the fourth side wall 14 and the second direction Y2 is a fourth Inclination angle ⁇ 4.
  • the ⁇ 1 , the ⁇ 2 , the ⁇ 3 and the ⁇ 4 are the inclination angles of the first electrode 100 .
  • the value ranges of the ⁇ 1, the ⁇ 2, the ⁇ 3 and the ⁇ 4 are all 3°-35°.
  • the value ranges of the ⁇ 1, the ⁇ 2, the ⁇ 3 and the ⁇ 4 are all 5°-15°.
  • the value range of the inclination angle is set between 3°-35°, which can reduce the invalid electric field component and electric field disorder area while taking into account the corresponding time, and reduce the area of the dark area displayed, thereby improving the transmittance.
  • the ⁇ 1 is equal to the ⁇ 3.
  • the ⁇ 2 is equal to the ⁇ 4.
  • the solid portion 10 further includes a fifth side wall 15 and a sixth side wall 16 .
  • the fifth side wall 15 is connected to the first surface 1001 and is connected to an end of the first side wall 11 away from the second side wall 12, and the sixth side wall 16 is connected to the first side wall 1001.
  • a surface 1001 is connected to and connected to an end of the third sidewall 13 away from the fourth sidewall 14 .
  • the fifth sidewall 15 and the sixth sidewall 16 constitute shoulders of the first electrode 100 .
  • ends of the fifth sidewall 15 and the sixth sidewall 16 that are far away from the first sidewall 11 and the third sidewall 13 are inclined opposite to each other. That is, the distance between the end of the fifth side wall 15 away from the first side wall 11 and the end of the sixth side wall 16 away from the third side wall 13 is greater than the d2.
  • connection between the fifth side wall 15 and the first side wall 11 is a smooth connection, that is, the junction between the fifth side wall 15 and the first side wall 11 is not form a sharp corner.
  • connection between the sixth side wall 16 and the third side wall 13 is smooth, that is, the intersection of the sixth side wall 16 and the third side wall 13 does not form a sharp corner.
  • the angle between the fifth side wall 15 and the second direction Y2 is defined as the fifth inclination angle ⁇ 1
  • the angle between the sixth side wall 16 and the second direction Y2 is the sixth angle.
  • the value ranges of the ⁇ 1 and the ⁇ 2 are both 0°-90°.
  • the value ranges of the ⁇ 1 and the ⁇ 2 are both 45°-60°.
  • setting the value range of the ⁇ 1 and the ⁇ 2 to 0°-90° can avoid the excessive angle between the fifth side wall 15 and the first side wall 11 (ie Avoid forming an anhedral angle between the fifth side wall 15 and the first side wall 11, the existence of the anhedral will produce dark chips, dark chips will reduce the transmittance of the electrode), and thus To avoid the loss of the transmittance of the first electrode 100 due to dark chips.
  • the fifth side wall 15 and the sixth side wall 16 may be left-right symmetrical or left-right asymmetrical.
  • the fifth side wall 15 and the sixth side wall 16 may be left-right symmetry.
  • the left-right asymmetry here refers to the connecting line between the ends of the fifth side wall 15 and the sixth side wall 16 far away from the first side wall 11 and the third side wall 13 and the first side wall 16 . Asymmetry caused when the angle between Y1 in one direction is greater than 0.
  • the ⁇ 1 and the ⁇ 2 may satisfy: ⁇ 2.
  • the fifth side wall 15 and the sixth side wall 16 are left-right asymmetric.
  • the distance between the ends of the fifth side wall 15 and the sixth side wall 16 away from the first side wall 11 and the third side wall 13 is greater than the d2 .
  • the solid portion 10 further includes a seventh side wall 17, the seventh side wall 17 is connected to the first surface 1001, the fifth side wall 15 and the sixth side wall respectively. 16 connections.
  • the seventh sidewall 17 constitutes the head of the first electrode 100 .
  • connection between the seventh side wall 17 and the fifth side wall 15 and the sixth side wall 16 is a smooth connection, that is, the seventh side wall 17 and the fifth side wall 17 are connected smoothly.
  • the intersection of the side wall 15 and the sixth side wall 16 does not form a sharp angle.
  • the seventh side wall 17 is a curved surface composed of three side walls. In other embodiments, the seventh side wall 17 may also be a plane composed of one side wall or a curved surface composed of two or more than three side walls.
  • the solid portion 10 further includes an eighth side wall 18 , and the eighth side wall 18 is connected to the first surface 1001 , the second side wall 12 and the fourth side wall respectively. 14 , the seventh side wall 17 and the eighth side wall 18 are located at both ends of the solid part 10 .
  • the eighth side wall 18 may also be a plane composed of one side wall. In other embodiments, the eighth side wall 18 may also be a curved surface composed of at least two side walls.
  • connection between the eighth side wall 18 and the second side wall 12 and the fourth side wall 14 is a smooth connection, that is, the eighth side wall 18 and the second No sharp corner is formed at the intersection of the side wall 12 and the fourth side wall 14 .
  • the first electrode 100 also includes a connection terminal 19, the connection terminal 19 is formed on the solid part 10, and the connection terminal 19 is used as the signal output or input of the first electrode 100 port.
  • the connecting terminal 19 is located adjacent to the seventh side wall 17 .
  • Fig. 5 is the real topography diagram of the electrode shown in Fig. 4
  • Fig. 6 is the simulated light effect diagram of the comb electrode in the prior art
  • Fig. 7 is provided by the present application The simulated light effect diagram of the electrode. It can be seen from Fig. 6 and Fig. 7 that the optical efficiency of the first electrode 100 provided by the present application shown in Fig. 7 is better than that of the comb electrode shown in Fig. The transmittance is higher than that of the comb electrodes.
  • the light efficiency of the first electrode 100 provided by the present application is more than 50% better than that of the comb electrode in the prior art, that is, the light efficiency of the first electrode 100 provided by the present application
  • the transmittance is higher than that of the comb electrodes in the prior art.
  • the second embodiment of the present application also provides a first electrode 200 , the structure of the first electrode 200 is similar to that of the first electrode 100 , the difference is that the first electrode 200 The distance between the ends of the fifth sidewall 21 and the sixth sidewall 22 away from the first sidewall 11 and the third sidewall 13 is smaller than the d2, that is, the first electrode 200 of the first electrode 200 The fifth sidewall 21 and the sixth sidewall 22 are inclined to each other.
  • the seventh sidewall 17 of the first electrode 200 is a curved surface composed of five sidewalls.
  • the distance from the end of the fifth side wall 21 and the sixth side wall 22 of the first electrode 200 away from the first side wall 11 and the third side wall 13 may also be equal to The d2, that is, the seventh side wall 17 of the first electrode 200 is a plane.
  • the third embodiment of the present application also provides a first electrode 300, the structure of the first electrode 300 is similar to that of the second electrode 200, the only difference is that the first electrode 300
  • the first bottom wall 31 and the second bottom wall 32 are not parallel, and neither the first bottom wall 31 nor the second bottom wall 32 extends along the second direction Y2.
  • the ends of the first bottom wall 31 and the second bottom wall 32 of the first electrode 300 respectively connected to the second side wall 12 and the fourth side wall 14 are inclined towards each other. That is, the distance between the end of the first side wall 31 connected to the second side wall 12 and the end of the second bottom wall 32 connected to the fourth side wall 14 is smaller than that of the first bottom wall 31 The distance between the end connected to the first side wall 11 and the end connected to the third side wall 13 of the second bottom wall 32 .
  • the fourth embodiment of the present application also provides a first electrode 400 , the structure of the first electrode 400 is similar to that of the second electrode 200 , the only difference is that the first electrode 400
  • the first bottom wall 31 and the second bottom wall 32 are not parallel, and one of the first bottom wall 31 and the second bottom wall 32 does not extend along the second direction Y2, and the other one extends along the second direction Y2.
  • the second direction Y2 extends.
  • the fifth embodiment of the present application also provides a first electrode 500, the structure of the first electrode 500 is similar to that of the second electrode 200, the only difference is that the first electrode 500
  • the first bottom wall 31 and the second bottom wall 32 are curved surfaces.
  • the curved surface may be a curved surface including at least two side walls, or an arc surface.
  • the sixth embodiment of the present application also provides a first electrode 600, the structure of the first electrode 600 is similar to that of the second electrode 200, the only difference is that the first side wall The angle ⁇ 1 between the end of 11 connected to the first bottom wall 31 and the end of the third side wall 13 connected to the second bottom wall 32 and the first direction Y1 is greater than 0°. That is, the first waist 101 and the second waist 102 of the first electrode 600 are asymmetrical.
  • the connecting line between the end of the second side wall 12 connected to the first bottom wall 31 and the end of the fourth side wall 14 connected to the second bottom wall 32 is connected to the first bottom wall 32 .
  • the included angle ⁇ 2 in one direction Y1 is greater than 0°.
  • the ⁇ 2 may be equal to or not equal to the ⁇ 1. In this embodiment, the ⁇ 2 is equal to the ⁇ 1.
  • the first electrode 600 has the first set of inclination angles and the second set of inclination angles, which not only increases the possibility of the inclination angle of the first electrode 600
  • the range of selection can also avoid the mutual interference area of liquid crystal rotation disorder, reduce dark domains, and improve transmittance.
  • the seventh embodiment of the present application also provides a first electrode 700 , the structure of the first electrode 700 is similar to that of the first electrode 200 , the only difference is that the first electrode 700 is a common electrode, and the first electrode 200 is a pixel electrode.
  • a cavity 103 is formed in the solid part 10 of the first electrode 700, the first side wall 11, the second side wall 12, the third side wall 13, the fourth side wall 14, the The first bottom wall 31 and the second bottom wall 32 are inner walls of the cavity.
  • the fifth side wall 15 , the sixth side wall 16 , the seventh side wall 17 and the eighth side wall 18 are also inner walls of the cavity 103 .
  • the solid part 10 of the first electrode 300 further includes an outer side wall 23, and the outer side wall 23 surrounds the first side wall 11, the second side wall 12, the third side wall 13, the fourth side wall
  • the side wall 14 , the fifth side wall 15 , the sixth side wall 16 , the seventh side wall 17 and the eighth side wall 18 are provided and are outer walls of the solid part 10 .
  • the cavity 103 is in a fish-like shape.
  • the eighth embodiment of the present application also provides a first electrode 800, the structure of the first electrode 800 is similar to that of the first electrode 700, the difference is that the first electrode 800
  • the angle between the line connecting the end of the first side wall 11 connected to the first bottom wall 31 and the end of the third side wall 13 connected to the second bottom wall 32 and the first direction Y1 ⁇ 1 is greater than 0°. That is, the first waist 101 and the second waist 102 of the first electrode 800 are asymmetrical.
  • the connecting line between the end of the second side wall 12 connected to the first bottom wall 31 and the end of the fourth side wall 14 connected to the second bottom wall 32 is connected to the first bottom wall 32 .
  • the included angle ⁇ 2 in one direction Y1 is greater than 0°.
  • the ⁇ 2 may be equal to or not equal to the ⁇ 1. In this embodiment, the ⁇ 2 is equal to the ⁇ 1.
  • the first side wall 11 is parallel to the fourth side wall 14, and the second side wall 12 is parallel to the third side wall 13;
  • the ⁇ 1 and the ⁇ 4 is the first group of inclination angles of the first electrode 100, and the ⁇ 2 and the ⁇ 3 are the second group of inclination angles of the first electrode 100;
  • the ⁇ 1 may be equal to or not equal to the ⁇ 2
  • the ⁇ 3 may be equal to or not equal to the ⁇ 4.
  • the first electrode 800 has the first set of inclination angles and the second set of inclination angles, which not only increases the possibility of the inclination angle of the first electrode 800
  • the range of selection can also avoid the mutual interference area of liquid crystal rotation disorder, reduce dark domains, and improve transmittance.
  • the present application also provides the first electrode (common electrode) whose inner wall shape of the cavity is the same as the outer wall shape of the first electrode in Embodiment 1, Embodiment 3, Embodiment 4, and Embodiment 5, and it is not mentioned here one by one. Repeatedly.
  • the shape of the first electrode is designed to have a first waist (consisting of a first side wall, a second side wall and a first bottom wall) and a second waist (consisting of the third side wall, the fourth side wall and the second bottom wall), and the shortest distance from the first waist to the second waist is smaller than the distance between the first side wall and the second side wall
  • the distance from one end to the end of the third side wall away from the fourth side wall is less than the distance from the end of the second side wall away from the first side wall to the fourth side wall away from the third side wall
  • the angle between the end of the first side wall close to the second side wall and the end of the third side wall close to the fourth side wall and the first direction is greater than 0° , making the first waist part and the second waist part asymmetrical, not only can increase the selectable range of the inclination angle of the first electrode, but also can avoid the mutual interference region of liquid crystal rotation disorder, reduce dark domains, and improve transmittance ; 3) Since the response time decreases with the increase of the electrode inclination angle and the penetration rate increases first and then decreases with the increase of the electrode inclination angle, therefore, the value of the inclination angle of the first electrode is set at 3°-35° In between, the transmittance of the display panel can be improved, and at the same time, it can have a better response time to meet the needs of the VR display device. 4) Since the first electrode provided by the application is a pixel electrode, the waist of the electrode shrinks, Therefore, the distance between two adjacent electrodes is increased, thereby reducing the risk of crosslinking of adjacent electrodes during

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Abstract

一种阵列基板(1210)，阵列基板(1210)包括第一电极(100,200,300,400,500,600,700,800)，第一电极(100,200,300,400,500,600,700,800)包括第一侧壁(11)、第二侧壁(12)、第三侧壁(13)和第四侧壁(14)及第一底壁(31)和第二底壁(32)；第三侧壁(13)与第四侧壁(14)的一端通过第二底壁(32)连接；第一底壁(31)到第二底壁(32)的最短距离为d1，第一侧壁(11)远离第二侧壁(12)的一端到第三侧壁(13)远离第四侧壁(14)的一端的距离为d2，第二侧壁(12)远离第一侧壁(11)的一端到第四侧壁(14)远离第三侧壁(13)的一端的距离为d3，d1＜d2，d1＜d3。

Description

阵列基板、液晶显示面板及显示装置 技术领域
本申请涉及虚拟现实技术领域，尤其涉及一种阵列基板、液晶显示面板及显示装置。
 背景技术
虚拟现实(virtual reality，VR)技术在显示技术中的发展是比较有竞争力的，VR显示装置的显示面板具有更高的响应速度和更高的分辨率(一般在1000PPI左右)，目前VR显示装置的显示面板的电极呈梳状，可以获得较好的响应时间，但梳状电极的透过率相对较低。
 技术问题
梳状电极的透过率相对较低。
 技术解决方案
有鉴于此，本申请提供一种具有较好响应时间及较高透过率的阵列基板。
本申请还提供一种包括上述电极的液晶显示面板。
本申请还提供一种包括上述液晶显示面板的现实显示装置。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括驱动电路层及位于所述驱动电路层上的第一电极，所述驱动电路层包括多条扫描线及多条数据线；定义所述扫描线的延伸方向为第一方向，所述数据线的延伸方向为第二方向，所述第二方向垂直于所述第一方向；所述第一电极还包括实体部；所述实体部包括：
第一侧壁、第二侧壁及第一底壁；所述第一侧壁与所述第二侧壁的一端通过所述第一底壁连接；及
第三侧壁、第四侧壁及第二底壁；所述第三侧壁与所述第四侧壁的一端通过所述第二底壁连接；
其中，所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的连线以及所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的连线均沿所述第一方向延伸；
其中，定义所述第一底壁到所述第二底壁的最短距离为d1，所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的距离为d2，所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的距离为d3，则d1<d2且d1<d3。
在本申请一可选实施例中，所述第一电极还包括位于所述实体部内的空腔，所述第一侧壁、所述第二侧壁、所述第三侧壁、所述第四侧壁、所述第一底壁及所述第二底壁为所述空腔的内壁。
在本申请一可选实施例中，所述实体部还包括外侧壁，所述外侧壁环绕所述第一侧壁、所述第二侧壁、所述第三侧壁及所述第四侧壁设置，所述外侧壁为所述实体部的外壁。
在本申请一可选实施例中，所述第一电极为公共电极。
在本申请一可选实施例中，所述第一电极为像素电极。
在本申请一可选实施例中，所述第一侧壁与所述第一底壁连接的一端与所述第三侧壁与所述第二底壁连接的一端的连线与所述第一方向的夹角大于0°。
在本申请一可选实施例中，定义所述第一侧壁与所述第二方向之间的夹角为第一倾角θ1，所述第二侧壁与所述第二方向之间的夹角为第二倾角θ2，所述第三侧壁与所述第二方向之间的夹角为第三倾角θ3，所述第四侧壁与所述第二方向之间的夹角为第四倾角θ4，所述θ1、所述θ2、所述θ3及所述θ4的取值范围均为3°-35°。
在本申请一可选实施例中，所述θ1、所述θ2、所述θ3及所述θ4的取值范围均为5°-15°。
在本申请一可选实施例中，所述第一侧壁平行于所述第四侧壁，所述第二侧壁平行于所述第三侧壁；所述θ1和θ4为所述第一电极的第一倾角，所述θ2和θ3为所述第一电极的第二倾角；所述θ1、所述θ2、所述θ3及所述θ4满足：θ1=θ4且θ2=θ3。
在本申请一可选实施例中，所述θ1等于或不等于所述θ2，所述θ3等于或不等于所述θ4。
在本申请一可选实施例中，θ1≠θ4且θ2≠θ3。
在本申请一可选实施例中，所述实体部还包括：
第一底壁，所述第一底壁的两端分别与所述第一侧壁及所述第二侧壁连接；及
第二底壁，所述第二底壁的两端分别与所述第三侧壁及所述第四侧壁连接。
在本申请一可选实施例中，所述第一底壁及所述第二底壁均为平行于所述第二方向或不平行于所述第二方向的平面。
在本申请一可选实施例中，所述第一底壁及所述第二底壁均为曲面。
在本申请一可选实施例中，所述实体部还包括：
第五侧壁，与所述第一侧壁的远离所述第二侧壁的一端相连接；及
第六侧壁，与所述第三侧壁的远离所述第四侧壁的一端相连接；
定义所述第五侧壁与所述第二方向之间的夹角为第五倾角β1，所述第六侧壁与所述第二方向之间的夹角为第六倾角β2，所述β1和所述β2的取值范围均为0°-90°。
在本申请一可选实施例中，所述β1和所述β2的取值范围均为45°-60°。
在本申请一可选实施例中，所述实体部还包括：
第七侧壁，分别与所述第五侧壁和所述第六侧壁连接；及
第八侧壁，分别与所述第二侧壁和所述第四侧壁连接；
其中，所述第八侧壁与所述第七侧壁位于所述实体部的两端。
在本申请一可选实施例中，所述阵列基板还包括衬底及与所述第一电极相对设置的第二电极，所述第二电极位于所述驱动电路层之内或位于所述驱动电路层之上，所述驱动电路层位于所述衬底上，所述第二电极位于所述衬底与所述第一电极之间。
本申请还提供一种液晶显示面板，包括液晶和彩膜基板，所述液晶显示面板还包括如上所述的阵列基板，所述液晶位于所述彩膜基板和所述阵列基板之间。
本申请还提供一种显示装置，所述显示装置包括如上所述的液晶显示面板。
 有益效果
本申请提供的阵列基板、液晶显示面板及显示装置，1)将第一电极的形状设计成：具有第一腰部(由第一侧壁、第二侧壁及第一底壁构成)和第二腰部(由第三侧壁、第四侧壁及第二底壁构成)，且所述第一腰部到所述第二腰部的最短距离小于所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的距离且小于所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的距离，从而得到类鱼形电极，通过改变第一电极的形状可以减少无效电场分量和电场紊乱区域，进而降低显示暗区的面积，从而在兼顾响应时间的同时，提升穿透率。2)所述第一侧壁的靠近所述第二侧壁的一端与所述第三侧壁的靠近所述第四侧壁的一端的连线与所述第一方向的夹角大于0°，使得所述第一腰部与所述第二腰部不对称，不仅能够增加所述第一电极的倾角可选择范围，还能够避开液晶旋转紊乱相互干扰区，减小暗畴，提升透过率；3)由于响应时间会随着电极倾角增大而减小且穿透率随着电极倾角增大先上升再下降，因此，将第一电极的倾角的取值设定在3°-35°之间，既能够提升显示面板的穿透率，同时又能具有较好响应时间，以满足VR显示装置的需求，4)由于本申请提供的第一电极为像素电极时，电极的腰部收缩，从而增大了相邻两个电极之间的距离，从而可以降低相邻电极在曝光显影制程中发生交联的风险。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请较佳实施例提供的一种虚拟现实显示装置的模块示意图。
图2为本申请较佳实施例提供的一种液晶显示面板的剖视图。
图3为所示的一种阵列基板的驱动电路的简化layout图。
图4为本申请第一实施例提供的一种第一电极(像素电极)的俯视图。
图5为图4所示的第一电极的真实形貌图。
图6为现有技术中的梳状电极的仿真光效图。
图7为图4所示的电极的仿真光效图。
图8为本申请第二实施例提供的一种第一电极(像素电极)的俯视图。
图9为本申请第三实施例提供的一种第一电极(像素电极)的俯视图。
图10为本申请第四实施例提供的一种第一电极(像素电极)的俯视图。
图11为本申请第五实施例提供的一种第一电极(像素电极)的俯视图。
图12为本申请第六实施例提供的一种第一电极(像素电极)的俯视图。
图13为本申请第七实施例提供的一种第一电极(公共电极)的俯视图。
图14为本申请第八实施例提供的一种第一电极(公共电极)的俯视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体地限定。
本申请可以在不同实施中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
以下将结合具体实施例及附图对本申请提供的阵列基板、液晶显示面板及显示装置进行详细描述。
请参阅图1，本申请还提供一种显示装置1000，所述显示装置1000包括所述液晶显示面板1200及主体部1100，所述液晶显示面板1200设置在所述主体部1100上/内。
在本申请一可选实施例中，所述显示装置1000为虚拟现实(VR)显示装置。当然，在其他实施例中，所述显示装置1000的种类并不局限于VR显示装置。
其中，所述液晶显示面板1200包括阵列基板、彩膜基板及液晶，所述液晶位于所述阵列基板及彩膜基板之间。
其中，所述液晶显示面板1200的显示模式可以为FFS模式、IPS模式及VA模式中的一种。
在本申请一可选实施例中，所述液晶显示面板1200的显示模式为FFS模式。具体地，所述阵列基板包括衬底、位于所述衬底上方的驱动电路层及形成在所述驱动电路层上的第一电极和第二电极，所述第二电极位于所述驱动电路层上，所述第一电极与所述第二电极位置相对，所述第一电极与所述第二电极之间通过一绝缘层间隔开来。所述第一电极位于所述第二电极上方，也即，所述第一电极为顶部电极(top电极)，所述第二电极为底部电极(bottom电极)。
当所述第一电极为公共电极时，所述第二电极与所述驱动电路层电连接。当所述第一电极为像素电极时，所述第一电极与所述驱动电路层电连接。
在其他实施例中，当所述第一电极为像素电极时，所述第二电极为公共电极，所述第二电极还可以设置在所述驱动电路层内。
在本申请另一可选实施例中，所述液晶显示面板1200的显示模式为IPS模式，所述阵列基板的所述第一电极及所述第二电极均设置在所述驱动电路层上且位于同一层。
在本申请另一可选实施例中，所述液晶显示面板的显示模式为VA模式，所述阵列基板的第一电极为像素电极且形成在所述驱动电路层上，所述第二电极位于所述彩膜基板内。
具体地，请参阅图2，下面将以图2所示的液晶显示面板1200的结构为例，简单描述所述液晶显示面板1200和所述阵列基板1210的结构。
在图2中，所述液晶显示面板1200包括阵列基板1210、彩膜基板1220及液晶1230，所述液晶1230位于所述阵列基板1210及彩膜基板1220之间。
在图2中，所述液晶显示面板1200的显示模式为FFS模式，所述阵列基板1210包括衬底110、位于所述衬底110上方的驱动电路层、形成在所述驱动电路层上的第一电极100及形成在所述驱动电路层内的第二电极130，所述第一电极100与所述第二电极130位置相对，所述第一电极100位于所述第二电极130上方，所述第一电极100与所述第二电极130之间绝缘。在本实施例中，所述第一电极100为像素电极。
其中，所述驱动电路层包括多个驱动晶体管，每个所述驱动晶体管包括形成在所述衬底110上的栅极120、形成在所述衬底110上且覆盖所述栅极120的栅极绝缘层140、形成在所述栅极绝缘层140上且与所述栅极120位置相对的有源层150、形成在所述栅极绝缘层140且分别与所述有源层150电连接的源漏极160、形成在所述栅极绝缘层140上且覆盖所述源漏极160及从所述源漏极160中裸露出来的所述有源层150的钝化层170及形成在所述钝化层170上的平坦层180。所述第二电极130形成在所述衬底110上且被所述栅极绝缘层140覆盖，所述第一电极100形成在所述平坦层180上且与所述第二电极130位置相对。
请参阅图3，在本实施例中，所述阵列基板1210还包括多条扫描线121和多条数据线161，所述扫描线121与所述栅极120同层设置且与所述栅极120电连接，所述数据线161与所述源漏极160同层设置且与所述源漏极160电连接。所述扫描线121用于为所述驱动晶体管提供扫描信号，所述数据线161用于为所述驱动晶体管提供数据信号。多条扫描线151和多条数据线161阵列设置，多条扫描线151沿行设置，多条数据线161沿列设置，多条扫描线151和多条数据线161构成多个像素单元，一个所述像素单元内具有至少一个所述驱动晶体管、一个所述第一电极100及一个所述第二电极130，所述第一电极100为像素电极，所述第二电极130为公共电极。所述第一电极100与所述第二电极130位置相对，以形成驱动所述液晶1230偏转的电场。
当然，在其他实施例中，所述阵列基板1210的结构并不局限于如上所述的结构。
在本实施例中，所述第一电极100呈类鱼形，所述第二电极130为片状电极，一个所述公共电极可以对应一个或多个像素电极。
定义所述扫描线121的延伸方向为第一方向Y1，所述数据线161的延伸方向为第二方向Y2。
请参阅图4，所述第一电极100包括实体部10。在本实施例中，所述第一电极100为像素电极，也即，所述第一电极100只包括所述实体部10。
具体地，所述实体部10包括一第一表面1001及一与所述第一表面1001相背的第二表面(图未示)，所述第二表面与所述平坦层180相接触。所述第一表面1001和所述第二表面之间的距离为所述实体部10(所述第一电极100)的厚度。
具体地，所述实体部10还包括一第一侧壁11、一第二侧壁12、一第三侧壁13、一第四侧壁14、一第一底壁31及一第二底壁32。所述第一侧壁11、所述第二侧壁12、所述第三侧壁13及所述第四侧壁14分别与所述第一表面1001连接且与所述第一表面1001处于不同的面上。所述第一侧壁11与所述第二侧壁12的一端通过所述第一底壁31连接，以形成所述第一电极100的第一腰部101，所述第三侧壁13与所述第四侧壁14通过所述第二底壁32相连接，以形成所述第一电极100的第二腰部102。
其中，所述第一侧壁11远离所述第二侧壁12的一端到所述第三侧壁13远离所述第四侧壁14的一端的连线沿所述第一方向Y1延伸，所述第二侧壁12远离所述第一侧壁11的一端到所述第四侧壁14远离所述第三侧壁13的一端的连线沿所述第一方向Y1延伸。
其中，定义所述第一腰部101到所述第二腰部102的最短距离为d1，所述第一侧壁11远离所述第二侧壁12的一端到所述第三侧壁13远离所述第四侧壁14的一端的距离为d2，所述第二侧壁12远离所述第一侧壁11的一端到所述第四侧壁14远离所述第三侧壁13的一端的距离为d3，则d1<d2且d1<d3。
其中，所述d2可以等于或不等于所述d3。在本实施例中，所述d2等于所述d3。
在本实施例中，所述第一底壁31及所述第二底壁32为相互平行的平面。
具体地，在本申请一可选实施例中，所述第一底壁31及所述第二底壁32分别沿所述第二方向Y2延伸。此时，所述第一腰部101到所述第二腰部102的最短距离d1即为所述第一底壁31及所述第二底壁32之间的垂直距离。
具体地，在本申请另一可选实施例中，所述第一底壁31及所述第二底壁32平行，且所述第一底壁31及所述第二底壁32不沿所述第二方向Y2延伸。
在本申请一可选实施例中，所述第一侧壁11与所述第三侧壁13左右对称。
在本申请一可选实施例中，所述第二侧壁12与所述第四侧壁14左右对称。
在本实施例中，所述第一侧壁11及所述第二侧壁12与所述第一底壁31的连接以及所述第三侧壁13和所述第四侧壁14与所述第二底壁32的连接均是平滑连接，也即，所述第一侧壁11及所述第二侧壁12分别与所述第一底壁31的交接处以及所述第三侧壁13及所述第四侧壁14分别与所述第二底壁32的交接处均未形成一尖角。
当然，在其他实施例中，如果工艺允许，所述第一侧壁11及所述第二侧壁12分别与所述第一底壁31的交接处以及所述第三侧壁13及所述第四侧壁14分别与所述第二底壁32的交接处也可以形成一尖角，也即可以不是平滑连接。
在本实施例中，所述第一侧壁11、所述第二侧壁12、所述第三侧壁13及所述第四侧壁14均与所述第一表面1001垂直连接。
其中，定义所述第一侧壁11与所述第二方向Y2之间的夹角为第一倾角θ1，所述第二侧壁12与所述第二方向Y2之间的夹角为第二倾角θ2，所述第三侧壁13与所述第二方向Y2之间的夹角为第三倾角θ3，所述第四侧壁14与所述第二方向Y2之间的夹角为第四倾角θ4。其中，所述θ1、所述θ2、所述θ3及所述θ4均为所述第一电极100的倾角。
其中，所述θ1、所述θ2、所述θ3及所述θ4的取值范围均为3°-35°。优选地，所述θ1、所述θ2、所述θ3及所述θ4的取值范围均为5°-15°。
由于响应时间会随着电极倾角增大而减小且穿透率随着电极倾角增大先上升再下降，考虑响应时间和穿透率与电极倾角之间的关系，本申请将所述第一倾角的取值范围设定在3°-35°之间，可以在兼顾相应时间的同时，减少无效电场分量和电场紊乱区域，降低显示暗区的面积，从而提升穿透率。
在本申请一可选实施例中，因所述第一侧壁11与所述第三侧壁13左右对称，所以，所述θ1等于所述θ3。
在本申请一可选实施例中，因所述第二侧壁12与所述第四侧壁14左右对称，所以，所述θ2等于所述θ4。
请继续参阅图4，所述实体部10还包括一第五侧壁15及第六侧壁16。其中，所述第五侧壁15与所述第一表面1001连接且与所述第一侧壁11远离所述第二侧壁12的一端相连接，所述第六侧壁16与所述第一表面1001连接且与所述第三侧壁13远离所述第四侧壁14的一端相连接。所述第五侧壁15及所述第六侧壁16构成所述第一电极100的肩部。
在本实施例中，所述第五侧壁15及第六侧壁16的分别远离所述第一侧壁11和第三侧壁13的一端相背倾斜。也即，所述第五侧壁15远离所述第一侧壁11的一端到所述第六侧壁16远离所述第三侧壁13的一端的距离大于所述d2。
在本实施例中，所述第五侧壁15与所述第一侧壁11的连接是平滑连接，也即，所述第五侧壁15与所述第一侧壁11的交接处并未形成一尖角。所述第六侧壁16与所述第三侧壁13的连接是平滑连接，也即，所述第六侧壁16与所述第三侧壁13的交接处并未形成一尖角。
其中，定义所述第五侧壁15与所述第二方向Y2之间的夹角为第五倾角β1，所述第六侧壁16与所述第二方向Y2之间的夹角为第六倾角β2，所述β1和所述β2的取值范围均为0°-90°。优选地，所述β1和所述β2的取值范围均为45°-60°。
其中，将所述β1和所述β2的取值范围设定为0°-90°，可以避免因所述第五侧壁15与所述第一侧壁11之间的夹角过大(即避免在所述第五侧壁15与所述第一侧壁11之间形成反角，反角的存在会产生暗筹，暗筹会降低所述电极的透过率)导致的暗筹，从而避免所述第一电极100的透过率因暗筹导致的损失。
在本申请一可选实施例中，所述β1和所述β2可以满足：β1=β2。相应地，所述第五侧壁15与所述第六侧壁16可以左右对称，也可以左右不对称，在本实施例中，所述第五侧壁15与所述第六侧壁16左右对称。其中，这里的左右不对称是指所述第五侧壁15和所述第六侧壁16的远离所述第一侧壁11和所述第三侧壁13的一端的连线与所述第一方向Y1之间的夹角大于0时导致的不对称。
在本申请另一实施例中，所述β1和所述β2可以满足：β≠β2。相应地，所述第五侧壁15与所述第六侧壁16左右不对称。
在本申请一可选实施例中，所述第五侧壁15及所述第六侧壁16的远离所述第一侧壁11和所述第三侧壁13的一端的距离大于所述d2。
请继续参阅图4，所述实体部10还包括一第七侧壁17，所述第七侧壁17分别与所述第一表面1001、所述第五侧壁15和所述第六侧壁16连接。所述第七侧壁17构成所述第一电极100的头部。
在本实施例中，所述第七侧壁17与所述第五侧壁15和所述第六侧壁16的连接是平滑连接，也即，所述第七侧壁17与所述第五侧壁15和所述第六侧壁16的交接处均未形成一尖角。
在本实施例中，所述第七侧壁17为由三个侧壁组成的曲面。在其他实施例中，所述第七侧壁17还可以为由一个侧壁组成的平面或由2个或3个以上的侧壁组成的曲面。
请继续参阅图4，所述实体部10还包括一第八侧壁18，所述第八侧壁18分别与所述第一表面1001、所述第二侧壁12和所述第四侧壁14连接，所述第七侧壁17与所述第八侧壁18位于所述实体部10的两端。
在本实施例中，所述第八侧壁18还可以为由一个侧壁组成的平面。在其他实施例中，第八侧壁18还可以为由至少两个侧壁组成的曲面。
在本实施例中，所述第八侧壁18与所述第二侧壁12和所述第四侧壁14的连接是平滑连接，也即，所述第八侧壁18与所述第二侧壁12和所述第四侧壁14的交接处均未形成一尖角。
请继续参阅图4，所述第一电极100还包括一连接端子19，所述连接端子19形成在所述实体部10上，所述连接端子19作为所述第一电极100的信号输出或输入端口。在本实施例中，所述连接端子19位于临近所述第七侧壁17。
请参阅图5、图6及图7，图5为图4所示的电极的真实形貌图，图6为现有技术中的梳状电极的仿真光效图，图7为本申请提供的电极的仿真光效图。从图6及图7中可以看出，图7所示的本申请提供的第一电极100的光效比图6所示的梳状电极的光效好，本申请提供的第一电极100的透过率高于梳状电极的透过率。具体地，经过仿真模拟，可以得出本申请提供的第一电极100的光效比现有技术中的梳状电极的光效好50%以上，也即，本申请提供的第一电极100的透过率高于现有技术中的梳状电极的透过率。
请参阅图8，本申请第二实施例还提供一种第一电极200，所述第一电极200的结构与所述第一电极100的结构相似，其区别在于，所述第一电极200的第五侧壁21及第六侧壁22的远离所述第一侧壁11和所述第三侧壁13的一端的距离小于所述d2，也即，所述第一电极200的所述第五侧壁21及所述第六侧壁22相向倾斜。
在本实施例中，所述第一电极200的所述第七侧壁17为由5个侧壁组成的曲面。
当然，在其他实施例中，所述第一电极200的第五侧壁21及第六侧壁22的远离所述第一侧壁11和所述第三侧壁13的一端的距离还可以等于所述d2，也即，所述第一电极200的所述第七侧壁17为平面。
请参阅图9，本申请第三实施例还提供一种第一电极300，所述第一电极300的结构与所述第二电极200的结构相似，其区别仅在于，所述第一电极300的第一底壁31和所述第二底壁32不平行，且所述第一底壁31和所述第二底壁32均不沿所述第二方向Y2延伸。
在本实施例中，所述第一电极300的第一底壁31和所述第二底壁32的分别与所述第二侧壁12和所述第四侧壁14相连接的一端相向倾斜。也即，所述第一侧壁31与所述第二侧壁12连接的一端到所述第二底壁32与所述第四侧壁14连接的一端的距离小于所述第一底壁31与所述第一侧壁11相连接的一端到所述第二底壁32与所述第三侧壁13连接的一端的距离。
请参阅图10，本申请第四实施例还提供一种第一电极400，所述第一电极400的结构与所述第二电极200的结构相似，其区别仅在于，所述第一电极400的第一底壁31和所述第二底壁32不平行，且所述第一底壁31和所述第二底壁32中的其中一个不沿所述第二方向Y2延伸，另一个沿所述第二方向Y2延伸。
请参阅图11，本申请第五实施例还提供一种第一电极500，所述第一电极500的结构与所述第二电极200的结构相似，其区别仅在于，所述第一电极500的第一底壁31和第二底壁32为曲面。
其中，所述曲面可以是包括至少两个侧壁的曲面，也可以是一弧面。
请参阅图12，本申请第六实施例还提供一种第一电极600，所述第一电极600的结构与所述第二电极200的结构相似，其区别仅在于，所述第一侧壁11与所述第一底壁31连接的一端与所述第三侧壁13与所述第二底壁32连接的一端的连线与所述第一方向Y1的夹角γ1大于0°。也即，所述第一电极600的所述第一腰部101与所述第二腰部102不对称。
在本实施例中，所述第二侧壁12与所述第一底壁31连接的一端与所述第四侧壁14与所述第二底壁32连接的一端的连线与所述第一方向Y1的夹角γ2大于0°。
其中，所述γ2可以等于或不等于所述γ1。在本实施例中，所述γ2等于所述γ1。
其中，因所述第一腰部101与所述第二腰部102不对称，使得所述第一电极600具有第一组倾角和第二组倾角，不仅能够增加所述第一电极600的倾角的可选择范围，还能够避开液晶旋转紊乱相互干扰区，减小暗畴，提升透过率。
当然，第六实施例中所涉及的改进还适用于第一实施例、第三实施例、第四实施例及第五实施例中。
请参阅图13，本申请第七实施例还提供一种第一电极700，所述第一电极700的结构与所述第一电极200的结构相似，其区别仅在于，所述第一电极700为公共电极，所述第一电极200为像素电极。所述第一电极700的实体部10内形成有空腔103，所述第一侧壁11、所述第二侧壁12、所述第三侧壁13、所述第四侧壁14、所述第一底壁31、所述第二底壁32为所述空腔的内壁。优选地，所述第五侧壁15、所述第六侧壁16、所述第七侧壁17及所述第八侧壁18也为所述空腔103的内壁。所述第一电极300的实体部10还包括外侧壁23，所述外侧壁23环绕所述第一侧壁11、所述第二侧壁12、所述第三侧壁13、所述第四侧壁14、所述第五侧壁15、所述第六侧壁16、所述第七侧壁17及所述第八侧壁18设置且为所述实体部10的外壁。
在本申请一可选实施例中，所述空腔103呈类鱼形。
请参阅图14，本申请第八实施例还提供一种第一电极800，所述第一电极800的结构与所述第一电极700的结构相似，其区别在于，所述第一电极800的所述第一侧壁11与所述第一底壁31连接的一端与所述第三侧壁13与所述第二底壁32连接的一端的连线与所述第一方向Y1的夹角γ1大于0°。也即，所述第一电极800的所述第一腰部101与所述第二腰部102不对称。
在本实施例中，所述第二侧壁12与所述第一底壁31连接的一端与所述第四侧壁14与所述第二底壁32连接的一端的连线与所述第一方向Y1的夹角γ2大于0°。
其中，所述γ2可以等于或不等于所述γ1。在本实施例中，所述γ2等于所述γ1。
在本申请一可选实施例中，所述第一侧壁11平行于所述第四侧壁14，所述第二侧壁12平行于所述第三侧壁13；所述θ1及所述θ4为所述第一电极100的第一组倾角，所述θ2及所述θ3为所述第一电极100的第二组倾角；所述θ1、所述θ2、所述θ3及所述θ4满足：θ1=θ4且θ2=θ3。此时，所述θ1可以等于或不等于θ2，所述θ3等于或不等于所述θ4。
其中，因所述第一腰部101与所述第二腰部102不对称，使得所述第一电极800具有第一组倾角和第二组倾角，不仅能够增加所述第一电极800的倾角的可选择范围，还能够避开液晶旋转紊乱相互干扰区，减小暗畴，提升透过率。
当然，本申请还提供了空腔的内壁形状与实施例1、实施例3、实施例4及实施例5的第一电极的外壁形状相同的第一电极(公共电极)，再此不一一赘述了。
本申请提供的阵列基板、液晶显示面板及显示装置，1)将第一电极的形状设计成：具有第一腰部(由第一侧壁、第二侧壁及第一底壁构成)和第二腰部(由第三侧壁、第四侧壁及第二底壁构成)，且所述第一腰部到所述第二腰部的最短距离小于所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的距离且小于所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的距离，从而得到类鱼形电极，通过改变第一电极的形状可以减少无效电场分量和电场紊乱区域，进而降低显示暗区的面积，从而在兼顾响应时间的同时，提升穿透率。2)所述第一侧壁的靠近所述第二侧壁的一端与所述第三侧壁的靠近所述第四侧壁的一端的连线与所述第一方向的夹角大于0°，使得所述第一腰部与所述第二腰部不对称，不仅能够增加所述第一电极的倾角可选择范围，还能够避开液晶旋转紊乱相互干扰区，减小暗畴，提升透过率；3)由于响应时间会随着电极倾角增大而减小且穿透率随着电极倾角增大先上升再下降，因此，将第一电极的倾角的取值设定在3°-35°之间，既能够提升显示面板的穿透率，同时又能具有较好响应时间，以满足VR显示装置的需求，4)由于本申请提供的第一电极为像素电极时，电极的腰部收缩，从而增大了相邻两个电极之间的距离，从而可以降低相邻电极在曝光显影制程中发生交联的风险。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括驱动电路层及位于所述驱动电路层上的第一电极，所述驱动电路层包括多条扫描线及多条数据线；定义所述扫描线的延伸方向为第一方向，所述数据线的延伸方向为第二方向，所述第二方向垂直于所述第一方向；所述第一电极还包括实体部；其中，所述实体部包括：
    第一侧壁、第二侧壁及第一底壁；所述第一侧壁与所述第二侧壁的一端通过所述第一底壁连接；及
    第三侧壁、第四侧壁及第二底壁；所述第三侧壁与所述第四侧壁的一端通过所述第二底壁连接；
    其中，所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的连线以及所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的连线均沿所述第一方向延伸；
    其中，定义所述第一底壁到所述第二底壁的最短距离为d1，所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的距离为d2，所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的距离为d3，则d1<d2且d1<d3。
  2. 如权利要求1所述的阵列基板，其中，所述第一电极还包括位于所述实体部内的空腔，所述第一侧壁、所述第二侧壁、所述第三侧壁、所述第四侧壁、所述第一底壁及所述第二底壁为所述空腔的内壁。
  3. 如权利要求2所述的阵列基板，其中，所述实体部还包括外侧壁，所述外侧壁环绕所述第一侧壁、所述第二侧壁、所述第三侧壁及所述第四侧壁设置，所述外侧壁为所述实体部的外壁。
  4. 如权利要求2所述的阵列基板，其中，所述第一电极为公共电极。
  5. 如权利要求1所述的阵列基板，其中，所述第一电极为像素电极。
  6. 如权利要求1所述的阵列基板，其中，所述第一侧壁与所述第一底壁连接的一端与所述第三侧壁与所述第二底壁连接的一端的连线与所述第一方向的夹角大于0°。
  7. 如权利要求1所述的阵列基板，其中，定义所述第一侧壁与所述第二方向之间的夹角为第一倾角θ1，所述第二侧壁与所述第二方向之间的夹角为第二倾角θ2，所述第三侧壁与所述第二方向之间的夹角为第三倾角θ3，所述第四侧壁与所述第二方向之间的夹角为第四倾角θ4，所述θ1、所述θ2、所述θ3及所述θ4的取值范围均为3°-35°。
  8. 如权利要求7所述的阵列基板，其中，所述θ1、所述θ2、所述θ3及所述θ4的取值范围均为5°-15°。
  9. 如权利要求7所述的阵列基板，其中，所述第一侧壁平行于所述第四侧壁，所述第二侧壁平行于所述第三侧壁；所述θ1和θ4为所述第一电极的第一倾角，所述θ2和θ3为所述第一电极的第二倾角；所述θ1、所述θ2、所述θ3及所述θ4满足：θ1=θ4且θ2=θ3。
  10. 如权利要求9所述的阵列基板，其中，所述θ1等于或不等于所述θ2，所述θ3等于或不等于所述θ4。
  11. 如权利要求7所述的阵列基板，其中，θ1≠θ4且θ2≠θ3。
  12. 如权利要求7所述的阵列基板，其中，所述实体部还包括：
    第一底壁，所述第一底壁的两端分别与所述第一侧壁及所述第二侧壁连接；及
    第二底壁，所述第二底壁的两端分别与所述第三侧壁及所述第四侧壁连接。
  13. 如权利要求12所述的阵列基板，其中，所述第一底壁及所述第二底壁均为平行于所述第二方向或不平行于所述第二方向的平面。
  14. 如权利要求12所述的阵列基板，其中，所述第一底壁及所述第二底壁均为曲面。
  15. 如权利要求1所述的阵列基板，其中，所述实体部还包括：
    第五侧壁，与所述第一侧壁的远离所述第二侧壁的一端相连接；及
    第六侧壁，与所述第三侧壁的远离所述第四侧壁的一端相连接；
    定义所述第五侧壁与所述第二方向之间的夹角为第五倾角β1，所述第六侧壁与所述第二方向之间的夹角为第六倾角β2，所述β1和所述β2的取值范围均为0°-90°。
  16. 如权利要求15所述的阵列基板，其中，所述β1和所述β2的取值范围均为45°-60°。
  17. 如权利要求15所述的阵列基板，其中，所述实体部还包括：
    第七侧壁，分别与所述第五侧壁和所述第六侧壁连接；及
    第八侧壁，分别与所述第二侧壁和所述第四侧壁连接；
    其中，所述第八侧壁与所述第七侧壁位于所述实体部的两端。
  18. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括衬底及与所述第一电极相对设置的第二电极，所述第二电极位于所述驱动电路层之内或位于所述驱动电路层之上，所述驱动电路层位于所述衬底上，所述第二电极位于所述衬底与所述第一电极之间。
  19. 一种液晶显示面板，包括液晶和彩膜基板，其中，所述液晶显示面板还包括阵列基板，所述液晶位于所述彩膜基板和所述阵列基板之间；所述阵列基板包括驱动电路层及位于所述驱动电路层上的第一电极，所述驱动电路层包括多条扫描线及多条数据线；定义所述扫描线的延伸方向为第一方向，所述数据线的延伸方向为第二方向，所述第二方向垂直于所述第一方向；所述第一电极还包括实体部；其中，所述实体部包括：
    第一侧壁、第二侧壁及第一底壁；所述第一侧壁与所述第二侧壁的一端通过所述第一底壁连接；及
    第三侧壁、第四侧壁及第二底壁；所述第三侧壁与所述第四侧壁的一端通过所述第二底壁连接；
    其中，所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的连线以及所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的连线均沿所述第一方向延伸；
    其中，定义所述第一底壁到所述第二底壁的最短距离为d1，所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的距离为d2，所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的距离为d3，则d1<d2且d1<d3。
  20. 一种显示装置，其中，所述显示装置包括液晶显示面板，所述液晶显示面板包括液晶和彩膜基板，其中，所述液晶显示面板还包括阵列基板，所述液晶位于所述彩膜基板和所述阵列基板之间；所述阵列基板包括驱动电路层及位于所述驱动电路层上的第一电极，所述驱动电路层包括多条扫描线及多条数据线；定义所述扫描线的延伸方向为第一方向，所述数据线的延伸方向为第二方向，所述第二方向垂直于所述第一方向；所述第一电极还包括实体部；其中，所述实体部包括：
    第一侧壁、第二侧壁及第一底壁；所述第一侧壁与所述第二侧壁的一端通过所述第一底壁连接；及
    第三侧壁、第四侧壁及第二底壁；所述第三侧壁与所述第四侧壁的一端通过所述第二底壁连接；
    其中，所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的连线以及所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的连线均沿所述第一方向延伸；
    其中，定义所述第一底壁到所述第二底壁的最短距离为d1，所述第一侧壁远离所述第二侧壁的一端到所述第三侧壁远离所述第四侧壁的一端的距离为d2，所述第二侧壁远离所述第一侧壁的一端到所述第四侧壁远离所述第三侧壁的一端的距离为d3，则d1<d2且d1<d3。
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