WO2023123469A1 - 一种发光二极管及其发光装置 - Google Patents

一种发光二极管及其发光装置 Download PDF

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Publication number
WO2023123469A1
WO2023123469A1 PCT/CN2021/143945 CN2021143945W WO2023123469A1 WO 2023123469 A1 WO2023123469 A1 WO 2023123469A1 CN 2021143945 W CN2021143945 W CN 2021143945W WO 2023123469 A1 WO2023123469 A1 WO 2023123469A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
type semiconductor
layer
emitting diode
light emitting
Prior art date
Application number
PCT/CN2021/143945
Other languages
English (en)
French (fr)
Inventor
张博扬
林凡威
林信泰
张中英
Original Assignee
厦门三安光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 厦门三安光电有限公司 filed Critical 厦门三安光电有限公司
Priority to PCT/CN2021/143945 priority Critical patent/WO2023123469A1/zh
Priority to CN202180006404.XA priority patent/CN114730817A/zh
Publication of WO2023123469A1 publication Critical patent/WO2023123469A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

Definitions

  • the invention relates to a photoelectric element, in particular to a light emitting diode structure and a light emitting device thereof.
  • the current vertical product technology only uses N-type conductive holes in the light-emitting area to achieve the functions of current expansion and current reduction.
  • the disadvantage is that after the area of the N-hole increases, the light-emitting area (roughened surface) will also become smaller, reducing its brightness. .
  • the core particle size is getting smaller and smaller to make N-type conductive holes, the process window is limited due to the process platform, which causes difficulties in the process.
  • a light emitting diode including:
  • Semiconductor layer sequence with side walls and oppositely arranged first and second surfaces comprising a first type semiconductor layer arranged in sequence between said first and second surfaces, an active layer designed to generate radiation , the second type semiconductor layer, the first electrical connection layer electrically connected with the first type semiconductor layer, the second electrical connection layer electrically connected with the second type semiconductor layer, the second surface of the semiconductor layer sequence has a recess, the recess At least through the active layer, the second type semiconductor layer and part of the first type semiconductor layer, the insulating layer extends from the recess to the second surface, the first electrical connection layer forms a protrusion in the recess, the first electrical connection layer passes through the recess The place is electrically connected with the first type semiconductor layer, and the first electrical connection layer is electrically isolated from the second electrical connection layer by an insulating layer, and the first electrical connection layer includes metal;
  • the recess is located at the edge of the side wall, and part of it is exposed from the side wall. Setting the recess at the edge of the light-emitting area reduces the difficulty of the process, enlarges the chip manufacturing window, and avoids exposure abnormalities caused by metal scattering or reflection.
  • the recess is arranged on the cutting line of the LED chip.
  • the first electrical connection layer includes reflective metal, and at least the sidewall above the recess has a surface roughness, so as to avoid the deviation of the photomask process from the design due to the reflective metal in the yellow light process, resulting in a decrease in yield. Blocking light from entering the semiconductor layer sequence, reflected by the reflective metal layer, causing photoresist (photoresist) anomalies.
  • the first surface position corresponding to the recess has a roughened surface or a patterned surface, and the area of the roughened surface or the patterned surface is at least 120% of the cross-sectional area of the recess.
  • the reflective metal includes silver, aluminum, gold, titanium or rhodium.
  • the average particle size of the surface roughening of the sidewall above the recess is 0.5 ⁇ m to 2 ⁇ m, and the roughening particles large enough prevent light from entering the semiconductor layer sequence and being reflected by the reflective metal.
  • the recesses are arranged continuously or discretely along the sidewall.
  • the recesses are continuously arranged along the side wall, and when the unilateral size of the light-emitting diode is not less than 500 ⁇ m, the recesses are discretely distributed along the side wall to increase the uniformity of current distribution .
  • the sidewalls between the recesses include the first type semiconductor layer, the active layer and the second type semiconductor layer.
  • the sidewall includes a first sidewall and a second sidewall
  • the first sidewall includes a first type semiconductor layer
  • the second sidewall includes a second type semiconductor layer
  • the average of the first sidewall The roughness is no less than that of the second sidewall.
  • the height of the first side wall is higher than that of the second side wall.
  • the angle between the first side wall and/or the second side wall and the vertical plane is 20° to 60°.
  • the sidewall surface has steps, and the number of steps is not less than three.
  • the step width ranges from 1 nm to 5000 nm.
  • At least part of the steps are surface roughened, from the second type semiconductor layer to the first type semiconductor layer, from smooth to rough from bottom to top.
  • the particle size of the surface roughening is arranged in layers from the second type semiconductor layer to the first type semiconductor layer from small to large from bottom to top.
  • a conductive or insulating substrate is further provided on one side of the second surface.
  • the first type semiconductor layer, the active layer and/or the second type semiconductor layer are based on gallium nitride, and the surface roughening adopts wet etching, and the etching liquid includes KOH or KOH with a relatively slow reaction speed. NaOH, the reaction speed is slow and relatively mild, which is conducive to the formation of multiple steps at a time.
  • the first surface is a light-emitting surface, and at least a partial area of the first surface is a roughened surface.
  • the first type semiconductor layer, the active layer and/or the second type semiconductor layer are gallium nitride based.
  • the sidewall of the recess includes a first-type semiconductor layer, the first-type semiconductor layer is an N-type semiconductor layer, the first-type semiconductor layer is doped with silicon, and the second-type semiconductor layer is a P-type semiconductor layer , the second type semiconductor layer is doped with magnesium, the growth temperature of the first type semiconductor layer is higher than that of the second type semiconductor layer, and the growth speed of the first type semiconductor layer is faster than that of the second type semiconductor layer.
  • the first electrical connection layer and/or the second electrical connection layer include a transparent conductive layer, and the transparent conductive layer is used to make an ohmic contact.
  • the distance between the protrusion and the side wall is not greater than 8 ⁇ m
  • the present invention also proposes another light-emitting diode, comprising:
  • Semiconductor layer sequence with side walls and oppositely arranged first and second surfaces comprising a first type semiconductor layer arranged in sequence between said first and second surfaces, an active layer designed to generate radiation , the second type semiconductor layer, the first electrical connection layer electrically connected with the first type semiconductor layer, the second electrical connection layer electrically connected with the second type semiconductor layer, the second surface has a recess, the recess at least runs through the active Layer, the second type semiconductor layer and part of the first type semiconductor layer, the insulating layer extends from the recess to the second surface, the first electrical connection layer is electrically connected to the first type semiconductor layer through the recess, and the first electrical connection layer is connected by the insulating layer
  • the connection layer is electrically isolated from the second electrical connection layer, and the first electrical connection layer includes reflective metal;
  • the distance between the recess and the side wall is 2 to 5 ⁇ m, especially the distance between the first electrical connection layer in the recess and the side wall is 2 to 5 ⁇ m, the recess is arranged in the light emitting area, and at least the side wall outside the recess has surface roughness , to avoid that in the yellow light process, the reflective metal causes the mask process to deviate from the design, resulting in a drop in yield, blocking light from entering the semiconductor layer sequence, and being reflected by the reflective metal layer, resulting in abnormal photoresist (photoresist).
  • the first surface position corresponding to the recess has a roughened surface or a patterned surface, and the area of the roughened surface or the patterned surface is at least 120% of the cross-sectional area of the recess.
  • the average particle size of the surface roughening of the sidewall above the recess is 0.5 ⁇ m to 2 ⁇ m, and the roughening particles large enough prevent light from entering the semiconductor layer sequence and being reflected by the reflective metal.
  • the recesses are arranged continuously or discretely along the sidewall.
  • a conductive or insulating substrate is further provided on one side of the second surface.
  • wet etching is used for surface roughening, and the etching liquid includes KOH or NaOH with a relatively slow reaction speed.
  • the first type semiconductor layer, the active layer and/or the second type semiconductor layer are gallium nitride based.
  • the present invention also provides a light-emitting device, which has a packaging substrate and an adhesive layer.
  • a light-emitting device which has a packaging substrate and an adhesive layer.
  • the above-mentioned light-emitting diode, the substrate of the light-emitting diode is partially or completely covered by the adhesive layer. In some embodiments, at least part of the side wall of the light-emitting diode is covered by the adhesive layer. .
  • it includes a substrate, at least one light-emitting diode chip mounted on the substrate, and an adhesive material covering part of the substrate and part of the side wall of the light-emitting diode chip, and the adhesive material covers the side of the light-emitting diode chip
  • the height of the position of the highest point of the wall does not exceed the height of the first surface of the semiconductor epitaxial stack of the light emitting diode chip.
  • the corner design of steps to effectively prevent the rubber material from climbing.
  • the angle range between the step slope and the horizontal plane of the step-shaped roughening structure is 30°-50°, taking into account the area of the light-emitting region and the resistance capability of the adhesive during packaging.
  • the distance between the highest point of the adhesive covering the sidewall of the LED chip and the first surface of the semiconductor epitaxial stack of the LED chip is greater than 0.1 ⁇ m.
  • the step width ranges from 1 nm to 5000 nm, and the step width is at least greater than 1 nm, so as to prevent the rubber material from climbing.
  • the step thickness ranges from 0.1 ⁇ m to 4 ⁇ m, or from 4 ⁇ m to 10 ⁇ m.
  • the step thickness increases and decreases stepwise from bottom to top, and the step thickness adjacent to the first surface of the semiconductor epitaxial stack is the smallest.
  • the corners of the steps can effectively prevent the adhesive material from climbing, and the closer the corners are to the first surface of the semiconductor epitaxial stack, the better the effect of preventing the adhesive material from climbing over to the chip surface.
  • Fig. 1 is the sectional structure schematic diagram of the first embodiment of the present invention
  • FIGS and Figure 3 are schematic top view structural diagrams of the first embodiment of the present invention, it should be noted that because the first type semiconductor layer above the recess has good light transmission, the first electrical connection layer can be directly seen in the top view;
  • Fig. 4 is the sectional structure schematic diagram of the second embodiment of the present invention.
  • Fig. 5 and Fig. 6 are the sectional structure schematic diagrams of the third embodiment of the present invention.
  • Fig. 7 is the schematic cross-sectional structure diagram of the fourth embodiment of the present invention.
  • Fig. 8 is a schematic cross-sectional structure diagram of a fifth embodiment of the present invention.
  • Fig. 9 is a schematic cross-sectional structure diagram of a sixth embodiment of the present invention.
  • Fig. 10 is a schematic cross-sectional structure diagram of a seventh embodiment of the present invention.
  • Fig. 11 is a schematic cross-sectional structure diagram of an eighth embodiment of the present invention.
  • 100 semiconductor layer sequence; 100 ⁇ : sidewall; 100A ⁇ : first sidewall; 100B ⁇ : second sidewall; 101, first surface; 102, second surface; 103, groove; 104 , step; 110, first type semiconductor layer; 120, second type semiconductor layer; 130, active layer; 210, first electrical connection layer; 211, bonding metal layer; 212, contact layer; 213, reflective layer; 220, second electrical connection layer; 221, transparent conductive layer; 222, reflective layer; 223, metal connection layer; 310, first insulating layer; 320, second insulating layer; 330, protective layer; 410, first electrode; 420, the second electrode; 421, the welding wire; 500, the light blocking layer; 510, the rough covering layer; 600, the white glue; 700, the packaging base frame; 800, the cavity.
  • a light emitting diode comprising: a semiconductor layer sequence 100 as an epitaxial structure, the semiconductor layer sequence 100 has a side wall 100' and a first A surface 101 and a second surface 102, including a first-type semiconductor layer 110 and a second-type semiconductor layer 120 arranged in sequence between the first surface 101 and the second surface 102, which are designed to produce
  • the active layer 130 that radiates light
  • the first electrical connection layer 210 that is electrically connected to the first type semiconductor layer 110
  • the second electrical connection layer 220 that is electrically connected to the second type semiconductor layer 120
  • the second surface 102 has a recess 103
  • the recess 103 at least runs through the active layer 130, the second type semiconductor layer 120 and part of the first type semiconductor layer 110, the first insulating layer 310 extends from the recess 103 to the second surface 102
  • the first electrical connection layer 210 is in the recess A protruding part is formed in the place, and is electrically connected to
  • the recesses 103 are arranged continuously or discretely along the side wall 100'. In this embodiment, two corresponding size designs are proposed. When the unilateral size of the light-emitting diode is less than 600 ⁇ m, the recess 103 is continuously arranged along the side wall 100′; when the unilateral size of the light-emitting diode is not less than 600 ⁇ m, the recess 103 is arranged discrete distribution. When the recesses 103 are discretely arranged, the sidewalls 100 ′ between the recesses 103 include the first type semiconductor layer 110 , the active layer 130 and the second type semiconductor layer 120 .
  • patterning technology is used to thicken the design on the first surface 101 corresponding to the recess 103, so as to avoid the abnormal current spreading caused by the thinning of the first type semiconductor layer 110 above the recess 103.
  • a conductive or insulating substrate is further disposed on the side of the second surface 102 .
  • the conductive substrate is taken as an example, and the conductive substrate is electrically connected to the contact layer 212 through the bonding metal layer 211 .
  • the material of the conductive substrate may include silicon, copper, molybdenum or tungsten.
  • the conductive substrate is used as the first electrode 410, connected to the first electrical connection layer 210, and the upper surface of the second electrical connection layer 220 is provided with a second electrode 420, the first electrode 410 and the second electrode 420 are used for connection with external circuits.
  • the second electrical connection layer 220 includes a transparent conductive layer 221 for contacting the semiconductor layer sequence 100 , a second reflective layer 2222 and a metal connection layer 223 .
  • the difference from Embodiment 1 is that the first electrical connection layer 210 includes a first reflective layer 213, and the reflective metal of the first reflective layer 213 includes silver, aluminum, gold , titanium or rhodium.
  • the distance between the first reflective layer 213 , especially the protrusion of the first electrical connection layer filling the recess, and the sidewall is no greater than 8 ⁇ m.
  • at least the sidewall 100' above the recess 103 is provided with surface roughening.
  • the surface roughening of the sidewall above the recess 103 has an average particle size of 0.1 ⁇ m to 2 ⁇ m, and the surface particles prevent light from entering the first reflective layer 213 from the outside.
  • the angle of the side wall 100' to the vertical is 20° to 60°.
  • the surface roughening method is wet etching, and the etching liquid includes KOH or NaOH, and the etching is completed in one time by using an alkaline etching liquid with relatively mild etching.
  • the first type semiconductor layer 110 , the active layer 130 and/or the second type semiconductor layer 120 are GaN-based.
  • the side wall 100' of the recess 103 includes a first type semiconductor layer 110, the first type semiconductor layer 110 is an N-type semiconductor layer, the first type semiconductor layer 110 is silicon-doped, and the second type semiconductor layer 120 is a P-type semiconductor layer , the second type semiconductor layer 120 is doped with magnesium, the growth temperature of the first type semiconductor layer 110 is higher than that of the second type semiconductor layer 120, the growth rate of the first type semiconductor layer 110 is faster than that of the second type semiconductor layer 120, during the etching process The etching speed of the first type semiconductor layer 110 is faster than that of the second type semiconductor layer 120 , so controlling the etching conditions can produce larger roughened particles.
  • Surface roughening structures include irregular roughening shapes, hemispherical, conical, or cone-like shapes.
  • the first surface 101 is a light-emitting surface, the light is excited by the active layer 130, and exits from the first surface 101, and at least part of the first surface 101 is rough. surface.
  • the position of the first surface 101 corresponding to the recess 103 has a roughened surface or a patterned surface, and the area of the roughened surface or the patterned surface is at least as large as that of the recess 103 when viewed from the top view.
  • the cross-sectional area 120% of the cross-sectional area, so as to ensure that the light in the photolithography process is sufficiently shielded from the reflective material in the recess 103, and the roughness of the roughened structure on the first surface 101 is not less than 0.5 ⁇ m, such as 0.5 ⁇ m to 2 ⁇ m.
  • the position of the first surface 101 corresponding to the recess 103 and the position of the upper side wall 100' are provided with a light-blocking layer 500, such as a reflective mirror or an opaque Optical layer, the light-blocking layer 500 is used to prevent light from entering the semiconductor layer sequence 100 during photolithography, such as a distributed Bragg reflection layer DBR or a selective light-transmitting layer.
  • the light-blocking layer 500 is an insulating material. The light blocking layer 500 extends from the light emitting surface toward the substrate.
  • the first surface 101 position corresponding to the recess 103 and the upper side wall 100' position have a roughened covering layer 510 as a light-blocking layer, for example, it may be a roughened insulation Layer, materials include silicon dioxide, aluminum oxide, silicon nitride or titanium oxide.
  • the light-blocking rough covering layer 510 is used to prevent light from entering the semiconductor layer sequence 100 during photolithography.
  • the rough covering layer 510 with a rough structure can prevent, in this embodiment, the rough covering layer 510 from the first surface 101 extends toward the second surface 102 .
  • the sidewall 100' includes a first sidewall 100A' and a second sidewall 100B', and the first sidewall 100A' includes a first type semiconductor layer 110 extending along a slope.
  • the inclined surface has a fixed or unfixed inclination angle.
  • the second sidewall 100B′ includes the second type semiconductor layer 120 extending along the inclination surface.
  • the inclined surface has a fixed or unfixed inclination angle.
  • the roughness of the first sidewall 110A′ is not Smaller than the second side wall 110B′, the beneficial effect is to effectively improve the small-angle light output effect.
  • the height of the first sidewall 110A′ is higher than that of the second sidewall 110B′, and the first sidewall 110A′ is closer to the first surface 101 than the second sidewall 110B′.
  • the angle between the first side wall 110A' and/or the second side wall 110B' and the vertical plane is 20° to 60°.
  • a step 104 is provided on the surface of the side wall, and the step 104 has a relatively dark and dark dividing line in appearance.
  • the steps include the top surface of the first surface, and the number of steps 104 is not less than three.
  • the width of the step 104 ranges from 1 nm to 2000 nm. At least part of the step 104 is roughened, from the second type semiconductor layer 120 to the first type semiconductor layer 110 , relatively speaking, the second type semiconductor layer has smooth sidewalls, and the first type semiconductor layer has rough sidewalls.
  • the particle size of the surface roughening is from the second type semiconductor layer 120 to the first type semiconductor layer 110 , arranged in layers from bottom to top from small to large.
  • the roughness of the stepped rough structure ranges from 0.1 ⁇ m to 2 ⁇ m, and the roughness of the second sidewall 100B′ is not greater than 0.1 ⁇ m.
  • a light-emitting device is provided.
  • the cavity 800 is filled with glue, such as white glue 600, and the white glue 600 is easy to climb over. through the chip to cover the light-emitting surface (first surface 101 ) of the chip to reduce the light-emitting area of the chip.
  • the light-emitting diode can increase the light extraction efficiency of the light-emitting diode and improve the luminous brightness by roughening the mesa of the semiconductor layer sequence. Since the side of the conventional chip is a continuous and simple semiconductor epitaxial surface, the roughening effect is not ideal, and when the glue is filled in the packaging process, the glue is easy to roll over the chip and cover the light-emitting surface of the chip, affecting the luminous efficiency of the chip. At the same time, the continuous and simple surface is easy to cause the rubber material to climb, causing abnormalities such as light loss. Therefore, setting the steps 104 on the surface of the side wall can prevent the adhesive material from climbing easily, and realize the effect of improving the overall light output brightness of the light emitting device.
  • the light-emitting device provided in this embodiment is a package structure of a light-emitting diode chip, which includes a package substrate 700, a light-emitting diode chip, and white glue 600, and may also include a phosphor layer.
  • a light emitting diode chip is mounted on the upper surface of the package substrate 700 .
  • the white glue 600 at least partially or completely covers the substrate (eg, a conductive substrate). In some embodiments, the white glue 600 at least partially covers the sidewall.
  • the light-emitting diode chip takes a vertical chip structure as an example, and the chip structure includes: a semiconductor layer sequence 100, a side wall 100', a first electrode 410, and a second electrode 420;
  • the semiconductor layer sequence 100 has a first surface 101 and a second surface 102 oppositely arranged.
  • the first type semiconductor layer 110 is an N-type semiconductor layer
  • the second type semiconductor layer 120 is a P-type semiconductor layer.
  • the active layer 130 is used to generate radiation multiple quantum wells;
  • the side wall 100' includes a first side wall 100A' and a second side wall 100B';
  • the first sidewall The first sidewall 100A′ is formed on the sides of the first conductivity type semiconductor layer 110 and the active layer 130;
  • the second sidewall 100B′ is formed on the side of the second conductivity type semiconductor layer 120;
  • a roughened structure is provided on all or part of the first side wall 100A', the roughened structure is arranged in a step shape, and the roughness of the first side wall 100A' is greater than that of the second side wall 100B';
  • steps 104 there are 2 or more steps 104 in the step-like coarsening structure, and the corners of the steps 104 can effectively prevent the rubber material from climbing. The better the effect of preventing the glue from crossing over the chip;
  • the roughness of the step-like coarsening structure ranges from 0.2 ⁇ m to 2 ⁇ m, and the roughness of the second side wall 602 is not greater than 1 ⁇ m.
  • the degree is arranged in layers from smooth to rough from bottom to top.
  • the stepped roughened structure can effectively reduce light loss caused by total reflection and improve luminous efficiency at the same time.
  • the angle range between the inclined plane of the step 104 and the horizontal plane of the stepped roughening structure is 30° ⁇ 50°, taking into account the sufficient area of the first surface 101 and the area of the active region 130, and at the same time, it is beneficial to prevent the design of creeping glue .
  • the width of the step 104 of the step-like coarsening structure ranges from 1 nm to 5000 nm, and the width of the step 104 is at least greater than 1 nm, so as to prevent the rubber material from climbing.
  • the thickness of the step 104 ranges from 0.1 ⁇ m to 4 ⁇ m, or from 4 ⁇ m to 10 ⁇ m.
  • the thickness of the steps 104 of the stepped roughening structure decreases stepwise from bottom to top, and the thickness of the first surface 101 adjacent to the semiconductor layer sequence is the smallest.
  • the corner steps of the steps 104 can effectively prevent the glue from climbing up, and the closer the corner is to the first surface 101 of the semiconductor epitaxial stack, the better the effect of preventing the glue from climbing over to the chip surface.
  • a roughened structure is provided on the first surface 101, and the roughness of the roughened structure ranges from 0.5 ⁇ m to 2 ⁇ m; in some embodiments, the first surface 101 is provided with a structure of alternating planes and slopes, thereby increasing the light output area , while increasing the roughening area and roughening density, effectively improving the luminous efficiency.
  • the positive side of the first type semiconductor layer 110 is provided with a first electrical connection layer 210, and the first electrode 410 faces the positive side; the back side of the second type semiconductor layer 120 is connected to the positive side of the second electrical connection layer 220; the substrate 400 can Including a conductive substrate and an insulating substrate, the conductive substrate material may include silicon, copper or molybdenum, and the insulating substrate such as sapphire or ceramics.
  • the first type semiconductor layer includes a low-temperature gallium nitride-based semiconductor material.
  • the second type semiconductor layer includes a high temperature gallium nitride based semiconductor material.
  • the active layer includes GaN/InGaN material.
  • the roughened structures of the first sidewall 100A', the second sidewall 100B' and the first surface 101 include irregular roughened shapes, regular spherical, conical roughened shapes.
  • the white glue covers the sidewall 100' of the light-emitting diode chip, and the 100-layer stepped roughening structure of the sidewall of the semiconductor layer sequence of the light-emitting diode chip can effectively form a blocking effect, preventing the white glue from easily crossing over the chip.
  • the height of the highest point of the white glue covering the side wall 100 ′ does not exceed the height of the first surface 101 of the first type semiconductor layer of the light-emitting diode chip, so as to prevent the white glue from covering the light-emitting surface of the chip and reducing the light-emitting area of the chip.
  • the side wall 100' is a multi-layered stepped coarsening structure, the particle size is arranged in layers from small to large from bottom to top, and the degree of roughness is arranged in layers from smooth to rough from bottom to top.
  • the surface can reduce the abnormalities such as light loss caused by white glue climbing.
  • the distance between the highest point of the white glue 600 covering the side wall 100' of the LED chip and the first surface 101 of the LED chip is not less than 0.1 ⁇ m.
  • the material of the white glue includes resin, such as silicone resin.
  • the commonly used silicone resin can be transparent or white.
  • white silicone resin is used.
  • the corner of the step surface of the step 104 can effectively prevent the glue from climbing.
  • the vertical distance between the step surface closest to the first surface and the first surface is no more than 2 ⁇ m.
  • the height of the second electrode 420 is lower than the semiconductor layer sequence 100.
  • the height of the second electrode 420 can also be higher than the semiconductor layer sequence 100, and at the same time, it can ensure that the adhesive material will not climb to the second electrode 420 .
  • the difference from the eighth embodiment is that at least the sidewall of the semiconductor epitaxial stack is covered with a protective layer 330, the protective layer 330 has the function of preventing glue creeping, and the refractive index of the protective layer 330 is less than
  • the refractive index of the semiconductor layer sequence 100 can be favorable for light emission from the side of the light emitting diode.
  • the protective layer 330 may include one or more insulating materials of silicon dioxide, silicon nitride, and aluminum oxide. In this embodiment, the material of the protection layer 330 is silicon dioxide.
  • the protective layer 330 has a thickness of 100 ⁇ 20000 angstroms. A multi-layer stepped roughening structure is formed on the protection layer 330 , replacing the structure directly roughened on the semiconductor layer sequence 100 in the ninth embodiment.
  • the difference from Embodiment 8 is that the side wall 100 ′ has several stepped surfaces, and the vertical distance D1 between the stepped surface of the step 104 closest to the first surface and the first surface 101 Not more than 2 ⁇ m.
  • the cushioning effect of the step surface is used to prevent the glue material from climbing to the first surface 101 during glue injection.
  • the distance between the highest point of the adhesive material covering the sidewall of the light emitting diode chip and the first surface 101 of the semiconductor epitaxial stack of the light emitting diode chip is greater than 0.1 ⁇ m.
  • the difference from the tenth embodiment is that the chip structure in the seventh embodiment can be used as the light source of the light emitting device.

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Abstract

本发明公开了一种发光二极管，包括：半导体层序列，具有侧壁以及相对设置的第一表面和第二表面，包括在所述第一表面和第二表面之间顺序排列的半导体层序列，第二表面具有至少贯穿有源层、第二类型半导体层和部分第一类型半导体层的凹处，第一电连接层通过凹处与第一类型半导体层电连接，第一电连接层包括反射金属；凹处位于侧壁，至少凹处上方的侧壁具有表面粗化，防止因为反射金属造成芯片工艺黄光制程异常，提升产品良率。

Description

一种发光二极管及其发光装置 技术领域
本发明涉及一种光电元件，尤其涉及一种发光二极管结构及其发光装置。
 背景技术
现行垂直产品工艺仅使用发光区内的N型导电孔来达到电流扩展及降电流的功能，缺点是N孔面积增大后让发光区（粗化面）也随之变小，使之亮度降低。当芯粒尺寸越来越小时进行N型导电孔制作，工艺窗口因工艺平台受限造成制程中的困难。
 技术解决方案
为了解决背景技术中的技术问题，提出了一种发光二极管，包括：
半导体层序列，具有侧壁以及相对设置的第一表面和第二表面，包括在所述第一表面和第二表面之间顺序排列的第一类型半导体层、设计用于产生辐射的有源层、第二类型半导体层，与第一类型半导体层电连接的第一电连接层，与第二类型半导体层电连接的第二电连接层，半导体层序列的第二表面具有凹处，凹处至少贯穿有源层、第二类型半导体层和部分第一类型半导体层，绝缘层从凹处延伸至第二表面，第一电连接层在凹处内形成突出部，第一电连接层通过凹处与第一类型半导体层电连接，利用绝缘层将第一电连接层和第二电连接层电隔离，第一电连接层包括金属；
凹处位于侧壁边缘，部分从侧壁露出，将凹处设置在发光区域边缘，降低工艺难度，放大芯片制程窗口，避免金属散射或者反光造成曝光异常。凹处设置在发光二极管芯片的切割道上。
根据本发明，优选的，第一电连接层包括反射金属，至少凹处上方的侧壁具有表面粗化，避免在黄光工艺中，由于反射金属导致光罩工艺偏离设计，造成良率下降，阻挡光进入半导体层序列，由反射金属层反射，造成光刻胶（光阻）异常。
根据本发明，优选的，凹处对应的第一表面位置具有粗化表面或者图案化表面，且粗化表面或者图案化表面的面积至少为凹处截面积的120%。
根据本发明，优选的，反射金属包括银、铝、金、钛或者铑。
根据本发明，优选的，凹处上方的侧壁表面粗化的平均粒径0.5μm至2μm，足够大的粗化颗粒阻止光进入半导体层序列被反射金属反射。
在一些实施方式中，优选的，凹处沿着侧壁连续或者离散设置。
在该些实施方式中，优选的，发光二极管单边尺寸小于500μm时，凹处沿侧壁连续设置，发光二极管单边尺寸不小于500μm时，凹处沿侧壁离散分布，增加电流分布均匀性。
在一些实施方式中，优选的，凹处离散设置时，凹处之间的侧壁包括第一类型半导体层、有源层和第二类型半导体层。
根据该些实施方式，优选的，侧壁包括第一侧壁和第二侧壁，第一侧壁包括第一类型半导体层，第二侧壁包括第二类型半导体层，第一侧壁的平均粗糙度不小于第二侧壁。
根据该些实施方式，优选的，第一侧壁的高度高于第二侧壁。
根据该些实施方式，优选的，第一侧壁和/或第二侧壁与竖直面的角度为20°至60°。
在本发明的一些实施方式中，侧壁表面具有阶梯，阶梯数量不小于3。
根据该些实施方式，优选的，所述阶梯宽度范围为1nm~5000nm。
根据该些实施方式，优选的，至少部分阶梯为表面粗化，从第二类型半导体层至第一类型半导体层，自下而上由光滑到粗糙。
根据该些实施方式，优选的，表面粗化的粒径从第二类型半导体层至第一类型半导体层，自下而上由小至大分层排布。
根据该些实施方式，优选的，第二表面一侧还设置有导电或者绝缘衬底。
根据本发明，优选的，第一类型半导体层、有源层和/或第二类型半导体层为氮化镓基，表面粗化采用的是湿法蚀刻，蚀刻液体包括反应速度较缓慢的KOH或者NaOH，反应速度慢，相对缓和，有利于一次形成多个阶梯。
根据本发明，优选的，第一表面为出光面，第一表面至少部分区域为粗化表面。
根据本发明，优选的，第一类型半导体层、有源层和/或第二类型半导体层为氮化镓基。
根据本发明，优选的，凹处的侧壁包括第一类型半导体层，第一类型半导体层为N型半导体层，第一类型半导体层为硅掺杂，第二类型半导体层为P型半导体层，第二类型半导体层为镁掺杂，第一类型半导体层生长温度高于第二类型半导体层，第一类型半导体层生长速度快于第二类型半导体层。
根据本发明，优选的，第一电连接层和/或第二电连接层包括透明导电层，透明导电层用于制作欧姆接触。
根据本发明，优选的，突出部距离侧壁的距离不大于8μm
本发明还提出了另一种发光二极管，包括：
半导体层序列，具有侧壁以及相对设置的第一表面和第二表面，包括在所述第一表面和第二表面之间顺序排列的第一类型半导体层、设计用于产生辐射的有源层、第二类型半导体层，与第一类型半导体层电连接的第一电连接层，与第二类型半导体层电连接的第二电连接层，第二表面具有凹处，凹处至少贯穿有源层、第二类型半导体层和部分第一类型半导体层，绝缘层从凹处延伸至第二表面，第一电连接层通过凹处与第一类型半导体层电连接，利用绝缘层将第一电连接层和第二电连接层电隔离，第一电连接层包括反射金属；
凹处距离侧壁距离为2至5μm，特别是凹处内的第一电连接层距离侧壁距离为2至5μm，将凹处设置在发光区，至少凹处外侧的侧壁具有表面粗化，避免在黄光工艺中，由于反射金属导致光罩工艺偏离设计，造成良率下降，阻挡光进入半导体层序列，由反射金属层反射，造成光刻胶（光阻）异常。
根据本发明，优选的，凹处对应的第一表面位置具有粗化表面或者图案化表面，且粗化表面或者图案化表面的面积至少为凹处截面积的120%。
根据本发明，优选的，凹处上方的侧壁表面粗化的平均粒径0.5μm至2μm，足够大的粗化颗粒阻止光进入半导体层序列被反射金属反射。
在一些实施方式中，优选的，凹处沿着侧壁连续或者离散设置。
根据本发明，优选的，第二表面一侧还设置有导电或者绝缘衬底。
根据本发明，优选的，表面粗化采用的是湿法蚀刻，蚀刻液体包括反应速度较缓慢的KOH或者NaOH。
根据本发明，优选的，第一类型半导体层、有源层和/或第二类型半导体层为氮化镓基。
本发明还提供了一种发光装置，具有封装基板和胶层，上述发光二极管，发光二极管的衬底部分或者全部被胶层覆盖，在一些实施方式中，发光二极管至少部分侧壁被胶层覆盖。
具体来说，包括基板、安装在所述基板上的至少一个发光二极管芯片以及覆盖部分所述基板和部分所述发光二极管芯片侧壁上的胶材，所述胶材覆盖所述发光二极管芯片侧壁的最高点的位置的高度不超过所述发光二极管芯片的半导体外延叠层的第一表面的高度。
根据本发明，优选的，采用阶梯的转角设计能有效阻止胶材攀爬，阶梯数量越多，转角越多，对阻止胶材翻越到芯片表面的效果越好。
作为进一步的设计，优选的，所述阶梯状粗化结构的阶梯斜面与水平面的角度范围为30°~50°，兼顾发光区域的面积和封装时爬胶的阻抗能力。
阶梯斜面与水平面的角度越大，所形成的阶梯数量越多，阶梯的转角越多，对阻止胶材翻越到芯片表面的效果越好。
根据本发明，优选的，所述胶材覆盖所述发光二极管芯片侧壁的最高点的位置距离所述发光二极管芯片的半导体外延叠层的第一表面的距离范围为大于0.1μm。
根据本发明，优选的，所述阶梯宽度范围为1nm~5000nm，阶梯宽度至少大于1nm，以达到阻止胶材攀爬的目的。
根据本发明，优选的，所述阶梯厚度范围为0.1μm~4μm，或4μm至10μm。
阶梯厚度越小，所形成的阶梯数量越多，转角越多，对阻止胶材翻越到芯片表面的效果越好。
根据本发明，优选的，所述阶梯厚度自下至上呈阶梯式递增减，且临近半导体外延叠层第一表面的阶梯厚度最小。
阶梯的转角能有效阻止胶材攀爬，转角越临近半导体外延叠层第一表面，对阻止胶材翻越到芯片表面的效果越好。
 有益效果
与现有技术相比，本申请至少具有如下有益效果：
1.解决了背景技术中，克服了工艺平台受限造成制程中的困难，通过将N孔（槽）对应的凹处设置在侧壁并部分暴露，扩大工艺窗口；
2. 通过侧壁表面粗化设置，防止芯片制程中光刻工艺受N孔（槽）凹处内反射金属材料影响，导致光刻异常，避免由侧壁进入的光反射至芯片表面的光刻胶，造成非预设的光刻胶吸收光，导致蚀刻出现问题而得不到设想的图案化结构；
3.通过侧壁表面粗化设置，防止胶层向上蔓延至第一表面，影响出光效果。
 附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本发明第一个实施例的剖面结构示意图；
图2和图3为本发明第一个实施例的俯视结构示意图，需要注意的是由于凹处上方的第一类型半导体层透光性好，因此俯视图中直接可看见第一电连接层；
图4为本发明第二个实施例的剖面结构示意图；
图5和图6为本发明第三个实施例的剖面结构示意图；
图7为本发明第四个实施例的剖面结构示意图；
图8为本发明第五个实施例的剖面结构示意图；
图9为本发明第六个实施例的剖面结构示意图；
图10为本发明第七个实施例的剖面结构示意图；
图11为本发明第八个实施例的剖面结构示意图；
图中标识：100、半导体层序列；100`:侧壁；100A`:第一侧壁；100B`:第二侧壁；101、第一表面；102、第二表面；103、凹槽；104、阶梯；110、第一类型半导体层；120、第二类型半导体层；130、有源层；210、第一电连接层；211、键合金属层；212、接触层；213、反射层；220、第二电连接层；221、透明导电层；222、反射层；223、金属连接层；310、第一绝缘层；320、第二绝缘层；330、保护层；410、第一电极；420、第二电极；421、焊线；500、阻光层；510、粗化覆盖层；600、白胶；700、封装基架；800、腔体。
 本发明的实施方式
以下通过特定的具体实施例说明本申请的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本申请的其他优点与功效。本申请还可以通过另外不同的具体实施方式加以实施或营业，本申请中的各项细节也可以基于不同观点与应用，在没有背离本申请的精神下进行各种修饰或改变。
参看图1至图3，在本发明的第一个实施例中，公开了一种发光二极管，包括：作为外延结构的半导体层序列100，半导体层序列100具有侧壁100`以及相对设置的第一表面101和第二表面102，包括在所述第一表面101和第二表面102之间顺序排列的第一类型半导体层110、第二类型半导体层120、位于两者之间设计用于产生辐射出光的有源层130，与第一类型半导体层110电连接的第一电连接层210，与第二类型半导体层120电连接的第二电连接层220，第二表面102具有凹处103，凹处103至少贯穿有源层130、第二类型半导体层120和部分第一类型半导体层110，第一绝缘层310从凹处103延伸至第二表面102，第一电连接层210在凹处内形成突出部，且通过凹处103与第一类型半导体层110电连接，利用第一绝缘层310和第二绝缘层320将第一电连接层210和第二电连接层220电隔离，第一电连接层210和/或第二电连接层220包括金属；在本实施例中，凹处103位于侧壁100`，凹处103部分从侧壁100`露出。
凹处103沿着侧壁100`连续或者离散设置。在本实施例中，提出两种对应的尺寸设计，发光二极管单边尺寸小于600μm时，凹处103沿侧壁100`连续设置，发光二极管单边尺寸不小于600μm时，凹处103沿侧壁离散分布。凹处103离散设置时，凹处103之间的侧壁100`包括第一类型半导体层110、有源层130和第二类型半导体层120。在减薄半导体层序列100时，利用图案化技术，对应凹处103的第一表面101上加厚设计，避免凹处103上方的第一类型半导体层110过薄导致电流扩展异常。
在本实施例中，第二表面102一侧还设置有导电或者绝缘的衬底。本实施例以导电衬底为例，导电衬底通过键合金属层211与接触层212电连接。导电衬底的材料可以包括硅、铜、钼或者钨。在本实施例中，导电衬底作为第一电极410，与第一电连接层电210连接，第二电连接层220上表面设置有第二电极420，第一电极410和第二电极420用于与外部电路连接。
在本实施例中，第二电连接层220包括用于与半导体层序列100接触的透明导电层221、第二反射层2222和金属连接层223。
参看图4，在本发明的第二个实施例中，与实施例1的区别在于，第一电连接层210包括第一反射层213，第一反射层213的反射金属包括银、铝、金、钛或者铑。第一反射层213，特别是第一电连接层填充凹处的突出部距离侧壁的距离不大于8μm。对应的，至少凹处103上方的侧壁100`设置有表面粗化。凹处103上方的侧壁表面粗化的平均粒径0. 1μm至2μm，通过表面颗粒避免光从外部射向第一反射层213。侧壁100`与竖直面的角度为20°至60°。在本实施例中，表面粗化的方式为湿法蚀刻，蚀刻液体包括KOH或者NaOH，利用蚀刻相对缓和的碱性蚀刻液，一次蚀刻制作完成。第一类型半导体层110、有源层130和/或第二类型半导体层120为氮化镓基。凹处103的侧壁100`包括第一类型半导体层110，第一类型半导体层110为N型半导体层，第一类型半导体层110为硅掺杂，第二类型半导体层120为P型半导体层，第二类型半导体层120为镁掺杂，第一类型半导体层110生长温度高于第二类型半导体层120，第一类型半导体层110生长速度快于第二类型半导体层120，在蚀刻过程中，第一类型半导体层110蚀刻速度快于第二类型半导体层120，因此控制蚀刻条件可以制作出更大的粗化颗粒。表面粗化的结构包含不规则粗化形状、半球型、锥形或者类锥状等形状。
参看图5和图6，在本发明的第三个实施例中，第一表面101为出光面，光由有源层130激发，从第一表面101出射，第一表面101至少部分区域为粗化表面。在本实施例的一些实施方式中，凹处103对应的第一表面101位置具有粗化表面或者图案化表面，从俯视方向上看，且粗化表面或者图案化表面的面积至少为凹处103截面积的120%，以保证足够遮挡光刻工艺中光线射至凹处103的反射材料上，第一表面101上的粗化结构的粗糙度范围不小于0.5μm，例如0.5μm至2μm。
参看图7，在本发明的第四个实施例中，凹处103对应的第一表面101位置以及上方侧壁100`位置，设置有阻光层500，阻光层500例如反射镜或者不透光层，阻光层500用于阻止光刻时光线射入半导体层序列100，例如分布布拉格反射层DBR或者选择性透光层，在本实施例中，阻光层500为绝缘材料。阻光层500从出光面向基板方向延伸。
参看图8，在本发明的第五个实施例中，凹处103对应的第一表面101位置以及上方侧壁100`位置，具有作为阻光的粗化覆盖层510，例如可以是粗化绝缘层，材料包括二氧化硅、氧化铝、氮化硅或者氧化钛。阻光的粗化覆盖层510用于阻止光刻时光线射入半导体层序列100，具有粗化结构的粗化覆盖层510能够防止，在本实施例中，粗化覆盖层510从第一表面101向第二表面102方向延伸。
参看图9，在本发明的第六个实施例中，侧壁100`包括第一侧壁100A`和第二侧壁100B`，第一侧壁100A`包括第一类型半导体层110沿斜面延伸形成，斜面具有固定或者不固定的倾斜角度，第二侧壁100B`包括第二类型半导体层120沿斜面延伸形成，斜面具有固定或者不固定的倾斜角度，第一侧壁110A`的粗糙度不小于第二侧壁110B`，有益效果在于有效提升小角度出光效果。其中第一侧壁110A`的高度高于第二侧壁110B`，相对于第二侧壁110B`，第一侧壁110A`更靠近第一表面101。第一侧壁110A`和/或第二侧壁110B`与竖直面的角度为20°至60°。
参看图10，在本发明的第七个实施例中，在实施例五的基础上，侧壁表面设置有阶梯104，在外观上阶梯104具有相对深色、暗色的分界线。阶梯包括第一表面的顶面，阶梯104数量不小于3。所述阶梯104宽度范围为1nm~2000nm。至少部分阶梯104为表面粗化，从第二类型半导体层120至第一类型半导体层110，相对来说第二类型半导体层为光滑侧壁，第一类型半导体层为粗糙侧壁。表面粗化的粒径从第二类型半导体层120至第一类型半导体层110，自下而上由小至大分层排布。阶梯状粗化结构的粗糙度范围为0.1μm~2μm，第二侧壁100B`的粗糙度不大于0.1μm。
参看图11，在本发明的第八个实施例中，提供了一种发光装置，在对发光芯片进行封装时，向腔体800填入胶材，例如白胶600时，白胶600容易翻越过芯片, 覆盖在芯片的发光面（第一表面101）上，减少芯片的发光面积。
发光二极管通过对半导体层序列的台面进行粗化，可提升发光二极管的光取出效率，提升发光亮度。由于常规芯片侧面是连续、简单的半导体外延表面，粗化效果不理想，且在封装工艺填入胶材时，胶材容易翻越过芯片, 覆盖在芯片的发光面上，影响芯片的发光效率。同时连续、简单的表面容易造成胶材攀爬，造成光损等异常。因此，在侧壁表面设置阶梯104，可以避免胶材轻易攀爬，实现提升发光装置整体出光亮度的效果。
本实施例提供的发光装置，作为一种发光二极管芯片的封装结构，其包括封装基板700、发光二极管芯片、白胶600，还可以包括荧光粉层。将发光二极管芯片安装在封装基板700的上表面。白胶600至少部分或者全部覆盖衬底（例如导电衬底），在一些实施方式中，白胶600至少部分覆盖在侧壁上。
在本实施例中发光二极管芯片以垂直芯片结构为例，该芯片结构包括：半导体层序列100，侧壁100`，第一电极410，第二电极420；
半导体层序列100，具有相对设置的第一表面101和第二表面102，本实施例的半导体层序列100，第一类型半导体层110为N型半导体层，第二类型半导体层120为P型半导体层，有源层130为用于产生辐射多量子阱；
侧壁100`包括第一侧壁100A`和第二侧壁100B`；
第一侧壁第一侧壁100A`, 形成于第一导电型半导体层110和有源层130的侧部；
第二侧壁100B`，形成于第二导电型半导体层120的侧部；
在第一侧壁100A`全部或者部分壁面上设置有粗化结构，所述粗化结构呈现阶梯状排布，第一侧壁100A`的粗糙度大于第二侧壁100B`；
阶梯状粗化结构的阶梯104数量2个或者3个以上，阶梯104的转角能有效阻止胶材攀爬，阶梯数量越多，转角越多，在封装工艺填入胶材时可形成阻碍效果，阻止胶材翻越过芯片的效果越好；
阶梯状粗化结构的粗糙度范围为0.2μm~2μm，第二侧壁602的粗糙度不大于1μm，阶梯状粗化结构的粒径自下而上由小至大分层排布，粗化程度自下而上由光滑至粗糙分层排布。阶梯状粗化结构可有效减少全反射造成光损，同时提升发光效率。
作为更好的选择，阶梯状粗化结构的阶梯104斜面与水平面的角度范围为30°~50°，兼顾保证足够的第一表面101面积和有源区130面积，同时利于阻止爬胶的设计。
阶梯104斜面与水平面的角度越大，所形成的阶梯数量越多，转角越多，对阻止胶材翻越到芯片表面的效果越好。
阶梯状粗化结构的阶梯104宽度范围为1nm~5000nm，阶梯104宽度至少大于1nm，以达到阻止胶材攀爬的目的。
阶梯104厚度范围为0.1μm~4μm，或4μm至10μm。
阶梯104厚度越小，所形成的阶梯104数量越多，转角越多，对阻止胶材翻越到芯片表面的效果越好。
阶梯状粗化结构的阶梯104厚度自下至上呈阶梯式递减，且临近半导体层序列的第一表面101的厚度最小。
阶梯104的转角台阶能有效阻止胶材攀爬，转角越临近半导体外延叠层第一表面101，对阻止胶材翻越到芯片表面的效果越好。
第一表面101上设置有粗化结构，粗化结构的粗糙度范围为0.5μm~2μm；在一些实施方式中，第一表面101上设置为平面与斜面交替的结构，可藉此增加出光面积，同时增加粗化面积与粗化密度，有效提升发光效率。
第一类型半导体层110的正侧设置有第一电连接层210，第一电极410朝向正侧；第二类型半导体层120的背侧与第二电连接层220正侧连接；衬底400可以包括导电衬底和绝缘衬底，导电衬底材料可以包括硅、铜或者钼，绝缘衬底例如蓝宝石或者陶瓷。第一类型半导体层包括低温氮化镓基半导体材料。第二类型半导体层包括高温氮化镓基半导体材料。有源层包括氮化镓/铟镓氮的材料。
第一侧壁100A`、第二侧壁100B`和第一表面101的粗化结构包含不规则粗化形状、规则的球形、锥形粗化形状。
在本实施例中，白胶覆盖发光二极管芯片的侧壁100`，发光二极管芯片的半导体层序列的侧壁100多层阶梯状粗化结构能有效形成阻挡效果，阻止白胶轻易翻越过芯片，使白胶覆盖侧壁100`的最高点的高度不超过发光二极管芯片的第一类型半导体层的第一表面101的高度，防止白胶覆盖在芯片的发光面上，避免减少芯片的发光面积。同时，侧壁100`为多层阶梯状粗化结构，粒径自下而上由小至大分层排布，粗化程度自下而上由光滑至粗糙分层排布，下部分的光滑面可以降低白胶攀爬造成光损等异常。
其中白胶600覆盖所述发光二极管芯片侧壁100`的最高点的位置距离所述发光二极管芯片的第一表面101的距离范围为不小于0.1μm。所述白胶的材料包括树脂，例如硅树脂，常用的硅树脂可以为透明或着白色，在本实施例采用白色硅树脂，现有设计中，存在爬胶现象，例如毛細现象。
阶梯104的台阶面转角能有效阻止白胶攀爬，台阶面转角越临近第一类型半导体层的第一表面101，对阻止白胶翻越到芯片表面的效果越好。最靠近第一表面的台阶面距离第一表面的竖直距离不大于2μm。
需要说明的是，在本实施例的附图中，第二电极420高度低于半导体层序列100，实际上第二电极420高度也可以高于半导体层序列100，同时可保证胶材不会爬到第二电极420。
在本发明的第九个实施例中，跟实施例8的区别在于，半导体外延叠层至少侧壁上覆盖有保护层330，保护层330具有防止爬胶的作用，保护层330的折射率小于半导体层序列100的折射率，可以有利于发光二极管侧面的出光。保护层330可以包括二氧化硅、氮化硅、氧化铝的一种或多种绝缘材料。在本实施例中，保护层330的材料为二氧化硅。保护层330的厚度为100～20000埃。多层阶梯状粗化结构形成于保护层330上，替代实施例9中在半导体层序列100上直接粗化的结构。
在本发明的第十个实施例中，跟实施例8的区别在于，侧壁100`具有若干个台阶面，最靠近第一表面的阶梯104的台阶面距离第一表面101的竖直距离D1不大于2μm。利用台阶面的缓冲作用，防止在注胶时，胶材攀爬至第一表面101。胶材覆盖所述发光二极管芯片侧壁的最高点的位置距离所述发光二极管芯片的半导体外延叠层的第一表面101的距离范围为大于0.1μm。
在本发明的第十一个实施例中，跟实施例10的区别在于，可采用实施例7的芯片结构作为发光装置的光源。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本申请的保护范围。

Claims (22)

  1. 一种发光二极管，包括：
    半导体层序列，具有侧壁以及相对设置的第一表面和第二表面，包括在所述第一表面和第二表面之间顺序排列的第一类型半导体层、设计用于产生辐射的有源层、第二类型半导体层，
    与第一类型半导体层电连接的第一电连接层，
    与第二类型半导体层电连接的第二电连接层，
    半导体层序列的第二表面具有凹处，凹处至少贯穿有源层、第二类型半导体层和部分第一类型半导体层，
    绝缘层从凹处延伸至第二表面，
    第一电连接层在凹处内形成突出部，第一电连接层通过凹处与第一类型半导体层电连接，
    在第一电连接层和第二电连接层之间设置绝缘层，利用绝缘层将第一电连接层和第二电连接层电隔离，第一电连接层包括反射金属；
    其特征在于，凹处位于侧壁边缘，
    部分从侧壁露出，至少凹处上方的侧壁具有表面粗化。
  2. 根据权利要求1所述的一种发光二极管，其特征在于，凹处上方的侧壁表面粗化的平均粒径0.05μm至2μm。
  3. 根据权利要求1所述的一种发光二极管，其特征在于，凹处沿着侧壁连续或者离散设置。
  4. 根据权利要求1所述的一种发光二极管，其特征在于，发光二极管单边尺寸小于500μm时，凹处沿侧壁连续设置，发光二极管单边尺寸不小于500μm时，凹处沿侧壁离散分布。
  5. 根据权利要求4所述的一种发光二极管，其特征在于，凹处离散设置时，凹处之间的侧壁包括第一类型半导体层、有源层和第二类型半导体层。
  6. 根据权利要求4所述的一种发光二极管，其特征在于，侧壁包括第一侧壁和第二侧壁，第一侧壁包括第一类型半导体层，第二侧壁包括第二类型半导体层，第一侧壁的平均粗糙度不小于第二侧壁。
  7. 根据权利要求1所述的一种发光二极管，其特征在于，第一侧壁的高度高于第二侧壁。
  8. 根据权利要求1所述的一种发光二极管，其特征在于，第一侧壁和/或第二侧壁与竖直面的角度为20°至60°。
  9. 根据权利要求1所述的一种发光二极管，其特征在于，侧壁表面具有阶梯，阶梯数量不小于3。
  10. 根据权利要求9所述的一种发光二极管，其特征在于，所述阶梯宽度范围为1nm~5000nm。
  11. 根据权利要求9所述的一种发光二极管，其特征在于，至少部分阶梯为表面粗化，从第二类型半导体层至第一类型半导体层，自下而上由光滑到粗糙，表面粗化的粒径从第二类型半导体层至第一类型半导体层，自下而上由小至大分层排布。
  12. 根据权利要求1所述的一种发光二极管，其特征在于，第二表面一侧还设置有导电或者绝缘衬底。
  13. 根据权利要求1所述的一种发光二极管，其特征在于，第一类型半导体层、有源层和/或第二类型半导体层为氮化镓基，表面粗化为湿法蚀刻，蚀刻液体包括KOH或者NaOH，一次蚀刻制作完成。
  14. 根据权利要求1所述的一种发光二极管，其特征在于，第一表面为出光面，第一表面至少部分区域为粗化表面。
  15. 根据权利要求14所述的一种发光二极管，其特征在于，凹处对应的第一表面位置具有粗化表面或者图案化表面，且粗化表面或者图案化表面的面积至少为凹处截面积的120%。
  16. 根据权利要求1所述的一种发光二极管，其特征在于，反射金属包括银、铝、金、钛或者铑。
  17. 根据权利要求1所述的一种发光二极管，其特征在于，凹处的侧壁包括第一类型半导体层，第一类型半导体层为N型半导体层，第一类型半导体层为硅掺杂，第二类型半导体层为P型半导体层，第一类型半导体层生长温度高于第二类型半导体层，第一类型半导体层生长速度快于第二类型半导体层。
  18. 根据权利要求1所述的一种发光二极管，其特征在于，第一电连接层和/或第二电连接层包括透明导电层，透明导电层用于制作欧姆接触。
  19. 根据权利要求1所述的一种发光二极管，其特征在于，突出部距离侧壁的距离不大于8μm。
  20. 根据权利要求1所述的一种发光二极管，其特征在于，凹处位于发光二极管的切割道上。
  21. 根据权利要求1所述的一种发光二极管，其特征在于，绝缘层部分覆盖凹处，凹处内设置有绝缘通孔，绝缘通孔漏出第一类型半导体层，使得第一电连接层的突出部与第一类型半导体层电接触；
    绝缘层与第二表面部分接触，并通过漏出第二类型半导体层，使得第二电连接层与第二类型半导体层电接触。
  22. 一种发光装置，具有封装基板和胶层，其特征在于，包括权利要求1至权利要求21中任意一项所述的发光二极管，发光二极管至少部分侧壁被胶层覆盖。
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US10290769B2 (en) * 2017-01-16 2019-05-14 Seoul Viosys Co., Ltd. Vertical type light emitting diode having groove disposed under the first conductivity type semiconductor layer
CN112018220A (zh) * 2019-05-30 2020-12-01 首尔伟傲世有限公司 垂直型发光二极管
CN112582522A (zh) * 2019-09-30 2021-03-30 成都辰显光电有限公司 微发光二极管芯片及其制作方法
CN111864022A (zh) * 2020-07-23 2020-10-30 天津三安光电有限公司 一种半导体发光元件及其制备方法

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