WO2022257061A1 - 发光二极管及制作方法 - Google Patents

发光二极管及制作方法 Download PDF

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Publication number
WO2022257061A1
WO2022257061A1 PCT/CN2021/099307 CN2021099307W WO2022257061A1 WO 2022257061 A1 WO2022257061 A1 WO 2022257061A1 CN 2021099307 W CN2021099307 W CN 2021099307W WO 2022257061 A1 WO2022257061 A1 WO 2022257061A1
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Prior art keywords
layer
light
emitting diode
metal
light emitting
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PCT/CN2021/099307
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English (en)
French (fr)
Inventor
贾月华
彭钰仁
王笃祥
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天津三安光电有限公司
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Priority to CN202180003029.3A priority Critical patent/CN113841261A/zh
Priority to PCT/CN2021/099307 priority patent/WO2022257061A1/zh
Publication of WO2022257061A1 publication Critical patent/WO2022257061A1/zh
Priority to US18/455,975 priority patent/US20230402572A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body

Definitions

  • the invention relates to a light-emitting diode, which belongs to the field of semiconductor optoelectronic devices and technologies.
  • LED Light Emitting Diode
  • LEDs have the advantages of high luminous intensity, high efficiency, small size, and long service life, and is considered to be one of the most potential light sources at present.
  • LEDs have been widely used in daily life, such as lighting, signal display, backlight, car lights, and large-screen displays. At the same time, these applications also put forward higher requirements for the brightness and luminous efficiency of LEDs.
  • Existing light emitting diodes include horizontal types and vertical types.
  • Vertical type light emitting diodes are obtained by transferring the semiconductor epitaxial stack to other substrates such as silicon, silicon carbide or metal substrates, and removing the original epitaxial growth substrate, which can effectively improve the epitaxial growth compared with the horizontal type
  • the technical problems of light absorption, current crowding or poor heat dissipation caused by the substrate generally adopts a bonding process, and the bonding is mainly through metal-metal high temperature and high pressure bonding, that is, a metal bonding layer is formed between the semiconductor epitaxial stack side and the substrate.
  • the other side of the semiconductor epitaxial stack provides a light-emitting side, and the light-emitting side is equipped with a wire electrode to provide current injection or outflow, and the substrate below the semiconductor epitaxial stack provides current outflow or inflow, thereby forming a current that passes through the semiconductor epitaxial stack vertically. layer of light-emitting diodes.
  • a metal reflective layer and a light-transmitting dielectric layer are usually designed on one side of the metal bonding layer to form an ODR reflection structure, which reflects the light from the side of the metal bonding layer to the light output side to improve the light extraction efficiency.
  • the opening of the light-transmitting dielectric layer produces an ohmic contact layer, and the adhesion layer is between the light-transmitting dielectric layer and the metal reflection layer, thereby improving the problem of poor adhesion between the light-transmitting dielectric layer and the metal reflection layer.
  • the ohmic contact between the ohmic contact layer and the semiconductor epitaxial stack is affected, resulting in the problem of high voltage in the chip structure.
  • the present invention forms an anti-metal diffusion layer between the ohmic contact layer and the adhesion layer, which can prevent the metal in the ohmic contact layer from diffusing to the adhesion layer, thereby solving the problem of metal diffusion in the ohmic contact layer.
  • the metal diffuses into the adhesion layer, affecting the ohmic contact between the ohmic contact layer and the semiconductor epitaxial stack, which causes the voltage rise of the light emitting diode.
  • the present invention provides a light emitting diode, comprising: a semiconductor epitaxial stack, including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer, with opposite first and second surfaces, Wherein the first surface is a light-emitting surface; the light-transmitting dielectric layer is located on the second surface side of the semiconductor epitaxial stack, and has a plurality of openings penetrating through the light-transmitting dielectric layer to form a plurality of through holes; the ohmic contact layer, Filling the through hole of the light-transmitting dielectric layer; an adhesion layer, located on the side of the light-transmitting dielectric layer away from the semiconductor epitaxial stack; a metal reflective layer, located on the side of the adhesion layer away from the semiconductor epitaxial stack side; it is characterized in that: an anti-metal diffusion layer is contained between the ohmic contact layer and the adhesion layer.
  • the metal diffusion prevention layer is located in the through hole of the light-transmitting dielectric layer.
  • the anti-metal diffusion layer fills the through holes of the light-transmitting dielectric layer and partially extends out of the through holes.
  • the ohmic contact layer and the adhesion layer contain the same metal atomic composition.
  • the mobility of the metal atoms in the metal diffusion preventing layer is lower than that of the metal atoms in the ohmic contact layer.
  • the anti-metal diffusion layer is a combination of one or more materials among Pt, Ti, Ni and Cr.
  • the thickness of the light-transmitting dielectric layer is greater than the thickness of the ohmic diffusion layer.
  • the thickness of the metal diffusion preventing layer is 30nm ⁇ 120nm.
  • the ohmic contact layer is a combination of one or more materials of conductive metal compounds, wherein the conductive metal is Au, Ag or Al, and the other material includes at least Zn, Be, Ge, Ni.
  • the thickness of the transparent dielectric layer is 100nm-500nm.
  • the adhesive layer is made of a material with high light transmittance for good adhesion between the light-transmitting dielectric layer and the metal reflective layer.
  • the adhesion layer is IZO or ITO.
  • the thickness of the adhesion layer is 2-10 nm.
  • the light-transmitting dielectric layer has a single-layer or multi-layer structure, and is composed of at least one material among nitrides, oxides or fluorides.
  • the metal reflective layer has a reflectivity above 70%.
  • the metal reflective layer is formed of at least one metal or alloy of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf.
  • the emission wavelength of the light emitting diode is red light or infrared light.
  • the light emitting diode further includes a first electrode on the light emitting surface and a second electrode electrically connected to the metal layer.
  • the substrate is a conductive substrate, and the substrate is located between the metal reflective layer and the second electrode.
  • the semiconductor epitaxial stack of the light emitting diode further includes a plurality of recesses, the plurality of recesses are opened from the second surface side and extend through the active layer to a bottom close to the first surface side.
  • the present invention also proposes an illuminating device, which is characterized in that it includes the light-emitting diode described in any one of the preceding items.
  • the present invention also proposes a method for manufacturing a light-emitting diode, comprising the following steps:
  • a semiconductor epitaxial stack including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer, the semiconductor epitaxial stack has opposite first and second surfaces, wherein the first surface for the light-emitting surface;
  • the manufacturing method of the light-emitting diode further includes forming a first electrode on the light-emitting surface and forming a second electrode on the metal reflective layer.
  • the anti-metal diffusion layer is a combination of one or more materials among Pt, Ti, Ni and Cr.
  • the thickness of the metal diffusion preventing layer is 30nm-120nm.
  • the ohmic contact layer and the anti-metal diffusion layer fill the through holes of the light-transmitting dielectric layer, which can ensure the flatness of the metal reflective layer interface and improve the emissivity of the light-emitting diode, thereby improving the light-emitting efficiency of the light-emitting diode;
  • the ohmic contact layer and the anti-metal diffusion layer fill the through holes of the light-transmitting dielectric layer, which can reduce the generation of holes when the semiconductor epitaxial stack is bonded to the substrate, and improve the bonding yield of the light-emitting diode.
  • FIG. 1 is a schematic cross-sectional view of the light emitting diode mentioned in Embodiment 1.
  • FIG. 2 is a schematic top view of the light emitting diode mentioned in Embodiment 1. Referring to FIG.
  • FIG. 3 is a schematic cross-sectional view of another light-emitting diode mentioned in Embodiment 1.
  • FIG. 4 is a schematic diagram of an epitaxial structure provided in the manufacturing process mentioned in Embodiment 2, and the epitaxial structure includes a semiconductor epitaxial stack.
  • FIG. 5 is a schematic diagram of forming a light-transmitting dielectric on the second surface side of the semiconductor epitaxial stack provided in the manufacturing process mentioned in Embodiment 2 and forming a through hole to expose the second surface side of the semiconductor epitaxial stack.
  • FIG. 6 is a schematic structural view of forming an ohmic contact layer and an anti-metal diffusion layer through holes in the light-transmitting dielectric layer provided in the manufacturing process mentioned in Example 2.
  • FIG. 6 is a schematic structural view of forming an ohmic contact layer and an anti-metal diffusion layer through holes in the light-transmitting dielectric layer provided in the manufacturing process mentioned in Example 2.
  • FIG. 7 is a schematic structural view of an adhesion layer formed on a light-transmitting dielectric layer provided in the manufacturing process mentioned in Embodiment 2.
  • FIG. 7 is a schematic structural view of an adhesion layer formed on a light-transmitting dielectric layer provided in the manufacturing process mentioned in Embodiment 2.
  • FIG. 8 is a schematic diagram of a structure obtained by transferring the semiconductor epitaxial stack provided in the manufacturing process mentioned in Embodiment 2 to a substrate through a bonding process and removing the growth substrate.
  • FIG. 9 is a schematic diagram of the structure obtained after forming the first electrode on the second conductivity type semiconductor layer in the manufacturing process mentioned in the second embodiment.
  • FIG. 10 is a schematic cross-sectional view of the light emitting diode mentioned in the third embodiment.
  • FIG. 11 is a schematic cross-sectional view of the light-emitting diode mentioned in Embodiment 4.
  • FIG. 12 is a schematic cross-sectional view of the light emitting diode mentioned in Embodiment 5.
  • 10 growth substrate; 100: substrate; 101: metal bonding layer; 102: metal reflective layer; 103: adhesion layer; 104: light-transmitting dielectric layer; 105: ohmic contact layer; 106 : anti-metal diffusion layer; 107: first conductivity type semiconductor layer; 108: active layer; 109: second conductivity type semiconductor layer; 110: first electrode; 110a: pad electrode; 110b: extension electrode; Two electrodes; 112: an insulating layer; 113: a second metal layer; S1: the first surface of the semiconductor epitaxial stack; S2: the second surface of the semiconductor epitaxial stack; V 1: the opening of the light-transmitting dielectric layer.
  • the present invention provides the following light-emitting diode, as shown in Figure 1, which includes the following stacked layers: 100: substrate; 101: metal bonding layer; 102: metal reflective layer; 103: adhesion layer; 104: transparent Photoelectric dielectric layer; 105: ohmic contact layer; 106: anti-metal diffusion layer; 107: first conductivity type semiconductor layer; 108: active layer; 109: second conductivity type semiconductor layer; 110: first electrode; 111: second electrode.
  • the substrate 100 is a conductive substrate, and the conductive substrate can be silicon, silicon carbide or a metal substrate, and the metal substrate is preferably a copper, tungsten or molybdenum substrate.
  • the thickness of the substrate 100 is preferably 50 ⁇ m or more.
  • the thickness of the substrate 100 is preferably not more than 300 ⁇ m. In this embodiment, preferably, the substrate 100 is a silicon substrate.
  • the metal bonding layer 101 is a bonding metal material used when one side of the semiconductor epitaxial stack is adhered to the substrate 100, such as metals such as gold, tin, titanium, nickel, platinum, and the metal bonding layer 101 can be a single layer
  • the structure, or multilayer structure, can be a combination of materials.
  • the metal reflective layer 102 is on the upper side of the metal bonding layer 101 and closer to the side of the semiconductor epitaxial stack.
  • the metal reflective layer 102 has a metal reflectivity of more than 70%, and is composed of Ag, Ni, Al, Rh, Pd, Ir, A metal or an alloy of at least one of Ru, Mg, Zn, Pt, Au, and Hf is formed.
  • the metal reflective layer 102 is Au.
  • the metal reflective layer 102 can reflect the light radiated from the semiconductor epitaxial stack toward the substrate 100 back to the semiconductor epitaxial stack, and radiate out from the light exit side.
  • the light emitting surface of the light emitting diode is located on a side of the second conductivity type semiconductor layer 109 away from the active layer 108 .
  • the light-transmitting dielectric layer 104 is located between the first conductivity type semiconductor layer 107 and the adhesion layer 103, and is used to provide an ohmic contact position on one side of the semiconductor epitaxial stack. Therefore, it is necessary to select a high-resistance insulating material such as fluorine compound or oxide or nitride, specifically at least one material among ZnO, SiO 2 , SiO x , SiO x N y , Si 3 N 4 , Al 2 O 3 , TiO x , MgF or GaF.
  • a high-resistance insulating material such as fluorine compound or oxide or nitride, specifically at least one material among ZnO, SiO 2 , SiO x , SiO x N y , Si 3 N 4 , Al 2 O 3 , TiO x , MgF or GaF.
  • the light-transmitting dielectric layer 104 is located on the side of the first conductive type semiconductor layer 107 away from the active layer 108, and the light-transmitting dielectric layer 104 is also used to reflect the light radiation of the active layer 108 back to the semiconductor epitaxial stack or The sidewall emits light. Therefore, it is preferable to select a material with a low refractive index to increase the probability of reflection of light radiation passing through the semiconductor epitaxial stack to the surface of the light-transmitting dielectric layer 104.
  • the refractive index is preferably below 1.5, such as silicon oxide.
  • the thickness of the light-transmitting dielectric layer 104 is preferably 100 nm or more, for example, 100-500 nm, more preferably 100-400 nm, or more preferably 150-400 nm.
  • the light transmittance of the light-transmitting dielectric layer 104 is at least 70%, preferably 80% or more, and more preferably 90% or more.
  • the light-transmitting dielectric layer 104 is a single layer or multiple layers of different materials, or is formed by stacking two above-mentioned insulating layer materials with different refractive indices. More preferably, the optical thickness of the light-transmitting dielectric layer is in the range of integer multiples of (light emitting wavelength/4). A series of openings V1 penetrating through the light-transmitting dielectric layer 104 are formed inside the light-transmitting dielectric layer 104. As shown in FIG. Shape or polygon, the horizontal width of the transparent dielectric layer 104 is preferably 2-10 ⁇ m.
  • An ohmic contact layer 105 may also be included between the metal reflective layer 102 and the light-transmitting dielectric layer 104.
  • the ohmic contact layer 105 passes through at least part of the multiple through holes filling the light-transmitting dielectric layer 104.
  • the ohmic contact layer 105 passes through a plurality of The through hole forms an ohmic contact with the first conductivity type semiconductor layer 107 to uniformly transmit current from the metal reflective layer 103 and the metal bonding layer 102 to the semiconductor epitaxial stack, so the ohmic contact layer 105 covers at least a plurality of through hole regions, Rather than covering the side contacting the first conductive type semiconductor layer 107 in the form of an entire surface.
  • the ohmic contact layer 105 uses a light-transmitting conductive metal.
  • the light-transmitting conductive metal is preferably an alloy material, such as gold-zinc, gold-germanium, gold-germanium-nickel or gold-beryllium, and the ohmic contact layer 105 may have a single-layer or multi-layer structure.
  • the ohmic contact layer 105 is gold zinc.
  • the metal reflective layer 102 and the light-transmitting dielectric layer 104 form an ODR reflective structure, which returns the light radiated from the semiconductor epitaxial stack towards the substrate 100 back to the semiconductor epitaxial stack, and radiates out from the light output side to improve the light output efficiency.
  • the adhesion layer 103 is formed on the side of the light-transmitting dielectric layer 104 away from the semiconductor epitaxial stack, and the adhesion layer 103 is a light-transmitting conductive material.
  • the light-transmitting conductive material is specifically IZO or ITO, etc., and more A material with good adhesion between the light-transmitting dielectric layer 104 and the metal reflective layer 102 such as gold or silver is preferred.
  • the thickness of the adhesion layer 103 is at most one-fifth of the thickness of the light-transmitting dielectric layer 104 , or specifically, the thickness of the adhesion layer is at most 10 nm, at least 1 nm. A range higher than this thickness will destroy the reflectivity of the light-transmitting dielectric layer 104, resulting in severe light absorption. Values below this thickness range will result in poor adhesion.
  • the light transmittance of the adhesive layer 103 such as IZO or ITO is generally lower than the light transmittance of the light-transmitting dielectric layer 104 .
  • the adhesive layer in this thickness range is a continuous film layer or more preferably a discrete layer.
  • the metal in the ohmic contact layer 105 is in direct contact with the adhesion layer 103, and a diffusion phenomenon will occur.
  • the ohmic contact layer 105 is AuZn
  • the adhesion layer 103 is IZO or ITO.
  • the metal Zn in the ohmic contact layer 105 will diffuse to the adhesion layer. 103 , thereby affecting the ohmic contact between the ohmic contact layer 105 and the first conductive type semiconductor layer 107 , thereby causing the voltage of the semiconductor light emitting diode to increase.
  • the light-emitting diode in this embodiment contains an anti-metal diffusion layer 106, and the anti-metal diffusion layer 106 is located between the ohmic contact layer 105 and the adhesion layer 103. Between, the mobility of the metal atoms in the metal diffusion preventing layer 106 is lower than that of the metal atoms in the ohmic contact layer 105 , so the metal diffusion layer 106 can block the diffusion of the metal atoms in the ohmic contact layer 105 .
  • the metal diffusion layer 106 is located in the through hole of the transparent dielectric layer 104. As shown in FIG. The surface of the layer is basically flat, which can ensure the flatness of the subsequent metal reflective layer 102, thereby improving the reflectivity of the metal reflective layer 102, thereby improving the reflectivity of the light-emitting diode.
  • the anti-metal diffusion layer 106 fills the through hole of the transparent dielectric layer 104 and partially extends out of the through hole, as shown in FIG. 3 .
  • the anti-metal diffusion layer 106 is a combination of one or more materials among Pt, Ti, Ni and Cr.
  • the thickness of the anti-metal diffusion layer 106 is 30nm-120nm, preferably 50nm-100nm.
  • the semiconductor epitaxial stack has a first surface S1, a second surface S2 opposite to the first surface S1, and sidewalls connecting the first surface S1 and the second surface S2.
  • the semiconductor epitaxial stack is obtained by MOCVD or other growth methods. It is a semiconductor material that can provide conventional radiation such as ultraviolet, blue, green, yellow, red, and infrared light.
  • it can be a material of 200 ⁇ 950nm, such as the common Nitride, specifically GaN-based semiconductor epitaxial stacks, GaN-based epitaxial stacks are often doped with elements such as aluminum and indium, which mainly provide radiation in the 200-550nm band; or common AlGaInP-based or AlGaAs-based semiconductor epitaxial stacks mainly provide radiation in the 550-950nm band.
  • the semiconductor epitaxial stack mainly includes a first conductivity type semiconductor layer 107 , a second conductivity type semiconductor layer 109 and an active layer 108 located between the first conductivity type semiconductor layer 107 and the second conductivity type semiconductor layer 109 .
  • the first conductive type semiconductor layer 107 and the second conductive type semiconductor layer 109 can be doped by n-type or p-type respectively to provide at least electrons or holes respectively.
  • the n-type semiconductor layer may be doped with an n-type dopant such as Si, Ge or Sn
  • the p-type semiconductor layer may be doped with a p-type dopant such as Mg, Zn, Ca, Sr or Ba.
  • the first conductive type semiconductor layer 107, the active layer 108, and the second conductive type semiconductor layer 109 can specifically be aluminum gallium indium nitrogen, gallium nitride, aluminum gallium nitrogen, aluminum indium phosphide, aluminum gallium indium phosphide, or gallium arsenide or aluminum Made of materials such as gallium arsenic.
  • the first conductivity type semiconductor layer 107 or the second conductivity type semiconductor layer 109 includes a cover layer that provides electrons or holes, and may include other layer materials such as a current spreading layer, a window layer or an ohmic contact layer, etc., according to the doping concentration or The content of the components is different to be set as different multi-layers.
  • the active layer 108 is a region for recombination of electrons and holes to provide light radiation. Different materials can be selected according to different emission wavelengths.
  • the active layer 108 can be a periodic structure of single quantum well or multiple quantum wells. By adjusting the composition ratio of the semiconductor material in the active layer 108 , it is desired to radiate light of different wavelengths.
  • the semiconductor epitaxial stack is made of AlGaInP-based material.
  • the first electrode 110 is disposed on the light emitting side of the semiconductor epitaxial stack.
  • the first electrode 110 includes a pad electrode 110a and an extension electrode 110b, wherein the pad electrode 110a is mainly used for external wiring during packaging.
  • the pad electrodes 110a can be designed in different shapes according to actual wire bonding needs, such as cylindrical or square or other polygonal shapes.
  • the extension electrode 110b may be formed in a predetermined pattern shape, and the extension electrode 110b may have various shapes, specifically, a strip shape.
  • the light emitting diode further includes a second electrode 111 , and in this embodiment, the second electrode 111 is formed on the back side of the substrate 100 in the form of an entire surface.
  • the substrate 100 in this embodiment is a conductive support substrate, and the first electrodes 110 and the second electrodes 111 are formed on both sides of the substrate 100 to realize vertical current flow through the semiconductor epitaxial stack and provide a uniform current density.
  • the first electrode 110 and the second electrode 111 are preferably made of metal materials. At least the pad electrode part 110a and the extension electrode part 110b of the first electrode 110 may also include a metal material to form a good ohmic contact with the semiconductor epitaxial stack.
  • a semiconductor epitaxial stack including the first conductivity type semiconductor layer 107, the second conductivity type semiconductor layer 109 and the semiconductor layer between the first conductivity type semiconductor layer 107 and the second conductivity type semiconductor layer 109.
  • the active layer 108 has a first surface S1 and a second surface S2 opposite to each other, wherein the first surface S1 is a light-emitting surface.
  • a growth substrate 10 preferably a gallium arsenide substrate, on which a semiconductor epitaxial stack is epitaxially grown by an epitaxial process such as MOCVD, and the semiconductor epitaxial stack includes a first conductivity type semiconductor layer 107 , the second conductivity type semiconductor layer 109 and the active layer 108 located between the first conductivity type semiconductor layer 107 and the second conductivity type semiconductor layer 109 .
  • the second conductivity type semiconductor layer 109 can be an n-type semiconductor with different electrical properties; on the contrary, when the first conductivity type semiconductor layer 107 is an n-type semiconductor, the second conductivity type The semiconductor 109 can be a p-type semiconductor with different electrical properties.
  • the active layer 108 can be a neutral, p-type or n-type semiconductor. When a current is applied through the semiconductor epitaxial stack, the active layer 108 is excited to emit light.
  • the first conductivity type semiconductor layer 107 is a p-type semiconductor layer.
  • the semiconductor epitaxial stack is preferably an AlGaInP-based material, and the active layer radiates red light or infrared light.
  • a light-transmitting dielectric layer 104 is prepared on the side of the first conductivity type semiconductor layer 107 away from the active layer 108.
  • the light-transmitting dielectric layer 104 is preferably SiO 2 or MgF 2 ;
  • the thickness of the light-transmitting dielectric layer 104 is preferably more than 100 nm, such as 100-500 nm, more preferably 100-400 nm, or more preferably 150-400 nm.
  • the ohmic contact layer 105 is formed in the through hole of the light-transmitting dielectric layer 104 , and the ohmic contact layer 105 uses a light-transmitting conductive metal.
  • the light-transmitting conductive metal is preferably an alloy material, such as gold-zinc, gold-germanium, gold-germanium-nickel, or gold-beryllium.
  • the ohmic contact 105 is gold zinc.
  • the thickness of the ohmic contact layer 105 is 80-400 nm, preferably more than 150 nm, more preferably more than 200 nm.
  • an anti-metal diffusion layer 106 is formed on the ohmic contact layer 105, and the material of the anti-metal diffusion layer 106 is a combination of one or more materials among Pt, Ti, Ni, and Cr.
  • the metal diffusion layer 106 of the anti-ohmic contact layer has a thickness of 30nm-120nm.
  • the light-transmitting dielectric layer 104 is substantially flush with the surface of the anti-metal diffusion layer 106, which can ensure the flatness of the metal reflective layer 102, thereby improving the reflectivity of the metal reflective layer 102 and improving the luminescence of the light-emitting diode. efficiency.
  • an adhesive layer 103 is then formed on the side of the light-transmitting dielectric layer 104 away from the active layer 108.
  • the adhesive layer 103 is such as IZO or ITO.
  • the adhesive layer 103 is preferably
  • the layer 103 is IZO, and the thickness is less than 10 nm, preferably 2-10 nm.
  • the metal reflective layer 102 is preferably Au or Ag, in this embodiment, the preferred material of the metal reflective layer is Au;
  • a bonding layer 101 is provided on one side of the metal reflective layer 102, and the substrate 100 is bonded through a bonding process; then, the growth substrate 10 is removed by a wet etching process to obtain the structure shown in FIG. 8 ;
  • the first electrode 110 is formed on the second conductive type semiconductor layer 109, the first electrode 110 includes the main electrode 110a and the extension electrode 110b of the wiring part, wherein the main electrode 110a and the extension electrode 110b are respectively provided Wire placement and horizontal current extension.
  • a back electrode 111 is formed on the back side of the substrate 100 to obtain a light emitting diode as shown in FIG. 1 .
  • the metal in the ohmic contact layer 105 can be prevented from diffusing to the adhesion layer 103, thereby solving the problem of metal diffusion in the ohmic contact layer 105.
  • the diffusion of the metal into the adhesion layer 103 affects the voltage rise of the light-emitting diode caused by the ohmic contact between the ohmic contact layer 105 and the semiconductor epitaxial stack.
  • the ohmic contact layer 105 and the anti-metal diffusion layer 106 fill the through hole of the light-transmitting dielectric layer 104, which can ensure the flatness of the interface of the metal reflective layer 102, improve the reflectivity of the light-emitting diode, thereby improving the light-emitting efficiency of the light-emitting diode;
  • the generation of holes when the semiconductor epitaxial stack is bonded to the substrate 100 is minimized, and the bonding yield of the light emitting diode is improved.
  • the first semiconductor epitaxial stack Surface S1 has a roughened structure.
  • the first electrode 110 and the second electrode 111 are led out from the second surface S2 side of the semiconductor epitaxial stack, and are electrically connected to the outside.
  • the structure includes a semiconductor epitaxial stack, wherein the first conductivity type semiconductor layer 107, the active layer 108 and the second conductivity type semiconductor layer 109 are stacked layer by layer, and the first surface of the semiconductor epitaxial stack S1 is the light-emitting surface, and the second surface S2 side is the first conductivity type semiconductor layer 107, which has a plurality of independent recesses, and the recesses extend from the second surface side to pass through the active layer 108 to the bottom and contact the second type semiconductor layer 109 , the horizontal width of the concave portion is more than 1 ⁇ m, and the concave portion occupies 1-20% of the area of the second surface side.
  • the light-transmitting dielectric layer 104 and the adhesion layer 103 are formed at least on the second surface S1 side of the semiconductor epitaxial stack, wherein the light-transmitting dielectric layer 104 can also extend to cover the sidewall surfaces of the plurality of recesses, and the light-transmitting dielectric layer 104 has a plurality of openings on the second surface S2 side of the semiconductor epitaxial stack to form a plurality of through holes, and the metal reflective layer 102 is located on the surface side of the adhesive layer.
  • the light-transmitting dielectric layer 104 exposes the positions of the plurality of recesses.
  • the ohmic contact layer 105 fills the through hole of the light-transmitting dielectric layer, and is in direct contact with the second surface S2 side of the semiconductor epitaxial stack.
  • the anti-metal diffusion layer 106 is located between the adhesion layer 103 and the ohmic contact layer 105, which can prevent the metal of the ohmic contact layer 105 from diffusing into the adhesion layer 103, thereby solving the problem of metal diffusion in the ohmic contact layer 105 to the adhesion layer.
  • the material of the insulating layer 112 can be oxide or nitride or fluoride, such as silicon oxide or silicon nitride.
  • the insulating layer 112 can also be extended To cover the side wall of the recess, exposing the bottom of the recess.
  • the second metal layer 113 is on the surface of the insulating layer 112 , and the second metal layer 113 is in contact with the second conductivity type semiconductor layer 109 by filling the plurality of openings of the semiconductor epitaxial stack through the recesses to the bottom.
  • the metal reflective layer 102 also includes a part of the surface is exposed to be provided with the first electrode 109
  • the second metal layer 113 also includes a part of the surface is exposed and provided with the second electrode 110
  • the first electrode 109 and the second electrode 110 are located on the semiconductor epitaxial stack Same side around, for external wire punching.
  • One side of the second metal layer 113 also has a substrate 100 , which is a conductive or non-conductive substrate, and the second metal layer 113 also includes a bonding layer for bonding the substrate.
  • the substrate 100 is a conductive substrate
  • the second electrode 111 is provided on the back side of the conductive substrate 100 for external electrical connection.

Abstract

本发明公开发光二极管，包括：半导体外延叠层，包含第一导电类型半导体层、有源层和第二导电类型半导体层，具有相对的第一表面和第二表面；透光性电介质层，位于所述半导体外延叠层的第二表面侧，具有多个开口贯穿所述透光性电介质层，形成多个贯穿孔；欧姆接触层，填充所述透光性电介质层的贯穿孔；粘附层，位于所述透光性电介质层远离半导体外延叠层的一侧；金属反射层，位于所述粘附层远离半导体外延叠层的一侧；其特征在于：所述欧姆接触层和粘附层之间含有防金属扩散层，可防止欧姆接触层中的金属往所述粘附层扩散，防止发光二极管的电压升高，欧姆接触层填充透光性电介质层的贯穿孔，可防止键合层的孔洞产生，提升发光二极管的打线良率。

Description

发光二极管及制作方法 技术领域
本发明涉及一种发光二极管，属于半导体光电子器件与技术领域。
 背景技术
发光二极管(Light Emitting Diode，简称LED)具有发光强度大、效率高、体积小、使用寿命长等优点，被认为是当前最具有潜力的光源之一。近年来，LED已在日常生活中得到广泛应用，例如照明、信号显示、背光源、车灯和大屏幕显示等领域，同时这些应用也对LED的亮度、发光效率提出了更高的要求。
现有的发光二极管包括水平类型和垂直类型。垂直类型的发光二极管通过把半导体外延叠层转移到其它的基板如硅、碳化硅或金属基板上，并移除原始外延生长的衬底的工艺获得，相较于水平类型，可以有效改善外延生长衬底带来的吸光、电流拥挤或散热性差的技术问题。衬底的转移一般采用键合工艺，键合主要通过金属-金属高温高压键合，即在半导体外延叠层一侧与基板之间形成金属键合层。半导体外延叠层的另一侧提供出光侧，出光侧配置有一打线电极提供电流的注入或流出，半导体外延叠层的下方的基板提供电流的流出或流入，由此形成电流垂直经过半导体外延叠层的发光二极管。
为了提高出光效率，通常会在金属键合层的一侧设计金属反射层与透光性电介质层形成ODR反射结构，将金属键合层一侧的出光反射至出光侧，提高出光效率。透光性电介质层开口制造欧姆接触层，粘附层在透光性电介质层和金属反射层之间，改善透光性电介质层和金属反射层粘附性较差的问题。
由于欧姆接触层和粘附层之间存在物质间的扩散，从而影响欧姆接触层与半导体外延叠层之间的欧姆接触，导致该芯片结构存在电压高的问题。
 技术解决方案
为了解决以上的问题，本发明通过在欧姆接触层和粘附层之间形成防金属扩散层，可阻挡欧姆接触层中的金属往所述粘附层扩散，从而可解决因欧姆接触层中的金属扩散至粘附层，影响欧姆接触层与半导体外延叠层的欧姆接触而引起的发光二极管的电压升高的问题。
为实现上述目的，本发明提供一种发光二极管，包括：半导体外延叠层，包含第一导电类型半导体层、有源层和第二导电类型半导体层，具有相对的第一表面和第二表面，其中第一表面为出光面；透光性电介质层，位于所述半导体外延叠层的第二表面侧，具有多个开口贯穿所述透光性电介质层，形成多个贯穿孔；欧姆接触层，填充所述透光性电介质层的贯穿孔；粘附层，位于所述透光性电介质层远离半导体外延叠层的一侧；金属反射层，位于所述粘附层远离半导体外延叠层的一侧；其特征在于：所述欧姆接触层和粘附层之间含有防金属扩散层。
优选地，所述防金属扩散层位于所述透光性电介质层的贯穿孔内。
优选地，所述防金属扩散层填充所述透光性电介质层的贯穿孔并部分延伸至贯穿孔之外。
优选地，所述欧姆接触层和粘附层含有相同的金属原子组成。
优选地，所述防金属扩散层中的金属原子的活动性低于欧姆接触层中的金属原子。
优选地，所述防金属扩散层为Pt，Ti，Ni，Cr中的一种或多种材料的组合。
优选地，所述透光性电介质层的厚度大于所述欧姆扩散层的厚度。
优选地，所述防金属扩散层的厚度为30nm~120nm。
优选地，所述欧姆接触层为导电金属化合物的一种或多种材料的组合，其中导电金属为Au、Ag或Al，另一材料至少包括Zn、Be、Ge、Ni。
优选地，所述透光性电介质层的厚度为100nm~500nm。
优选地，所述粘附层为为对透光性电介质层和金属反射层之间粘附好，透光率高的材料。
优选地，所述粘附层为IZO或者ITO。
优选地，所述粘附层的厚度为2~10nm。
优选地，所述透光性电介质层为单层或者多层结构，为氮化物、氧化物或氟化物中至少一种材料组成。
优选地，所述金属反射层具有70%以上的反射率。
优选地，所述金属反射层为Ag、Ni、Al、Rh、Pd、Ir、Ru、Mg、Zn、Pt、Au以及Hf中的至少一种的金属或者合金形成。
优选地，所述发光二极管的发光波长为红光或者红外光。
优选地，所述发光二极管还包括位于出光面上的第一电极和与金属层电连接的第二电极。
优选地，所述金属反射层下方还具有基板，所述基板为导电性基板，所述基板位于所述金属反射层和第二电极之间。
优选地，所述发光二极管的半导体外延叠层还包含多个凹部，所述多个凹部自第二表面侧开口并延伸穿过有源层至底部靠近第一表面侧。
本发明还提出一种照明装置，其特征在于：包含前述任一项所述的发光二极管。
本发明还提出一种发光二极管的制作方法，包含以下步骤：
（1）提供一半导体外延叠层，包含第一导电类型半导体层、有源层和第二导电类型半导体层，所述半导体外延叠层具有相对的第一表面和第二表面，其中第一表面为出光面；
（2）在所述半导体外延叠层的第二表面侧形成透光性电介质层，在所述透光性电介质层上形成多个开口贯穿所述透光性电介质层，形成多个贯穿孔；
（3）在所述透光性电介质层的贯穿孔内形成欧姆接触层，与所述第一导电类型半导体层接触；
（4）在所述欧姆接触层上形成防金属扩散层；
（5）在所述透光性电介质层远离半导体外延叠层的一侧形成粘附层；
（6）在所述粘附层远离半导体外延叠层的一侧形成金属反射层。
优选地，所述发光二极管的制作方法还包含在所述出光面上形成第一电极和在所述金属反射层上形成第二电极。
优选地，所述防金属扩散层为Pt，Ti，Ni，Cr中的一种或多种材料的组合。
优选地，所述防金属扩散层的厚度为30nm~120nm。
 有益效果
通过本发明的结构和方法设计，可以实现如下技术效果：
1，通过在欧姆接触层和粘附层之间加入防金属扩散层，可阻挡欧姆接触层中的金属往所述粘附层扩散，从而可解决因欧姆接触层中的金属扩散至粘附层，影响欧姆接触层与半导体外延叠层的欧姆接触而引起的发光二极管的电压升高的问题；
2.欧姆接触层和防金属扩散层填充透光性介电层的贯穿孔，可保证金属反射层界面的平整度，提升发光二极管的发射率，从而提升发光二极管的出光效率；
3.欧姆接触层和防金属扩散层填充透光性介电层的贯穿孔，可减少将半导体外延叠层键合至基板时孔洞的产生，提升发光二极管的打线良率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
虽然在下文中将结合一些示例性实施及使用方法来描述本发明，但本领域技术人员应当理解，并不旨在将本发明限制于这些实施例。反之，旨在覆盖包含在所附的权利要求书所定义的本发明的精神与范围内的所有替代品、修正及等效物。
 附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图1为实施例1中所提到的发光二极管的剖面示意图。
图2为实施例1中所提到的发光二极管的俯视示意图。
图3为实施例1 中所提到的另外一种发光二极管的剖面示意图。
图4为实施例2中所提到的制作工艺中提供的外延结构的示意图，外延结构包括半导体外延叠层。
图5为实施例2中所提到的制作工艺中提供的半导体外延叠层第二表面侧形成透光性电介质并形成贯穿孔暴露半导体外延叠层的第二表面侧的示意图。
图6为实施例2中所提到的制作工艺中提供的透光性介电质层的贯穿孔形成欧姆接触层和防金属扩散层的结构示意图。
图7为实施例2中所提到的制作工艺中提供的在透光性电介质层上形成粘附层的结构示意图。
图8为实施例2中所提到的制作工艺中提供的半导体外延叠层经过键合工艺转移至基板并去除生长衬底获得的结构的示意图。
图9为实施例2中所提到的制作工艺中在第二导电型半导体层上形成第一电极后获得的结构的示意图。
图10为实施例3中所提到的发光二极管的剖面示意图。
图11为实施例4中所提到的发光二极管的剖面示意图。
图12为实施例5中所提到的发光二极管的剖面示意图。
图中元件标号说明：10：生长衬底；100：基板；101：金属键合层；102：金属反射层；103：粘附层；104：透光性电介质层；105：欧姆接触层；106：防金属扩散层；107：第一导电类型半导体层；108：有源层；109：第二导电类型半导体层； 110：第一电极；110a：焊盘电极；110b：延伸电极；111：第二电极；112：绝缘层；113：第二金属层；S1：半导体外延叠层的第一表面； S2：半导体外延叠层的第二表面；V 1：透光性电介质层的开口。
 本发明的实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。
实施例 1
本发明提供如下一种发光二极管，如图1所示的剖面示意图，其包括如下堆叠层：100：基板；101：金属键合层；102：金属反射层；103：粘附层；104：透光性电介质层；105：欧姆接触层；106：防金属扩散层；107：第一导电类型半导体层；108：有源层；109：第二导电类型半导体层； 110：第一电极；111：第二电极。
下面针对各结构堆叠层进行详细描述。
所述基板100为导电性基板，导电性基板可以为硅、碳化硅或者金属基板，所述金属基板优选为铜、钨或者钼基板。为了能够以充分的机械强度支撑半导体外延叠层，基板100的厚度优选为50μm以上。另外，为了便于在向半导体外延叠层键合后对基板100的机械加工，优选基板100的厚度不超过300μm。本实施例中，优选基板100为硅基板。
金属键合层101为将半导体外延叠层一侧粘附到基板100上时使用的键合金属材料，如金、锡、钛、镍、铂等金属，该金属键合层101可以是单层结构或者多层结构，可以是多种材料的组合。
金属反射层102在金属键合层101上侧并更靠近半导体外延叠层的一侧，金属反射层102具有70%以上的金属反射率，由包含Ag、Ni、Al、Rh、Pd、Ir、Ru、Mg、Zn、Pt、Au以及Hf中的至少一个的金属或者合金形成。本实施例中，优选所述金属反射层102为Au。该金属反射层102能够反射半导体外延叠层朝向基板100一侧辐射的光线返回至半导体外延叠层，并从出光侧辐射出去。所述发光二极管的出光面位于所述第二导电类型半导体层109远离有源层108的一侧。
透光性电介质层104，位于第一导电类型半导体层107和粘附层103之间，用于在半导体外延叠层一侧开口提供欧姆接触位置，因此，需要选择高阻值的绝缘材料如氟化物或氧化物或氮化物，具体的如ZnO、SiO 2、SiO x、SiO xN y、Si 3N 4、Al 2O 3、TiO x、MgF或GaF中的至少一种材料形成。透光性电介质层104位于所述第一导电型半导体层107的远离有源层108的一侧，透光性电介质层104还用于反射有源层108的光辐射返回至半导体外延叠层或侧壁出光，因此，优选的选用低折射率材料，以增加光辐射穿过半导体外延叠层至透光性电介质层104表面时发生反射的几率，其折射率优选为1.5以下，如氧化硅，透光性电介质层104的厚度优选为100nm以上，例如100~500nm，更优选的是100~400nm，或者更优选的是150~400nm。透光性电介质层104的透光率至少为70%，优选为80%以上，更优选的为90%以上。
更优选的是，所述透光性介电层104为单层或多层不同材料或者由两种不同折射率的上述绝缘层材料重复堆叠而成。更优选地，所述透光性介电层的光学厚度为（发光波长/4）的整数倍数范围。所述透光性电介质层104的内部形成一系列贯穿该透光性电介质层104的开口V1，如图2所示，形成多个贯穿孔，所述开口的水平截面形状可以是圆形或者椭圆形或者多边形，所述透光性电介质层104的水平宽度尺寸优选为2~10μm。
金属反射层102与透光性电介质层104之间还可以包括欧姆接触层105，欧姆接触层105通过至少填充透光性电介质层104的多个贯穿孔的部分区域，欧姆接触层105通过多个贯穿孔与第一导电类型半导体层107形成欧姆接触，以将电流从金属反射层103、金属键合层102均匀地传递到半导体外延叠层，因此欧姆接触层105至少覆盖多个贯穿孔区域，而并不是以整面的形式覆盖接触第一导电型半导体层107的一侧。所述欧姆接触层105使用光透射导电金属。所述光透射导电金属优选为合金材料，如金锌、金锗、金锗镍或金铍等材料，所述欧姆接触层105可以具有单层或者多层结构。本实施例中，优选所述欧姆接触层105为金锌。
所述金属反射层102与透光性电介质层104形成ODR反射结构，将半导体外延叠层朝向基板100一侧辐射的光线返回至半导体外延叠层，并从出光侧辐射出去，提高出光效率。
粘附层103形成在透光性介电层104远离半导体外延叠层的一面侧，所述粘附层103为透光性导电材料，该透光性导电材料具体的如IZO或者ITO等，更优选的是对透光性电介质层104以及金属反射层102如金或银之间粘附性好的材料。
更优选的是粘附层103的厚度至多为透光性电介质层104的厚度的五分之一，或者具体的所述粘附层的厚度至多为10nm，至少1nm。高于该厚度的范围将破坏透光性电介质层104的反射性，导致严重吸光。低于该厚度范围值将导致粘附效果差。粘附层103如IZO或ITO的透光率通常会低于透光性电介质层104的透光率。该厚度范围的粘附层为连续的膜层或更优选的为离散状的层。
欧姆接触层105中的金属与粘附层103直接接触会发生扩散现象，例如欧姆接触层105为AuZn，粘附层103为IZO或者ITO，其中欧姆接触层105的金属Zn会扩散至粘附层103中，从而影响欧姆接触层105与第一导电型半导体层107之间的欧姆接触，从而导致半导体发光二极管的电压会升高。
为了阻挡欧姆接触层105的金属扩散至粘附层103中，本实施例中发光二极管含有防金属扩散层106，所述防金属扩散层106位于所述欧姆接触层105与所述粘附层103之间，所述防金属扩散层106的金属原子的活动性低于所述欧姆接触层105的金属原子，从而金属扩散层106可阻挡欧姆接触层105的金属原子的扩散。
在一些实施例中，所述金属扩散层106位于所述透光性电介质层104的贯穿孔内，如图1所示，所述防金属扩散层106和透光性电介质层104远离半导体外延叠层的表面基本平齐，可保证后续金属反射层102的平整度，从而提升金属反射层102的反射率，从而提升发光二极管的反射率。
在一些实施例中，所述防金属扩散层106填充所述透光性电介质层104的贯穿孔并部分延伸至贯穿孔之外，如图3所示。
所述防金属扩散层106为Pt，Ti，Ni，Cr中的一种或多种材料的组合。所述防金属扩散层106的厚度为30nm~120nm，优选为50nm~100nm。
半导体外延叠层具有第一表面S1和与第一表面S1相对的第二表面S2以及连接第一表面S1和第二表面S2的侧壁。半导体外延叠层通过MOCVD或其它的生长方式获得，为能够提供常规的如紫外、蓝、绿、黄、红、红外光等辐射的半导体材料，具体的可以是200~950nm的材料，如常见的氮化物，具体的如氮化镓基半导体外延叠层，氮化镓基外延叠层常见有掺杂铝、铟等元素，主要提供200~550nm波段的辐射；或者常见的铝镓铟磷基或铝镓砷基半导体外延叠层，主要提供550~950nm波段的辐射。
半导体外延叠层主要包括第一导电型半导体层107、第二导电型半导体层109和位于第一导电型半导体层107和第二导电型半导体层109之间的有源层108。所述第一导电型半导体层107和第二导电型半导体层109可分别通过n型掺杂或p型掺杂以实现至少分别提供电子或空穴。n型半导体层可以掺杂有诸如Si、Ge或者Sn的n型掺杂物，p型半导体层可以掺杂有诸如Mg、Zn、Ca、Sr或者Ba的p型掺杂物。第一导电型半导体层107、有源层108、第二导电型半导体层109具体可以是铝镓铟氮、氮化镓、铝镓氮、铝铟磷、铝镓铟磷或砷化镓或铝镓砷等材料制作形成。第一导电型半导体层107或第二导电型半导体层109中包括提供电子或空穴的覆盖层，以及可以包括其它层材料如电流扩展层、窗口层或欧姆接触层等，根据掺杂浓度或组分含量不同进行设置为不同的多层。有源层108为提供电子和空穴复合提供光辐射的区域，根据发光波长的不同可选择不同的材料，有源层108可以是单量子阱或多量子阱的周期性结构。通过调整活性层有源层108中半导体材料的组成比，以期望辐射出不同波长的光。在本实施例中，优选半导体外延叠层为AlGaInP基材料组成。
第一电极110配置在半导体外延叠层的出光侧上。在一些实施例中，所述第一电极110包括焊盘电极110a和延伸电极110b，其中所述焊盘电极110a主要用于封装时进行外部打线。焊盘电极110a可以根据实际的打线需要设计成不同的形状，具体如圆柱状或方块或其它的多边形。延伸电极110b可以以预定的图案形状形成，并且延伸电极110b可以具有各种形状，具体的如条状。
所述发光二极管还包括第二电极111，本实施例中所述第二电极111以整面的形式形成在基板100的背面侧。本实施例的基板100为导电性支撑基板，第一电极110与第二电极111形成在基板100的两面侧，以实现电流垂直流过半导体外延叠层，提供均匀的电流密度。
第一电极110和第二电极111优选为金属材料制成。第一电极110至少焊盘电极部分110a以及延伸电极部分110b还可以包括实现与半导体外延叠层之间形成良好的欧姆接触的金属材料。
实施例 2
下面对上述实施例1的发光二极管的制作工艺进行详细的说明。
如图4所示，首先提供一半导体外延叠层，包含第一导电类型半导体层107、第二导电类型半导体层109和位于第一导电类型半导体层107和第二导电类型半导体层109之间的有源层108，具有相对的第一表面S1和第二表面S2，其中第一表面S1为出光面。
具体包括以下步骤：提供一个生长衬底10，优选为砷化镓衬底，生长衬底10上通过磊晶工艺如MOCVD外延生长半导体外延叠层，半导体外延叠层包含第一导电类型半导体层107、第二导电类型半导体层109和位于第一导电类型半导体层107和第二导电类型半导体层109之间的有源层108。当第一导电类型半导体层107为p型半导体，第二导电类型半导体层109可为相异电性的n型半导体，相反，当第一导电类型半导体层107为n型半导体，第二导电类型半导体109可为相异电性的p型半导体。有源层108可为中性、p型或n型电性的半导体。施以电流通过半导体外延叠层时，激发有源层108发出光线。本实施例中，优选所述第一导电类型半导体层107为p型半导体层。所述半导体外延叠层优选为AlGaInP基材料，所述活性层辐射红光或者红外光。
如图5所示，接着，在第一导电类型半导体层107远离有源层108的一侧制备透光性电介质层104，本实施例中优选透光性电介质层104为SiO 2或者MgF 2；所述透光性电介质层104的厚度优选为100nm以上，例如100~500nm，更优选的是100~400nm，或者更优选的是150~400nm。通过掩膜和蚀刻工艺，在所述透光性电介质层104形成开口暴露所述半导体外延叠层的第二表面侧，形成多个贯穿孔。
如图6所示，接着，在所述透光性电介质层104的贯穿孔内形成所述欧姆接触层105，所述欧姆接触层105使用光透射导电金属。所述光透射导电金属优选为合金材料，如金锌、金锗、金锗镍或金铍等材料。本实施例中，优选所述欧姆接触105为金锌。所述欧姆接触层105的厚度为80~400nm，优选为150nm以上，更优选的为200nm以上。然后在所述欧姆接触层105上形成防金属扩散层106，所述防金属扩散层106的材料为Pt，Ti，Ni，Cr中的一种或多种材料的组合。优选地，所述防欧姆接触层金属扩散层106的厚度为30nm~120nm。优选地，所述透光性电介质层104与所述防金属扩散层106的表面基本平齐，可保证金属反射层102的平整度，从而提高金属反射层102的反射率，提升发光二极管的发光效率。
如图7所示，接着在所述透光性电介质层104远离有源层108的一侧形成粘附层103，所述粘附层103如IZO或者ITO，本实施例中优选所述粘附层103为IZO，厚度为10nm以下，优选为2~10nm。
如图8所示，然后在所述粘附层103上形成金属反射层102，所述金属反射层优选为Au或者Ag，本实施例中，优选所述金属反射层材料为Au；在所述金属反射层102一侧设置键合层101，并通过键合工艺键合基板100；接着，采用湿法蚀刻工艺将生长衬底10移除，获得如图8所示的结构；
接着，如图9所示，在第二导电型半导体层109上形成第一电极110，第一电极110包括打线部分的主电极110a以及延伸电极110b，其中主电极110a与延伸电极110b分别提供打线位置以及水平电流扩展。
最后，形成背面电极111在基板100的背面侧，得到如图1所示的发光二极管。
本发明通过在欧姆接触层105和粘附层103之间加入防金属扩散层106，可阻挡欧姆接触层105中的金属往所述粘附层103扩散，从而可解决因欧姆接触层105中的金属扩散至粘附层103，影响欧姆接触层105与半导体外延叠层的欧姆接触而引起的发光二极管的电压升高的问题。同时欧姆接触层105和防金属扩散层106填充透光性电介质层104的贯穿孔，可保证金属反射层102界面的平整度，提升发光二极管的反射率，从而提升发光二极管的出光效率；可减小将半导体外延叠层键合至基板100时孔洞的产生，提升发光二极管的打线良率。
实施例 3
与实施例1中图1所示的发光二极管相比，为了进一步提升从有源层108辐射出的光线从出光面中出射的效率，如图10所示，所述半导体外延叠层的第一表面S1具有粗化结构。
实施例 4
作为图1所述结构的改进，如图11所示，第一电极110和第二电极111自所述半导体外延叠层的第二表面S2侧引出，与外部电性连接。
具体的，如图11所示，该结构包括半导体外延叠层，其中第一导电类型半导体层107、有源层108和第二导电类型半导体层109逐层堆叠，半导体外延叠层的第一表面S1为出光面，第二表面S2侧为第一导电类型半导体层107，具有多个独立的凹部，凹部自第二表面侧延伸至穿过有源层108至底部与第二类型半导体层109接触，所示凹部的水平宽度为1μm以上，凹部占据第二表面侧的面积为1~20%。
透光性电介质层104和粘附层103至少形成在半导体外延叠层的第二表面S1侧，其中透光性电介质层104也可延伸至覆盖多个凹部的侧壁表面，透光性电介质层104在半导体外延叠层的第二表面S2侧具有多个开口，形成多个贯穿孔，金属反射层102位于粘附层的表面侧。透光性电介质层104暴露多个凹部的位置。欧姆接触层105填充透光性电介质层的贯穿孔，与半导体外延叠层的第二表面S2侧直接接触。防金属扩散层106位于粘附层103和欧姆接触层105之间，可防止欧姆接触层105的金属扩散至粘附层103中，从而可解决因欧姆接触层105中的金属扩散至粘附层103，影响欧姆接触层105与半导体外延叠层的欧姆接触而引起的发光二极管的电压升高的问题。在金属反射层的表面侧还具有一绝缘层112，绝缘层112的材料可以是氧化物或者氮化物或者氟化物，如氧化硅，氮化硅，在一些实施例中，绝缘层112也可以延伸至覆盖凹部的侧壁，露出凹部的底部。
在绝缘层112的表面具有第二金属层113，第二金属层113通过凹部填充半导体外延叠层的多个开口至底部与第二导电类型半导体层109接触。
金属反射层102还包括一部分表面被暴露以设置有第一电极109，第二金属层113还包含一部分表面暴露设置有第二电极110，第一电极109和第二电极110位于半导体外延叠层的周围的同一侧，用于外部打线。
第二金属层113的一侧还具有基板100，基板为导电或者不导电的基板，第二金属层113还包含键合层，用于键合基板。
实施例 5
作为实施例4的替代性实施例，如图12所示，其中基板100为导电性基板，第二电极111设置在导电性基板100的背面侧用于外部电性连接。
需要说明的是，以上实施方式仅用于说明本发明，而并非用于限定本发明，本领域的技术人员，在不脱离本发明的精神和范围的情况下，可以对本发明做出各种修饰和变动，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应视权利要求书范围限定。

Claims (20)

  1. 发光二极管，包括：
    半导体外延叠层，包含第一导电类型半导体层、有源层和第二导电类型半导体层，具有相对的第一表面和第二表面，其中第一表面为出光面；
    透光性电介质层，位于所述半导体外延叠层的第二表面侧，具有多个开口贯穿所述透光性电介质层，形成多个贯穿孔；
    欧姆接触层，填充所述透光性电介质层的贯穿孔，与所述第一导电类型半导体层接触；
    粘附层，位于所述透光性电介质层远离半导体外延叠层的一侧；
    金属反射层，位于所述粘附层远离半导体外延叠层的一侧；
    其特征在于：所述欧姆接触层和粘附层之间含有防金属扩散层。
  2. 根据权利要求1所述的发光二极管，其特征在于：所述防金属扩散层位于所述透光性电介质层的贯穿孔内。
  3. 根据权利要求1所述的发光二极管，其特征在于：所述透光性电介质层填充所述透光性电介质层的贯穿孔并部分延伸至贯穿孔之外。
  4. 根据权利要求1所述的发光二极管，其特征在于：所述欧姆接触层和粘附层含有相同的金属原子。
  5. 根据权利要求1所述的发光二极管，其特征在于：所述防金属扩散层中的金属原子的活动性低于欧姆接触层中的金属原子。
  6. 根据权利要求1所述的发光二极管，其特征在于：所述防金属扩散层为Pt，Ti，Ni，Cr中的一种或多种材料的组合。
  7. 根据权利要求1所述的发光二极管，其特征在于：所述透光性电介质层的厚度大于所述欧姆扩散层的厚度。
  8. 根据权利要求1所述的发光二极管，其特征在于：所述防金属扩散层的厚度为30nm~120nm。
  9. 根据权利要求1所述的发光二极管，其特征在于：所述欧姆接触层为导电金属化合物的一种或多种材料的组合，其中导电金属为Au、Ag或Al，另一材料至少包括Zn、Be、Ge、Ni。
  10. 根据权利要求1所述的发光二极管，其特征在于：所述透光性电介质层的厚度为100nm~500nm。
  11. 根据权利要求1所述的发光二极管，其特征在于：所述粘附层为对透光性电介质层和金属反射层之间粘附好，透光率高的材料。
  12. 根据权利要求1所述的发光二极管，其特征在于：所述粘附层为IZO或者ITO。
  13. 根据权利要求1所述的发光二极管，其特征在于：所述粘附层的厚度为2~10nm。
  14. 根据权利要求1所述的发光二极管，其特征在于：所述透光性介电层为单层或者多层结构，为氮化物、氧化物或氟化物中至少一种材料组成。
  15. 根据权利要求1所述的发光二极管，其特征在于：所述金属反射层具有70%以上的反射率。
  16. 根据权利要求1所述的发光二极管，其特征在于：所述金属反射层为Ag、Ni、Al、Rh、Pd、Ir、Ru、Mg、Zn、Pt、Au以及Hf中的至少一种的金属或者合金形成。
  17. 根据权利要求1所述的发光二极管，其特征在于：所述发光二极管的发光波长为红光或者红外光。
  18. 根据权利要求1所述的发光二极管，其特征在于：所述发光二极管的半导体外延叠层还包含凹部，所述凹部自第二表面侧开口并延伸穿过有源层至底部靠近第一表面侧。
  19. 一种照明装置，其特征在于：包含权利要求1~18中任一项所述的发光二极管。
  20. 一种发光二极管的制作方法，包含以下步骤：
    （1）提供一半导体外延叠层，包含第一导电类型半导体层、有源层和第二导电类型半导体层，所述半导体外延叠层具有相对的第一表面和第二表面，其中第一表面为出光面；
    （2）在所述半导体外延叠层的第二表面侧形成透光性电介质层，在所述透光性电介质层上形成多个开口贯穿所述透光性电介质层，形成多个贯穿孔；
    （3）在所述透光性电介质层的贯穿孔内形成欧姆接触层；
    （4）在所述欧姆接触层上形成防金属扩散层；
    （5）在所述透光性电介质层远离半导体外延叠层的一侧形成粘附层；
    （6）在所述粘附层远离半导体外延叠层的一侧形成金属反射层。
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CN117790659A (zh) * 2024-02-26 2024-03-29 诺视科技(苏州)有限公司 具有全方位反射镜结构的微显示发光像素及其制作方法

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