WO2023116357A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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WO2023116357A1
WO2023116357A1 PCT/CN2022/134890 CN2022134890W WO2023116357A1 WO 2023116357 A1 WO2023116357 A1 WO 2023116357A1 CN 2022134890 W CN2022134890 W CN 2022134890W WO 2023116357 A1 WO2023116357 A1 WO 2023116357A1
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region
conductivity type
doped region
doped
doping concentration
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French (fr)
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李永顺
金华俊
宋亮
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/114—PN junction isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/151—LDMOS having built-in components
    • H10D84/153—LDMOS having built-in components the built-in component being PN junction diodes
    • H10D84/154—LDMOS having built-in components the built-in component being PN junction diodes in antiparallel diode configurations

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device with an isolation structure and a manufacturing method thereof.
  • isolation can be performed through the PN junction reverse biased well isolation structure, for example, through the DN-BN-DN (deep N well-N buried layer-deep N well) ring to perform device-to-device isolation. isolation.
  • DN-BN-DN deep N well-N buried layer-deep N well
  • the potential on the BN ring drops rapidly, even lower than the potential of the P-type substrate (Psub), the PN junction formed by Psub and BN is forward-biased, and the holes in the Psub Carriers will be injected into BN, and electrons in BN will be injected into Psub, thus forming a large Psub leakage.
  • Psub P-type substrate
  • a semiconductor device with an isolation structure comprising: a substrate having a second conductivity type; a buried layer of a first conductivity type disposed in the substrate; a drift region having a first conductivity type disposed in the first On the buried layer of conductivity type; the drain region, having the first conductivity type, is disposed in the drift region; the body region, having the second conductivity type, is disposed on the buried layer of the first conductivity type; the source region has the The first conductivity type is arranged in the body region; the first doped region has the second conductivity type and is arranged on the side of the drift region opposite to the body region, and the first conductivity type is buried On the layer; the second doped region, having the first conductivity type, is arranged on the side of the first doped region opposite to the drift region, on the buried layer of the first conductivity type; the third doped a region of the second conductivity type, disposed on the side of the second doped region opposite to the first doped region and on the buried layer of the first conduct
  • a method for manufacturing a semiconductor device with an isolation structure comprising: obtaining a wafer; the wafer includes: a substrate, a first conductivity type buried layer in the substrate, and a first conductivity type buried layer on the first conductivity type buried layer a drift region, a body region on the buried layer of the first conductivity type, a drain region in the drift region and a source region in the body region; the substrate and the body region have a second conductivity type, so The drift region, the drain region and the source region have a first conductivity type, the first conductivity type and the second conductivity type are opposite conductivity types; the drift region is formed on the buried layer of the first conductivity type A first doped region, a second doped region, a third doped region and a fourth doped region arranged in sequence in a direction away from the body region, the first doped region and the third doped region have the first doped region Two conductivity types, the second doped region and the fourth doped region have the first conductivity type, the doping concentration of
  • the doping concentration of the second doping region is greater than the doping concentration of the fourth doping region; forming a second voltage port electrically connected to the third doping region and the fourth doping region, and connecting to the first doping region A doped region and a first voltage port electrically connected to the second doped region, the external voltage of the second voltage port is higher than the external voltage of the first voltage port.
  • Fig. 1 is a schematic diagram of a semiconductor device in an embodiment
  • Fig. 2 is the flowchart of the manufacturing method of semiconductor device in an embodiment
  • FIG. 3 is a schematic diagram of forming a buried layer of the first conductivity type by a method for manufacturing a semiconductor device in an embodiment
  • Fig. 4 is a schematic diagram of drift region implantation performed by a manufacturing method of a semiconductor device in an embodiment
  • FIG. 5 is a schematic diagram of forming a body region in a method for manufacturing a semiconductor device in an embodiment
  • FIG. 6 is a schematic diagram of forming a first doped region and a third doped region by a manufacturing method of a semiconductor device in an embodiment
  • FIG. 7 is a schematic diagram of forming a second doped region and a fourth doped region by a method for manufacturing a semiconductor device in an embodiment
  • FIG. 8 is a schematic diagram of a semiconductor device in another embodiment
  • FIG. 9 is a schematic diagram of a semiconductor device in another embodiment.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • P+ type simply represents P-type with heavy doping concentration
  • P-type represents medium P-type with doping concentration
  • P-type represents P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents light-doped concentration Type N.
  • FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment.
  • the semiconductor device 100 includes a substrate 110, a first conductivity type buried layer 120, a source region 130, a drain region 140, a body region 132, a drift region 142, a first doped region 162, a second doped region The impurity region 164 , the third doped region 166 and the fourth doped region 168 .
  • the substrate 110 has a second conductivity type.
  • the buried layer 120 of the first conductivity type is disposed on the substrate 110 .
  • the drift region 142 has the first conductivity type and is disposed on the buried layer 120 of the first conductivity type.
  • the drain region 140 has the first conductivity type and is disposed in the drift region 142 .
  • the body region 132 has the second conductivity type and is disposed on the buried layer 120 of the first conductivity type.
  • the source region 130 has a first conductivity type and is disposed in the body region 132 .
  • the first doped region 162 has the second conductivity type, is disposed on the side of the drift region 142 opposite to the body region 132 , and is located on the buried layer 120 of the first conductivity type.
  • the second doped region 164 has the first conductivity type, is disposed on a side of the first doped region 162 opposite to the drift region 142 , and is located on the buried layer 120 of the first conductivity type.
  • the third doped region 166 has the second conductivity type, is disposed on the side of the second doped region 164 opposite to the first doped region 162 , and is located on the buried layer 120 of the first conductivity type.
  • the fourth doped region 168 has the first conductivity type, is disposed on a side of the third doped region 166 opposite to the second doped region 164 , and is located on the buried layer 120 of the first conductivity type.
  • the buried layer 120 of the first conductivity type can completely cover the bottom of the fourth doped region 168 as shown in FIG. The right border of miscellaneous region 168 is flush.
  • the buried layer 120 of the first conductivity type, the first doped region 162 , the second doped region 164 , the third doped region 166 and the fourth doped region 168 serve as isolation structures.
  • the voltage of the potential connected to the third doped region 166 and the fourth doped region 168 is higher than the voltage of the potential connected to the first doped region 162 and the second doped region 164 . Since the third doped region 166 and the fourth doped region 168 are connected to a high potential, the first doped region 162 and the second doped region 164 are connected to a low potential, so that the body diode formed by the body region 132 and the drift region 142 continues When current flows, the triode composed of the second doped region 164-the third doped region 166-the fourth doped region 168 works in the amplification region, which can absorb the current rushing into the buried layer 120 of the first conductivity type and prevent it from flowing into The substrate 110, thereby significantly shielding the substrate leakage caused by body diode freewheeling.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the BJT composed of the second doped region 164-the third doped region 166-the fourth doped region 168 It is an NPN transistor.
  • the third doped region 166 and the fourth doped region 168 are electrically connected to the second voltage port 200
  • the first doped region 162 and the second doped region 164 are electrically connected to each other.
  • the first voltage port 300 The external voltage of the second voltage port 200 is higher than the external voltage of the second voltage port 200 .
  • the drift region 142 and the body region 132 may be arranged at intervals, or may be arranged adjacently as shown in FIG. 1 (that is, the drift region 142 and the body region 132 are in direct contact).
  • the spacing between the drift region 142 and the body region 132 can increase the breakdown voltage (BV) of the entire device, and when the drift region 142 and the body region 132 are adjacent to each other, the breakdown voltage of the entire device is lower than that of the spacing, but The device size can be reduced.
  • the drift region 142 and the first doped region 162 can be arranged adjacently as shown in FIG. 1 (that is, the drift region 142 is in direct contact with the first doped region 162 ), or can be arranged at intervals.
  • a doped region 122 of the second conductivity type is further provided between the drift region 142 , the body region 132 and the buried layer 120 of the first conductivity type.
  • the drift region 142 is N-drift
  • the second conductivity type doped region 122 below the N-drift is a P-type reduced surface electric field region (P-RESURF).
  • the doped region 122 of the second conductivity type and the buried layer 120 of the first conductivity type may be arranged adjacently as shown in FIG. set up.
  • the buried layer 120 of the first conductivity type is at least partially in contact with the fourth doped region 168, and the first doped region 162, the second doped region 164 and the third doped region
  • the bottoms of regions 166 are each spaced apart from 120 .
  • the second doped region 164, the second conductivity type doped region 122, the first conductivity type buried layer 120 and the substrate 110 will form an NPNP structure, which can Better shield the substrate leakage.
  • the doping concentration of the third doping region 166 is smaller than that of the first doping region 162 .
  • the third doped region 166 is used as the base region of the BJT structure for releasing parasitic leakage, appropriately reducing its doping concentration can increase the gain of the BJT and improve the leakage shielding capability.
  • the doping concentration of the third doped region 166 is too high, a parasitic leakage path composed of the third doped region 166 - the buried layer 120 of the first conductivity type - the substrate 110 will be introduced, which will instead increase the leakage of the substrate.
  • the first doped region 162 is a deep P-well
  • the third doped region 166 is a deep P-type ring.
  • the doping concentration of the second doping region 164 is greater than that of the fourth doping region 168 .
  • the second doped region 164 serves as the emitter of the BJT structure for releasing parasitic leakage, and increasing its doping concentration can increase the injection efficiency of the emitter, thereby improving the shielding ability of the substrate leakage.
  • the doping concentration of the buried layer 120 of the first conductivity type is greater than that of the second doped region 164, and the doping concentration of the buried layer 120 of the first conductivity type is greater than that of the fourth doped region. 168 doping concentration.
  • the semiconductor device further includes a gate 150 disposed over a region between the drain region 140 and the source region 130 .
  • the gate 150 is made of polysilicon.
  • the gate 150 may also use metal, metal nitride, metal silicide or similar compounds as the material of the gate 150 .
  • a gate dielectric layer may also be provided below the gate 150, and the gate dielectric layer may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). things.
  • the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100.
  • Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanates (BSTs), and lead zirconate titanates (PZTs).
  • the semiconductor device further includes a first contact region 161 , a second contact region 163 , a third contact region 165 and a fourth contact region 167 .
  • the first contact region 161 has the second conductivity type and is disposed on the surface of the first doped region 162 .
  • the doping concentration of the first contact region 161 is greater than that of the first doped region 162 .
  • the second contact region 163 has the first conductivity type and is disposed on the surface of the second doped region 164 .
  • the doping concentration of the second contact region 163 is greater than the doping concentration of the second doped region 164 .
  • the third contact region 165 has the second conductivity type and is disposed on the surface of the third doped region 166 .
  • the doping concentration of the third contact region 165 is greater than the doping concentration of the third doped region 166 .
  • the fourth contact region 167 has the first conductivity type and is disposed on the surface of the fourth doped region 168 .
  • the doping concentration of the fourth contact region 167 is greater than that of the fourth doped region 168 .
  • the first contact region 161 and the second contact region 163 form an ohmic contact with the cathode
  • the third contact region 165 and the fourth contact region 167 form an ohmic contact with the anode.
  • the first doped region 162, the second doped region 164, the third doped region 166 and the fourth doped region 168 cannot be connected to the same potential, because if connected to the same potential, the body region 132 and the drift region 142 composed of body diode freewheeling conditions, a large amount of electron current pouring into the buried layer 120 of the first conductivity type will cause the potential of the buried layer 120 of the first conductivity type to be lower than the third doped region 166, so that the third doped region 166—the buried layer of the first conductivity type 120—the parasitic transistor (PNP transistor) formed by the substrate 110 is turned on, the leakage current of the substrate increases, and the isolation structure fails.
  • PNP transistor parasitic transistor
  • the semiconductor device further includes a shallow trench isolation (STI) structure 170 .
  • the shallow trench isolation structure 170 is disposed between the top of the drift region 142 and the top of the first doped region 162, between the top of the first doped region 162 and the top of the second doped region 164, and the second doped region 164 and the top of the third doped region 166 , and between the top of the third doped region 166 and the top of the fourth doped region 168 .
  • STI shallow trench isolation
  • the semiconductor device further includes a local oxidation of silicon isolation (LOCOS) 180, and the local oxidation of silicon isolation 180 is disposed between the top of the drift region 142 and the top of the first doped region 162, the second Between the top of the first doped region 162 and the top of the second doped region 164, between the top of the second doped region 164 and the top of the third doped region 166, between the top of the third doped region 166 and the fourth between the tops of doped regions 168 .
  • LOC local oxidation of silicon isolation
  • the semiconductor device further includes a fifth contact region 169 disposed on top of the substrate 110 .
  • the fifth contact region 169 has the second conductivity type, and its doping concentration is greater than that of the substrate 110 .
  • the fifth contact region 169 and the fourth contact region 167 are also isolated by the shallow trench isolation structure 170 .
  • the doping concentration of the drain region 140 is greater than that of the drift region 142 .
  • the doping concentration of the source region 130 is greater than that of the body region 132 .
  • the above-mentioned semiconductor device can be applied to a lateral device, such as an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device.
  • LDMOS Laterally Diffused Metal Oxide Semiconductor
  • the drain region 140, the source region 130, the gate 150, the body region 132, and the drift region 142 are corresponding structures of LDMOS.
  • Fig. 2 is the flowchart of the manufacturing method of semiconductor device in an embodiment, and this method comprises the following steps:
  • a buried layer of the first conductivity type needs to be formed in the substrate of the wafer.
  • a buried layer 320 of the first conductivity type may be formed by doping in a substrate 310 of the second conductivity type, and then on the substrate 310 and the buried layer 320 of the first conductivity type An epitaxial layer 322 of the second conductivity type is epitaxially grown, and subsequent device structures and isolation structures are formed in the epitaxial layer 322 .
  • the buried layer of the first conductivity type may also be directly formed in the middle of the substrate by high-energy ion implantation, and subsequent device structures and isolation structures are formed in the substrate above the buried layer of the first conductivity type.
  • the first conductivity type is N type
  • the second conductivity type is P type.
  • a drift region and a body region can be formed by doping.
  • a doped region 341 of the first conductivity type is formed in the epitaxial layer 322 on the buried layer 320 of the first conductivity type by ion implantation. Then implant the second conductivity type ions into the first conductivity type doped region 341, so that the dopant ions in a part of the first conductivity type doped region 341 are neutralized to form the body region 332, and the first conductivity type doped region The region 341 that is not neutralized serves as the drift region 342 .
  • the drift region 342 is an N-drift
  • the body region 332 is a P-body
  • the ion implantation of the P-body adopts high-energy and high-dose P-type impurity implantation.
  • This drift region/body region formation method can use the P-RESURF injection at the bottom of the N-drift to increase the concentration of the P-body, thereby enhancing the ability of the P-body to recombine the electronic current generated during the freewheeling of the body diode.
  • the source region 330 can also be formed in the body region 332
  • the drain region 340 can be formed in the drift region 342
  • the drain region 340 and the A gate 350 is formed over the region between the source regions 330 .
  • the first doped region 362 and the third doped region 366 can be formed by ion implantation of ions of the second conductivity type, and then ion implantation of ions of the first conductivity type A second doped region 364 and a fourth doped region 368 are formed.
  • the first doped region 362 , the second doped region 364 , the third doped region 366 and the fourth doped region 368 are sequentially arranged in a direction in which the drift region 342 is away from the body region 332 .
  • the doping concentration of the third doping region 366 is smaller than that of the first doping region 362 .
  • the doping concentration of the second doping region 364 is greater than that of the fourth doping region 368 .
  • the buried layer 320 of the first conductivity type can completely cover the bottom of the fourth doped region 368 as shown in FIG. The right border of miscellaneous region 368 is flush.
  • the implantation depths of the first doped region 362, the second doped region 364 and the third doped region 366 may not reach the buried layer 320 of the first conductivity type, that is, the first doped region 362, the second doped region 364 and the An epitaxial layer 322 may be spaced between the third doped region 366 and the buried layer 320 of the first conductivity type.
  • the second voltage port 200 is electrically connected to the third doped region 366 and the fourth doped region 368
  • the first voltage port 300 is electrically connected to the first doped region 362 and the second doped region 364 .
  • the voltage connected to the second voltage port 200 is higher than the voltage connected to the first voltage port 300 .
  • the second voltage port 200 is an anode
  • the first voltage port 300 is a cathode.
  • the second voltage port 200 is connected to a high potential
  • the first voltage port 300 is connected to a low potential.
  • step S230 a step of forming a first contact region, a second contact region, a third contact region and a fourth contact region by ion implantation is also included.
  • the first contact region has a second conductivity type and is provided on the surface of the first doped region, and the doping concentration of the first contact region is greater than that of the first doped region;
  • the first contact region The second contact region has the first conductivity type and is arranged on the surface of the second doped region, the doping concentration of the second contact region is greater than the doping concentration of the second doped region;
  • the third contact region It has the second conductivity type and is provided on the surface of the third doped region, the doping concentration of the third contact region is greater than the doping concentration of the third doped region;
  • the fourth contact region has the first conductivity type, set on the surface of the fourth doped region, the doping concentration of the fourth contact region is greater than the doping concentration of the fourth doped region;
  • the second voltage port and the third contact region and the fourth contact region form an ohmic contact, and the first voltage port forms an ohmic contact with the first contact region and the second contact region.
  • a step of forming the shallow trench isolation structure 170 is further included.
  • the shallow trench isolation structure 170 may be formed between the top of the drift region 342 and the top of the first doped region 362, between the top of the first doped region 362 and the top of the second doped region 364, the second doped region Between the top of region 364 and the top of third doped region 366 , and between the top of third doped region 366 and the top of fourth doped region 368 .
  • a step of forming a local silicon oxide isolation 180 is also included, and the local silicon oxide isolation 180 is provided on the top of the drift region 342 and the first doped Between the tops of the regions 362, between the tops of the first doped regions 362 and the tops of the second doped regions 364, between the tops of the second doped regions 364 and the tops of the third doped regions 366, between the tops of the third doped regions 364, between the top of the doped region 366 and the top of the fourth doped region 368 .

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体器件（100）包括：衬底（110）；第一导电类型埋层（120），设于衬底（110）中；漂移区（142），设于埋层（120）上；漏极区（130），设于漂移区（142）内；体区（132），设于埋层（120）上；源极区（130），设于体区（132）内；设于埋层（120）上并且在漂移区（142）背离体区（132）的方向上依次排列的第一至第四掺杂区（162、164、166、168）；其中，所述第三掺杂区（166）的掺杂浓度小于所述第一掺杂区（162）的掺杂浓度，所述第二掺杂区（164）的掺杂浓度大于所述第四掺杂区（168）的掺杂浓度。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求2021年12月24日申请的，申请号为2021115997056，名称为“具有隔离结构的半导体器件及其制造方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本发明涉及半导体制造领域，特别是涉及一种具有隔离结构的半导体器件及其制造方法。
背景技术
在现有的LDMOS中，可以通过PN结反偏的阱区隔离结构来进行隔离，例如通过DN-BN-DN(深N阱-N型埋层-深N阱)环来进行器件之间的隔离。但是当LDMOS应用于死区时间的条件下，由于LDMOS的体二极管续流，体二极管的N型漂移区(N-Drift)和P型体区(P-Body)形成的PN结会产生负压降，电子电流大量涌入P-Body，且N型漂移区/P型体区/N型埋层组成的NPN三极管开启且工作在放大区，部分电子电流在BN和P-Body形成的反偏电场的作用下流入BN。由于DN-BN-DN环高阻区的存在，使得BN环上的电位快速下降，甚至低于P型衬底(Psub)的电位，Psub和BN形成的PN结正偏，Psub内的空穴载流子就会注入BN，BN内的电子会注入Psub，从而形成较大的Psub漏电。
发明内容
基于此，有必要提供一种半导体器件。
一种具有隔离结构的半导体器件，包括：衬底，具有第二导电类型；第 一导电类型埋层，设于所述衬底中；漂移区，具有第一导电类型，设于所述第一导电类型埋层上；漏极区，具有第一导电类型，设于所述漂移区内；体区，具有第二导电类型，设于所述第一导电类型埋层上；源极区，具有第一导电类型，设于所述体区内；第一掺杂区，具有第二导电类型，设于所述漂移区的与所述体区相背的一侧、所述第一导电类型埋层上；第二掺杂区，具有第一导电类型，设于所述第一掺杂区的与所述漂移区相背的一侧、所述第一导电类型埋层上；第三掺杂区，具有第二导电类型，设于所述第二掺杂区的与所述第一掺杂区相背的一侧、所述第一导电类型埋层上；第四掺杂区，具有第一导电类型，设于所述第三掺杂区的与所述第二掺杂区相背的一侧、所述第一导电类型埋层上；其中，所述第一导电类型和第二导电类型为相反的导电类型，所述第一掺杂区和所述第二掺杂区连接第一电压端口，所述第三掺杂区和所述第四掺杂区连接至第二电压端口，所述第二电压端口的外接电压高于所述第一电压端口的外接电压。
还有必要提供一种具有隔离结构的半导体器件的制造方法。
一种具有隔离结构的半导体器件的制造方法，包括：获取晶圆；所述晶圆包括：衬底，所述衬底中的第一导电类型埋层，所述第一导电类型埋层上的漂移区，所述第一导电类型埋层上的体区，所述漂移区内的漏极区及所述体区内的源极区；所述衬底和体区具有第二导电类型，所述漂移区、漏极区及源极区具有第一导电类型，所述第一导电类型和第二导电类型为相反的导电类型；在所述第一导电类型埋层上形成在所述漂移区背离所述体区的方向上依次排列的第一掺杂区、第二掺杂区、第三掺杂区及第四掺杂区，所述第一掺杂区和第三掺杂区具有第二导电类型，所述第二掺杂区和第四掺杂区具有第一导电类型，所述第三掺杂区的掺杂浓度小于所述第一掺杂区的掺杂浓度，所述第二掺杂区的掺杂浓度大于所述第四掺杂区的掺杂浓度；形成与所述第三掺杂区和第四掺杂区电性连接的第二电压端口，和与所述第一掺杂区和第二掺杂区电性连接的第一电压端口，所述第二电压端口的外接电压高于所述第一电压端口的外接电压。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中半导体器件的示意图；
图2是一实施例中半导体器件的制造方法的流程图；
图3是一实施例中半导体器件的制造方法形成第一导电类型埋层的示意图；
图4是一实施例中半导体器件的制造方法进行漂移区注入的示意图；
图5是一实施例中半导体器件的制造方法形成体区的示意图；
图6是一实施例中半导体器件的制造方法形成第一掺杂区和第三掺杂区的示意图；
图7是一实施例中半导体器件的制造方法形成第二掺杂区和第四掺杂区的示意图；
图8是另一实施例中半导体器件的示意图；
图9是另一实施例中半导体器件的示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技 术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的 存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是根据一实施例的半导体器件的结构示意图。在该实施例中，半导体器件100包括衬底110、第一导电类型埋层120、源极区130、漏极区140、体区132、漂移区142、第一掺杂区162、第二掺杂区164、第三掺杂区166及第四掺杂区168。衬底110具有第二导电类型。第一导电类型埋层120设于衬底110上。漂移区142具有第一导电类型，设于第一导电类型埋层120上。漏极区140具有第一导电类型，设于漂移区142内。体区132具有第二导电类型，设于第一导电类型埋层120上。源极区130具有第一导电类型，设于体区132内。
第一掺杂区162具有第二导电类型，设于漂移区142的与体区132相背的一侧，且位于第一导电类型埋层120上。第二掺杂区164具有第一导电类型，设于第一掺杂区162的与漂移区142相背的一侧，且位于第一导电类型埋层120上。第三掺杂区166具有第二导电类型，设于第二掺杂区164的与 第一掺杂区162相背的一侧，且位于第一导电类型埋层120上。第四掺杂区168具有第一导电类型，设于第三掺杂区166的与第二掺杂区164相背的一侧，且位于第一导电类型埋层120上。第一导电类型埋层120可以如图1所示完整覆盖第四掺杂区168的底部，也可以是部分覆盖，即在图1中第一导电类型埋层120的右边界不与第四掺杂区168的右边界平齐。第一导电类型埋层120、第一掺杂区162、第二掺杂区164、第三掺杂区166及第四掺杂区168作为隔离结构。
在上述半导体器件工作时，第三掺杂区166和第四掺杂区168连接的电位的电压高于第一掺杂区162和第二掺杂区164连接的电位的电压。由于第三掺杂区166和第四掺杂区168接高电位，第一掺杂区162和第二掺杂区164接低电位，这样在由体区132和漂移区142组成的体二极管续流时，由第二掺杂区164-第三掺杂区166-第四掺杂区168组成的三极管工作在放大区，可以将涌入第一导电类型埋层120的电流吸收，避免其流入衬底110，从而显著地屏蔽了由于体二极管续流导致的衬底漏电。在本申请的一个实施例中，第一导电类型为N型，第二导电类型为P型，因此由第二掺杂区164-第三掺杂区166-第四掺杂区168组成的BJT为NPN三极管。在图1所示的实施例中，第三掺杂区166和第四掺杂区168均电性连接第二电压端口200，第一掺杂区162和第二掺杂区164均电性连接第一电压端口300。第二电压端口200的外接电压高于第二电压端口200的外接电压。
漂移区142和体区132可以间隔设置，也可以如图1所示相邻设置(即漂移区142和体区132直接接触)。漂移区142和体区132间隔设置可以提高整个器件的击穿电压(BV)，而漂移区142和体区132相邻设置时整个器件的击穿电压与间隔设置相比虽然有所降低，但可以减小器件尺寸。
漂移区142与第一掺杂区162可以如图1所示相邻设置(即漂移区142与第一掺杂区162直接接触)，也可以间隔设置。在图1所示的实施例中，漂移区142和体区132与第一导电类型埋层120之间还设有第二导电类型掺杂区122。在本申请的一个实施例中，漂移区142为N-drift，N-drift下方的第 二导电类型掺杂区122为P型降低表面电场区域(P-RESURF)。第二导电类型掺杂区122与第一导电类型埋层120可以如图1所示相邻设置(即第二导电类型掺杂区122与第一导电类型埋层120直接接触)，也可以间隔设置。
参见图8，在本申请的另一个实施例中，第一导电类型埋层120与第四掺杂区168至少部分接触，第一掺杂区162、第二掺杂区164及第三掺杂区166的底部均与120间隔设置。图8所示的实施例相比图1所示的实施例，第二掺杂区164、第二导电类型掺杂区122、第一导电类型埋层120及衬底110会组成NPNP结构，可以较好地屏蔽衬底漏电。
在本申请的一个实施例中，第三掺杂区166的掺杂浓度小于第一掺杂区162的掺杂浓度。第三掺杂区166作为泄放寄生漏电的BJT结构的基区，适当降低其掺杂浓度可以增大BJT的增益，提高漏电屏蔽能力。此外，如果第三掺杂区166掺杂浓度太高，会引入第三掺杂区166-第一导电类型埋层120-衬底110组成的寄生漏电路径，反而会增大衬底漏电。在本申请的一个实施例中，第一掺杂区162为深P阱，第三掺杂区166为深P型环。
在本申请的一个实施例中，第二掺杂区164的掺杂浓度大于第四掺杂区168的掺杂浓度。第二掺杂区164作为泄放寄生漏电的BJT结构的发射极，提高其掺杂浓度可以增加发射极注入效率，从而提高对衬底漏电的屏蔽能力。
可选地，使第一导电类型埋层120的掺杂浓度尽可能地高，以保证当体二极管续流时电流涌入第一导电类型埋层120中时，第一导电类型埋层120不会产生太大的压降。在本申请的一个实施例中，第一导电类型埋层120的掺杂浓度大于第二掺杂区164的掺杂浓度，且第一导电类型埋层120的掺杂浓度大于第四掺杂区168的掺杂浓度。
在图1所示的实施例中，半导体器件还包括设于漏极区140和源极区130之间的区域上方的栅极150。在本申请的一个实施例中，栅极150为多晶硅材料。在其他实施例中，栅极150也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极150的材料。栅极150下方还可以设置栅极介电层，栅极介电层可以包括传统的电介质材料诸如具有电介质常数从大约4到大约 20(真空中测量)的硅的氧化物、氮化物和氮氧化物。或者，栅极介电层可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电介质材料可以包括但不限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。
在本申请的一个实施例中，半导体器件还包括第一接触区161、第二接触区163、第三接触区165及第四接触区167。第一接触区161具有第二导电类型，设于第一掺杂区162的表面，第一接触区161的掺杂浓度大于第一掺杂区162的掺杂浓度。第二接触区163具有第一导电类型，设于第二掺杂区164的表面，第二接触区163的掺杂浓度大于第二掺杂区164的掺杂浓度。第三接触区165具有第二导电类型，设于第三掺杂区166的表面，第三接触区165的掺杂浓度大于第三掺杂区166的掺杂浓度。第四接触区167具有第一导电类型，设于第四掺杂区168的表面，第四接触区167的掺杂浓度大于第四掺杂区168的掺杂浓度。在图1所示的实施例中，第一接触区161和第二接触区163与阴极形成欧姆接触，第三接触区165和第四接触区167与阳极形成欧姆接触。需注意的是，第一掺杂区162、第二掺杂区164、第三掺杂区166及第四掺杂区168不能接同电位，因为接同电位的话，在体区132和漂移区142组成的体二极管续流的条件下，涌入第一导电类型埋层120的大量电子电流会导致第一导电类型埋层120的电位低于第三掺杂区166，使得第三掺杂区166-第一导电类型埋层120-衬底110组成的寄生三极管(PNP三极管)开启，衬底漏电流增大，隔离结构失效。
在图1所示的实施例中，半导体器件还包括浅沟槽隔离(STI)结构170。浅沟槽隔离结构170设于漂移区142的顶部和第一掺杂区162的顶部之间、第一掺杂区162的顶部和第二掺杂区164的顶部之间、第二掺杂区164的顶部和第三掺杂区166的顶部之间、第三掺杂区166的顶部和第四掺杂区168的顶部之间。
请参阅图9，在另一个实施例中，半导体器件还包括局部硅氧化隔离(LOCOS)180，局部硅氧化隔离180设于漂移区142的顶部和第一掺杂区 162的顶部之间、第一掺杂区162的顶部和第二掺杂区164的顶部之间、第二掺杂区164的顶部和第三掺杂区166的顶部之间、第三掺杂区166的顶部和第四掺杂区168的顶部之间。
在图1所示的实施例中，半导体器件还包括设于衬底110顶部的第五接触区169。第五接触区169具有第二导电类型，且掺杂浓度大于衬底110的掺杂浓度。在图1所示的实施例中，第五接触区169和第四接触区167之间也通过浅沟槽隔离结构170进行隔离。
在本申请的一个实施例中，漏极区140的掺杂浓度大于漂移区142的掺杂浓度。源极区130的掺杂浓度大于体区132的掺杂浓度。
上述半导体器件可应用于横向器件，例如LDMOS(横向扩散金属氧化物半导体)器件中。漏极区140、源极区130、栅极150、体区132、漂移区142为LDMOS的相应结构。
根据一个实施例，还提供一种半导体器件的制造方法，可以用于制造前述任一实施例的半导体器件。图2是一实施例中半导体器件的制造方法的流程图，该方法包括下列步骤：
S210，获取晶圆。
需要在晶圆的衬底中形成第一导电类型埋层。参照图3，在本申请的一个实施例中，可以在第二导电类型的衬底310中通过掺杂形成第一导电类型埋层320，然后在衬底310和第一导电类型埋层320上外延生长第二导电类型的外延层322，后续的器件结构和隔离结构形成在外延层322中。在另一个实施例中，也可以通过高能离子注入直接在衬底的中部形成第一导电类型埋层，后续的器件结构和隔离结构形成在第一导电类型埋层上方的衬底中。在本申请的一个实施例中，第一导电类型为N型，第二导电类型为P型。
形成第一导电类型埋层后可以通过掺杂形成漂移区和体区。参照图4和图5，在本申请的一个实施例中，通过离子注入在第一导电类型埋层320上的外延层322中形成第一导电类型掺杂区341。然后向第一导电类型掺杂区341中注入第二导电类型离子，使第一导电类型掺杂区341的部分区域的掺 杂离子被中和后形成体区332，第一导电类型掺杂区341未被中和的区域作为漂移区342。在本申请的一个实施例中，漂移区342为N-drift，体区332为P-body，P-body的离子注入采用高能量高剂量的P型杂质注入。这种漂移区/体区的形成方式，能够利用N-drift底部的P-RESURF注入，提高P-body的浓度，从而增强P-body对体二极管续流时产生的电子电流的复合能力。
在本申请的一个实施例中，形成漂移区342和体区332后，还可以在体区332中形成源极区330，在漂移区342中形成漏极区340，以及在漏极区340和源极区330之间的区域上方形成栅极350。
S220，在晶圆中形成第一掺杂区、第二掺杂区、第三掺杂区及第四掺杂区。
参见图6和图7，在本申请的一个实施例中，可以先通过离子注入第二导电类型离子形成第一掺杂区362和第三掺杂区366，再通过离子注入第一导电类型离子形成第二掺杂区364和第四掺杂区368。第一掺杂区362、第二掺杂区364、第三掺杂区366及第四掺杂区368在漂移区342背离体区332的方向上依次排列。在本申请的一个实施例中，第三掺杂区366的掺杂浓度小于第一掺杂区362的掺杂浓度。在本申请的一个实施例中，第二掺杂区364的掺杂浓度大于第四掺杂区368的掺杂浓度。第一导电类型埋层320可以如图7所示完整覆盖第四掺杂区368的底部，也可以是部分覆盖，即在图7中第一导电类型埋层320的右边界不与第四掺杂区368的右边界平齐。第一掺杂区362、第二掺杂区364及第三掺杂区366的注入深度也可以不到达第一导电类型埋层320，即第一掺杂区362、第二掺杂区364及第三掺杂区366与第一导电类型埋层320之间可以间隔有外延层322。
S230，形成与第三、第四掺杂区，以及与第一、第二掺杂区电性连接第一、第二电压端口。
第二电压端口200与第三掺杂区366和第四掺杂区368电性连接，第一电压端口300与第一掺杂区362和第二掺杂区364电性连接。半导体器件工作时，第二电压端口200接入的电压高于第一电压端口300接入的电压。在 本申请的一个实施例中，第二电压端口200为阳极，第一电压端口300为阴极。第二电压端口200接高电位，第一电压端口300接低电位。
在本申请的一个实施例中，步骤S230之前还包括通过离子注入形成第一接触区、第二接触区、第三接触区及第四接触区的步骤。
所述第一接触区具有第二导电类型，设于所述第一掺杂区的表面，所述第一接触区的掺杂浓度大于所述第一掺杂区的掺杂浓度；所述第二接触区具有第一导电类型，设于所述第二掺杂区的表面，所述第二接触区的掺杂浓度大于所述第二掺杂区的掺杂浓度；所述第三接触区具有第二导电类型，设于所述第三掺杂区的表面，所述第三接触区的掺杂浓度大于所述第三掺杂区的掺杂浓度；所述第四接触区具有第一导电类型，设于所述第四掺杂区的表面，所述第四接触区的掺杂浓度大于所述第四掺杂区的掺杂浓度；所述第二电压端口与所述第三接触区及第四接触区形成欧姆接触，所述第一电压端口与所述第一接触区及第二接触区形成欧姆接触。
在本申请的一个实施例中，在步骤S210形成第一导电类型埋层320之后，还包括形成浅沟槽隔离结构170的步骤。浅沟槽隔离结构170可以形成于漂移区342的顶部和第一掺杂区362的顶部之间、第一掺杂区362的顶部和第二掺杂区364的顶部之间、第二掺杂区364的顶部和第三掺杂区366的顶部之间、以及第三掺杂区366的顶部和第四掺杂区368的顶部之间。在本申请的其他实施例中，在步骤S210形成第一导电类型埋层320之后，还包括形成局部硅氧化隔离180的步骤，局部硅氧化隔离180设于漂移区342的顶部和第一掺杂区362的顶部之间、第一掺杂区362的顶部和第二掺杂区364的顶部之间、第二掺杂区364的顶部和第三掺杂区366的顶部之间、第三掺杂区366的顶部和第四掺杂区368的顶部之间。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，本申请的流程图中的至少一部分步骤可以包括多个步 骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体器件，包括：
    衬底，具有第二导电类型；
    第一导电类型埋层，设于所述衬底中；
    漂移区，具有第一导电类型，设于所述第一导电类型埋层上；
    漏极区，具有所述第一导电类型，设于所述漂移区内；
    体区，具有所述第二导电类型，设于所述第一导电类型埋层上；
    源极区，具有所述第一导电类型，设于所述体区内；
    第一掺杂区，具有所述第二导电类型，设于所述第一导电类型埋层上且位于所述漂移区的与所述体区相背的一侧；
    第二掺杂区，具有所述第一导电类型，设于所述第一导电类型埋层上且位于所述第一掺杂区的与所述漂移区相背的一侧；
    第三掺杂区，具有所述第二导电类型，设于所述第一导电类型埋层上且位于所述第二掺杂区的与所述第一掺杂区相背的一侧；及
    第四掺杂区，具有所述第一导电类型，设于所述第一导电类型埋层上且位于所述第三掺杂区的与所述第二掺杂区相背的一侧；
    其中，所述第一导电类型和所述第二导电类型为相反的导电类型，所述第一掺杂区和所述第二掺杂区连接第一电压端口，所述第三掺杂区和所述第四掺杂区连接至第二电压端口，所述第二电压端口的外接电压高于所述第一电压端口的外接电压。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述第三掺杂区的掺杂浓度小于所述第一掺杂区的掺杂浓度。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述第二掺杂区的掺杂 浓度大于所述第四掺杂区的掺杂浓度。
  4. 根据权利要求1所述的半导体器件，还包括设于所述漂移区和所述体区与所述第一导电类型埋层之间的第二导电类型掺杂区。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述漂移区为N-drift，所述第二导电类型掺杂区为P-RESURF。
  6. 根据权利要求1所述的半导体器件，还包括设于所述漏极区和所述源极区之间的区域的上方的栅极。
  7. 根据权利要求1所述的半导体器件，其特征在于，所述第一导电类型埋层的掺杂浓度大于所述第二掺杂区的掺杂浓度和所述第四掺杂区的掺杂浓度。
  8. 根据权利要求1所述的半导体器件，还包括：
    第一接触区，具有所述第二导电类型，设于所述第一掺杂区的表面，所述第一接触区的掺杂浓度大于所述第一掺杂区的掺杂浓度；
    第二接触区，具有所述第一导电类型，设于所述第二掺杂区的表面，所述第二接触区的掺杂浓度大于所述第二掺杂区的掺杂浓度；
    第三接触区，具有所述第二导电类型，设于所述第三掺杂区的表面，所述第三接触区的掺杂浓度大于所述第三掺杂区的掺杂浓度；及
    第四接触区，具有所述第一导电类型，设于所述第四掺杂区的表面，所述第四接触区的掺杂浓度大于所述第四掺杂区的掺杂浓度。
  9. 根据权利要求1所述的半导体器件，其特征在于，所述半导体器件为LDMOS器件。
  10. 根据权利要求1所述的半导体器件，还包括多个浅沟槽隔离结构，其中所述多个浅沟槽隔离结构分别设于所述漂移区的顶部和所述第一掺杂区的顶部之间、所述第一掺杂区的顶部和所述第二掺杂区的顶部之间、所述第二掺 杂区的顶部和所述第三掺杂区的顶部之间、所述第三掺杂区的顶部和所述第四掺杂区的顶部之间。
  11. 根据权利要求8所述的半导体器件，还包括设于所述衬底顶部的第五接触区，所述第五接触区具有所述第二导电类型，所述第五接触区的掺杂浓度大于所述衬底的掺杂浓度，所述第五接触区和所述第四接触区之间通过浅沟槽隔离结构进行隔离。
  12. 根据权利要求1所述的半导体器件，其特征在于，所述漏极区的掺杂浓度大于所述漂移区的掺杂浓度，所述源极区的掺杂浓度大于所述体区的掺杂浓度。
  13. 根据权利要求1所述的半导体器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第三掺杂区为P型环。
  14. 一种半导体器件的制造方法，包括：
    获取晶圆，所述晶圆包括：衬底，所述衬底中的第一导电类型埋层，所述第一导电类型埋层上的漂移区，所述第一导电类型埋层上的体区，所述漂移区内的漏极区及所述体区内的源极区；所述衬底和所述体区具有第二导电类型，所述漂移区、漏极区及源极区具有第一导电类型，所述第一导电类型和第二导电类型为相反的导电类型；
    在所述第一导电类型埋层上形成在所述漂移区背离所述体区的方向上依次排列的第一掺杂区、第二掺杂区、第三掺杂区及第四掺杂区，所述第一掺杂区和第三掺杂区具有第二导电类型，所述第二掺杂区和第四掺杂区具有第一导电类型，所述第三掺杂区的掺杂浓度小于所述第一掺杂区的掺杂浓度，所述第二掺杂区的掺杂浓度大于所述第四掺杂区的掺杂浓度；及
    形成与所述第三掺杂区和所述第四掺杂区电性连接的第二电压端口，形成与 所述第一掺杂区和所述第二掺杂区电性连接的第一电压端口，所述第二电压端口的外接电压高于所述第一电压端口的外接电压。
  15. 根据权利要求14所述的方法，其特征在于，所述获取晶圆包括：
    通过离子注入在所述第一导电类型埋层上形成第一导电类型掺杂区；
    向所述第一导电类型掺杂区中注入第二导电类型离子，使所述第一导电类型掺杂区的部分区域的掺杂离子被中和后形成体区，第一导电类型掺杂区未被中和的区域作为漂移区；及
    形成所述源极区、漏极区及位于所述漏极区和源极区之间的区域上方的栅极。
PCT/CN2022/134890 2021-12-24 2022-11-29 半导体器件及其制造方法 Ceased WO2023116357A1 (zh)

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