WO2023115803A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023115803A1
WO2023115803A1 PCT/CN2022/094114 CN2022094114W WO2023115803A1 WO 2023115803 A1 WO2023115803 A1 WO 2023115803A1 CN 2022094114 W CN2022094114 W CN 2022094114W WO 2023115803 A1 WO2023115803 A1 WO 2023115803A1
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Prior art keywords
layer
bit line
insulating layer
insulating
air interlayer
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French (fr)
Inventor
刘志拯
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/954,648 priority Critical patent/US12538476B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps

Definitions

  • Embodiments of the present disclosure relate to a semiconductor structure and a method for forming the same.
  • a semiconductor device such as a dynamic random access memory (Dynamic Random Access Memory, DRAM) includes a plurality of memory cells, a word line (Word Line, WL) and a bit line (Bit Line, BL).
  • each memory cell generally includes a transistor and a capacitor, the gate of the transistor is connected to WL, the drain or source region of the transistor is connected to BL, and the source or drain region of the transistor is connected to the capacitor. Applying a voltage signal on the WL can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the BL, or write the data information into the capacitor through the BL for storage.
  • the semiconductor device may further include a storage node contact (Node Contact, NC) and a bit line contact (Bit line Contact, BLC).
  • NC is used for electrically connecting the source/drain region and other parts in the semiconductor structure
  • BLC is used for electrically connecting the active region and BL.
  • embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising: providing a substrate; forming bit line contact holes arranged at intervals on the substrate; A bit line contact and a bit line structure, wherein the bit line structure includes at least a conductive layer and an insulating cap layer; the insulating cap layer is located on the conductive layer; The first insulating layer of the line contact hole; an insulating structure with an air interlayer is formed on both side walls of the bit line structure, wherein the height of the air interlayer is greater than that of the conductive layer in the bit line structure.
  • forming an insulating structure with an air interlayer on both side walls of the bit line structure includes: sequentially forming a second insulating layer, a sacrificial layer and a third insulating layer on both side walls of the bit line structure , exposing part of the surface of the sacrificial layer; etching the sacrificial layer along a first direction to form the air interlayer, wherein the first direction is a direction perpendicular to the substrate; forming a layer covering the third insulating layer, the air interlayer, and the fourth insulating layer of the second insulating layer to obtain an insulating structure with air interlayers on both side walls of the bit line structure, wherein the insulating structure includes the first stacked in sequence The second insulating layer, the air interlayer, the third insulating layer and the fourth insulating layer.
  • the etching the sacrificial layer along the first direction to form the air interlayer includes: etching the sacrificial layer along the first direction by using a dry etching process to form the air interlayer.
  • a second insulating layer, a sacrificial layer, and a third insulating layer are sequentially formed on both side walls of the bit line structure, exposing part of the surface of the sacrificial layer, including: forming an initial second insulating layer and an initial sacrificial layer on the surface in sequence; etching the initial sacrificial layer above the top of the bit line structure to form the sacrificial layer; forming the sacrificial layer on the surface of the initial second insulating layer and the sacrificial The initial third insulating layer is formed on the surface of the layer; the initial third insulating layer and the initial second insulating layer above the top of the bit line structure are etched to expose part of the surface of the sacrificial layer, forming an initial A second insulating layer, a sacrificial layer and a third insulating layer are sequentially formed on both side walls of the bit line structure.
  • the formation of the fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer includes: on the upper surface of the bit line structure, the second forming an initial fourth insulating layer on the surface of the insulating layer, the air interlayer and the third insulating layer; etching the initial fourth insulating layer above the top of the bit line structure to form a layer covering the third insulating layer , the fourth insulating layer of the air interlayer and the second insulating layer.
  • the method further includes: forming a storage node contact between adjacent fourth insulating layers.
  • the method further includes: forming a metal layer on the surface of the insulating structure, the surface of the storage node contact and the upper surface of the bit line structure; etching part of the metal layer to form a first opening, to expose part of the surface of the insulating structure located on the first sidewall of the bit line structure; wherein, the remaining metal layer after etching forms a landing pad electrically connected to the storage node contact, and the landing pad covers the The surface of the storage node contact, the surface of the insulating structure of the second sidewall of the bit line structure and the upper surface of the bit line structure.
  • the air interlayer near the first side wall is a first air interlayer with a first height
  • the air interlayer near the second side wall is a second air interlayer with a second height
  • the first height is less than the first height Describe the second height.
  • the method further includes: forming an isolation structure between adjacent landing pads and on the surface of the landing pads.
  • the isolation structure includes a first filling layer and a second filling layer
  • the formation of the isolation structure between adjacent landing pads and on the surface of the landing pads includes: Depositing a first filling layer on the insulating structure of the first side wall and the surface of the landing pad; depositing a second filling layer on the surface of the first filling layer.
  • the method before forming a storage node contact between adjacent fourth insulating layers, the method further includes: forming a fifth insulating layer on the surface of the initial fourth insulating layer; etching the fifth insulating layer, The initial fourth insulating layer and part of the substrate on the surface of the substrate are exposed to the substrate; correspondingly, the initial fourth insulating layer above the top of the bit line structure is etched to form a covering
  • the third insulating layer, the air interlayer, and the fourth insulating layer of the second insulating layer include: etching the initial fourth insulating layer and the fifth insulating layer above the upper surface of the bit line structure. an insulating layer, forming a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer.
  • the material of the first insulating layer includes nitride; the material of the second insulating layer, the third insulating layer and the fourth insulating layer includes oxide.
  • the material of the sacrificial layer includes silicon.
  • an embodiment of the present disclosure provides a semiconductor structure, the structure comprising: a substrate; bit line contact holes arranged at intervals on the substrate, bit line contacts partially in contact with the bit line contact holes, and A bit line structure, wherein the bit line structure at least includes a conductive layer and an insulating capping layer; the insulating capping layer is located on the conductive layer; A first insulating layer; an insulating structure with an air interlayer located on both side walls of the bit line structure, wherein the height of the air interlayer is greater than that of the conductive layer in the bit line structure.
  • the insulating structure includes a second insulating layer, an air interlayer, a third insulating layer, and a fourth insulating layer stacked in sequence, wherein the fourth insulating layer covers the third insulating layer, the air interlayer and the second insulating layer.
  • the air interlayer includes a first air interlayer having a first height and a second air interlayer having a second height, wherein the first air interlayer is adjacent to the first sidewall of the bit line structure , the second air interlayer is close to the second sidewall of the bit line structure, and the first height is smaller than the second height.
  • it further includes: a storage node contact located between adjacent fourth insulating layers; an upper surface covering the storage node contact, the insulating structure of the second sidewall and the bit line structure
  • the landing pad is electrically connected to the storage node contact.
  • it further includes: an isolation structure located between adjacent landing pads and on the surface of the landing pads.
  • the isolation structure includes a first filling layer and a second filling layer, the first filling layer is located on the insulating structure of the first sidewall of the bit line structure and the surface of the landing pad, the The second filling layer is located on the surface of the first filling layer.
  • FIG. 1a is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • 1b to 2c are process schematic diagrams of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3a is a schematic flowchart of another method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • 3b to 3d are process schematic diagrams of another method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • 4a to 4g are process schematic diagrams of another method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a method for forming a semiconductor structure, as shown in FIG. 1a, the method includes the following steps:
  • Step S101 providing a substrate.
  • the substrate may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display, or It may include multiple layers, such as a silicon on insulator (Silicon On Insulator, SOI) substrate, or a germanium on insulator (Germanium On Insulator, GOI) substrate, and the like.
  • Shallow Trench Isolation can also be formed in the substrate to isolate several active regions in the substrate.
  • the STI can be formed by filling the trench with an isolation material layer after forming a trench in the substrate.
  • Materials filled in the STI may include silicon nitride or silicon oxide, etc., and silicon oxide may be formed by thermal oxidation.
  • the STI can isolate several active regions distributed in an array or other distribution types on the substrate.
  • a buffer layer located on the shallow trench isolation and the active region may also be formed in the substrate, the buffer layer may include at least one insulating layer, and the material of the buffer layer may include silicon oxide, silicon nitride or Silicon oxynitride, etc.
  • Step S101 can refer to FIG. 1b.
  • the provided substrate 101 includes an active region 1012, a shallow trench isolation 1011 and a buffer layer 1013, wherein the shallow trench isolation 1011 and the active region 1012 are arranged at intervals, and the buffer layer 1013 is located in the shallow trench isolation 1011 and active region 1012 above.
  • Step S102 forming bit line contact holes arranged at intervals on the substrate, bit line contacts partially in contact with the bit line contact holes, and a bit line structure;
  • the material used for the bit line contact may include but not limited to conductive materials such as polysilicon, for example, polysilicon doped with impurities or polysilicon not doped with impurities.
  • the bit line structure at least includes a conductive layer and an insulating capping layer; the insulating capping layer is located on the conductive layer.
  • bit line contact holes 102 arranged at intervals, bit line contacts 103 partially in contact with the bit line contact holes 102, and a bit line structure 104 are formed on the substrate 101, wherein the bit line contact holes 102 penetrate part of the substrate.
  • the bit line contact 103 is located in the bit line contact hole 102
  • the bit line contact hole 102 has a space not occupied by the bit line contact 103 .
  • a part of the bit line structure 104 is located on the bit line contact 103 and connected to the active region 1012 through the bit line contact 103
  • another part of the bit line structure 104 is located on the substrate 101 .
  • the bit line structure 104 at least includes a conductive layer 1042 and an insulating capping layer 1041 on the conductive layer 1042 .
  • the material of the conductive layer can be polysilicon, metal silicide, conductive metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.) and metal (such as tungsten (W), titanium (Ti), tantalum (Ta), etc.).
  • the material of the insulating capping layer may be at least one of oxide, silicon nitride and silicon oxynitride, and the insulating capping layer may be formed by chemical vapor deposition process.
  • the bit line structure may further include a diffusion barrier layer located between the bit line contact and the conductive layer.
  • the diffusion barrier layer can insulate the conductive layer from the active area, and at the same time prevent metal ions in the conductive layer from entering the active area.
  • the diffusion barrier layer may include a single-layer structure, for example, a metal titanium layer; or may include a multi-layer structure, for example, a metal titanium layer and a titanium nitride layer.
  • Step S103 forming a first insulating layer filling the bit line contact hole in the bit line contact hole;
  • a first insulating layer 105 filling the bit line contact hole 102 is formed in the bit line contact hole 102 (as shown in FIG. 1d ). Wherein, the surface of the first insulating layer 105 is flush with the surface of the bit line contact hole 102 .
  • the first insulating layer can be used to reduce damage of the BLC in subsequent processes.
  • the material used for the first insulating layer may be nitride, and the nitride may include but not limited to silicon nitride, silicon oxynitride, and the like.
  • the first insulating layer in order to facilitate the control of the thickness of the first insulating layer, may be formed by an atomic layer deposition process. In some other embodiments, other processes may also be used to form the first insulating layer, such as physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer deposition process, plasma enhanced vapor phase deposition process, etc.
  • step S103 may first deposit and form an initial first insulating layer on the upper surface of the substrate and the surface of the bit line contact hole, and then remove the initial first insulating layer above the upper surface of the substrate by etching, A first insulating layer is formed to fill the bit line contact hole.
  • Step S104 forming an insulating structure with an air interlayer on both side walls of the bit line structure, wherein the height of the air interlayer is greater than that of the conductive layer in the bit line structure.
  • the form of the insulating structure can be an air interlayer between two insulating layers on both sides. aluminum etc.
  • the materials of the two insulating layers may be the same or different.
  • the insulating layer in the insulating structure may be formed by an atomic layer deposition process.
  • other processes can also be used to form the insulating layer in the insulating structure, such as physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer deposition process, plasma enhanced vapor phase deposition process wait.
  • step S104 may be implemented by sequentially depositing a first insulating layer, a sacrificial layer, and a second insulating layer on the surface of the bit line structure, and then dry etching the sacrificial layer in the middle to form an air interlayer.
  • An insulating layer of the same material is deposited on the surfaces of the second insulating layer, the air interlayer and the first insulating layer to cover the exposed gaps on the surface of the air interlayer to form an insulating structure with an air interlayer.
  • step S104 referring to FIG. 1e, an insulating structure 106 with an air interlayer 1061 is formed on both side walls of the bit line structure 104, wherein the two sides of the air interlayer 1061 are insulating layers 1062, and the height of the air interlayer 1061 is higher than that in the bit line structure 104.
  • the height of the conductive layer 1042 is the height of the conductive layer 1042 .
  • the dielectric layer between the NC and BL changes from a single insulating layer to an insulating layer plus air.
  • the bit line contacts partially in contact with the bit line contact holes, and the bit line structure;
  • the first insulating layer; an insulating structure with an air interlayer is formed on the two side walls of the bit line structure, wherein the height of the air interlayer is greater than the height of the conductive layer in the bit line structure, providing a new bit line structure sidewall that has A method for forming an insulating structure of an air interlayer. Since the insulating structure with air interlayer is located between BL and NC, and the dielectric constant of the air interlayer is smaller than that of the insulating layer in the insulating structure without air interlayer, therefore, the dielectric constant between NC and BL is reduced. The parasitic capacitance increases the readout capacity of the memory.
  • an embodiment of the present disclosure provides a semiconductor structure.
  • the structure includes:
  • bit line contact holes (the holes where the first insulating layer 105 is located) arranged at intervals on the substrate 101, the bit line contacts 103 partially in contact with the bit line contact holes, and the bit line structure 104, wherein the bit line structure 104 includes at least A conductive layer 1042 and an insulating capping layer 1041; the insulating capping layer 1041 is located on the conductive layer 1042;
  • the first insulating layer 105 filling the bit line contact hole in the bit line contact hole;
  • step S102 may include:
  • Step S1021 forming bit line contact holes on the substrate
  • step S1021 may be implemented by forming a first photoresist layer on the substrate, patterning the first photoresist layer, forming a first mask pattern with a bit line contact hole pattern, and using the first mask pattern The base is etched for the mask to form a bit line contact hole.
  • photoresist also known as photoresist, refers to a resist etching thin film material whose solubility changes through irradiation or radiation of ultraviolet light, electron beam, ion beam, X-ray, etc.
  • Photoresist is sensitive to light, including components such as photosensitive resin, sensitizer and solvent. Used as an anti-corrosion coating material during photolithography processes.
  • Step S1022 Depositing a first initial bit line contact filling the bit line contact hole in the bit line contact hole;
  • step S1022 can use physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer deposition process, plasma enhanced vapor phase deposition process, etc. to deposit and form the filled bit line in the bit line contact hole.
  • Contact hole for the first initial bitline contact can be used to deposit and form the filled bit line in the bit line contact hole.
  • depositing a first initial bit line contact that fills the bit line contact hole can deposit a second initial bit line contact on the bit line contact hole and the surface of the substrate, and then use chemical mechanical polishing to remove the bit line contact above the upper surface of the substrate.
  • a second initial bit line contact is formed to form the first initial bit line contact.
  • Step S1023 sequentially depositing and forming an initial conductive layer, an initial insulating cap layer and a second photoresist layer on the upper surface of the substrate;
  • step S1023 may adopt physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer deposition process, plasma enhanced vapor phase deposition process, etc. to sequentially deposit an initial conductive layer on the upper surface of the substrate, An initial insulating capping layer and a second photoresist layer.
  • Step S1024 patterning the second photoresist layer to form a second mask pattern having a bit line structure pattern
  • patterning the second photoresist layer may be to expose and develop the second photoresist layer, dissolve the part in the second photoresist layer, and form the undissolved part in the second photoresist layer Second mask pattern.
  • Step S1025 using the second mask pattern as a mask, etching the initial conductive layer and the initial insulating capping layer to form the conductive layer and the insulating capping layer;
  • step S1025 may be implemented by using a dry etching process (such as reactive ion etching technology, plasma etching technology, etc.) to etch the initial conductive layer and the initial insulating cap layer to form the conductive layer and the insulating cap layer.
  • a dry etching process such as reactive ion etching technology, plasma etching technology, etc.
  • Step S1026 removing the second photoresist layer
  • step S1026 may adopt a wet or dry etching process to remove the second photoresist layer.
  • Step S1027 Using the conductive layer and the insulating capping layer as a mask, etch the first initial bit line contact in the bit line contact hole to form the bit line contact, wherein the bit line contact is connected to the The bit line contact holes are partially contacted.
  • step S1027 may be implemented by using a wet or dry etching process to etch the first initial bit line contact in the bit line contact hole to form a bit line contact.
  • step S104 forming an insulating structure with an air interlayer on both sidewalls of the bit line structure.
  • Step S1041 sequentially forming a second insulating layer, a sacrificial layer and a third insulating layer on both side walls of the bit line structure, exposing part of the surface of the sacrificial layer;
  • Figure 2a shows the formation process of the insulating structure on both side walls of a bit line structure in Figure 1e, as shown in Figure (1) in Figure 2a, a second insulating layer 203 is sequentially formed on both side walls of the bit line structure 104 , the sacrificial layer 202 and the third insulating layer 201 , exposing part of the surface of the sacrificial layer 202 , that is, the top of the sacrificial layer 202 , wherein the upper surfaces of the second insulating layer 203 , the sacrificial layer 202 and the third insulating layer 201 are flush.
  • step S1041 can be implemented by sequentially depositing an initial second insulating layer, an initial sacrificial layer, and an initial third insulating layer on both side walls of the bit line structure, and then etching the upper surface of the bit line structure. an initial second insulating layer, an initial sacrificial layer, and an initial third insulating layer, forming the second insulating layer, the sacrificial layer, and the third insulating layer, exposing part of the surface of the sacrificial layer.
  • Step S1042 Etching the sacrificial layer along a first direction to form the air interlayer, wherein the first direction is a direction perpendicular to the substrate;
  • the sacrificial layer 202 is etched along the first direction (the direction indicated by the arrow) to form the air interlayer 1061 shown in Figure (2) in Figure 2a, wherein the first One direction is a direction perpendicular to the base, and it can be seen from FIG. 1e that the first direction is the direction indicated by the arrow in FIG. 2a.
  • step S1042 may be implemented by etching the sacrificial layer along the first direction by a dry etching process, such as reactive ion etching technology, plasma etching technology, etc. to form an air interlayer.
  • a dry etching process such as reactive ion etching technology, plasma etching technology, etc.
  • the sacrificial layer is etched by using a dry etching process to utilize the anisotropy of the dry etching, so as to facilitate the formation of an air interlayer.
  • Step S1043 forming a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer to obtain an insulating structure with air interlayers on both side walls of the bit line structure, wherein the The insulation structure includes the second insulation layer, the air interlayer, the third insulation layer and the fourth insulation layer stacked in sequence.
  • step S1043 may use a deposition process to form a fourth insulating layer on the upper surface of the bit line structure, the surface of the second insulating layer, the air interlayer and the third insulating layer, such as physical vapor deposition process, chemical vapor deposition process, low Pressure chemical vapor deposition process, molecular layer deposition process, plasma enhanced vapor phase deposition process, atomic layer deposition process, etc.
  • a deposition process to form a fourth insulating layer on the upper surface of the bit line structure, the surface of the second insulating layer, the air interlayer and the third insulating layer, such as physical vapor deposition process, chemical vapor deposition process, low Pressure chemical vapor deposition process, molecular layer deposition process, plasma enhanced vapor phase deposition process, atomic layer deposition process, etc.
  • the material used for the fourth insulating layer may include oxides, such as silicon oxide, aluminum oxide, and the like.
  • the material used for the fourth insulating layer can be at least the same as that used for the second insulating layer or the third insulating layer, so that the fourth insulating layer can cover the voids on the surface of the air interlayer.
  • the fourth insulating layer 205 covering the third insulating layer 201, the air interlayer 1061 and the second insulating layer 203 is formed, that is, the fourth insulating layer 205 covers the third insulating layer, the air
  • the surfaces of the interlayer 1061 and the second insulating layer 203 can be used to obtain an insulating structure 106 with an air interlayer 1061 on both side walls of the bit line structure 104, wherein the insulating structure 106 includes the second insulating layer 203, the air interlayer 1061, and the third stacked in sequence.
  • insulating layer 201 and a fourth insulating layer 205 are examples of the fourth insulating layer 205 .
  • step S1043 may include:
  • Step S1431 forming an initial fourth insulating layer on the upper surface of the bit line structure, the surfaces of the second insulating layer, the air interlayer and the third insulating layer;
  • the material used for the initial fourth insulating layer may be at least the same as that used for the second insulating layer or the third insulating layer, so that the initial fourth insulating layer can cover the voids on the surface of the air interlayer.
  • an initial fourth insulating layer 209 is formed on the upper surface of the bit line structure 104 , the second insulating layer 203 , the air interlayer 1061 and the third insulating layer 201 .
  • Step S1432 Etching the initial fourth insulating layer above the top of the bit line structure to form a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer.
  • step S1432 may use a dry etching process to etch the initial fourth insulating layer above the top of the bit line structure, such as reactive ion etching technology, plasma etching technology and the like.
  • the initial fourth insulating layer 209 above the top of the bit line structure 104 is etched to form a covering third insulating layer as shown in diagram (2) in FIG. 2b 201 , the air interlayer 1061 and the fourth insulating layer 205 of the second insulating layer 203 .
  • a second insulating layer, a sacrificial layer, and a third insulating layer are sequentially deposited on the surface of the bit line structure, and then the intermediate sacrificial layer is etched to form an air interlayer. After that, the second insulating layer, the air A fourth insulating layer is deposited on the surface of the interlayer and the third insulating layer to cover the exposed gap at the top of the air interlayer to form an insulating structure with an air interlayer.
  • step S1041 may include:
  • Step S1411 sequentially forming an initial second insulating layer and an initial sacrificial layer on the surface of the bit line structure;
  • an initial second insulating layer 206 and an initial sacrificial layer 207 are sequentially formed on the surface of the bit line structure 104 .
  • step S1411 may use a deposition process to sequentially form an initial second insulating layer and an initial sacrificial layer on the surface of the bit line structure, such as physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer deposition process , plasma enhanced vapor deposition process, atomic layer deposition process, etc.
  • a deposition process to sequentially form an initial second insulating layer and an initial sacrificial layer on the surface of the bit line structure, such as physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer deposition process , plasma enhanced vapor deposition process, atomic layer deposition process, etc.
  • the material used for the initial second insulating layer may be oxide, such as silicon oxide, aluminum oxide, and the like.
  • the material used for the initial sacrificial layer may include polysilicon.
  • Step S1412 Etching the initial sacrificial layer above the top of the bit line structure to form the sacrificial layer
  • step S1412 may use a dry etching process to etch the initial sacrificial layer above the top of the bit line structure, such as reactive ion etching technology, plasma etching technology and the like.
  • Step S1413 forming an initial third insulating layer on the surface of the initial second insulating layer and the surface of the sacrificial layer;
  • an initial third insulating layer 208 is formed on the surface of the initial second insulating layer 206 and the surface of the sacrificial layer 202 .
  • step S1413 may use a deposition process to form an initial third insulating layer on the surface of the initial second insulating layer and the surface of the sacrificial layer, such as physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer Deposition process, plasma enhanced vapor deposition process, atomic layer deposition process, etc.
  • a deposition process to form an initial third insulating layer on the surface of the initial second insulating layer and the surface of the sacrificial layer, such as physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer Deposition process, plasma enhanced vapor deposition process, atomic layer deposition process, etc.
  • the material used for the initial third insulating layer may include oxides, such as silicon oxide, aluminum oxide, and the like.
  • the material used for the initial third insulating layer may be the same as or different from the material used for the initial second insulating layer.
  • Step S1414 Etching the initial third insulating layer and the initial second insulating layer above the top of the bit line structure, exposing part of the surface of the sacrificial layer, forming The second insulating layer, the sacrificial layer and the third insulating layer are sequentially formed on the wall.
  • the initial third insulating layer 208 and the initial second insulating layer 206 above the top of the bit line structure 104 are etched to expose part of the surface of the sacrificial layer 202, forming a
  • the second insulating layer 203 , the sacrificial layer 202 and the third insulating layer 201 are sequentially formed on both side walls of the bit line structure 104 .
  • step S1414 may be implemented by using a dry etching process to etch the initial third insulating layer and the initial second insulating layer above the top of the bit line structure, such as reactive ion etching technology, plasma etching technology and the like.
  • An embodiment of the present disclosure also provides a method for forming a semiconductor structure, as shown in FIG. 3a, the method includes:
  • steps S201 to S203 reference may be made to steps S101 to S103.
  • Step S204 sequentially forming an initial second insulating layer and an initial sacrificial layer on the surface of the bit line structure
  • Step S205 etching the initial sacrificial layer above the top of the bit line structure to form the sacrificial layer
  • Step S206 forming an initial third insulating layer on the surface of the initial second insulating layer and the surface of the sacrificial layer;
  • Step S207 Etching the initial third insulating layer and the initial second insulating layer above the top of the bit line structure, exposing part of the surface of the sacrificial layer, forming The second insulating layer, the sacrificial layer and the third insulating layer are sequentially formed on the wall.
  • step S204 to step S207 may refer to step S1411 to step S1414.
  • Step S208 Etching the sacrificial layer along a first direction to form the air interlayer, wherein the first direction is a direction perpendicular to the substrate;
  • step S208 may refer to step S1042.
  • Step S209 forming an initial fourth insulating layer on the upper surface of the bit line structure, the surfaces of the second insulating layer, the air interlayer and the third insulating layer;
  • Step S210a Etching the initial fourth insulating layer above the top of the bit line structure to form a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer.
  • step S209 and step S210a refer to step S1431 and step S1432 respectively.
  • Step S211a forming a storage node contact between adjacent fourth insulating layers.
  • the storage node contact may include polysilicon doped with impurities or polysilicon not doped with impurities.
  • storage node contacts 301 are formed between adjacent fourth insulating layers 205 .
  • step S210b to step S212b are also included:
  • Step S210b forming a fifth insulating layer on the surface of the initial fourth insulating layer
  • the material used for the fifth insulating layer may include oxides, such as silicon oxide, aluminum oxide, and the like.
  • the material of the fifth insulating layer may be the same as that of the fourth insulating layer, or may be different from that of the fourth insulating layer.
  • a fifth insulating layer 302 is formed on the surface of the initial fourth insulating layer 209 .
  • the structure of the initial fourth insulating layer 209 can refer to the diagram (1) in FIG. 2b.
  • Step S211b etching the fifth insulating layer, the initial fourth insulating layer on the surface of the substrate and part of the substrate to expose the substrate;
  • the fifth insulating layer 302, the initial fourth insulating layer 209 on the surface of the substrate 101 and part of the substrate 101 are etched by a dry etching process to expose the substrate 101, that is, the blank area 303 on the substrate in FIG. 3d .
  • Step S212b Etching the initial fourth insulating layer and the fifth insulating layer above the upper surface of the bit line structure to form a layer covering the third insulating layer, the air interlayer and the second insulating layer The fourth insulating layer.
  • Step S213b forming a storage node contact between adjacent fourth insulating layers.
  • the fourth insulating layer is protected by the fifth insulating layer. layer, which reduces the risk of etching off the fourth insulating layer on the surface of the bit line structure during the etching process, thereby protecting the insulating structure.
  • An embodiment of the present disclosure also provides a method for forming a semiconductor structure. After step S211a or step S213b, the method includes:
  • Step S301 forming a metal layer on the surface of the insulating structure, the surface of the storage node contact and the surface of the bit line structure;
  • the material used for the metal layer may be a conductive material, such as tungsten (W).
  • the plasma enhanced chemical vapor deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD) is used to deposit conductive materials to reduce the possibility of voids during filling.
  • the conductive material may also be deposited by appropriate processes such as chemical vapor deposition, low-pressure chemical vapor deposition, and atomic layer deposition.
  • a metal layer 401 is formed on the surface of the insulating structure 106 , the surface of the storage node contact 301 and the upper surface of the bit line structure 104 .
  • Step S302 Etching part of the metal layer to form a first opening to expose a part of the surface of the insulating structure located on the first sidewall of the bit line structure;
  • the remaining metal layer after etching forms a landing pad electrically connected to the storage node contact, and the landing pad covers the surface of the storage node contact and the insulating structure of the second side wall of the bit line structure. surface and the upper surface of the bitline structure.
  • the metal layer may be selectively etched by a dry etching process or a wet etching process, and the etching gas may be hydrogen bromide (HBr)/chlorine (Cl 2 ).
  • the function of the landing pad is to electrically connect the storage node contact with the capacitor.
  • Step S302 can refer to FIGS. 4b and 4a. As shown in FIG. 4a, a part of the metal layer 401 is etched to form a first opening 402 as shown in FIG. surface.
  • the remaining metal layer after etching forms a landing pad 403 electrically connected to the storage node contact 301, and the landing pad 403 covers the surface of the storage node contact 301, the surface of the insulating structure 106 of the second side wall A of the bit line structure, and the bit line structure 104 of the upper surface.
  • Step S303a forming an isolation structure between adjacent landing pads and on the surface of the landing pads.
  • the material of the isolation structure may be silicon oxide, silicon nitride (such as silicon nitride (Si 3 N 4 )) or silicon oxynitride.
  • Step S303 a may refer to FIG. 4 c , forming an isolation structure 404 between adjacent landing pads 403 and on the surface of the landing pads 403 .
  • the isolation structure includes a first filling layer and a second filling layer.
  • the implementation of step S303a "forming the isolation structure between adjacent landing pads and on the surface of the landing pad" includes Step S33a1 and step S33a2, wherein:
  • Step S33a1 depositing a first filling layer on the insulating structure of the first sidewall of the bit line structure and the surface of the landing pad;
  • step S33a1 may refer to FIG. 4d , depositing a first filling layer 4042 on the surface of the insulating structure 106 and the landing pad 403 on the first side wall B of the bit line structure 104 .
  • the material used for the first filling layer may be the same as the material used for at least one of the second insulating layer, the third insulating layer, or the fourth insulating layer in the insulating structure, or it may be the same as the material used in the insulating structure.
  • the materials used for the second insulating layer, the third insulating layer and the fourth insulating layer are different.
  • Step S33a2 depositing a second filling layer on the surface of the first filling layer.
  • step S33a2 may refer to FIG. 4d, depositing a second filling layer 4041 on the surface of the first filling layer 4042, and the material of the second filling layer may be the same as or different from that of the first filling layer.
  • a metal layer is formed on the surface of the insulating structure, the surface of the storage node contact, and the surface of the bit line structure, and then a part of the metal layer is etched to form the first opening, exposing the first side wall of the bit line structure.
  • Part of the surface of the insulating structure forms a landing pad, and then forms an isolation structure between adjacent landing pads and on the surface of the landing pad to form mutually isolated landing pads, so that when the insulating structure has an air interlayer, the NC can pass through each other.
  • the isolated landing pads are connected to other parts in the semiconductor structure.
  • An embodiment of the present disclosure provides a semiconductor structure, as shown in FIG. 4d, the structure includes:
  • bit line contact holes (the holes where the first insulating layer 105 is located) arranged at intervals on the substrate 101, the bit line contacts 103 partially in contact with the bit line contact holes, and the bit line structure 104, wherein the bit line structure 104 includes at least A conductive layer 1042 and an insulating capping layer 1041; the insulating capping layer 1041 is located on the conductive layer 1042;
  • the first insulating layer 105 filling the bit line contact hole in the bit line contact hole;
  • the insulating structure 106 can be understood with reference to the diagram (2) in FIG. 2b.
  • the landing pad 403 covering the storage node contact 301 , the insulating structure 106 of the second sidewall A and the upper surface of the bit line structure 104 is electrically connected to the storage node contact 301 .
  • the isolation structure 404 is located between adjacent landing pads 403 and on the surface of the landing pads 403 .
  • the isolation structure 404 includes a first filling layer 4042 and a second filling layer 4041, the first filling layer 4042 is located on the surface of the insulating structure 106 and the landing pad 403 on the first side wall B of the bit line structure 104, the second The filling layer 4041 is located on the surface of the first filling layer 4042 .
  • An embodiment of the present disclosure also provides a method for forming a semiconductor structure. After step S302, the method further includes:
  • Step S303b continue to etch the first opening along the first direction, the height of the etching stop position is higher than the height of the conductive layer in the bit line structure, and form a second opening; wherein, near the first side
  • the air interlayer of the wall is a first air interlayer having a first height
  • the air interlayer adjacent to the second side wall is a second air interlayer having a second height
  • the first height is smaller than the second height.
  • Step S303b can refer to FIG. 4e and FIG. 4b.
  • the first direction is the direction perpendicular to the substrate 101, that is, the direction indicated by the arrow in the figure.
  • the height of the stop position is higher than the height of the conductive layer 1042 in the bit line structure 104, forming a second opening 405 as shown in FIG.
  • the air interlayer near the second side wall A is the second air interlayer 406 with the second height h2
  • the first side wall B is the right side wall of all the bit line structures 104 in Figure 4e
  • the second side wall A is the The left side walls of all the bit line structures 104 in 4e, that is, the air interlayer close to the right side wall of the bit line structure 104 is the first air interlayer 407 having the first height h1
  • the air interlayer close to the left side wall of the bit line structure 104 has a The second air interlayer 406 of the second height h2, and the first height h1 is smaller than the second height h2.
  • Step S304b forming an isolation structure between adjacent landing pads and on the surface of the landing pads.
  • step S304b referring to FIG. 4f , an isolation structure 404 is formed between adjacent landing pads 403 and on the surface of the landing pads 403 .
  • the isolation structure includes a first filling layer and a second filling layer.
  • the implementation of step S304b "forming the isolation structure between adjacent landing pads and on the surface of the landing pad" includes Step S34b1 and step S34b2, wherein:
  • Step S34b1 depositing a first filling layer on the insulating structure of the first sidewall of the bit line structure and the surface of the landing pad;
  • step S34b1 may refer to FIG. 4g , depositing a first filling layer 4042 on the surface of the insulating structure 106 and the landing pad 403 on the first side wall B of the bit line structure 104 .
  • the material used for the first filling layer may be the same as that used for at least one of the second insulating layer, the third insulating layer, or the fourth insulating layer in the insulating structure 106, so as to seal the first air interlayer. 407 to form a closed first air interlayer 407 .
  • Step S34b2 depositing a second filling layer on the surface of the first filling layer.
  • step S34b2 may refer to FIG. 4g, depositing a second filling layer 4041 on the surface of the first filling layer 4042, and the material of the second filling layer may be the same as or different from that of the first filling layer.
  • the isolation structure in the embodiment of the present disclosure includes a first filling layer and a second filling layer.
  • a first filling layer in the isolation structure By using the first filling layer in the isolation structure to close the opening of the first air interlayer, an airtight first air interlayer is formed, and then filled in the first
  • the second filling layer is deposited on the surface of the layer to form an isolation structure, and the first air interlayer and the second air interlayer with different heights are obtained.
  • the height of the first air interlayer is higher than that of the conductive layer in the bit line structure, it can reduce NC and The role of parasitic capacitance between BL; at the same time, since the height of the first air interlayer is lower than the height of the second air interlayer, compared with the case where the height of the first air interlayer and the second air interlayer are the same, a part of the space is reserved for the landing pad , making the landing pad thicker, thereby reducing the resistance of the landing pad and enhancing the conductivity of the landing pad.
  • An embodiment of the present disclosure provides a semiconductor structure, as shown in FIG. 4g, the structure includes:
  • bit line contact holes (the holes where the first insulating layer 105 is located) arranged at intervals on the substrate 101, the bit line contacts 103 partially in contact with the bit line contact holes, and the bit line structure 104, wherein the bit line structure 104 includes at least A conductive layer 1042 and an insulating capping layer 1041; the insulating capping layer 1041 is located on the conductive layer 1042;
  • the first insulating layer 105 filling the bit line contact hole in the bit line contact hole;
  • the insulating structure 106 can be understood with reference to the diagram (2) in FIG. 2b.
  • the air interlayer includes a first air interlayer 407 having a first height h1 and a second air interlayer 406 having a second height h2, wherein the first air interlayer 406 is adjacent to the first sidewall of the bit line structure 104 B, the second air interlayer 406 is close to the second sidewall A of the bit line structure 104, and the first height h1 is smaller than the second height h2.
  • the landing pad 403 covering the storage node contact 301 , the insulating structure 106 of the second sidewall A and the upper surface of the bit line structure 104 is electrically connected to the storage node contact 301 .
  • the isolation structure 404 is located between adjacent landing pads 403 and on the surface of the landing pads 403 .
  • the isolation structure 404 includes a first filling layer 4042 and a second filling layer 4041, the first filling layer 4042 is located on the surface of the insulating structure 106 and the landing pad 403 on the first side wall B of the bit line structure 104, the second The filling layer 4041 is located on the surface of the first filling layer 4042 .
  • An embodiment of the present disclosure provides a semiconductor structure and a method for forming the same, including: providing a substrate; forming bit line contact holes arranged at intervals on the substrate, bit line contacts partially in contact with the bit line contact holes, and a bit line structure, wherein the bit line structure at least includes a conductive layer and an insulating capping layer; the insulating capping layer is located on the conductive layer; Insulating layer: an insulating structure with an air interlayer is formed on both side walls of the bit line structure, wherein the height of the air interlayer is greater than that of the conductive layer in the bit line structure.
  • the bit line contacts partially in contact with the bit line contact holes, and the bit line structure;
  • the first insulating layer; an insulating structure with an air interlayer is formed on the two side walls of the bit line structure, wherein the height of the air interlayer is greater than the height of the conductive layer in the bit line structure, providing a new bit line structure sidewall that has A method for forming an insulating structure of an air interlayer. Since the insulating structure with air interlayer is located between BL and NC, and the dielectric constant of the air interlayer is smaller than that of the insulating layer in the insulating structure without air interlayer, therefore, the dielectric constant between NC and BL is reduced. The parasitic capacitance increases the readout capacity of the memory.

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Abstract

本公开实施例提供一种半导体结构及其形成方法，包括：提供基底；在所述基底上形成间隔排布的位线接触孔、与所述位线接触孔部分接触的位线接触以及位线结构，其中，所述位线结构至少包括导电层和绝缘盖帽层；所述绝缘盖帽层位于所述导电层上；在所述位线接触孔内形成填满所述位线接触孔的第一绝缘层；在所述位线结构的两侧壁形成具有空气夹层的绝缘结构，其中，所述空气夹层的高度大于所述位线结构中导电层的高度。

Description

半导体结构及其形成方法
相关申请的交叉引用
本公开基于申请号为202111570795.6、申请日为2021年12月21日、申请名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本公开实施例涉及一种半导体结构及其形成方法。
背景技术
半导体器件，例如动态随机存储器(Dynamic Random Access Memory，DRAM)包括多个存储单元、字线(Word Line，WL)和位线(Bit Line，BL)。其中，每个存储单元通常包括晶体管和电容器，晶体管的栅极与WL相连，晶体管的漏区或源区与BL相连，晶体管的源区或漏区与电容器相连。在WL上施加电压信号能够控制晶体管的打开或关闭，进而通过BL读取存储在电容器中的数据信息，或者通过BL将数据信息写入到电容器中进行存储。
半导体器件还可以包括存储节点接触(Node Contact，NC)和位线接触(Bit line Contact，BLC)。其中，NC用于电连接源/漏区和半导体结构中的其他部分，BLC用于电连接有源区和BL。随着半导体存储器件的高度集成，BL和NC之间的距离变得更短，从而增加了BL和NC之间的寄生电容，进而导致存储器的感测容限和读取速度降低。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其形成方法。
第一方面，本公开实施例提供一种半导体结构的形成方法，所述方法包括：提供基底；在所述基底上形成间隔排布的位线接触孔、与所述位线接触孔部分接触的位线接触以及位线结构，其中，所述位线结构至少包括导电层和绝缘盖帽层；所述绝缘盖帽层位于所述导电层上；在所述位线接触孔内形成填满所述位线接触孔的第一绝缘层；在所述位线结构的两侧壁形成具有空气夹层的绝缘结构，其中，所述空气夹层的高度大于所述位线结构中导电层的高度。
在一些实施例中，在所述位线结构的两侧壁形成具有空气夹层的绝缘结构，包括：在所述位线结构的两侧壁依次形成第二绝缘层、牺牲层和第三绝缘层，暴露出部分所述牺牲层的表面；沿第一方向刻蚀所述牺牲层，形成所述空气夹层，其中，所述第一方向为垂直于所述基底的方向；形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层，得到位于所述位线结构两侧壁具有空气夹层的绝缘结构，其中，所述绝缘结构包括依次堆叠的所述第二绝缘层、所述空气夹层、所述第三绝缘层和所述第四绝缘层。
在一些实施例中，所述沿第一方向刻蚀所述牺牲层，形成所述空气夹层，包括：采用干法刻蚀工艺沿第一方向刻蚀所述牺牲层，形成所述空气夹层。
在一些实施例中，在所述位线结构的两侧壁依次形成第二绝缘层、牺牲层和第三绝缘层，暴露出部分所述牺牲层的表面，包括：在所述位线结构的表面依次形成初始第二绝缘层和初始牺牲层；刻蚀位于所述位线结构顶部以上的所述初始牺牲层，形成所述牺牲层；在所述初始第二绝缘层的表面和所述牺牲层的表面形成初始第三绝缘层；刻蚀位于所述位线结构顶部以上的所述初始第三绝缘层和所述初始第二绝缘层，暴露出部分所述牺牲层的表面，形成位于所述位线结构的两侧壁依次形成的第二绝缘层、牺牲层和第三绝缘层。
在一些实施例中，所述形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层，包括：在所述位线结构的上表面，所述第二绝缘层、所述空气夹层和所述第三绝缘层的表面形成初始第四绝缘层；刻蚀位于所述位线结构顶部以上的所述初始第四绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层。
在一些实施例中，在形成所述第四绝缘层之后，还包括：在相邻所述第四绝缘层之间形成存储节点接触。
在一些实施例中，还包括：在所述绝缘结构的表面、所述存储节点接触的表面和所述位线结构的上表面形成金属层；刻蚀部分所述金属层，形成第一开口，以暴露出位于所述位线结构第一侧壁的绝缘结构的部分表面；其中，刻蚀后剩余的所述金属层形成与所述存储节点接触电连接的着落垫，所述着落垫覆盖所述存储节点接触的表面、所述位线结构第二侧壁的绝缘结构的表面和所述位线结构的上表面。
在一些实施例中，还包括：沿所述第一方向继续刻蚀所述第一开口，刻蚀停止位置的高度高于所述位线结构中导电层的高度，形成第二开口；其中，靠近所述第一侧壁的空气夹层为具有第一高度的第一空气夹层，靠近所述第二侧壁的空气夹层为具有第二高度的第二空气夹层，且所述第一高度小于所述第二高度。
在一些实施例中，还包括：在相邻所述着落垫之间和所述着落垫的表面形成隔离结构。
在一些实施例中，所述隔离结构包括第一填充层和第二填充层，所述在相邻所述着落垫之间和所述着落垫的表面形成隔离结构，包括：在所述位线结构第一侧壁的绝缘结构和所述着落垫的表面沉积第一填充层；在所述第一填充层的表面沉积第二填充层。
在一些实施例中，在相邻所述第四绝缘层之间形成存储节点接触之前，还包括：在所述初始第四绝缘层表面形成第五绝缘层；刻蚀所述第五绝缘层、所述基底表面的所述初始第四绝缘层和部分所述基底，以暴露所述基底；对应地，所述刻蚀位于所述位线结构顶部以上的所述初始第四绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层，包括：刻蚀位于所述位线结构上表面以上的所述初始第四绝缘层和所述第五绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层。
在一些实施例中，所述第一绝缘层的材料包括氮化物；所述第二绝缘层、所述第三绝缘层和所述第四绝缘层的材料包括氧化物。
在一些实施例中，所述牺牲层的材料包括硅。
第二方面，本公开实施例提供一种半导体结构，所述结构包括：基底；位于所述基底上的间隔排布的位线接触孔、与所述位线接触孔部分接触的位线接触以及位线结构，其中，所述位线结构至少包括导电层和绝缘盖帽层；所述绝缘盖帽层位于所述导电层上；位于所述位线接触孔内的填满所述位线接触孔的第一绝缘层；位于所述位线结构两侧壁的具有空气夹层的绝缘结构，其中，所述空气夹层的高度大于所述位线结构中导电层的高度。
在一些实施例中，所述绝缘结构包括依次堆叠的第二绝缘层、空气夹层、第三绝缘层和第四绝缘层，其中，所述第四绝缘层覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层。
在一些实施例中，所述空气夹层包括具有第一高度的第一空气夹层和具有第二高度的第二空气夹层，其中，所述第一空气夹层靠近所述位线结构的第一侧壁，所述第二空气夹层靠近所述位线结构的第二侧壁，所述第一高度小于所述第二高度。
在一些实施例中，还包括：位于相邻所述第四绝缘层之间的存储节点接触；覆盖所述存储节点接触、所述第二侧壁的绝缘结构和所述位线结构上表面的着落垫，所述着落垫与所述存储节点接触电连接。
在一些实施例中，还包括：位于相邻所述着落垫之间和所述着落垫的表面的隔离结构。
在一些实施例中，所述隔离结构包括第一填充层和第二填充层，所述第一填充层位于所述位线结构第一侧壁的绝缘结构和所述着落垫的表面，所述第二填充层位于所述第一填充层的表面。
附图说明
图1a为本公开实施例提供的一种半导体结构形成方法的流程示意图；
图1b至图2c为本公开实施例提供的一种半导体结构形成方法的过程示意图；
图3a为本公开实施例提供的另一种半导体结构形成方法的流程示意图；
图3b至图3d为本公开实施例提供的另一种半导体结构形成方法的过程示意图；
图4a至图4g为本公开实施例提供的另一种半导体结构形成方法的过程示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需至少一个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
本公开实施例提供一种半导体结构的形成方法，如图1a所示，所述方法包括以下步骤：
步骤S101、提供基底。
这里，基底可以是硅(Si)衬底、锗(Ge)衬底、硅锗(SiGe)衬底、镓砷化物衬底、陶瓷衬底、石英衬底或用于显示器的玻璃衬底，也可以包括多层，例如绝缘体上硅(Silicon On Insulator，SOI)衬底、或绝缘体上锗(Germanium On Insulator，GOI)衬底等。
基底内还可以形成有浅沟槽隔离(Shallow Trench Isolation，STI)，在基底内隔离出若干有源区。STI可以通过在基底内形成沟槽后，再在沟槽内填充隔离材料层而形成。STI中填充的材料可以包括氮化硅或氧化硅等，氧化硅可以通过热氧化形成。STI可以在基底隔离出的若干个呈阵列分布或其他分布类型的有源区。
在一些实施例中，基底内还可以形成有位于浅沟槽隔离和有源区之上的缓冲层，缓冲层可以包括至少一个绝缘层，缓冲层的材料可以包括硅氧化物、硅氮化物或硅氮氧化物等。
步骤S101可以参考图1b，提供的基底101包括有源区1012、浅沟槽隔离1011和缓冲层1013，其中，浅沟槽隔离1011与有源区1012间隔排布，缓冲层1013位于浅沟槽隔离1011和有源区1012之上。
步骤S102、在所述基底上形成间隔排布的位线接触孔、与所述位线接触孔部分接触的位线接触以及位线结构；
其中，位线接触采用的材料可以包括但不限于多晶硅等导电材料，例如，掺杂杂质的多 晶硅或未掺杂杂质的多晶硅。位线结构至少包括导电层和绝缘盖帽层；所述绝缘盖帽层位于所述导电层上。
如图1c所示，在基底101上形成间隔排布的位线接触孔102、与位线接触孔102部分接触的位线接触103以及位线结构104，其中，位线接触孔102贯穿部分基底101，位线接触103位于位线接触孔102之内，且位线接触孔102内具有未被位线接触103占据的空间。位线结构104中的一部分位于位线接触103之上，通过位线接触103连接到有源区1012，另一部分位线结构104位于基底101之上。位线结构104至少包括导电层1042和位于导电层1042上的绝缘盖帽层1041。
在实际应用中，导电层的材料可以采用多晶硅、金属硅化物、导电金属氮化物(例如钛氮化物(TiN)、钽氮化物(TaN)、钨氮化物(WN)等)和金属(例如钨(W)、钛(Ti)、钽(Ta)等)中的一种或更多种。在实际应用中，绝缘盖帽层的材料可以是氧化物、硅氮化物和硅氮氧化物中的至少一个，绝缘盖帽层可以采用化学气相沉积工艺形成。
在另一些实施例中，位线结构还可以包括扩散阻挡层，扩散阻挡层位于位线接触和导电层之间。扩散阻挡层可以使导电层与有源区绝缘，同时可以阻止导电层中的金属离子进入有源区。扩散阻挡层可以包括单层结构，例如，金属钛层；也可以包括多层结构，例如，金属钛层和氮化钛层。
步骤S103、在所述位线接触孔内形成填满所述位线接触孔的第一绝缘层；
结合图1c和图1d，在位线接触孔102内形成填满位线接触孔102的第一绝缘层105(如图1d所示)。其中，第一绝缘层105的表面与位线接触孔102的表面齐平。这里，第一绝缘层可以用来降低BLC在后续的工艺中的破坏。
第一绝缘层采用的材料可以为氮化物，氮化物可以包括但不限于氮化硅、氮氧化硅等。在一些实施例中，为了便于控制第一绝缘层的厚度，可以通过原子层沉积工艺形成第一绝缘层。在另一些实施例中，也可以采用其他工艺形成第一绝缘层，例如物理气相沉积工艺、化学气相沉积工艺、低气压化学气相沉积工艺、分子层沉积工艺、等离子体增强化气相沉积工艺等。
在一些实施例中，步骤S103的实施可以先在基底的上表面和位线接触孔的表面沉积形成初始第一绝缘层，再通过刻蚀去除基底上表面以上的所述初始第一绝缘层，形成填满位线接触孔的第一绝缘层。
步骤S104、在所述位线结构的两侧壁形成具有空气夹层的绝缘结构，其中，所述空气夹层的高度大于所述位线结构中导电层的高度。
这里，绝缘结构的形式可以为两侧两层绝缘层中间一层空气夹层，即绝缘结构从左到右分别为绝缘层、空气夹层、绝缘层；其中，绝缘层的材料可以是氧化硅、氧化铝等。在实施时，两层绝缘层的材料可以相同，也可以不同。
在一些实施例中，为了便于控制绝缘结构中绝缘层的厚度，可以通过原子层沉积工艺形成绝缘结构中的绝缘层。在另一些实施例中，也可以采用其他工艺形成绝缘结构中的绝缘层，例如物理气相沉积工艺、化学气相沉积工艺、低气压化学气相沉积工艺、分子层沉积工艺、等离子体增强化气相沉积工艺等。
在一些实施例中，步骤S104的实施可以通过在位线结构的表面依次沉积形成第一绝缘层、牺牲层和第二绝缘层，再干法刻蚀中间的牺牲层形成空气夹层，之后，在第二绝缘层、空气夹层和第一绝缘层的表面沉积相同材料的绝缘层，覆盖空气夹层表面暴露的空隙，形成具有空气夹层的绝缘结构。
步骤S104可以参考图1e，在位线结构104的两侧壁形成具有空气夹层1061的绝缘结构106，其中，空气夹层1061的两侧为绝缘层1062，空气夹层1061的高度大于位线结构104中导电层1042的高度。
这里，由于空气夹层的高度大于位线结构中导电层的高度，而NC位于相邻两个BL之 间，使得NC与BL之间的介质层从单一的绝缘层，变成了绝缘层加空气夹层，又由于空气夹层的介电常数相比于绝缘层的介电常数小，因此，可以降低NC与BL之间的寄生电容。
本公开实施例中，通过在基底上形成间隔排布的位线接触孔、与位线接触孔部分接触的位线接触以及位线结构；在位线接触孔内形成填满位线接触孔的第一绝缘层；在位线结构的两侧壁形成具有空气夹层的绝缘结构，其中，空气夹层的高度大于位线结构中导电层的高度，提供了一种新的位线结构侧墙即具有空气夹层的绝缘结构的形成方法。由于具有空气夹层的绝缘结构位于BL和NC之间，而空气夹层的介电常数相比于没有空气夹层的绝缘结构中的绝缘层的介电常数小，因此，降低了NC与BL之间的寄生电容，提高了存储器的读出容量。
基于图1a所示的一种半导体结构的形成方法，本公开实施例提供一种半导体结构，如图1e所示，该结构包括：
基底101；
位于基底101上的间隔排布的位线接触孔(第一绝缘层105所在的孔)、与位线接触孔部分接触的位线接触103以及位线结构104，其中，位线结构104至少包括导电层1042和绝缘盖帽层1041；绝缘盖帽层1041位于导电层1042上；
位于位线接触孔内的填满位线接触孔的第一绝缘层105；
位于位线结构104两侧壁的具有空气夹层1061的绝缘结构106，其中，空气夹层1061的高度大于位线结构104中导电层1042的高度。
在一些实施例中，步骤S102的实施可以包括：
步骤S1021：在基底上形成位线接触孔；
这里，步骤S1021的实施可以为在基底上形成第一光刻胶层，图案化第一光刻胶层，形成具有位线接触孔图案的第一掩膜图案，以所述第一掩膜图案为掩膜刻蚀基底，形成位线接触孔。
其中，光刻胶又称光致抗蚀剂，是指通过紫外光、电子束、离子束、X射线等的照射或辐射，其溶解度发生变化的耐蚀剂刻薄膜材料。光刻胶对光敏感，包括感光树脂、增感剂和溶剂等成分。在光刻工艺过程中，用作抗腐蚀涂层材料。
步骤S1022：在位线接触孔内沉积填满位线接触孔的第一初始位线接触；
这里，步骤S1022的实施可以采用物理气相沉积工艺、化学气相沉积工艺、低气压化学气相沉积工艺、分子层沉积工艺、等离子体增强化气相沉积工艺等在位线接触孔内沉积形成填满位线接触孔的第一初始位线接触。
在一些实施例中，沉积填满位线接触孔的第一初始位线接触可以在位线接触孔和基底的表面沉积第二初始位线接触，再利用化学机械抛光清除位于基底上表面以上的第二初始位线接触，形成所述第一初始位线接触。
步骤S1023：在基底的上表面依次沉积形成初始导电层、初始绝缘盖帽层和第二光刻胶层；
这里，步骤S1023的实施可以采用物理气相沉积工艺、化学气相沉积工艺、低气压化学气相沉积工艺、分子层沉积工艺、等离子体增强化气相沉积工艺等在基底的上表面依次沉积形成初始导电层、初始绝缘盖帽层和第二光刻胶层。
步骤S1024：图案化所述第二光刻胶层，形成具有位线结构图案的第二掩膜图案；
这里，图案化第二光刻胶层可以是，对第二光刻胶层进行曝光和显影，溶解掉光第二刻胶层中的部分，第二光刻胶层中未被溶解的部分形成第二掩膜图案。
步骤S1025：以所述第二掩膜图案为掩膜，刻蚀初始导电层和初始绝缘盖帽层，形成所述导电层和所述绝缘盖帽层；
这里，步骤S1025的实施可以采用干法刻蚀工艺(例如反应离子刻蚀技术、等离子体刻蚀技术等)刻蚀初始导电层和初始绝缘盖帽层，形成导电层和绝缘盖帽层。
步骤S1026：清除所述第二光刻胶层；
这里，步骤S1026的实施可以采用湿法或干法刻蚀工艺，清除第二光刻胶层。
步骤S1027：以所述导电层和所述绝缘盖帽层为掩膜，刻蚀位线接触孔内的第一初始位线接触，形成所述位线接触，其中，所述位线接触与所述位线接触孔部分接触。
这里，步骤S1027的实施可以采用湿法或干法刻蚀工艺，刻蚀位线接触孔内的第一初始位线接触，形成位线接触。
在一些实施例中，步骤S104“在所述位线结构的两侧壁形成具有空气夹层的绝缘结构”的实施可以包括：
步骤S1041：在所述位线结构的两侧壁依次形成第二绝缘层、牺牲层和第三绝缘层，暴露出部分所述牺牲层的表面；
图2a显示了图1e中一个位线结构其两侧壁的绝缘结构的形成过程，如图2a中的图(1)所示，在位线结构104的两侧壁依次形成第二绝缘层203、牺牲层202和第三绝缘层201，暴露出部分牺牲层202的表面，即牺牲层202的顶部，其中，第二绝缘层203、牺牲层202和第三绝缘层201的上表面平齐。
在一些实施例中，步骤S1041的实施可以通过在位线结构的两侧壁依次沉积形成初始第二绝缘层、初始牺牲层和初始第三绝缘层，再刻蚀位于位线结构上表面之上的初始第二绝缘层、初始牺牲层和初始第三绝缘层，形成所述第二绝缘层、所述牺牲层和所述第三绝缘层，暴露出部分所述牺牲层的表面。
步骤S1042：沿第一方向刻蚀所述牺牲层，形成所述空气夹层，其中，所述第一方向为垂直于所述基底的方向；
结合图2a中的图(1)和图(2)，沿第一方向(箭头所指方向)刻蚀牺牲层202，形成图2a中的图(2)所示的空气夹层1061，其中，第一方向为垂直于基底的方向，结合图1e可知，第一方向为图2a中箭头所指的方向。
在一些实施例中，步骤S1042的实施可以采用干法刻蚀工艺沿第一方向刻蚀牺牲层，形成空气夹层，例如反应离子刻蚀技术、等离子体刻蚀技术等。
本公开实施例中，通过采用干法刻蚀工艺，利用干法刻蚀的各向异性，刻蚀牺牲层，方便形成空气夹层。
步骤S1043：形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层，得到位于所述位线结构两侧壁具有空气夹层的绝缘结构，其中，所述绝缘结构包括依次堆叠的所述第二绝缘层、所述空气夹层、所述第三绝缘层和所述第四绝缘层。
这里，步骤S1043的实施可以采用沉积工艺在位线结构的上表面，第二绝缘层、空气夹层和第三绝缘层的表面形成第四绝缘层，例如物理气相沉积工艺、化学气相沉积工艺、低气压化学气相沉积工艺、分子层沉积工艺、等离子体增强化气相沉积工艺、原子层沉积工艺等。
其中，第四绝缘层采用的材料可以包括氧化物，例如氧化硅、氧化铝等。第四绝缘层采用的材料可以至少与第二绝缘层或第三绝缘层采用的材料相同，以使得第四绝缘层可以覆盖空气夹层表面的空隙。
如图2a中的图(3)所示，形成覆盖第三绝缘层201、空气夹层1061和第二绝缘层203的第四绝缘层205，即第四绝缘层205覆盖在第三绝缘层、空气夹层1061和第二绝缘层203的表面，得到位于位线结构104两侧壁具有空气夹层1061的绝缘结构106，其中，绝缘结构106包括依次堆叠的第二绝缘层203、空气夹层1061、第三绝缘层201和第四绝缘层205。
在一些实施例中，步骤S1043的实施可以包括：
步骤S1431：在所述位线结构的上表面，所述第二绝缘层、所述空气夹层和所述第三绝缘层的表面形成初始第四绝缘层；
这里，初始第四绝缘层采用的材料可以至少与第二绝缘层或第三绝缘层采用的材料相同，以使得初始第四绝缘层可以覆盖空气夹层表面的空隙。
如图2b中的图(1)所示，在位线结构104的上表面，第二绝缘层203、空气夹层1061和第三绝缘层201的表面形成初始第四绝缘层209。
步骤S1432：刻蚀位于所述位线结构顶部以上的所述初始第四绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层。
这里，步骤S1432的实施可以采用干法刻蚀工艺刻蚀位于位线结构顶部以上的初始第四绝缘层，例如反应离子刻蚀技术、等离子体刻蚀技术等。
结合图2b中的图(1)和图(2)，刻蚀位于位线结构104顶部以上的初始第四绝缘层209，形成如图2b中的图(2)所示的覆盖第三绝缘层201、空气夹层1061和第二绝缘层203的第四绝缘层205。
本公开实施例中，通过在位线结构的表面依次沉积形成第二绝缘层、牺牲层和第三绝缘层，再刻蚀中间的牺牲层，形成空气夹层，之后，在第二绝缘层、空气夹层和第三绝缘层的表面沉积第四绝缘层，覆盖空气夹层顶部暴露的空隙，形成具有空气夹层的绝缘结构。
在一些实施例中，步骤S1041的实施可以包括：
步骤S1411：在所述位线结构的表面依次形成初始第二绝缘层和初始牺牲层；
如图2c中的图(1)所示，在位线结构104的表面依次形成初始第二绝缘层206和初始牺牲层207。
这里，步骤S1411的实施可以采用沉积工艺依次在位线结构的表面形成初始第二绝缘层和初始牺牲层，例如物理气相沉积工艺、化学气相沉积工艺、低气压化学气相沉积工艺、分子层沉积工艺、等离子体增强化气相沉积工艺、原子层沉积工艺等。
其中，初始第二绝缘层采用的材料可以为氧化物，例如氧化硅、氧化铝等。初始牺牲层采用的材料可以包括多晶硅。
步骤S1412：刻蚀位于所述位线结构顶部以上的所述初始牺牲层，形成所述牺牲层；
结合图2c中的图(1)和图(2)，刻蚀位于位线结构104顶部以上的所述初始牺牲层207，形成如图2c中的图(2)所示的牺牲层202。
这里，步骤S1412的实施可以采用干法刻蚀工艺刻蚀位于位线结构顶部以上的初始牺牲层，例如反应离子刻蚀技术、等离子体刻蚀技术等。
步骤S1413：在所述初始第二绝缘层的表面和所述牺牲层的表面形成初始第三绝缘层；
如图2c中的图(3)所示，在初始第二绝缘层206的表面和牺牲层202的表面形成初始第三绝缘层208。
这里，步骤S1413的实施可以采用沉积工艺在初始第二绝缘层的表面和牺牲层的表面形成初始第三绝缘层，例如物理气相沉积工艺、化学气相沉积工艺、低气压化学气相沉积工艺、分子层沉积工艺、等离子体增强化气相沉积工艺、原子层沉积工艺等。
其中，初始第三绝缘层采用的材料可以包括氧化物，例如氧化硅、氧化铝等。初始第三绝缘层采用的材料可以和初始第二绝缘层采用的材料相同，也可以不同。
步骤S1414：刻蚀位于所述位线结构顶部以上的所述初始第三绝缘层和所述初始第二绝缘层，暴露出部分所述牺牲层的表面，形成位于所述位线结构的两侧壁依次形成的第二绝缘层、牺牲层和第三绝缘层。
结合图2c中的图(3)和图(4)，刻蚀位于位线结构104顶部以上的初始第三绝缘层208和初始第二绝缘层206，暴露出部分牺牲层202的表面，形成位于位线结构104的两侧壁依次形成的第二绝缘层203、牺牲层202和第三绝缘层201。
这里，步骤S1414的实施可以采用干法刻蚀工艺刻蚀位于位线结构顶部以上的初始第三绝缘层和初始第二绝缘层，例如反应离子刻蚀技术、等离子体刻蚀技术等。
本公开实施例还提供一种半导体结构的形成方法，如图3a所示，所述方法包括：
步骤S201至步骤S203可参见步骤S101至步骤S103。
步骤S204：在所述位线结构的表面依次形成初始第二绝缘层和初始牺牲层；
步骤S205：刻蚀位于所述位线结构顶部以上的所述初始牺牲层，形成所述牺牲层；
步骤S206：在所述初始第二绝缘层的表面和所述牺牲层的表面形成初始第三绝缘层；
步骤S207：刻蚀位于所述位线结构顶部以上的所述初始第三绝缘层和所述初始第二绝缘层，暴露出部分所述牺牲层的表面，形成位于所述位线结构的两侧壁依次形成的第二绝缘层、牺牲层和第三绝缘层。
这里，步骤S204至步骤S207可参见步骤S1411至步骤S1414。
步骤S208：沿第一方向刻蚀所述牺牲层，形成所述空气夹层，其中，所述第一方向为垂直于所述基底的方向；
这里，步骤S208可参见步骤S1042。
步骤S209：在所述位线结构的上表面，所述第二绝缘层、所述空气夹层和所述第三绝缘层的表面形成初始第四绝缘层；
步骤S210a：刻蚀位于所述位线结构顶部以上的所述初始第四绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层。
这里，步骤S209和步骤S210a分别参见步骤S1431和步骤S1432。
步骤S211a：在相邻所述第四绝缘层之间形成存储节点接触。
这里，存储节点接触可以包括掺杂杂质的多晶硅或未掺杂杂质的多晶硅。
如图3b所示，在相邻第四绝缘层205之间形成存储节点接触301。
在另一些实施例中，步骤S209之后，还包括步骤S210b至步骤S212b：
步骤S210b：在所述初始第四绝缘层表面形成第五绝缘层；
这里，第五绝缘层采用的材料可以包括氧化物，例如氧化硅、氧化铝等。第五绝缘层的材料可以和第四绝缘层的材料相同，也可以和第四绝缘层的材料不同。
如图3c所示，在初始第四绝缘层209表面形成第五绝缘层302。其中，初始第四绝缘层209的结构可参见图2b中的图(1)。
步骤S211b：刻蚀所述第五绝缘层、所述基底表面的所述初始第四绝缘层和部分所述基底，以暴露所述基底；
如图3d所示，采用干法刻蚀工艺刻蚀第五绝缘层302、基底101表面的初始第四绝缘层209和部分基底101，以暴露基底101，即图3d中基底上的空白区域303。
步骤S212b：刻蚀位于所述位线结构上表面以上的所述初始第四绝缘层和所述第五绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层。
步骤S213b：在相邻所述第四绝缘层之间形成存储节点接触。
本公开实施例中，通过在初始第四绝缘层表面形成第五绝缘层，然后再刻蚀第五绝缘层、基底表面的初始第四绝缘层和部分基底，利用第五绝缘层保护第四绝缘层，降低了在刻蚀过程中，刻蚀掉位线结构表面的第四绝缘层的风险，从而保护绝缘结构。
本公开实施例还提供一种半导体结构的形成方法，在步骤S211a或步骤S213b之后，所述方法包括：
步骤S301：在所述绝缘结构的表面、所述存储节点接触的表面和所述位线结构的表面形成金属层；
这里，金属层采用的材料可以是导电材料，例如钨(W)。采用等离子体增强化学的气相沉积工艺(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积导电材料，降低在填充时出现空洞的可能。在一些实施例中，也可以采用化学气相沉积工艺、低气压化学气相沉积工艺、原子层沉积等合适工艺沉积导电材料。
步骤S301可以参考图4a，在绝缘结构106的表面、存储节点接触301的表面和位线结构104的上表面形成金属层401。
步骤S302：刻蚀部分所述金属层，形成第一开口，以暴露出位于所述位线结构第一侧壁的绝缘结构的部分表面；
其中，刻蚀后剩余的所述金属层形成与所述存储节点接触电连接的着落垫，所述着落垫覆盖所述存储节点接触的表面、所述位线结构第二侧壁的绝缘结构的表面和所述位线结构的上表面。
这里，可以采用干法刻蚀工艺或者湿法刻蚀工艺选择性地刻蚀金属层，蚀刻气体可以是溴化氢(HBr)/氯气(Cl 2)。着落垫的作用是将存储节点接触与电容电连接。
步骤S302可以参考图4b和4a，如图4a，刻蚀部分金属层401，形成如图4b所示的第一开口402，暴露出位于位线结构104第一侧壁B的绝缘结构106的部分表面。
刻蚀后剩余的金属层形成与存储节点接触301电连接的着落垫403，着落垫403覆盖存储节点接触301的表面、位线结构第二侧壁A的绝缘结构106的表面和位线结构104的上表面。
步骤S303a、在相邻所述着落垫之间和所述着落垫的表面形成隔离结构。
这里，隔离结构的材料可以是硅氧化物、硅氮化物(例如氮化硅(Si 3N 4))或者硅氮氧化物等。
步骤S303a可以参考图4c，在相邻着落垫403之间和着落垫403的表面形成隔离结构404。
在一些实施例中，隔离结构包括第一填充层和第二填充层，对应地，步骤S303a“所述在相邻所述着落垫之间和所述着落垫的表面形成隔离结构”的实施包括步骤S33a1和步骤S33a2，其中：
步骤S33a1：在所述位线结构第一侧壁的绝缘结构和所述着落垫的表面沉积第一填充层；
这里，步骤S33a1可以参考图4d，在位线结构104第一侧壁B的绝缘结构106和着落垫403的表面沉积第一填充层4042。
在一些实施例中，第一填充层采用的材料可以和绝缘结构中的第二绝缘层、第三绝缘层或第四绝缘层中的至少一种采用的材料相同，也可以和绝缘结构中的第二绝缘层、第三绝缘层和第四绝缘层采用的材料不同。
步骤S33a2：在所述第一填充层的表面沉积第二填充层。
这里，步骤S33a2可以参考图4d，在第一填充层4042的表面沉积第二填充层4041，第二填充层的材料可以与第一填充层的材料相同或不同。
本公开实施例中，通过在绝缘结构的表面、存储节点接触的表面和位线结构的表面形成金属层，然后刻蚀部分金属层，形成第一开口，暴露出位于位线结构第一侧壁的绝缘结构的部分表面，形成着落垫，再在相邻着落垫之间和着落垫的表面形成隔离结构，形成相互隔离的着落垫，实现在绝缘结构具有空气夹层的情况下，使得NC通过相互隔离的着落垫连接到半导体结构中的其他部分。
本公开实施例提供一种半导体结构，如图4d所示，所述结构包括：
基底101；
位于基底101上的间隔排布的位线接触孔(第一绝缘层105所在的孔)、与位线接触孔部分接触的位线接触103以及位线结构104，其中，位线结构104至少包括导电层1042和绝缘盖帽层1041；绝缘盖帽层1041位于导电层1042上；
位于位线接触孔内的填满位线接触孔的第一绝缘层105；
位于位线结构104两侧壁的具有空气夹层1061的绝缘结构106，其中，空气夹层1061的高度大于位线结构104中导电层1042的高度，绝缘结构106包括依次堆叠的第二绝缘层203、空气夹层1061、第三绝缘层和第四绝缘层205，其中，第四绝缘层205覆盖第三绝缘层、空气夹层1061和第二绝缘层203。这里，绝缘结构106可参见图2b中的图(2)进行理解。
位于相邻第四绝缘层205之间的存储节点接触301；
覆盖存储节点接触301、第二侧壁A的绝缘结构106和位线结构104上表面的着落垫403， 着落垫403与存储节点接触301电连接。
位于相邻着落垫403之间和着落垫403的表面的隔离结构404。
在一些实施例中，隔离结构404包括第一填充层4042和第二填充层4041，第一填充层4042位于位线结构104第一侧壁B的绝缘结构106和着落垫403的表面，第二填充层4041位于第一填充层4042的表面。
本公开实施例还提供一种半导体结构的形成方法，在步骤S302之后，所述方法还包括：
步骤S303b：沿所述第一方向继续刻蚀所述第一开口，刻蚀停止位置的高度高于所述位线结构中导电层的高度，形成第二开口；其中，靠近所述第一侧壁的空气夹层为具有第一高度的第一空气夹层，靠近所述第二侧壁的空气夹层为具有第二高度的第二空气夹层，且所述第一高度小于所述第二高度。
步骤S303b可以参考图4e和图4b，如图4b所示，第一方向为垂直于基底101的方向，即图中箭头所指的方向，沿第一方向继续刻蚀第一开口402，刻蚀停止位置的高度高于位线结构104中导电层1042的高度，形成如图4e所示第二开口405；其中，靠近第一侧壁B的空气夹层为具有第一高度h1的第一空气夹层407，靠近第二侧壁A的空气夹层为具有第二高度h2的第二空气夹层406，第一侧壁B为图4e中所有位线结构104的右侧壁，第二侧壁A为图4e中所有位线结构104的左侧壁，即靠近位线结构104右侧壁的空气夹层为具有第一高度h1的第一空气夹层407，靠近位线结构104左侧壁的空气夹层为具有第二高度h2的第二空气夹层406，且第一高度h1小于第二高度h2。
步骤S304b：在相邻所述着落垫之间和所述着落垫的表面形成隔离结构。
步骤S304b可以参考图4f，在相邻着落垫403之间和着落垫403的表面形成隔离结构404。
在一些实施例中，隔离结构包括第一填充层和第二填充层，对应地，步骤S304b“所述在相邻所述着落垫之间和所述着落垫的表面形成隔离结构”的实施包括步骤S34b1和步骤S34b2，其中：
步骤S34b1：在所述位线结构第一侧壁的绝缘结构和所述着落垫的表面沉积第一填充层；
这里，步骤S34b1可以参考图4g，在位线结构104第一侧壁B的绝缘结构106和着落垫403的表面沉积第一填充层4042。
在一些实施例中，第一填充层采用的材料可以和绝缘结构106中的第二绝缘层、第三绝缘层或第四绝缘层中的至少一种采用的材料相同，以封闭第一空气夹层407的开口，形成密闭的第一空气夹层407。
步骤S34b2：在所述第一填充层的表面沉积第二填充层。
这里，步骤S34b2可以参考图4g，在第一填充层4042的表面沉积第二填充层4041，第二填充层的材料可以与第一填充层的材料相同或不同。
本公开实施例中的隔离结构包括第一填充层和第二填充层，通过利用隔离结构中的第一填充层封闭第一空气夹层的开口，形成密闭的第一空气夹层，再在第一填充层的表面沉积第二填充层，形成隔离结构，得到高低不同的第一空气夹层和第二空气夹层，由于第一空气夹层的高度高于位线结构中导电层的高度，起到降低NC与BL之间寄生电容的作用；同时，由于第一空气夹层的高度低于第二空气夹层的高度，相比于第一空气夹层与第二空气夹层高度相同的情况，留出一部分空间给着落垫，使得着落垫的厚度更大，从而降低了着落垫的电阻，增强了着落垫的导电性。
本公开实施例提供一种半导体结构，如图4g所示，所述结构包括：
基底101；
位于基底101上的间隔排布的位线接触孔(第一绝缘层105所在的孔)、与位线接触孔部分接触的位线接触103以及位线结构104，其中，位线结构104至少包括导电层1042和绝缘盖帽层1041；绝缘盖帽层1041位于导电层1042上；
位于位线接触孔内的填满位线接触孔的第一绝缘层105；
位于位线结构104两侧壁的具有空气夹层1061的绝缘结构106，其中，空气夹层1061的高度大于位线结构104中导电层1042的高度，绝缘结构106包括依次堆叠的第二绝缘层203、空气夹层1061、第三绝缘层和第四绝缘层205，其中，第四绝缘层205覆盖第三绝缘层、空气夹层1061和第二绝缘层203。这里，绝缘结构106可参见图2b中的图(2)进行理解。
在一些实施例中，空气夹层包括具有第一高度h1的第一空气夹层407和具有第二高度h2的第二空气夹层406，其中，第一空气夹层406靠近位线结构104的第一侧壁B，第二空气夹层406靠近位线结构104的第二侧壁A，第一高度h1小于第二高度h2。
位于相邻第四绝缘层205之间的存储节点接触301；
覆盖存储节点接触301、第二侧壁A的绝缘结构106和位线结构104上表面的着落垫403，着落垫403与存储节点接触301电连接。
位于相邻着落垫403之间和着落垫403的表面的隔离结构404。
在一些实施例中，隔离结构404包括第一填充层4042和第二填充层4041，第一填充层4042位于位线结构104第一侧壁B的绝缘结构106和着落垫403的表面，第二填充层4041位于第一填充层4042的表面。
本公开所提供的几个方法或结构实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或结构实施例。
以上半导体结构实施例的描述，与上述方法实施例的描述是类似的，具有同方法实施例相似的有益效果。对于本公开半导体结构实施例中未披露的技术细节，请参照本公开方法实施例的描述而理解。
以上所述，仅为本公开的示例性的实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例提供一种半导体结构及其形成方法，包括：提供基底；在所述基底上形成间隔排布的位线接触孔、与所述位线接触孔部分接触的位线接触以及位线结构，其中，所述位线结构至少包括导电层和绝缘盖帽层；所述绝缘盖帽层位于所述导电层上；在所述位线接触孔内形成填满所述位线接触孔的第一绝缘层；在所述位线结构的两侧壁形成具有空气夹层的绝缘结构，其中，所述空气夹层的高度大于所述位线结构中导电层的高度。
本公开实施例中，通过在基底上形成间隔排布的位线接触孔、与位线接触孔部分接触的位线接触以及位线结构；在位线接触孔内形成填满位线接触孔的第一绝缘层；在位线结构的两侧壁形成具有空气夹层的绝缘结构，其中，空气夹层的高度大于位线结构中导电层的高度，提供了一种新的位线结构侧墙即具有空气夹层的绝缘结构的形成方法。由于具有空气夹层的绝缘结构位于BL和NC之间，而空气夹层的介电常数相比于没有空气夹层的绝缘结构中的绝缘层的介电常数小，因此，降低了NC与BL之间的寄生电容，提高了存储器的读出容量。

Claims (19)

  1. 一种半导体结构的形成方法，包括：
    提供基底；
    在所述基底上形成间隔排布的位线接触孔、与所述位线接触孔部分接触的位线接触以及位线结构，其中，所述位线结构至少包括导电层和绝缘盖帽层；所述绝缘盖帽层位于所述导电层上；
    在所述位线接触孔内形成填满所述位线接触孔的第一绝缘层；
    在所述位线结构的两侧壁形成具有空气夹层的绝缘结构，其中，所述空气夹层的高度大于所述位线结构中导电层的高度。
  2. 根据权利要求1所述的形成方法，其中，在所述位线结构的两侧壁形成具有空气夹层的绝缘结构，包括：
    在所述位线结构的两侧壁依次形成第二绝缘层、牺牲层和第三绝缘层，暴露出部分所述牺牲层的表面；
    沿第一方向刻蚀所述牺牲层，形成所述空气夹层，其中，所述第一方向为垂直于所述基底的方向；
    形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层，得到位于所述位线结构两侧壁具有空气夹层的绝缘结构，其中，所述绝缘结构包括依次堆叠的所述第二绝缘层、所述空气夹层、所述第三绝缘层和所述第四绝缘层。
  3. 根据权利要求2所述的形成方法，其中，所述沿第一方向刻蚀所述牺牲层，形成所述空气夹层，包括：
    采用干法刻蚀工艺沿第一方向刻蚀所述牺牲层，形成所述空气夹层。
  4. 根据权利要求2所述的形成方法，其中，在所述位线结构的两侧壁依次形成第二绝缘层、牺牲层和第三绝缘层，暴露出部分所述牺牲层的表面，包括：
    在所述位线结构的表面依次形成初始第二绝缘层和初始牺牲层；
    刻蚀位于所述位线结构顶部以上的所述初始牺牲层，形成所述牺牲层；
    在所述初始第二绝缘层的表面和所述牺牲层的表面形成初始第三绝缘层；
    刻蚀位于所述位线结构顶部以上的所述初始第三绝缘层和所述初始第二绝缘层，暴露出部分所述牺牲层的表面，形成位于所述位线结构的两侧壁依次形成的第二绝缘层、牺牲层和第三绝缘层。
  5. 根据权利要求2所述的形成方法，其中，所述形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层，包括：
    在所述位线结构的上表面，所述第二绝缘层、所述空气夹层和所述第三绝缘层的表面形成初始第四绝缘层；
    刻蚀位于所述位线结构顶部以上的所述初始第四绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层。
  6. 根据权利要求5所述的形成方法，其中，在形成所述第四绝缘层之后，还包括：
    在相邻所述第四绝缘层之间形成存储节点接触。
  7. 根据权利要求6所述的形成方法，还包括：
    在所述绝缘结构的表面、所述存储节点接触的表面和所述位线结构的上表面形成金属层；
    刻蚀部分所述金属层，形成第一开口，以暴露出位于所述位线结构第一侧壁的绝缘结构的部分表面；
    其中，刻蚀后剩余的所述金属层形成与所述存储节点接触电连接的着落垫，所述着落垫覆盖所述存储节点接触的表面、所述位线结构第二侧壁的绝缘结构的表面和所述位线结构的上表面。
  8. 根据权利要求7所述的形成方法，还包括：
    沿所述第一方向继续刻蚀所述第一开口，刻蚀停止位置的高度高于所述位线结构中导电层的高度，形成第二开口；其中，靠近所述第一侧壁的空气夹层为具有第一高度的第一空气夹层，靠近所述第二侧壁的空气夹层为具有第二高度的第二空气夹层，且所述第一高度小于所述第二高度。
  9. 根据权利要求7或8所述的形成方法，还包括：
    在相邻所述着落垫之间和所述着落垫的表面形成隔离结构。
  10. 根据权利要求9所述的形成方法，其中，所述隔离结构包括第一填充层和第二填充层，所述在相邻所述着落垫之间和所述着落垫的表面形成隔离结构，包括：
    在所述位线结构第一侧壁的绝缘结构和所述着落垫的表面沉积第一填充层；
    在所述第一填充层的表面沉积第二填充层。
  11. 根据权利要求6所述的形成方法，其中，在相邻所述第四绝缘层之间形成存储节点接触之前，还包括：
    在所述初始第四绝缘层表面形成第五绝缘层；
    刻蚀所述第五绝缘层、所述基底表面的所述初始第四绝缘层和部分所述基底，以暴露所述基底；
    对应地，所述刻蚀位于所述位线结构顶部以上的所述初始第四绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层，包括：
    刻蚀位于所述位线结构上表面以上的所述初始第四绝缘层和所述第五绝缘层，形成覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层的第四绝缘层。
  12. 根据权利要求2至11任一项所述的形成方法，其中，
    所述第一绝缘层的材料包括氮化物；
    所述第二绝缘层、所述第三绝缘层和所述第四绝缘层的材料包括氧化物。
  13. 根据权利要求2至11任一项所述的形成方法，其中，所述牺牲层的材料包括硅。
  14. 一种半导体结构，包括：
    基底；
    位于所述基底上的间隔排布的位线接触孔、与所述位线接触孔部分接触的位线接触以及位线结构，其中，所述位线结构至少包括导电层和绝缘盖帽层；所述绝缘盖帽层位于所述导电层上；
    位于所述位线接触孔内的填满所述位线接触孔的第一绝缘层；
    位于所述位线结构两侧壁的具有空气夹层的绝缘结构，其中，所述空气夹层的高度大于所述位线结构中导电层的高度。
  15. 根据权利要求14所述的半导体结构，其中，
    所述绝缘结构包括依次堆叠的第二绝缘层、空气夹层、第三绝缘层和第四绝缘层，其中，所述第四绝缘层覆盖所述第三绝缘层、所述空气夹层和所述第二绝缘层。
  16. 根据权利要求15所述的半导体结构，其中，
    所述空气夹层包括具有第一高度的第一空气夹层和具有第二高度的第二空气夹层，其中，所述第一空气夹层靠近所述位线结构的第一侧壁，所述第二空气夹层靠近所述位线结构的第二侧壁，所述第一高度小于所述第二高度。
  17. 根据权利要求16所述的半导体结构，还包括：
    位于相邻所述第四绝缘层之间的存储节点接触；
    覆盖所述存储节点接触、所述第二侧壁的绝缘结构和所述位线结构上表面的着落垫，所述着落垫与所述存储节点接触电连接。
  18. 根据权利要求17所述的半导体结构，还包括：
    位于相邻所述着落垫之间和所述着落垫的表面的隔离结构。
  19. 根据权利要求18所述的半导体结构，其中，所述隔离结构包括第一填充层和第二填充层，所述第一填充层位于所述位线结构第一侧壁的绝缘结构和所述着落垫的表面，所述第二填充层位于所述第一填充层的表面。
PCT/CN2022/094114 2021-12-21 2022-05-20 半导体结构及其形成方法 Ceased WO2023115803A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108206184A (zh) * 2016-12-19 2018-06-26 三星电子株式会社 半导体存储器件
CN110718502A (zh) * 2018-07-13 2020-01-21 爱思开海力士有限公司 具有气隙的半导体器件以及用于制造其的方法
CN111354711A (zh) * 2018-12-24 2020-06-30 三星电子株式会社 半导体存储器装置及其制造方法
CN113690219A (zh) * 2020-05-18 2021-11-23 中国科学院微电子研究所 一种半导体器件及其制作方法、电子设备

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102226159B1 (ko) * 2013-11-07 2021-03-11 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
KR102238951B1 (ko) * 2014-07-25 2021-04-12 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
CN108573926B (zh) * 2017-03-09 2020-01-21 联华电子股份有限公司 半导体存储装置以及其制作方法
CN110875314B (zh) * 2018-08-30 2024-09-13 长鑫存储技术有限公司 位线结构及其制备方法、存储器
CN112447604B (zh) * 2019-08-30 2022-06-10 长鑫存储技术有限公司 存储器及其形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108206184A (zh) * 2016-12-19 2018-06-26 三星电子株式会社 半导体存储器件
CN110718502A (zh) * 2018-07-13 2020-01-21 爱思开海力士有限公司 具有气隙的半导体器件以及用于制造其的方法
CN111354711A (zh) * 2018-12-24 2020-06-30 三星电子株式会社 半导体存储器装置及其制造方法
CN113690219A (zh) * 2020-05-18 2021-11-23 中国科学院微电子研究所 一种半导体器件及其制作方法、电子设备

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