WO2023115666A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2023115666A1
WO2023115666A1 PCT/CN2022/071228 CN2022071228W WO2023115666A1 WO 2023115666 A1 WO2023115666 A1 WO 2023115666A1 CN 2022071228 W CN2022071228 W CN 2022071228W WO 2023115666 A1 WO2023115666 A1 WO 2023115666A1
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sub
pad
groove
substrate
semiconductor structure
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PCT/CN2022/071228
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English (en)
French (fr)
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陈小璇
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长鑫存储技术有限公司
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Priority to US17/806,264 priority Critical patent/US20230197589A1/en
Publication of WO2023115666A1 publication Critical patent/WO2023115666A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof.
  • the semiconductor structure includes a substrate and one or more chips on the substrate.
  • the surface of the substrate is provided with pads, and the chips are electrically connected to the pads on the surface of the substrate through bonding wires.
  • An embodiment of the present disclosure provides a semiconductor structure, including:
  • An adapter plate is located on the substrate, and the bottom surface of the adapter plate covers the first welding pad; wherein, the adapter plate includes a second welding pad and a connection structure; the second welding pad is located on On any surface of the adapter board except the bottom surface; one end of the connection structure is connected to the first welding pad, and the other end of the connection structure is connected to the second welding pad.
  • the adapter board further includes: a sealing layer, the bottom of the sealing layer covers the first welding pad, and the second welding pad is located on a side surface of the sealing layer.
  • connection structure is located within the sealing layer.
  • the second pad includes a plurality of second sub-pad groups with different heights, and each of the second sub-pad groups includes a plurality of second sub-pads arranged and distributed along the first direction .
  • the first pad includes one or more first sub-pad groups, and the first sub-pad group includes a plurality of first sub-pads arranged and distributed along the first direction.
  • the distance between two adjacent first sub-pads in the first sub-pad group along the first direction is smaller than that in the second sub-pad group along the first direction.
  • connection structure includes a plurality of sub-connection structures; wherein the sub-connection structures have different heights.
  • connection structure includes a plurality of sub-connection structures arranged and distributed along the first direction; wherein, two adjacent sub-connection structures have different heights.
  • the sub-connection structure includes a first connection sub-portion and a second connection sub-portion extending in different directions and connected to each other; the first connection sub-portion is connected to the first pad, the The second connection subsection is connected to the second welding pad.
  • the extending direction of the first connecting sub-portion is perpendicular to the substrate, and the extending direction of the second connecting sub-portion is parallel to the substrate.
  • the semiconductor structure further includes: one or more chips disposed on the substrate, the surface of the chip has a pad, and the pad is connected to the second sub-substrate through a bonding wire.
  • the pad groups are electrically connected.
  • the plurality of chips includes two chips stacked on each other, and the plurality of second sub-pad groups includes two second sub-pad groups with different heights; wherein, the two Among the chips, the upper chip is electrically connected to the upper second sub-pad group of the two second sub-pad groups, and the lower chip of the two chips is electrically connected to the two second sub-pad groups.
  • the second sub-pad group located below is electrically connected.
  • the semiconductor structure further includes: an encapsulation layer covering at least the chip and the interposer.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including:
  • the surface of the substrate has a first pad
  • an adapter plate on the substrate including: forming a connection structure and a second pad, the second pad being located on any surface of the adapter plate except the bottom surface;
  • connection structure One end of the connection structure is connected to the first pad, and the other end of the connection structure is connected to the second pad.
  • forming the interposer board on the substrate further includes: forming a sealing layer on the substrate, the sealing layer covering the connecting structure, and making the second welding pad the side surface of the sealing layer.
  • connection structure and the second pad includes:
  • the sacrificial layer is removed.
  • the groove includes a plurality of sub-grooves uniformly arranged and distributed along the first direction, and each of the sub-grooves includes a first groove sub-section, a second groove sub-section and a third groove sub-section connected in sequence.
  • the groove subsection; etching the sacrificial layer includes: etching downward from the top surface of the sacrificial layer to form the first groove subsection, the first groove subsection exposing the first pad;
  • the vertical depth of the second groove subsection is smaller than the vertical depth of the first groove subsection
  • the depth of the third groove sub-section along the vertical direction is greater than the depth of the second groove sub-section along the vertical direction and less than The depth of the first groove subsection along the vertical direction.
  • the second groove subsections in the adjacent sub-grooves along the first direction have different depths in the vertical direction, and the adjacent sub-grooves along the first direction Said third groove subsections in the groove have different depths in the vertical direction.
  • filling the groove with a conductive material to form the connection structure and the second pad includes:
  • the method further includes: fixing at least one chip on the substrate, the surface of the chip has a bonding pad; using a bonding wire to electrically connect the bonding pad to the second bonding pad .
  • the sealing layer is formed using a molding process.
  • the semiconductor structure includes: a substrate having a first pad; an interposer located on the substrate, and the interposer The bottom surface of the adapter board covers the first pad; wherein, the adapter board includes a second pad and a connection structure; the second pad is located on any surface of the adapter board except the bottom surface; the One end of the connection structure is connected to the first pad, and the other end of the connection structure is connected to the second pad.
  • the first welding pad located on the substrate is led out to any surface of the interposer board except the bottom surface through the connection structure to form the second welding pad.
  • the adapter plate is located above the substrate, and its side surface has a relatively large area, so that the arrangement density of the second pads can be smaller than that of the first pads, and the adjacent pads can be reduced during wiring.
  • the semiconductor structure provided by the embodiments of the present disclosure can have a smaller substrate size, a larger number of pads, and a lower arrangement density of the pads.
  • the presence of the adapter plate can also shorten the length of the bonding wire, thereby reducing heat generation and signal attenuation.
  • FIG. 1a is a perspective view of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 1b is a schematic cross-sectional structure diagram taken along line AA' of FIG. 1a
  • FIG. 1c is a perspective view of the first pad and connection structure in FIG. 1a;
  • FIG. 2a is a perspective view of a semiconductor structure provided by another embodiment of the present disclosure
  • FIG. 2b is a schematic cross-sectional structure diagram taken along line AA' of FIG. 2a;
  • FIG. 3a is a perspective view of a semiconductor structure provided by another embodiment of the present disclosure
  • FIG. 3b is a schematic cross-sectional structure diagram taken along line AA' of FIG. 3a;
  • FIG. 4 is a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 5a to 10b are process flow charts of the semiconductor structure provided by the embodiments of the present disclosure.
  • the semiconductor structure includes a substrate and one or more chips on the substrate.
  • the surface of the substrate is provided with pads, and the chips are electrically connected to the pads on the surface of the substrate through bonding wires.
  • An embodiment of the present disclosure provides a semiconductor structure, including: a substrate having a first pad; an interposer located on the substrate, the bottom surface of the interposer covering the first welding pad; wherein, the adapter board includes a second welding pad and a connection structure; the second welding pad is located on any surface of the adapter board except the bottom surface; one end of the connection structure is connected to the first A welding pad is connected, and the other end of the connection structure is connected to the second welding pad.
  • the first welding pad located on the substrate is led out to any surface of the interposer board except the bottom surface through the connection structure to form the second welding pad.
  • the adapter plate is located above the substrate, and its side surface has a relatively large area, so that the arrangement density of the second pads can be smaller than that of the first pads, and the adjacent pads can be reduced during wiring. The possibility of short circuits between the second pads and between adjacent bond wires.
  • the semiconductor structure provided by the embodiments of the present disclosure can have a smaller substrate size, a larger number of pads, and a lower arrangement density of the pads.
  • the presence of the adapter plate can also shorten the length of the bonding wire, thereby reducing heat generation and signal attenuation.
  • Figures 1a, 2a, and 3a are perspective views of semiconductor structures provided by embodiments of the present disclosure
  • Figures 1b, 2b, and 3b are cross-sectional structures taken along the line AA' of Figures 1a, 2a, and 3a, respectively.
  • Schematic diagram, FIG. 1c is a perspective view of the first pad and connection structure in FIG. 1a.
  • the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to FIGS. 1 a to 3 b.
  • the semiconductor structure includes: a substrate 10, the substrate 10 has a first pad P1; an interposer 16, located on the substrate 10, the interposer 16
  • the bottom surface of the adapter board 16 covers the first welding pad P1; wherein, the adapter board 16 includes a second welding pad P2 and a connection structure L; the second welding pad P2 is located on the adapter board 16 except the bottom surface
  • one end of the connection structure L is connected to the first pad P1, and the other end of the connection structure L is connected to the second pad P2.
  • the substrate 10 may be a rigid printed circuit board, a flexible printed circuit board, a rigid-flexible printed circuit board, or any combination thereof.
  • the substrate 10 is a multi-layer circuit board with various circuit components inside.
  • the surface of the substrate 10 includes an insulating layer (not shown), the first pad P1 is located in the insulating layer (not shown), and the first pad The upper surface of P1 is flush with the upper surface of the insulating layer (not shown).
  • the material of the first pad P1 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, conductive carbon, or any combination thereof.
  • the material of the insulating layer (not shown) may be solder resist.
  • the adapter board 16 further includes: a sealing layer 15, the bottom of the sealing layer 15 covers the first welding pad P1, and the second welding pad P2 is located on the side of the sealing layer 15. surface. But not limited thereto, in other embodiments, the second welding pad P2 may also be located on the top surface of the sealing layer 15 .
  • the sealing layer 15 is made of insulating material, such as epoxy molding compound.
  • the material of the second pad P2 may be the same as or different from that of the first pad P1.
  • the material of the second pad P2 may include metal, metal nitride, metal silicide, metal alloy, conductive carbon or any combination thereof.
  • the second pad P2 includes a plurality of second sub-pad groups P20 with different heights, and each of the second sub-pad groups P20 includes a plurality of second pad groups arranged and distributed along the first direction. sub-pad 14.
  • the first direction is parallel to the surface of the substrate 10 .
  • a plurality of the second sub-pad groups P20 are exposed on the side surface of the sealing layer 15 , and are arranged and distributed along a direction perpendicular to the substrate 10 .
  • the first pad P1 includes at least one first sub-pad group P10, and the first sub-pad group P10 includes a plurality of The first sub-pad 11 .
  • the distance between two adjacent first sub-pads 11 in the first sub-pad group P10 along the first direction is smaller than the distance between the second sub-pad group P20 The distance between two adjacent second sub-pads 14 along the first direction.
  • the arrangement of the second sub-pads 14 is sparser than that of the first sub-pads 11 .
  • first sub-pads 11 and the second sub-pads 14 have a one-to-one correspondence, the reason why two adjacent second sub-pads 14 in the first direction The distance between them is greater than the distance between two adjacent first sub-pads 11, because each first sub-pad group P10 corresponds to a plurality of second sub-pad groups P20 with different heights, thus, in The number of second sub-pads 14 in each second sub-pad group P20 is less than the number of first sub-pads 11 in each first sub-pad group P10, therefore, each second sub-pad group The distance between adjacent second sub-pads 14 in P20 is greater than the distance between adjacent first sub-pads 11 in each first sub-pad group P10.
  • each of the first sub-pad groups P10 corresponds to two of the second sub-pad groups P20 with different heights. But not limited thereto, each of the first sub-pad groups P10 may also correspond to more second sub-pad groups P20 with different heights, for example, 3, 4 or 5 sub-groups.
  • Each riser board 16 shown in FIGS. 1 a to 1 c covers a group of the first sub-pad group P10 . But not limited thereto, as shown in Figure 2a to Figure 2b, in another embodiment, each adapter board 16 covers multiple groups of the first sub-pad groups P10, the multiple groups of the first sub-pad groups The groups P10 are arranged and distributed along the second direction on the substrate 10 . In a specific embodiment, the second direction is perpendicular to the first direction.
  • the number of the first sub-pad group and the number of the second sub-pad group are not limited to those shown in FIGS.
  • the number of sub-pad groups can be more or less.
  • connection structure L is located in the sealing layer 15, the second pad P2 and the first pad P1 are connected one by one through the connection structure L, and the connection structure L
  • the arrangement is the same as that of the first welding pads P1, and the height of the connection structure L determines the height of the second welding pads P2.
  • the connection structure L includes a plurality of sub-connection structures 13; wherein, the sub-connection structures 13 have different heights.
  • the connection structure L includes a plurality of sub-connection structures 13 arranged and distributed along the first direction; wherein, two adjacent sub-connection structures 13 have different heights.
  • the sub-connection structure 13 includes a first connection sub-portion 131 and a second connection sub-portion 132 extending in different directions and connected to each other; the first connection sub-portion 131 and the first pad P1 is connected, and the second connection sub-portion 132 is connected to the second pad P2.
  • the extending direction of the first connecting sub-portion 131 is perpendicular to the substrate 10
  • the extending direction of the second connecting sub-portion 132 is parallel to the substrate 10 .
  • the first connecting sub-portion 131 and the second connecting sub-portion 132 can be formed simultaneously or sequentially; the materials of the first connecting sub-portion 131 and the second connecting sub-portion 132 can include metal, Metal nitrides, metal suicides, metal alloys, conductive carbon, or any combination thereof.
  • the materials of the first pad P1, the connection structure L, and the second pad P2 are the same, for example, copper (Cu).
  • the semiconductor structure further includes: one or more chips C disposed on the substrate 10, the surface of the chip C has a pad 18, and the pad 18 passes through a bonding wire 19 It is electrically connected with the second sub-pad group P20.
  • the chip C may be a memory, such as a dynamic random access memory (DRAM).
  • the bonding wire 19 is used to conduct signals, and its material may be metal, such as gold (Au).
  • the number of chips C disposed on the substrate 10 is multiple, and the side surfaces of a plurality of chips C are aligned in a direction perpendicular to the substrate 10, as shown in Fig. 1a to Fig. 2b.
  • two adjacent chips C may be offset from each other by a predetermined distance, as shown in FIGS. 3 a to 3 b.
  • the plurality of chips C include two chips C1 and C2 stacked on each other, and the plurality of second sub-pad groups P20 include two chips C1 and C2 with different heights.
  • the two stacked chips C1 and C2 can also be electrically connected to two second sub-pad groups P20 with the same height, wherein the two second sub-pad groups P20
  • the welding pad groups P20 are respectively located on the side surfaces of the two adapter plates 16 , as shown in FIGS. 3 a to 3 b .
  • the chip C further includes an adhesive layer 17, and the adhesive layer 17 is located on the lower surface of the chip C for sequentially bonding one or more chips C to the substrate.
  • the adhesive layer 17 includes an adhesive film, for example, a direct adhesive film (DAF).
  • DAF direct adhesive film
  • the number of the riser boards 16 is multiple, and the multiple riser boards 16 are arranged around the one or more chips C. As shown in FIG. 1 a to FIG. 1 b , in some embodiments, the number of the riser boards 16 is two, and the two riser boards 16 are located on two sides of the one or more chips C respectively. But not limited thereto, the number of adapter plates 16 can be more or less, for example, 1, 3 or 4.
  • the semiconductor structure further includes: an encapsulation layer (not shown), and the encapsulation layer (not shown) covers at least the chip C and the interposer 16 . It can be understood that the encapsulation layer (not shown) also covers the bonding wire 19 and part of the surface of the substrate 10 .
  • the first pad P1 located on the substrate 10 is led out to any surface of the interposer 16 except the bottom surface through the connection structure L to form the second pad P2.
  • the adapter board 16 is located above the substrate 10, and its side surface has a relatively large area, so that the arrangement density of the second pads P2 can be smaller than that of the first pads P1.
  • the possibility of short circuit between adjacent second pads P2 and between adjacent bonding wires 19 can be reduced.
  • the semiconductor structure provided by the embodiments of the present disclosure can have a smaller substrate size, a larger number of pads, and a lower arrangement density of the pads.
  • the existence of the adapter plate 16 can also shorten the length of the bonding wire 19, thereby reducing heat generation and signal attenuation.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, as shown in FIG. 4 , the method includes the following steps:
  • Step 401 providing a substrate, the surface of the substrate has a first pad
  • Step 402 forming an adapter board on the substrate, including: forming a connection structure and a second pad, and the second pad is located on any surface of the adapter board except the bottom surface; the connection structure One end of the connection structure is connected to the first pad, and the other end of the connection structure is connected to the second pad.
  • FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. 9a, and FIG. 10a are perspective views of the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure in different process steps
  • FIG. 5b, FIG. 6b, FIG. 7b, and FIG. 8b, FIG. 9b, and FIG. 10b are schematic cross-sectional structure diagrams taken along the line AA' of FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. 9a, and FIG. 10a, respectively.
  • step 401 is performed to provide a substrate 10 having a first pad P1 on its surface, as shown in FIGS. 5 a to 5 b .
  • the substrate 10 may be a rigid printed circuit board, a flexible printed circuit board, a rigid-flexible printed circuit board, or any combination thereof.
  • the substrate 10 is a multi-layer circuit board with various circuit components inside.
  • the surface of the substrate 10 includes an insulating layer (not shown), the first pad P1 is located in the insulating layer (not shown), and the first pad The upper surface of P1 is flush with the upper surface of the insulating layer (not shown).
  • the material of the first pad P1 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, conductive carbon, or any combination thereof.
  • the material of the insulating layer (not shown) may be solder resist.
  • the first pad P1 includes at least one first sub-pad group P10, and the first sub-pad group P10 includes a plurality of first sub-pads 11 arranged and distributed along a first direction.
  • the number of the first sub-pad groups P10 shown in FIGS. 5a-5b is two, and subsequently two adapter plates 16 will be respectively formed on the two first sub-pad groups P10 (see FIG. 10a Referring to FIG. 10 b ), that is, each adapter plate 16 covers one of the first sub-pad groups P10. But not limited thereto, the number of the first sub-pad group P10 can also be more, and the number of the first sub-pad group P10 covered by each adapter plate 16 can also be more many. As shown in FIGS. 2 a - 2 b , in one embodiment, a plurality of the first sub-pad groups P10 covered by the same riser board 16 are arranged and distributed along the second direction. In a specific embodiment, the second direction is perpendicular to the first direction.
  • step 402 is performed, as shown in FIG. 6a to FIG. 10b , forming an interposer 16 on the substrate 10 includes: forming a connection structure L and a second welding pad P2, and the second welding pad P2 is located at the Any surface of the adapter board 16 except the bottom surface; one end of the connection structure L is connected to the first pad P1, and the other end of the connection structure L is connected to the second pad P2.
  • forming the adapter plate 16 on the substrate 10 further includes: forming a sealing layer 15 on the substrate 10, the sealing layer 15 covers the connection structure L, and makes the The second pad P2 is located on the side surface of the sealing layer 15 .
  • the second pad P2 may also be formed on the top surface of the sealing layer 15 .
  • the sealing layer 15 may be formed by a molding process, and the material of the sealing layer 15 is an insulating material, such as epoxy resin molding compound.
  • connection structure L and the second pad P2 includes:
  • connection structure L and the second pad P2 filling the groove T with a conductive material to form the connection structure L and the second pad P2, as shown in FIGS. 8a to 8b;
  • the sacrificial layer 12 is removed, as shown in FIGS. 9a to 9b.
  • the formation process of the conductive material may be chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering and the like.
  • the conductive material may be the same as or different from that of the first pad P1.
  • the conductive material may include metal, metal nitride, metal silicide, metal alloy, conductive carbon or any combination thereof.
  • the materials of the first pad P1 , the connection structure L and the second pad P2 are the same, for example, copper (Cu).
  • the groove T includes a plurality of sub-grooves T4 arranged and distributed along the first direction, and each of the sub-grooves T4 includes successively connected first groove sub-grooves.
  • T1, the second groove sub-section T2 and the third groove sub-section T3; etching the sacrificial layer 12 includes:
  • the second groove sub-section T2 is formed by etching downward from the top surface of the sacrificial layer 12, and the depth of the second groove sub-section T2 along the vertical direction is smaller than that of the first groove sub-section T1 along the vertical direction. depth;
  • the third groove subsection T3 is formed by etching downward from the top surface of the sacrificial layer 12, and the depth of the third groove subsection T3 along the vertical direction is greater than that of the second groove subsection T2 along the vertical direction. The depth is less than the vertical depth of the first groove sub-section T1.
  • the material of the sacrificial layer 12 may be photoresist, and the groove T is formed in the sacrificial layer 12 by exposing and developing the sacrificial layer 12 .
  • the first groove sub-section T1 , the second groove sub-section T2 and the third groove sub-section T3 with different depths can be obtained by adjusting the exposure time, beam radiation dose or development time.
  • filling the groove T with conductive material to form the connection structure L and the second pad P2 includes:
  • connection structure L includes a plurality of sub-connection structures 13 uniformly arranged and distributed along the first direction.
  • the sub-connection structure 13 includes a first connection sub-portion 131 and a second connection sub-portion 132 extending in different directions and connected to each other; wherein, the first connection sub-portion 131 is in the The first groove sub-portion T1 is filled with conductive material, and the second connection sub-portion 132 is formed by filling the second groove sub-portion T2 with conductive material.
  • the second pad P2 includes a plurality of second sub-pad groups P20 with different heights, and each of the second sub-pad groups P20 includes a plurality of second sub-pad groups arranged and distributed along the first direction. Pad 14.
  • the depth of the second groove subsection T2 along the vertical direction determines the height of the sub-connection structure 13, the depth of the second groove subsection T2 along the vertical direction and the depth of the third groove subsection T3 The depth along the vertical direction determines the height of the second sub-pad 14 .
  • the second groove sub-portions T2 in the adjacent sub-grooves T4 along the first direction have different depths in the vertical direction, and the adjacent ones along the first direction
  • the third groove sub-part T3 in the sub-groove T4 has different depths in the vertical direction, so that the two adjacent sub-connecting structures 13 finally formed have different heights, and the two adjacent sub-connecting structures 13 have different heights.
  • the second sub-pads 14 connected by the connecting structures 13 also have different heights.
  • the first sub-pads 11 and the second sub-pads 14 have a one-to-one correspondence, and each first sub-pad group P10 corresponds to a plurality of second sub-pad groups P20 with different heights. Therefore, the distance between the adjacent second sub-pads 14 along the first direction in the second sub-pad group P20 is greater than the distance between the adjacent first sub-pads 14 along the first direction in each first sub-pad group P10. distance between pads 11.
  • the second sub-pads 14 are more sparsely arranged than the first sub-pads 11 .
  • the semiconductor structure provided by the embodiments of the present disclosure can have a smaller substrate size, a larger number of pads, and a lower pad arrangement density.
  • each of the first sub-pad groups P10 corresponds to two of the second sub-pad groups P20 with different heights. But not limited thereto, each of the first sub-pad groups P10 may also correspond to more second sub-pad groups P20 with different heights, for example, 3, 4 or 5 sub-groups.
  • the method further includes: fixing at least one chip C on the substrate 10, the surface of the chip C having a pad 18; using a bonding wire 19 to electrically connect the pad 18 to
  • the second pad P2 forms a semiconductor structure as shown in FIGS. 1 a to 1 b.
  • the bonding wire 19 is used for conducting signals.
  • the first pad P1 located on the substrate 10 is led to the side surface of the transfer board 16 by using the adapter plate 16 to form the second pad P2, and the bonding wire 19 and The direct connection of the second pad P2 can effectively shorten the length of the bonding wire 19 , thereby enhancing signal transmission performance and reducing heat generation and signal attenuation.
  • the chip C may be a memory, such as a dynamic random access memory (DRAM).
  • the material of the bonding wire 19 may be metal, such as gold (Au).
  • the number of chips C disposed on the substrate 10 is multiple, and the side surfaces of a plurality of chips C are aligned in a direction perpendicular to the substrate 10, as shown in Fig. 1a to Fig. 2b.
  • two adjacent chips C may be offset from each other by a predetermined distance, as shown in FIGS. 3 a to 3 b.
  • the plurality of chips C includes two chips C1 and C2 stacked on each other, and the plurality of second sub-pad groups P20 includes two second sub-pad groups P21, P22; wherein, the upper chip C2 of the two chips C1 and C2 is electrically connected to the upper second sub-pad group P22 of the two second sub-pad groups P21 and P22, and the two chips The lower chip C1 among C1 and C2 is electrically connected to the lower second sub-pad group P21 of the two second sub-pad groups P21 and P22 , as shown in FIG. 1 a to FIG. 1 b .
  • the two stacked chips C1 and C2 can also be electrically connected to two second sub-pad groups P20 with the same height, wherein the two second sub-pad groups P20
  • the welding pad groups P20 are respectively located on the side surfaces of the two adapter plates 16 , as shown in FIGS. 3 a to 3 b .
  • the chip C further includes an adhesive layer 17, and the adhesive layer 17 is located on the lower surface of the chip C for sequentially bonding one or more chips C to the substrate.
  • the adhesive layer 17 includes an adhesive film, for example, a direct adhesive film (DAF).
  • DAF direct adhesive film
  • the number of the riser boards 16 is multiple, and the multiple riser boards 16 are arranged around the one or more chips C. As shown in FIG. 1 a to FIG. 1 b , in some embodiments, the number of the riser boards 16 is two, and the two riser boards 16 are located on two sides of the one or more chips C respectively. But not limited thereto, the number of adapter plates 16 can be more or less, for example, 1, 3 or 4.
  • the method further includes: forming an encapsulation layer (not shown), the encapsulation layer (not shown) covers at least the chip C and the interposer 16 . It can be understood that the encapsulation layer (not shown) also covers the bonding wire 19 and part of the surface of the substrate 10 .
  • the first welding pad located on the substrate is led out to any surface of the interposer board except the bottom surface through the connection structure to form the second welding pad.
  • the adapter plate is located above the substrate, and its side surface has a relatively large area, so that the arrangement density of the second pads can be smaller than that of the first pads, and the adjacent pads can be reduced during wiring. The possibility of short circuits between the second pads and between adjacent bond wires.
  • the semiconductor structure provided by the embodiments of the present disclosure can have a smaller substrate size, a larger number of pads, and a lower arrangement density of the pads.
  • the presence of the adapter plate can also shorten the length of the bonding wire, thereby reducing heat generation and signal attenuation.

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Abstract

本公开实施例公开了一种半导体结构及其制造方法，所述半导体结构包括：衬底，所述衬底具有第一焊垫；转接板，位于所述衬底上，所述转接板的底表面覆盖所述第一焊垫；其中，所述转接板包括第二焊垫和连接结构；所述第二焊垫位于所述转接板除底表面以外的任意表面上；所述连接结构的一端与所述第一焊垫连接，所述连接结构的另一端与所述第二焊垫连接。

Description

一种半导体结构及其制造方法
相关的交叉引用
本公开基于申请号为202111570972.0、申请日为2021年12月21日、发明名称为“一种半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体结构及其制造方法。
背景技术
半导体结构，包括衬底以及位于所述衬底上的一个或多个芯片，所述衬底的表面设置有焊垫，所述芯片通过键合线与所述衬底表面的焊垫电连接。
然而，随着半导体结构朝着小尺寸、高集成度的方向发展，位于衬底表面的焊垫的排布密度越来越大，相邻的焊垫以及相邻的键合线之间容易发生短路，影响半导体结构的可靠性。
发明内容
本公开实施例提供一种半导体结构，包括：
衬底，所述衬底具有第一焊垫；
转接板，位于所述衬底上，所述转接板的底表面覆盖所述第一焊垫；其中，所述转接板包括第二焊垫和连接结构；所述第二焊垫位于所述转接板除底表面以外的任意表面上；所述连接结构的一端与所述第一焊垫连接，所述连接结构的另一端与所述第二焊垫连接。
在一些实施例中，所述转接板还包括：密封层，所述密封层的底部覆盖所述第一焊垫，所述第二焊垫位于所述密封层的侧表面。
在一些实施例中，所述连接结构位于所述密封层内。
在一些实施例中，所述第二焊垫包括高度不同的多个第二子焊垫组，每个所述第二子焊垫组包括多个沿第一方向排列分布的第二子焊垫。
在一些实施例中，所述第一焊垫包括一个或者多个第一子焊垫组，所述第一子焊垫组包括多个沿第一方向排列分布的第一子焊垫。
在一些实施例中，所述第一子焊垫组中沿第一方向上相邻的两个所述第一子焊垫之间的距离小于所述第二子焊垫组中沿第一方向上相邻的两个所述第二子焊垫之间的距离。
在一些实施例中，所述连接结构包括多个子连接结构；其中，所述子连接结构具有不同的高度。
在一些实施例中，所述连接结构包括多个沿第一方向排列分布的子连接结构；其中，相邻的两个所述子连接结构具有不同的高度。
在一些实施例中，所述子连接结构包括沿不同方向延伸且彼此连接的第一连接子部和第二连接子部；所述第一连接子部与所述第一焊垫连接，所述第二连接子部与所述第二焊垫连接。
在一些实施例中，所述第一连接子部的延伸方向与所述衬底垂直，所述第二连接子部的延伸方向与所述衬底平行。
在一些实施例中，所述半导体结构还包括：设置于所述衬底上的一个或者多个芯片，所述芯片的表面具有焊盘，所述焊盘通过键合线与所述第二子焊垫组电连接。
在一些实施例中，所述多个芯片中包括相互堆叠的两个芯片，多个所述第二子焊垫组中包括高度不同的两个第二子焊垫组；其中，所述两个芯片中位于上方的芯片与所述两个第二子焊垫组位于上方的第二子焊垫组电连接，所述两个芯片中位于下方的芯片与所述两个第二子焊垫组位于下方的第二子焊垫组电连接。
在一些实施例中，所述半导体结构还包括：封装层，所述封装层至少覆盖所述芯片及所述转接板。
在一些实施例中，所述转接板的数量为多个，多个所述转接板围绕所述一个或者多个芯片设置。
本公开实施例还提供了一种半导体结构的制造方法，包括：
提供衬底，所述衬底的表面具有第一焊垫；
在所述衬底上形成转接板，包括：形成连接结构和第二焊垫，所述第二焊垫位于所述转接板除底表面以外的任意表面上；
所述连接结构的一端与所述第一焊垫连接，所述连接结构的另一端与所述第二焊垫连接。
在一些实施例中，在所述衬底上形成转接板，还包括：在所述衬底上形成密封层，所述密封层包覆所述连接结构，并使所述第二焊垫位于所述密封层的侧表面。
在一些实施例中，形成连接结构和第二焊垫，包括：
在所述衬底上形成牺牲层，所述牺牲层覆盖所述第一焊垫；
刻蚀所述牺牲层，在所述牺牲层内形成凹槽；
在所述凹槽内填充导电材料，形成所述连接结构和所述第二焊垫；
移除所述牺牲层。
在一些实施例中，所述凹槽包括多个沿第一方向均匀排列分布的子凹槽，每个所述子凹槽包括依次连通的第一凹槽子部，第二凹槽子部和第三凹槽子部；刻蚀所述牺牲层，包括：从所述牺牲层的顶表面向下刻蚀形成所述第一凹槽子部，所述第一凹槽子部暴露出所述第一焊垫；
从所述牺牲层的顶表面往下刻蚀形成所述第二凹槽子部，所述第二凹槽子部沿竖直方向的深度小于所述第一凹槽子部沿竖直方向的深度；
从所述牺牲层的顶表面往下刻蚀形成所述第三凹槽子部，所述第三凹槽子部沿竖直方向的深度大于所述第二凹槽子部沿竖直方向的深度且小于所述第一凹槽子部沿竖直方向的深度。
在一些实施例中，沿第一方向上相邻的所述子凹槽中的所述第二凹槽子部在竖直方向具有不同的深度，且沿第一方向上相邻的所述子凹槽中的所述第三凹槽子部在竖直方向具有不同的深度。
在一些实施例中，在所述凹槽内填充导电材料，形成所述连接结构和所述第二焊垫，包括：
在所述第一凹槽子部和所述第二凹槽子部内填充导电材料形成所述连接结构，在所述第三凹槽子部内填充导电材料形成所述第二焊垫。
在一些实施例中，所述方法还包括：在所述衬底上固定至少一个芯片，所述芯片的表面具有焊盘；采用键合线将所述焊盘电连接至所述第二焊垫。
在一些实施例中，采用模塑工艺形成所述密封层。
本公开实施例提供的半导体结构及其制造方法，其中，所述半导体结构包括：衬底，所述衬底具有第一焊垫；转接板，位于所述衬底上，所述转接板的底表面覆盖所述第一焊垫；其中，所述转接板包括第二焊垫和连 接结构；所述第二焊垫位于所述转接板除底表面以外的任意表面上；所述连接结构的一端与所述第一焊垫连接，所述连接结构的另一端与所述第二焊垫连接。本公开实施例通过连接结构将位于衬底的第一焊垫引出至转接板除底表面以外的任意表面上，形成第二焊垫。所述转接板位于衬底上方，其侧表面具有较大的面积，因而使第二焊垫的排布密度可以小于所述第一焊垫的排布密度，在打线时可以降低相邻的第二焊垫之间以及相邻的键合线之间短路的可能性。相比于传统技术，本公开实施例提供的半导体结构可以具有更小的衬底尺寸、更多的焊垫数量及更低的焊垫排布密度。此外，所述转接板的存在还可以缩短键合线的长度，从而减小发热及信号衰减。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为本公开实施例提供的半导体结构的透视图，图1b为沿图1a的线A-A'截取的剖面结构示意图，图1c为图1a中第一焊垫及连接结构的透视图；
图2a为本公开另一实施例提供的半导体结构的透视图，图2b为沿图2a的线A-A'截取的剖面结构示意图；
图3a为本公开另一实施例提供的半导体结构的透视图，图3b为沿图3a的线A-A'截取的剖面结构示意图；
图4为本公开实施例提供的半导体结构制造方法的流程框图；
图5a至图10b为本公开实施例提供的半导体结构的工艺流程图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方 式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复 数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
半导体结构，包括衬底以及位于所述衬底上的一个或多个芯片，所述衬底的表面设置有焊垫，所述芯片通过键合线与所述衬底表面的焊垫电连接。随着半导体结构向小尺寸、高集成度的方向发展，衬底的尺寸逐渐减小，焊垫的数量逐渐增加，从而使得焊垫的排布密度越来越大，在打线时，相邻的焊垫以及相邻的键合线之间容易发生短路，影响半导体结构的可靠性。
基于此，提出了本公开实施例的以下技术方案：
本公开实施例提供了一种半导体结构，包括：衬底，所述衬底具有第一焊垫；转接板，位于所述衬底上，所述转接板的底表面覆盖所述第一焊垫；其中，所述转接板包括第二焊垫和连接结构；所述第二焊垫位于所述转接板除底表面以外的任意表面上；所述连接结构的一端与所述第一焊垫连接，所述连接结构的另一端与所述第二焊垫连接。
本公开实施例通过连接结构将位于衬底的第一焊垫引出至转接板除底表面以外的任意表面上，形成第二焊垫。所述转接板位于衬底上方，其侧表面具有较大的面积，因而使第二焊垫的排布密度可以小于所述第一焊垫的排布密度，在打线时可以降低相邻的第二焊垫之间以及相邻的键合线之间短路的可能性。相比于传统技术，本公开实施例提供的半导体结构可以具有更小的衬底尺寸、更多的焊垫数量及更低的焊垫排布密度。此外，所述转接板的存在还可以缩短键合线的长度，从而减小发热及信号衰减。
下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例做局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图1a、图2a、图3a为本公开实施例提供的半导体结构的透视图，图1b、图2b、图3b分别为沿图1a、图2a、图3a的线A-A'截取的剖面结构示意图，图1c为图1a中第一焊垫及连接结构的透视图。以下结合图1a至图3b对本公开实施例提供的半导体结构再作进一步详细的说明。
如图1a至图1c所示，所述半导体结构包括：衬底10，所述衬底10具 有第一焊垫P1；转接板16，位于所述衬底10上，所述转接板16的底表面覆盖所述第一焊垫P1；其中，所述转接板16包括第二焊垫P2和连接结构L；所述第二焊垫P2位于所述转接板16除底表面以外的任意表面上；所述连接结构L的一端与所述第一焊垫P1连接，所述连接结构L的另一端与所述第二焊垫P2连接。
所述衬底10可以是刚性印刷电路板、柔性印刷电路板、刚性-柔性印刷电路板或其任何组合。在一具体实施例中，所述衬底10为内部设置有各种电路元件的多层电路板。在一更具体实施例中，所述衬底10的表面包括绝缘层(未图示)，所述第一焊垫P1位于所述绝缘层(未图示)内，且所述第一焊垫P1的上表面与所述绝缘层(未图示)的上表面齐平。所述第一焊垫P1的材料可以包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金、导电碳或其任何组合。所述绝缘层(未图示)的材料可以是阻焊剂。
在一实施例中，所述转接板16还包括：密封层15，所述密封层15的底部覆盖所述第一焊垫P1，所述第二焊垫P2位于所述密封层15的侧表面。但不限于此，在其他实施例中，所述第二焊垫P2还可以位于所述密封层15的顶表面。所述密封层15的材料为绝缘材料，例如，环氧树脂模塑料。所述第二焊垫P2的材料可以与所述第一焊垫P1的材料相同或不同。可选的，所述第二焊垫P2的材料可以包括金属、金属氮化物、金属硅化物、金属合金、导电碳或其任何组合。
在一实施例中，所述第二焊垫P2包括高度不同的多个第二子焊垫组P20，每个所述第二子焊垫组P20包括多个沿第一方向排列分布的第二子焊垫14。可选的，所述第一方向平行于所述衬底10表面。如图1a所示，多个所述第二子焊垫组P20暴露于所述密封层15的侧表面，且沿垂直于所述衬底10的方向上排列分布。
参见图1a、图1c，在一实施例中，所述第一焊垫P1包括至少一个第一子焊垫组P10，所述第一子焊垫组P10包括多个沿第一方向排列分布的第一子焊垫11。在一具体的实施例中，所述第一子焊垫组P10中沿第一方向上相邻的两个所述第一子焊垫11之间的距离小于所述第二子焊垫组P20中沿第一方向上相邻的两个所述第二子焊垫14之间的距离。换句话说，在第一方向上，所述第二子焊垫14的排布相比所述第一子焊垫11的排布更加稀疏。如此，在打线时，相邻的第二子焊垫14之间以及与所述相邻的第二 子焊垫14连接的键合线之间不容易短路，提高了半导体结构的可靠性。可以理解的是，所述第一子焊垫11和所述第二子焊垫14是一一对应的关系，之所以在第一方向上相邻的两个所述第二子焊垫14之间的距离大于相邻的两个所述第一子焊垫11之间的距离，是因为每一个第一子焊垫组P10对应高度不同的多个第二子焊垫组P20，从而，在每一个第二子焊垫组P20中第二子焊垫14的数量要少于每一个第一子焊垫组P10中第一子焊垫11的数量，因此，每一个第二子焊垫组P20中相邻的第二子焊垫14的距离要大于每一个第一子焊垫组P10中相邻的第一子焊垫11之间的距离。如图1c所示，每一个所述第一子焊垫组P10对应高度不同的2个所述第二子焊垫组P20。但不限于此，每一个所述第一子焊垫组P10还可以对应高度不同的更多个所述第二子焊垫组P20，例如3个、4个或5个。
图1a至图1c示出的每一转接板16覆盖一组所述第一子焊垫组P10。但不限于此，如图2a至图2b所示，在另一实施例中，每一转接板16覆盖多组所述第一子焊垫组P10，该多组所述第一子焊垫组P10在所述衬底10上沿第二方向排列分布。在一具体实施例中，第二方向与第一方向垂直。
需要说明的是，所述第一子焊垫组的数量与所述第二子焊垫组的数量不限于图1a至图3b所示，所述第一子焊垫组的数量以及所述第二子焊垫组的数量可以更多或更少。
继续参见图1c，所述连接结构L位于所述密封层15内，所述第二焊垫P2与所述第一焊垫P1通过所述连接结构L一一对应连接，所述连接结构L的排布方式与所述第一焊垫P1的排布方式相同，所述连接结构L的高度决定了所述第二焊垫P2的高度。在一实施例中，所述连接结构L包括多个子连接结构13；其中，所述子连接结构13具有不同的高度。在一些实施例中，所述连接结构L包括多个沿第一方向排列分布的子连接结构13；其中，相邻的两个所述子连接结构13具有不同的高度。
在一实施例中，所述子连接结构13包括沿不同方向延伸且彼此连接的第一连接子部131和第二连接子部132；所述第一连接子部131与所述第一焊垫P1连接，所述第二连接子部132与所述第二焊垫P2连接。在一具体实施例中，所述第一连接子部131的延伸方向与所述衬底10垂直，所述第二连接子部132的延伸方向与所述衬底10平行。所述第一连接子部131和所述第二连接子部132可以是同时形成，也可以依次形成；所述第一连接子部131和所述第二连接子部132的材料可以包括金属、金属氮化物、金 属硅化物、金属合金、导电碳或其任何组合。在一具体实施例中，所述第一焊垫P1、所述连接结构L、所述第二焊垫P2的材料相同，例如，铜(Cu)。
在一实施例中，所述半导体结构还包括：设置于所述衬底10上的一个或多个芯片C，所述芯片C的表面具有焊盘18，所述焊盘18通过键合线19与所述第二子焊垫组P20电连接。这里，所述芯片C可以是存储器，例如动态随机存储器(DRAM)。所述键合线19用于传导信号，其材料可以是金属，例如，金(Au)。
在一实施例中，设置于所述衬底10上的芯片C的数量为多个，多个所述芯片C的侧表面在垂直于所述衬底10的方向上对齐，如图1a至图2b所示。但不限于此，在其他实施例中，相邻的两个芯片C可以相互偏移一预定距离，如图3a至图3b所示。
在一实施例中，如图1a至图1b所示，所述多个芯片C中包括相互堆叠的两个芯片C1、C2，多个所述第二子焊垫组P20中包括高度不同的两个第二子焊垫组P21、P22；其中，所述两个芯片C1、C2中位于上方的芯片C2与所述两个第二子焊垫组P21、P22位于上方的第二子焊垫组P22电连接，所述两个芯片C1、C2中位于下方的芯片C1与所述两个第二子焊垫组P21、P22位于下方的第二子焊垫组P21电连接。但不限于此，在另一实施例中，相互堆叠的两个芯片C1、C2还可以分别与具有同一高度的两个第二子焊垫组P20电连接，其中，所述两个第二子焊垫组P20分别位于两个所述转接板16的侧表面，如图3a至图3b所示。
在一实施例中，所述芯片C还包括粘接层17，所述粘接层17位于所述芯片C的下表面，用于将一个或多个所述芯片C顺序粘合至所述衬底10上。所述粘接层17包括粘合膜，例如，直接粘合膜(DAF)。
在一实施例中，所述转接板16的数量为多个，多个所述转接板16围绕所述一个或多个芯片C设置。如图1a至图1b所示，在一些实施例中，所述转接板16的数量为2个，2个所述转接板16分别位于所述一个或多个芯片C的两侧。但不限于此，所述转接板16的数量还可以更多或更少，例如1个、3个或4个。
在一实施例中，所述半导体结构还包括：封装层(未图示)，所述封装层(未图示)至少覆盖所述芯片C及所述转接板16。可以理解的是，所述封装层(未图示)还包覆所述键合线19以及所述衬底10的部分表面。
综上可知，本公开实施例通过连接结构L将位于衬底10的第一焊垫 P1引出至转接板16除底表面以外的任意表面上，形成第二焊垫P2。所述转接板16位于衬底10上方，其侧表面具有较大的面积，因而使第二焊垫P2的排布密度可以小于所述第一焊垫P1的排布密度，在打线时可以降低相邻的第二焊垫P2之间以及相邻的键合线19之间短路的可能性。相比于传统技术，本公开实施例提供的半导体结构可以具有更小的衬底尺寸、更多的焊垫数量及更低的焊垫排布密度。此外，所述转接板16的存在还可以缩短键合线19的长度，从而减小发热及信号衰减。
本公开实施例还提供了一种半导体结构的制造方法，如图4所示，所述方法包括以下步骤：
步骤401、提供衬底，所述衬底的表面具有第一焊垫；
步骤402、在所述衬底上形成转接板，包括：形成连接结构和第二焊垫，所述第二焊垫位于所述转接板除底表面以外的任意表面上；所述连接结构的一端与所述第一焊垫连接，所述连接结构的另一端与所述第二焊垫连接。
下面，结合图5a至图10b对本公开实施例的半导体结构的制造方法再做进一步详细的说明。其中，图5a、图6a、图7a、图8a、图9a、图10a为本公开实施例提供的半导体结构的制造方法在不同工艺步骤中的透视图，图5b、图6b、图7b、图8b、图9b、图10b分别为沿着图5a、图6a、图7a、图8a、图9a、图10a的线A-A'截取的剖面结构示意图。
首先，执行步骤401，提供衬底10，所述衬底10的表面具有第一焊垫P1，如图5a至图5b所示。
所述衬底10可以是刚性印刷电路板、柔性印刷电路板、刚性-柔性印刷电路板或其任何组合。在一具体实施例中，所述衬底10为内部设置有各种电路元件的多层电路板。在一更具体实施例中，所述衬底10的表面包括绝缘层(未图示)，所述第一焊垫P1位于所述绝缘层(未图示)内，且所述第一焊垫P1的上表面与所述绝缘层(未图示)的上表面齐平。所述第一焊垫P1的材料可以包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金、导电碳或其任何组合。所述绝缘层(未图示)的材料可以是阻焊剂。
在一实施例中，所述第一焊垫P1包括至少一个第一子焊垫组P10，所述第一子焊垫组P10包括多个沿第一方向排列分布的第一子焊垫11。
图5a-5b示出的所述第一子焊垫组P10的数量为两个，后续将在该两个所述第一子焊垫组P10上分别形成两个转接板16(参见图10a至图10b)， 即每一转接板16覆盖一个所述第一子焊垫组P10。但不限于此，所述第一子焊垫组P10的个数还可以为更多，被每一所述转接板16覆盖的所述第一子焊垫组P10的个数也可以为更多。如图2a-2b所示，在一实施例中，被同一所述转接板16覆盖的多个所述第一子焊垫组P10沿第二方向排列分布。在一具体实施例中，第二方向与第一方向垂直。
接着，执行步骤402，如图6a至图10b所示，在所述衬底10上形成转接板16，包括：形成连接结构L和第二焊垫P2，所述第二焊垫P2位于所述转接板16除底表面以外的任意表面上；所述连接结构L的一端与所述第一焊垫P1连接，所述连接结构L的另一端与所述第二焊垫P2连接。
在一实施例中，在所述衬底10上形成转接板16，还包括：在所述衬底10上形成密封层15，所述密封层15包覆所述连接结构L，并使所述第二焊垫P2位于所述密封层15的侧表面。但不限于此，在其他实施例中，所述第二焊垫P2还可以形成于所述密封层15的顶表面。这里，可以采用模塑工艺形成所述密封层15，所述密封层15的材料为绝缘材料，例如，环氧树脂模塑料。
在一实施例中，形成连接结构L和第二焊垫P2，包括：
在所述衬底10上形成牺牲层12，所述牺牲层12覆盖所述第一焊垫P1，如图6a至图6b所示；
刻蚀所述牺牲层12，在所述牺牲层12内形成凹槽T，如图7a至图7b所示；
在所述凹槽T内填充导电材料，形成所述连接结构L和所述第二焊垫P2，如图8a至图8b所示；
移除所述牺牲层12，如图9a至图9b所示。
所述导电材料的形成工艺可以是化学气相沉积(CVD)、等离子增强CVD(PECVD)、物理气相沉积(PVD)、原子层沉积(ALD)、电镀、化学镀、溅射等。所述导电材料可以与所述第一焊垫P1的材料相同或不同。可选的，所述导电材料可以包括金属、金属氮化物、金属硅化物、金属合金、导电碳或其任何组合。在一实施例中，所述第一焊垫P1、所述连接结构L、所述第二焊垫P2的材料相同，例如，铜(Cu)。
再次参考图7a至图7b，在一实施例中，所述凹槽T包括多个沿第一方向排列分布的子凹槽T4，每个所述子凹槽T4包括依次连通的第一凹槽子部T1，第二凹槽子部T2和第三凹槽子部T3；刻蚀所述牺牲层12，包括：
从所述牺牲层12的顶表面向下刻蚀形成所述第一凹槽子部T1，所述第一凹槽子部T1暴露出所述第一焊垫P1；
从所述牺牲层12的顶表面往下刻蚀形成所述第二凹槽子部T2，所述第二凹槽子部T2沿竖直方向的深度小于所述第一凹槽子部T1沿竖直方向的深度；
从所述牺牲层12的顶表面往下刻蚀形成所述第三凹槽子部T3，所述第三凹槽子部T3沿竖直方向的深度大于所述第二凹槽子部T2沿竖直方向的深度且小于所述第一凹槽子部T1沿竖直方向的深度。
可选的，所述牺牲层12的材料可以为光刻胶，通过对所述牺牲层12执行曝光、显影工艺以在所述牺牲层12内形成凹槽T。并且，可以通过调整曝光时间、光束辐射剂量或显影时间得到具有不同深度的所述第一凹槽子部T1、所述第二凹槽子部T2和所述第三凹槽子部T3。
再次参考图8a至图8b，在一实施例中，在所述凹槽T内填充导电材料，形成所述连接结构L和所述第二焊垫P2，包括：
在所述第一凹槽子部T1和所述第二凹槽子部T2内填充导电材料形成所述连接结构L，在所述第三凹槽子部T3内填充导电材料形成所述第二焊垫P2。
具体的，所述连接结构L包括多个沿第一方向均匀排列分布的子连接结构13。在一个具体的实施例中，所述子连接结构13包括沿不同方向延伸且彼此连接的第一连接子部131和第二连接子部132；其中，所述第一连接子部131是在所述第一凹槽子部T1内填充导电材料形成的，所述第二连接子部132是在所述第二凹槽子部T2内填充导电材料形成的。
更具体的，所述第二焊垫P2包括高度不同的多个第二子焊垫组P20，每个所述第二子焊垫组P20包括多个沿第一方向排列分布的第二子焊垫14。
可以理解的，所述第二凹槽子部T2沿竖直方向的深度决定了子连接结构13的高度，所述第二凹槽子部T2沿竖直方向的深度以及所述第三凹槽子部T3沿竖直方向的深度决定了所述第二子焊垫14的高度。在一实施例中，沿第一方向上相邻的所述子凹槽T4中的所述第二凹槽子部T2在竖直方向具有不同的深度，且沿第一方向上相邻的所述子凹槽T4中的所述第三凹槽子部T3在竖直方向具有不同的深度，使得最终形成的相邻的两个子连接结构13具有不同的高度，与该相邻的两个所述子连接结构13相连的所 述第二子焊垫14亦具有不同的高度。所述第一子焊垫11和所述第二子焊垫14是一一对应的关系，每一个第一子焊垫组P10对应高度不同的多个第二子焊垫组P20。因此，第二子焊垫组P20中沿第一方向上相邻的第二子焊垫14的距离要大于每一个第一子焊垫组P10中沿第一方向上相邻的第一子焊垫11之间的距离。换句话说，在第一方向上，所述第二子焊垫14相比所述第一子焊垫11排列的更加稀疏。如此，在打线时，相邻的第二子焊垫14之间以及与所述相邻的第二子焊垫14连接的键合线之间不容易短路，提高了半导体结构的可靠性。相比于传统技术，本公开实施例提供的半导体结构可以具有更小的衬底尺寸、更多的焊垫数量及更低的焊垫排布密度。
再次参见图9a，每一个所述第一子焊垫组P10对应高度不同的2个所述第二子焊垫组P20。但不限于此，每一个所述第一子焊垫组P10还可以对应高度不同的更多个所述第二子焊垫组P20，例如3个、4个或5个。
在一实施例中，所述方法还包括：在所述衬底10上固定至少一个芯片C，所述芯片C的表面具有焊盘18；采用键合线19将所述焊盘18电连接至所述第二焊垫P2，形成如图1a至图1b所示的半导体结构。所述键合线19用于传导信号。本公开实施例通过采用转接板16将位于所述衬底10上的第一焊垫P1引至所述转接板16的侧表面，形成第二焊垫P2，所述键合线19与所述第二焊垫P2直接连接，可以有效缩短所述键合线19的长度，从而增强信号的传输性能，减小发热及信号衰减。这里，所述芯片C可以是存储器，例如动态随机存储器(DRAM)。所述键合线19的材料可以是金属，例如，金(Au)。
在一实施例中，设置于所述衬底10上的芯片C的数量为多个，多个所述芯片C的侧表面在垂直于所述衬底10的方向上对齐，如图1a至图2b所示。但不限于此，在其他实施例中，相邻的两个芯片C可以相互偏移一预定距离，如图3a至图3b所示。
在一实施例中，所述多个芯片C中包括相互堆叠的两个芯片C1、C2，多个所述第二子焊垫组P20中包括高度不同的两个第二子焊垫组P21、P22；其中，所述两个芯片C1、C2中位于上方的芯片C2与所述两个第二子焊垫组P21、P22位于上方的第二子焊垫组P22电连接，所述两个芯片C1、C2中位于下方的芯片C1与所述两个第二子焊垫组P21、P22位于下方的第二子焊垫组P21电连接，如图1a至图1b所示。但不限于此，在另一实施例中，相互堆叠的两个芯片C1、C2还可以分别与具有同一高度的两个第二子 焊垫组P20电连接，其中，所述两个第二子焊垫组P20分别位于两个所述转接板16的侧表面，如图3a至图3b所示。
在一实施例中，所述芯片C还包括粘接层17，所述粘接层17位于所述芯片C的下表面，用于将一个或多个所述芯片C顺序粘合至所述衬底10上。所述粘接层17包括粘合膜，例如，直接粘合膜(DAF)。
在一实施例中，所述转接板16的数量为多个，多个所述转接板16围绕所述一个或多个芯片C设置。如图1a至图1b所示，在一些实施例中，所述转接板16的数量为2个，2个所述转接板16分别位于所述一个或多个芯片C的两侧。但不限于此，所述转接板16的数量还可以更多或更少，例如1个、3个或4个。
在一实施例中，所述方法还包括：形成封装层(未图示)，所述封装层(未图示)至少覆盖所述芯片C及所述转接板16。可以理解的是，所述封装层(未图示)还包覆所述键合线19以及所述衬底10的部分表面。
应当说明的是，本领域技术人员能够对上述步骤顺序进行变换而并不离开本公开的保护范围，以上所述，仅为本公开的可选实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例通过连接结构将位于衬底的第一焊垫引出至转接板除底表面以外的任意表面上，形成第二焊垫。所述转接板位于衬底上方，其侧表面具有较大的面积，因而使第二焊垫的排布密度可以小于所述第一焊垫的排布密度，在打线时可以降低相邻的第二焊垫之间以及相邻的键合线之间短路的可能性。相比于传统技术，本公开实施例提供的半导体结构可以具有更小的衬底尺寸、更多的焊垫数量及更低的焊垫排布密度。此外，所述转接板的存在还可以缩短键合线的长度，从而减小发热及信号衰减。

Claims (22)

  1. 一种半导体结构，包括：
    衬底，所述衬底具有第一焊垫；
    转接板，位于所述衬底上，所述转接板的底表面覆盖所述第一焊垫；其中，所述转接板包括第二焊垫和连接结构；所述第二焊垫位于所述转接板除底表面以外的任意表面上；所述连接结构的一端与所述第一焊垫连接，所述连接结构的另一端与所述第二焊垫连接。
  2. 根据权利要求1所述的半导体结构，其中，所述转接板还包括：密封层，所述密封层的底部覆盖所述第一焊垫，所述第二焊垫位于所述密封层的侧表面。
  3. 根据权利要求2所述的半导体结构，其中，所述连接结构位于所述密封层内。
  4. 根据权利要求1所述的半导体结构，其中，所述第二焊垫包括高度不同的多个第二子焊垫组，每个所述第二子焊垫组包括多个沿第一方向排列分布的第二子焊垫。
  5. 根据权利要求4所述的半导体结构，其中，所述第一焊垫包括一个或者多个第一子焊垫组，所述第一子焊垫组包括多个沿第一方向排列分布的第一子焊垫。
  6. 根据权利要求5所述的半导体结构，其中，所述第一子焊垫组中沿第一方向上相邻的两个所述第一子焊垫之间的距离小于所述第二子焊垫组中沿第一方向上相邻的两个所述第二子焊垫之间的距离。
  7. 根据权利要求1所述的半导体结构，其中，所述连接结构包括多个子连接结构；其中，所述子连接结构具有不同的高度。
  8. 根据权利要求1所述的半导体结构，其中，所述连接结构包括多个沿第一方向排列分布的子连接结构；其中，相邻的两个所述子连接结构具有不同的高度。
  9. 根据权利要求7或8所述的半导体结构，其中，所述子连接结构包括沿不同方向延伸且彼此连接的第一连接子部和第二连接子部；所述第一连接子部与所述第一焊垫连接，所述第二连接子部与所述第二焊垫连接。
  10. 根据权利要求9所述的半导体结构，其中，所述第一连接子部的延伸方向与所述衬底垂直，所述第二连接子部的延伸方向与所述衬底 平行。
  11. 根据权利要求4所述的半导体结构，其中，所述半导体结构还包括：设置于所述衬底上的一个或者多个芯片，所述芯片的表面具有焊盘，所述焊盘通过键合线与所述第二子焊垫组电连接。
  12. 根据权利要求11所述的半导体结构，其中，所述多个芯片中包括相互堆叠的两个芯片，多个所述第二子焊垫组中包括高度不同的两个第二子焊垫组；其中，所述两个芯片中位于上方的芯片与所述两个第二子焊垫组位于上方的第二子焊垫组电连接，所述两个芯片中位于下方的芯片与所述两个第二子焊垫组位于下方的第二子焊垫组电连接。
  13. 根据权利要求11所述的半导体结构，其中，所述半导体结构还包括：封装层，所述封装层至少覆盖所述芯片及所述转接板。
  14. 根据权利要求11所述的半导体结构，其中，所述转接板的数量为多个，多个所述转接板围绕所述一个或者多个芯片设置。
  15. 一种半导体结构的制造方法，所述方法包括：
    提供衬底，所述衬底的表面具有第一焊垫；
    在所述衬底上形成转接板，包括：形成连接结构和第二焊垫，所述第二焊垫位于所述转接板除底表面以外的任意表面上；
    所述连接结构的一端与所述第一焊垫连接，所述连接结构的另一端与所述第二焊垫连接。
  16. 根据权利要求15所述的制造方法，其中，在所述衬底上形成转接板，还包括：在所述衬底上形成密封层，所述密封层包覆所述连接结构，并使所述第二焊垫位于所述密封层的侧表面。
  17. 根据权利要求15所述的制造方法，其中，形成连接结构和第二焊垫，包括：
    在所述衬底上形成牺牲层，所述牺牲层覆盖所述第一焊垫；
    刻蚀所述牺牲层，在所述牺牲层内形成凹槽；
    在所述凹槽内填充导电材料，形成所述连接结构和所述第二焊垫；
    移除所述牺牲层。
  18. 根据权利要求17所述的制造方法，其中，所述凹槽包括多个沿第一方向均匀排列分布的子凹槽，每个所述子凹槽包括依次连通的第一凹槽子部，第二凹槽子部和第三凹槽子部；刻蚀所述牺牲层，包括：从所述牺牲层的顶表面向下刻蚀形成所述第一凹槽子部，所述第一凹槽子 部暴露出所述第一焊垫；
    从所述牺牲层的顶表面往下刻蚀形成所述第二凹槽子部，所述第二凹槽子部沿竖直方向的深度小于所述第一凹槽子部沿竖直方向的深度；
    从所述牺牲层的顶表面往下刻蚀形成所述第三凹槽子部，所述第三凹槽子部沿竖直方向的深度大于所述第二凹槽子部沿竖直方向的深度且小于所述第一凹槽子部沿竖直方向的深度。
  19. 根据权利要求18所述的制造方法，其中，沿第一方向上相邻的所述子凹槽中的所述第二凹槽子部在竖直方向具有不同的深度，且沿第一方向上相邻的所述子凹槽中的所述第三凹槽子部在竖直方向具有不同的深度。
  20. 根据权利要求18所述的制造方法，其中，在所述凹槽内填充导电材料，形成所述连接结构和所述第二焊垫，包括：
    在所述第一凹槽子部和所述第二凹槽子部内填充导电材料形成所述连接结构，在所述第三凹槽子部内填充导电材料形成所述第二焊垫。
  21. 根据权利要求15所述的制造方法，其中，所述方法还包括：在所述衬底上固定至少一个芯片，所述芯片的表面具有焊盘；采用键合线将所述焊盘电连接至所述第二焊垫。
  22. 根据权利要求16所述的制造方法，其中，采用模塑工艺形成所述密封层。
PCT/CN2022/071228 2021-12-21 2022-01-11 一种半导体结构及其制造方法 WO2023115666A1 (zh)

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KR20100088514A (ko) * 2009-01-30 2010-08-09 주식회사 하이닉스반도체 반도체 패키지
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