TWI769679B - 互連結構及相關聯系統及方法 - Google Patents

互連結構及相關聯系統及方法 Download PDF

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TWI769679B
TWI769679B TW110102999A TW110102999A TWI769679B TW I769679 B TWI769679 B TW I769679B TW 110102999 A TW110102999 A TW 110102999A TW 110102999 A TW110102999 A TW 110102999A TW I769679 B TWI769679 B TW I769679B
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Taiwan
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trace
leg
interconnect structure
cavity
semiconductor
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TW110102999A
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TW202135259A (zh
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凱爾 K 克比
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美商美光科技公司
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  • Engineering & Computer Science (AREA)
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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

本文中提供一種用於一半導體裝置之互連結構。該互連結構通常包括電耦接至定位於一半導體晶粒上之一導電觸點之一導電柱及位於該柱之一遠端上之一跡線收納器。該跡線收納器具有電耦接至該遠端之一本體，且可包括自該本體之一第一側遠離該遠端突出的一第一支腳及自該本體之一第二側遠離該遠端突出的一第二支腳，使得該本體、該第一支腳及該第二支腳一起形成一空腔。在該半導體裝置之組裝期間，該空腔經組態以至少部分地環繞定位於一絕緣基板中之一半導體跡線之一部分。為了形成電連接，可將一焊料材料安置於該跡線收納器與該跡線之間。

Description

互連結構及相關聯系統及方法
本發明大體上係關於半導體裝置，且在若干實施例中，更特定地係關於用於晶粒至基板及/或三維積體電路互連之互連結構。
諸如記憶體裝置、微處理器及發光二極體之微電子裝置通常包括安裝至基板且包覆於保護蓋中之一或多個半導體晶粒。半導體晶粒包括諸如記憶體單元、處理器電路、互連電路等等功能特徵。為縮減半導體晶粒佔據之體積，同時提高所得經囊封總成之容量及/或速度，半導體晶粒製造商正面臨愈來愈大之壓力。為了滿足此等需求，半導體晶粒製造商常常將多個半導體晶粒豎直地堆疊於彼此頂部上，以增大在安裝有半導體晶粒之電路板或其他元件上的有限體積內之微電子裝置的容量或效能。對於豎直地堆疊式半導體晶粒，常常使用矽穿孔(TSV)。鄰近之半導體晶粒上之此類TSV通常使用直接實體耦接彼此電連接，其中一個晶粒之接合襯墊直接接合至另一晶粒之接合襯墊。
個別或堆疊式半導體晶粒通常經由晶粒上之金屬接合襯墊或藉由形成於接合襯墊上之柱進行電連接。當晶粒電連接至基板時，襯墊或柱通常使用附接至金屬襯墊或柱之焊料凸塊與基板中之經曝露跡線形成連接。在組裝期間，回焊焊料凸塊以形成自晶粒至基板(D2S)之連接。習知組裝方法通常產生侷限於金屬柱之尖端及基板中跡線之頂側的焊料連接。常常，每一半導體晶粒之接合襯墊一起緊密地間隔開，使得當焊料在堆疊過程期間回焊以形成焊料凸塊時，焊料會在鄰近金屬柱之間形成電「橋」，以電連接鄰近柱並使半導體裝置短接。
本發明之一個態樣提供一種用於一半導體裝置之互連結構，該互連結構包含：一導電柱，其電耦接至定位於一半導體晶粒上之一導電觸點，該導電柱具有與該導電觸點相對之一遠端；及一跡線收納器，其具有：一本體，其電耦接至該柱之該遠端；一第一支腳，其自該本體之一第一側遠離該遠端突出；及一第二支腳，其自該本體之一第二側遠離該遠端突出，其中該本體、該第一支腳及該第二支腳一起形成一空腔，該空腔經組態以在其中收納一半導體跡線之一部分。
本發明之另一態樣係關於一種半導體總成，其包含：一基板，其具有曝露於該基板之一表面處之一跡線；一半導體晶粒，其具有一導電觸點；及一互連結構，其電耦接該跡線及該導電觸點，該互連結構具有：一導電柱，其電耦接至該導電觸點；及一跡線收納器，其具有電耦接至該柱之與該導電觸點相對之一遠端的一本體、自該本體之一第一側遠離該遠端突出的一第一支腳，及自該本體之一第二側遠離該遠端突出的一第二支腳，其中該本體、該第一支腳及該第二支腳一起形成一空腔，該空腔經組態以在其中收納該跡線之一部分。
本發明之又一態樣提供一種半導體總成，其包含：一基板，其具有曝露於該基板之一表面處之一第一跡線及一第二跡線；一半導體晶粒，其具有一第一導電觸點及一第二導電觸點；一第一互連結構，其電耦接該第一跡線及該第一導電觸點；及一第二互連結構，其電耦接該第二跡線及該第二導電觸點，其中該等第一及第二互連結構中之每一者具有：一導電柱，其電耦接至一對應導電觸點；及一跡線收納器，其具有電耦接至該柱之與該導電觸點相對之一遠端的一本體、自該本體之一第一側遠離該遠端突出的一第一支腳，及自該本體之一第二側遠離該遠端突出的一第二支腳，其中該本體、該第一支腳及該第二支腳一起形成一空腔，該空腔經組態以在其中收納一對應跡線之一部分，其中該第一互連結構之該第一支腳定位於該等第一及第二跡線之相對周邊表面之間，使得安置於該第一互連結構之該跡線收納器中之一焊料材料不能形成至該第二跡線之一電橋。
本文中所揭示之技術係關於半導體裝置、具有半導體裝置之系統及用於製造半導體裝置之相關方法。術語「半導體裝置」通常係指包括一或多種半導體材料之固態裝置。半導體裝置之實例包括邏輯裝置、記憶體裝置及二極體以及其他。此外，術語「半導體裝置」可指成品裝置或在變為成品裝置之前的各種處理階段處的總成或其他結構。
取決於其使用之上下文，術語「基板」可指支撐電子組件(例如晶粒)之結構，諸如晶圓級基板、單體化晶粒級基板或用於晶粒堆疊應用之另一晶粒。一般熟習相關技術者將認識到，本文中所描述之方法之合適步驟可在晶圓級或在晶粒級執行。此外，除非上下文另外指示，否則本文中所揭示之結構可使用習知半導體製造技術形成。可例如使用化學氣相沈積、物理氣相沈積、原子層沈積、旋塗、鍍敷及/或其他合適技術來沈積材料。類似地，可例如使用電漿蝕刻、濕式蝕刻、化學機械平坦化或其他合適技術來移除材料。
在若干實施例中，半導體晶粒包括曝露於表面處之至少一個觸點(例如，延伸穿過晶粒之接合襯墊或TSV之部分)。在此等實施例中，互連結構電耦接至觸點，用於與半導體裝置之其他組件形成電連接。在一些實施例中，互連結構包括晶粒之接合襯墊上之導電金屬柱，該導電金屬柱經組態以電耦接至曝露於基板(例如，晶粒堆疊應用中之另一晶粒、印製電路板、晶粒級或晶圓級基板等等)中之跡線。如上文所指出，此等連接通常被稱為D2S連接。
在一些習知互連結構中，柱形成於晶粒之接合襯墊上。柱藉由在柱之尖端回焊或重整焊料材料而電耦接至基板中之跡線。焊料材料與柱上之表面及跡線上之表面接觸以形成電連接。在此等組態中，介接焊料材料之柱及跡線之有限表面積導致相對薄弱之結構連接。D2S互連方法在組裝過程中易受各種可靠性問題之影響，包括未對準、焊料橋接、焊料坍落、不完全潤濕、晶粒翹曲、邊緣或轉角連接、熱膨脹係數不匹配及低機械強度以及其他。隨著陣列組態密度增大，每一晶粒之接合襯墊可能有較大間距，此增加了遇到上述困難之趨勢。
在本文中所描述之一些實施例中，在柱之與晶粒相對之一端形成額外導電結構。該額外結構包括經組態用於保持焊料材料之跡線收納器。如下文將更詳細地所描述，此等跡線收納器形成有具有至少一個開口之一或多個空隙或空腔，且在若干實施例中，空隙或空腔具有與基板中跡線之形狀互補之形狀(例如，跡線收納器之空腔大體上對應於跡線表面之大小、形狀、間距、深度等等)。舉例而言，收納器可為大體上狹長桿，其具有曝露於基板中之三個實質上直線側，使得空腔具有遠離柱面朝跡線之C形開口。在此等實施例中，跡線收納器中之空腔之大小及形狀可經組態以當晶粒相對於基板置放在經組裝位置中時，允許跡線收納器與跡線之間的焊料材料間隙。在其他實施例中，空隙或空腔之形狀為適合於將跡線介接於基板中之任何形狀(例如，彎曲的內表面)。
除優於習知技術之其他優點外，本文中描述之跡線收納器組態：(a)有助於柱與跡線之對準；(b)提供較大機械穩定性；(c)可在組裝多晶粒堆疊時承受焊料材料之多次回焊；(d)可適應較高程度之晶粒翹曲；(e)減少焊料橋接；(f)允許較緊密間距互連及基板設計；(g)有助於非導電薄膜處理(NCF)；及(h)允許較緊密接合線控制。本發明技術之組態可在本文中參考TSV及/或三維積體電路(3DI)加以描述；然而，本發明技術亦適用於其他互連類型，包括覆晶接合(FC)、直接晶片附接(DCA)及D2S及其他。結合特定組態對本發明技術之描述不應被解釋為限制本發明技術之應用。
本文中對跡線收納器及跡線之形狀之描述及說明為例示性的，且不應被解釋為限制本發明之範疇。在此方面，在若干實施例中，基板中之跡線之形狀為藉由合適製造製程產生以曝露實現電連接之導電材料的任何形狀，且此形狀可在基板、同一基板上之跡線及/或鄰近跡線之間變化。同樣，在其他實施例中，跡線收納器中之空腔之形狀為經組態以實現與跡線之電連接的任何適合形狀，且可能未必與跡線之形狀互補地成形(例如，跡線收納器中之弓形空腔與實質上直線跡線相容等等)。在此等實施例中，跡線收納器經大小設定及成形以電連接至跡線且形成相較於習知技術具有增加的機械強度之結合。此外，跡線收納器中之空腔經組態以將焊料材料實質上限制於空腔中，使得防止焊料短接及電橋接。
如本文中所使用，術語「豎直」、「橫向」、「上部」及「下部」可指鑒於諸圖中所展示之定向的半導體裝置中之特徵的相對方向或位置。舉例而言，「上部」或「最上部」可指與另一特徵相比更接近頁面之頂部定位的特徵。然而，此等術語應解釋為包括具有其他定向(諸如反向或傾斜定向)之半導體裝置，其中可取決於定向而互換頂部/底部、之上/之下、上方/下方、上/下、左/右及遠側/近側。此外，為了易於參考，在整個本發明中使用相同參考數字來識別類似或相似組件或特徵，但使用相同參考數字並不暗示特徵應被解釋為相同的。實際上，在本文中所描述之許多實例中，相同編號之特徵具有在結構及/或功能上彼此不同之複數個實施例。此外，相同陰影可用於指示在組成上可類似之橫截面中的材料，但使用相同陰影並不暗示該等材料應解釋為相同的，除非本文中特定指出。
本發明亦可參考數量及數目。除非特定地陳述，否則此類數量及數目不應被視為限制性的，而是例示與新技術相關聯的可能數量或數目。又，就此而言，本發明可使用術語「複數個」來參考數量或數目。就此而言，術語「複數個」意謂多於一個之任何數目，例如，兩個、三個、四個、五個等等。出於本發明之目的，片語「A、B及C中之至少一者」例如意謂(A)、(B)、(C)、(A及B)、(A及C)、(B及C)或(A、B及C)，當列出多於三個要素時包括所有其他可能的排列。
圖1A及圖1B展示根據本發明技術之實施例之半導體裝置100的橫截面圖。圖1A展示在電連接組件之前的一位置中之半導體裝置100，且圖1B展示在電連接組件之後的半導體裝置100。半導體裝置100 (例如，半導體晶粒總成)通常包括基板120及藉由互連總成130電耦接至基板120之半導體晶粒110。如本文中所描述，半導體晶粒110可為具有一或多個積體電路之個別晶粒，或者半導體晶粒110可為多個電連接半導體晶粒之堆疊。
在本發明技術之一些實施例中，基板120包括介電材料124 (例如，鈍化材料、聚醯亞胺材料、阻焊劑/遮罩及/或用於覆蓋半導體裝置頂表面之其他材料)及具有周邊表面128及遠側表面132之導電跡線122。絕緣材料124至少部分地覆蓋基板120之表面，且經局部移除以形成開放區域126以至少部分地曝露導電跡線122。絕緣材料124可經移除至曝露跡線122之周邊表面128之深度。
半導體晶粒110通常包括曝露於半導體晶粒110之表面上的複數個導電觸點112，該等導電觸點電耦接至半導體晶粒110之積體電路，且經組態以電耦接至晶粒堆疊之另一半導體晶粒或另一類型之基板(例如，印製電路板)。在一些實施例中，觸點112為接合襯墊，而在其他實施例中，觸點112可為部分或完全延伸穿過半導體晶粒110之貫孔(例如TSV)之一部分。半導體晶粒110之積體電路可包括記憶體電路(例如動態隨機記憶體(DRAM))、控制器電路(例如DRAM控制器)、邏輯電路及/或其他電路或電路之組合。
在一些實施例中，互連總成130包括自半導體晶粒110上之觸點112突出並在大體上垂直於半導體晶粒110之方向上延伸之導電(例如金屬)柱114。然而，在其他實施例中，柱114以85°與90°之間的角度自半導體晶粒110延伸。在另外的實施例中，柱114以88°與90°之間的角度自半導體晶粒110延伸。當組裝半導體裝置100時，柱114可具有經組態以在半導體晶粒110與基板120之間提供所要間距之長度。
在習知半導體裝置中，柱通常使用經曝露焊料材料(例如，焊料材料並不藉由任何結構保持)電連接至跡線。相比之下，本發明技術之實施例在柱114之端處包括經組態以保持一定數量之焊料材料142之跡線收納器140。跡線收納器140在與跡線122之縱向軸線相對應的方向上之長度可小於基板120中之經曝露跡線122之長度(參見例如圖3)。在此等實施例中，個別跡線收納器140產生與經曝露跡線122之僅一部分的電連接。跡線收納器140在與跡線122之縱向軸線相對應的方向上之長度可與跡線122之經曝露長度實質上相同或比該經曝露長度長。
如圖1A及圖1B中所展示，個別跡線收納器140可具有本體145、遠離本體145之一側突出的第一支腳147a及遠離本體145之另一側突出的第二支腳147b，以產生經組態以保持焊料材料142之空腔144。在若干實施例中，空腔144具有與基板120之對應跡線122之形狀大體上互補的形狀。跡線收納器140可形成於對應柱114上，其中空腔144具有三個實質上直線內表面(參見例如圖2A及圖2B)，該等內表面與跡線122之表面的大小、形狀、間距、深度等等相對應。舉例而言，跡線收納器之空腔144可具有「C形」，其中空腔144之開口遠離柱114面朝跡線122。
個別跡線收納器140之空腔144可至少部分地填充有焊料材料142，以在組裝半導體裝置100時與跡線122形成電連接。焊料材料142可符合空腔144之形狀以大體上與跡線122之形狀相對應(例如，圖2A)，或焊料材料142可以其他組態填充空腔144，諸如平坦組態(例如，圖2B)。通常，跡線收納器140中之空腔144之大小及形狀可經組態以當半導體晶粒110相對於基板120置放在經組裝位置中時，允許跡線收納器140與跡線122之間的焊料材料142中的間隙。在此等實施例中，規定焊料材料142之體積及空腔144之大小及形狀，使得焊料徑流最小化以防止焊料短接。另外，焊料材料142在跡線收納器140與跡線122之間流動的間隙可經組態以具有在半導體晶粒110翹曲、鄰近柱114具有不同長度等等情況下仍然允許在跡線收納器140與跡線122之間形成電連接之規定公差。在經組裝位置中，跡線收納器140之最遠端可與基板120之表面接觸(圖1B)以進一步抑制焊料橋接。
圖2C及圖2D展示具有不同形狀之空腔之跡線收納器的實施例。更特定言之，圖2C展示具有經組態以保持焊料材料142的弓形空腔244之跡線收納器240。在此實施例中，弓形空腔244可能與實質上直線跡線122之形狀不匹配，但是此類弓形空腔244與本發明技術範疇內之各種跡線形狀相容。圖2D展示具有角形空腔344之跡線收納器340，其可與本發明技術範疇內之各種跡線形狀相容。因為焊料材料142填充間隙並產生電連接，所以跡線收納器140、240及340可在經組裝位置中之某些點處與跡線122接觸。在其他實施例中，每一跡線收納器中之空腔之形狀係由於製造能力、製造製程、成本、可靠性、接合強度、跡線形狀、基板差異、設計者偏好等等中之一或多者而形成。
互連總成130之組件通常由導電材料形成，諸如銅、鎳、金等等及其組合。在一些實施例中，柱114及跡線收納器140可以使用任何合適之圖案化方法形成，諸如使用藉由光罩之減材處理來形成可在其中鍍敷跡線收納器140之坑。
圖3展示耦接至跡線122之跡線收納器140。在半導體裝置100之組裝期間，半導體晶粒110被定位成使得跡線收納器140與跡線122對準以在空腔144內收納跡線122之一部分。在一些實施例中，在半導體晶粒110之跡線收納器140靠近跡線122之前，對空腔144內之焊料材料142進行預熱以允許焊料流動。當組裝時，半導體裝置100可在跡線收納器140與跡線122之間具有實質上均一的間隙。空腔144可僅部分地填充有具有預製形狀之焊料材料142，使得焊料材料142在焊料回焊之前環繞跡線122之遠側表面132的至少一部分及周邊表面128的至少一部分。在其他實施例中，焊料材料142未經預熱，而是與跡線122之一或多個表面接觸定位，使得焊料材料142可在成組回焊期間與其他互連總成130一起加熱。跡線收納器140及跡線122之組態允許焊料材料142之多次回焊，從而降低焊料橋接之風險。在未預熱焊料材料142之實施例中，可使用聲波能量執行成組回焊，藉以材料之間的摩擦產生熱以回焊焊料材料142。
圖4為繪示根據本發明技術之實施例的包含半導體裝置之系統之方塊圖。具有上文參考圖1A至圖3所描述之特徵的半導體裝置中之任一者可併入至多種較大及/或較複雜系統中之任一者中，其代表性實例為在圖4中示意性地展示之系統400。系統400可包括處理器402、記憶體404 (例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置406及/或其他子系統或組件408。上文參考圖1A至圖3所描述之半導體總成、裝置及裝置封裝可包括於圖4中所展示之元件中之任一者中。所得系統400可經組態以執行廣泛多種合適的計算、處理、儲存、感測、成像及/或其他功能中之任一者。因此，系統400之代表性實例包括但不限於電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路設備、手持型裝置(例如，掌上型電腦、可穿戴式電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等等)、平板電腦、多處理器系統、基於處理器之或可程式化消費型電子裝置、網路電腦及小型電腦。系統400之額外代表性實例包括燈、攝影機、車輛等等。在此等及其他實例中，系統400可容納於單一單元中或例如經由通信網路分佈於多個互連單元上。系統400之組件可因此包括本端及/或遠端記憶體儲存裝置及廣泛多種合適的電腦可讀媒體中之任一者。
自前文應瞭解，儘管已出於說明的目的而在本文中描述新技術之特定實施例，但可在不偏離本發明之情況下進行各種修改。因此，本發明不受除隨附申請專利範圍以外的限制。此外，在其他實施例中，亦可組合或消除在特定實施例之情形下描述的新技術之某些態樣。此外，儘管與新技術之某些實施例相關聯之優點已在此等實施例之上下文中描述，但其他實施例亦可展現此類優點，且並非所有實施例必定需要展現屬於本發明之範疇內的此類優點。因此，本發明及相關聯技術可涵蓋未在本文中明確展示或描述之其他實施例。
100:半導體裝置 110:半導體晶粒 112:導電觸點 114:柱 120:基板 122:導電跡線 124:介電材料 126:開放區域 128:周邊表面 130:互連總成 132:遠側表面 140:跡線收納器 142:焊料材料 144:空腔 145:本體 147a:第一支腳 147b:第二支腳 240:跡線收納器 244:弓形空腔 340:跡線收納器 344:角形空腔 400:系統 402:處理器 404:記憶體 406:輸入/輸出 408:子系統及其他組件
圖1A為展示在經由互連件形成電連接之前的半導體裝置之放大橫截面圖，該半導體裝置具有根據本發明技術之實施例組態的包括跡線收納器之互連結構。
圖1B為展示在經由互連件形成電連接之後的圖1A之半導體裝置之放大橫截面圖。
圖2A至圖2D為根據本發明技術之實施例組態的具有各種跡線收納器之互連結構之橫截面詳圖。
圖3為展示在經由互連件形成電連接之前的半導體裝置之透視圖，該半導體裝置具有根據本發明技術之實施例組態的包括跡線收納器之互連結構。
圖4為根據本發明技術之實施例組態的包括半導體裝置之系統之示意圖。
100:半導體裝置
110:半導體晶粒
112:導電觸點
114:柱
120:基板
122:導電跡線
124:介電材料
126:開放區域
128:周邊表面
130:互連總成
132:遠側表面
140:跡線收納器
142:焊料材料
144:空腔
145:本體
147a:第一支腳
147b:第二支腳

Claims (20)

  1. 一種用於一半導體裝置之互連結構，該互連結構包含：一導電柱，其電耦接至定位於一半導體晶粒上之一導電觸點，該導電柱具有與該導電觸點相對之一遠端；及一跡線收納器，其具有：一本體，其電耦接至該柱之該遠端；一第一支腳，其形成一第一板，該第一板自該本體之一第一側遠離該遠端突出；一第二支腳，其形成一第二板，該第二板自相對於該第一側之該本體之一第二側突出且遠離該遠端，其中該本體之一上表面、該第一板之一內表面及該第二板之一內表面一起形成一空腔，該空腔經組態以在其中收納一跡線之一部分，其中該空腔沿平行於該第一板之該內表面及該第二板之該內表面且垂直於該導電柱之一主軸線(major axis)之一橫向軸線(lateral axis)而開放；及一焊料材料，其安置於該空腔之一部分中且與該本體之該上表面、該第一板之該內表面及該第二板之該內表面接觸。
  2. 如請求項1之互連結構，其中當該半導體裝置處於一經組裝位置時，該第一支腳及該第二支腳至少部分地沿著該跡線之周邊表面延伸。
  3. 如請求項1之互連結構，其中該焊料材料具有一預製形狀(preformed shape)，其具有對應於在一經組裝位置中之該跡線之一遠側表面及沿著該 跡線之一側之至少一個周邊表面之若干表面。
  4. 如請求項1之互連結構，其中在一經組裝位置中該跡線收納器經組態以在該跡線收納器與該跡線之間形成一間隙，使得當該焊料材料在該半導體裝置之組裝期間被加熱時，該跡線收納器內之該焊料材料流動以至少部分地環繞該跡線之經曝露表面。
  5. 如請求項1之互連結構，其中該等第一及第二支腳形成板，該等板遠離該本體垂直地突出，使得該空腔具有三個直線內表面。
  6. 如請求項1之互連結構，其中該跡線定位於具有一絕緣材料之一半導體基板上。
  7. 如請求項6之互連結構，其中該跡線藉由該絕緣材料中之一開口曝露。
  8. 一種半導體總成，其包含：一基板，其具有曝露於該基板之一表面處之一狹長跡線(elongate trace)，該跡線具有一縱向軸線(longitudinal axis)；一半導體晶粒，其具有一導電觸點；及一互連結構，其電耦接該跡線及該導電觸點，該互連結構具有：一導電柱，其電耦接至該導電觸點；及一跡線收納器，其具有電耦接至該柱之與該導電觸點相對之一遠 端的一本體、自該本體之一第一側遠離該遠端突出的一第一支腳，及自相對於該第一側之該本體之一第二側突出且遠離該遠端的一第二支腳，其中該本體、該第一支腳及該第二支腳一起形成一空腔，該空腔經組態以在其中收納該跡線之一部分，其中該空腔在相鄰於該第一支腳及該第二支腳之該空腔之若干側邊上具有若干側向開口，其中該跡線之一縱向長度大於該跡線收納器在沿著該縱向軸線之一方向上之一長度，使得該跡線經由該空腔延伸出該等側向開口。
  9. 如請求項8之半導體總成，其中該跡線收納器之該第一支腳及該第二支腳至少部分地沿著該跡線之周邊表面延伸。
  10. 如請求項8之半導體總成，其中該跡線收納器藉由安置於該跡線收納器與該跡線之間的一焊料材料電耦接至該跡線。
  11. 如請求項10之半導體總成，其中該焊料材料與該跡線之一遠側表面及沿著該跡線之一側之至少一個周邊表面接觸。
  12. 如請求項8之半導體總成，其中該等第一及第二支腳形成板，該等板遠離該本體垂直地突出，使得該空腔具有三個直線內表面。
  13. 如請求項8之半導體總成，其中該跡線藉由該基板上之一絕緣材料中之一開口曝露。
  14. 一種半導體總成，其包含：一基板，其具有一狹長的第一跡線及一狹長的第二跡線，該第一跡線具有一第一縱向軸線，該第二跡線具有一第二縱向軸線，該第一跡線及該第二跡線曝露於該基板之一表面處；一半導體晶粒，其具有一第一導電觸點及一第二導電觸點；一第一互連結構，其電耦接該第一跡線及該第一導電觸點；及一第二互連結構，其電耦接該第二跡線及該第二導電觸點，其中該等第一及第二互連結構中之每一者具有：一導電柱，其電耦接至一對應導電觸點；及一跡線收納器，其具有電耦接至該柱之與該導電觸點相對之一遠端的一本體、自該本體之一第一側遠離該遠端突出的一第一支腳，及自相對於該第一側之該本體之一第二側突出且遠離該遠端的一第二支腳，其中該本體、該第一支腳及該第二支腳一起形成一空腔，該空腔經組態以在其中收納一對應跡線之一部分，其中該空腔在相鄰於該第一支腳及該第二支腳之該空腔之若干側邊上具有若干側向開口，其中該第一跡線之一縱向長度大於該第一互連結構之該跡線收納器在沿著該第一縱向軸線之一方向上之一長度，使得該第一跡線經由該第一互連結構之該空腔延伸出該等側向開口，其中該第一互連結構之該第一支腳定位於該等第一及第二跡線之相對周邊表面之間，使得安置於該第一互連結構之該跡線收納器中之一焊料材料不能形成至該第二跡線之一電橋。
  15. 如請求項14之半導體總成，其中該第二互連結構之該第二支腳定位於該第一互連結構之該第一支腳與該第二跡線之該周邊表面之間。
  16. 如請求項14之半導體總成，其中該第一互連結構之該第一支腳及該第二支腳至少部分地沿著該第一跡線之周邊表面延伸。
  17. 如請求項14之半導體總成，其中：該第一互連結構藉由安置於該第一互連結構之該跡線收納器與該第一跡線之間的該焊料材料電耦接至該第一跡線，且該第二互連結構藉由安置於該第二互連結構之該跡線收納器與該第二跡線之間的該焊料材料電耦接至該第二跡線。
  18. 如請求項17之半導體總成，其中該焊料材料與該等第一及第二跡線之遠側表面及沿著該等第一及第二跡線中之每一者之一側的至少一個周邊表面接觸。
  19. 如請求項14之半導體總成，其中該等第一及第二互連結構中之每一者之該等第一及第二支腳形成板，該等板遠離該本體垂直地突出，使得該等第一及第二互連結構之該等空腔具有三個直線內表面。
  20. 如請求項14之半導體總成，其中該等第一及第二跡線藉由該基板上之一絕緣材料中之一開口曝露。
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