TW202027181A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TW202027181A
TW202027181A TW108135005A TW108135005A TW202027181A TW 202027181 A TW202027181 A TW 202027181A TW 108135005 A TW108135005 A TW 108135005A TW 108135005 A TW108135005 A TW 108135005A TW 202027181 A TW202027181 A TW 202027181A
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Taiwan
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area
bump
conductive bumps
bumps
design
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TW108135005A
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TWI745754B (zh
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李苓瑋
黃震麟
劉明達
喬福康
周彥彬
羅俊彥
朱則榮
陳文明
劉國洲
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種半導體裝置的形成方法，包括：接收中介片的第一表面上的複數個導電凸塊的第一設計，所述第一設計中的所述導電凸塊具有相同的橫剖面積；將所述第一設計中的所述導電凸塊分組為所述第一表面的第一區域中的第一組導電凸塊和所述第一表面的第二區域中的第二組導電凸塊，其中所述第二區域的凸塊圖案密度小於所述第一區域的凸塊圖案密度；透過修改所述第一設計形成第二設計，其中修改所述第一設計包括修改所述第二區域中的所述第二組導電凸塊的橫剖面積；以及根據所述第二設計形成所述導電凸塊於所述中介片的所述第一表面上，其中，在形成之後，所述第一組導電凸塊和所述第二組導電凸塊具有不同的橫剖面積。本發明實施例也提供一種半導體裝置。

Description

半導體裝置及其形成方法
本發明實施例係關於半導體裝置及其形成方法，且特別是有關於半導體裝置中凸塊的佈局設計。
由於各種電子元件（例如：電晶體、二極體、電阻器、電容器等）的積體密度的不斷提高，半導體工業已歷經快速的發展。在大多數情況下，積體密度的提高是由於最小部件（feature）尺寸迭代的減少所致，這使得更多元件能夠整合至一給定區域中。
隨著對微縮化電子裝置的需求增長，產生了對更小和更有創意的半導體晶粒封裝技術的需求。這種封裝系統的一個例子為堆疊式封裝（Package-on-Package；PoP）技術。在堆疊式封裝（PoP）裝置中，頂部半導體封裝堆疊在底部半導體封裝的頂部上，以提供高水平的整合度（integration）和元件密度。另一個例子是基板上晶圓上晶片（Chip-On-Wafer-On-Substrate；CoWoS）結構。在一些實施例中，為了形成基板上晶圓上晶片（CoWoS）結構，將複數個半導體晶片附接到（attached to）晶圓，並接著進行切割製程以將晶圓分成複數個中介片（interposers），其中每一個中介片具有一個或多個半導體晶片與其附接。在一些實施例中，附接有半導體晶片的中介片被稱為晶圓上晶片（Chip-On-Wafer；CoW）結構。然後，將晶圓上晶片（CoW）結構附接到基板（例如，印刷電路板）以形成基板上晶圓上晶片（CoWoS）結構。這些和其他先進的封裝技術得以生產出具有增強功能和小覆蓋區域（footprints）的半導體裝置。
根據本發明的一實施例，提供一種半導體裝置的形成方法，包括：接收用於中介片的第一表面上之複數個導電凸塊的第一設計，所述第一設計中的所述導電凸塊具有相同的橫剖面積；將所述第一設計中的所述導電凸塊分組為所述第一表面的第一區域中的第一組導電凸塊和所述第一表面的第二區域中的第二組導電凸塊，其中所述第二區域的凸塊圖案密度小於所述第一區域的凸塊圖案密度；透過修改所述第一設計來形成第二設計，其中修改所述第一設計包括修改所述第二區域中的所述第二組導電凸塊的橫剖面積；以及，根據所述第二設計形成導電凸塊於所述中介片的第一表面上，其中，在形成之後，所述第一組導電凸塊和所述第二組導電凸塊具有不同的橫剖面積。
根據本發明的另一實施例，提供一種半導體裝置的形成方法，包括：分析用於工件的第一表面上之複數個導電凸塊的第一設計，其中所述分析包括將工件的第一表面分成具有複數個第一導電凸塊的第一區域和具有複數個第二導電凸塊的第二區域，其中所述第一區域中第一導電凸塊的第一凸塊圖案密度大於所述第二區域中第二導電凸塊的第二凸塊圖案密度，其中所述第一區域中的第一導電凸塊的第一凸塊節距小於所述第二區域中的第二導電凸塊的第二凸塊節距；修改所述第一設計以產生第二設計，其中修改所述第一設計包括添加複數個虛設凸塊於所述第二區域中以縮小所述第二凸塊節距；根據所述第二設計，形成導電凸塊和虛設凸塊於所述工件的第一表面上；以及，透過所述導電凸塊將所述工件接合到基板。
又根據本發明的另一實施例，提供一種半導體裝置，包括：附接至中介片的上表面之晶粒；複數個第一導電凸塊，位於所述中介片的下表面的第一區域中，所述第一區域具有第一凸塊圖案密度；複數個第二導電凸塊，位於所述中介片的下表面的第二區域中，所述第二區域具有小於所述第一凸塊圖案密度的第二凸塊圖案密度；以及，複數個虛設凸塊，位於所述中介片的下表面的周邊區域中，所述周邊區域圍繞所述第一區域和所述第二區域。
以下揭示提供許多不同的實施例或是例子來實行本發明實施例之不同部件。以下描述具體的元件及其排列的例子以簡化本發明實施例。當然這些僅是例子且不該以此限定本發明實施例的範圍。例如，在描述中提及第一個部件形成於第二個部件「之上」或「上」時，其可能包括第一個部件與第二個部件直接接觸的實施例，也可能包括兩者之間有其他部件形成而沒有直接接觸的實施例。另外，本發明可能在不同實施例中重複參照符號及/或標記。在整份說明書中，除非另有說明，否則不同圖式中的相同參照符號表示由使用相同或類似材料的相同或類似方法所形成的相同或相似的元件。
此外，其中用到與空間相關的用詞，例如：「在…下方」、「下方」、「較低的」、「上方 」、「較高的」及其類似的用詞係為了便於描述圖式中所示的一個元件或部件與另一個元件或部件之間的關係。這些空間關係詞係用以涵蓋圖式所描繪的方位之外的使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位（旋轉90度或其他方位），則其中使用的空間相關形容詞也可相同地照著解釋。
在形成導電凸塊的背景下討論本發明實施例，特別地，在中介片的表面（例如，下表面）上形成具有改良的平坦性之導電凸塊。在一些實施例中，在具有低凸塊圖案密度的區域中之導電凸塊的尺寸（例如，橫剖面積）相對於在具有高凸塊圖案密度的區域中之導電凸塊的尺寸增加。在一些實施例中，形成虛設凸塊於具有低凸塊圖案密度的區域中之導電凸塊之間以縮小低凸塊圖案密度區域中的凸塊節距（pitch），沒有虛設凸塊形成於高凸塊圖案密度區域中。在一些實施例中，形成虛設凸塊於中介片的表面之周邊區域中以縮小周邊區域中的凸塊節距，而由周邊區域圍繞的表面之其他區域中的凸塊節距則保持不變（例如，沒有虛設凸塊形成於其他區域中）。
第1圖根據一些實施例顯示出半導體裝置100的部分剖面圖。半導體裝置100具有基板上晶圓上晶片（CoWoS）結構。為達簡潔的目的，第1圖僅顯示出半導體裝置100的左側部分，而半導體裝置100的右側部分可以與第1圖所示的左側部分相同（例如，對稱）或相似，如本技術領域具有通常知識者可理解的。
為了形成半導體裝置100，將一個或多個晶粒101（也可稱為半導體晶粒、晶片、或積體電路（integrated circuit；IC）晶粒）附接到中介片200以形成晶圓上晶片（CoW）結構，然後將晶圓上晶片（CoW）結構附接到基板300（例如，印刷電路板）以形成基板上晶圓上晶片（CoWoS）結構。在一些實施例中，晶粒101是相同類型的晶粒（例如，記憶體晶粒或邏輯晶粒）。在其他實施例中，晶粒101是不同的類型，例如，一些晶粒101是邏輯晶粒而其他晶粒101是記憶體晶粒。
每一個晶粒101包括基底、形成在基底中/上的電子元件（例如，電晶體、電阻器、電容器、二極體、或其類似元件）、以及位於基底之上用以連接電子元件以形成晶粒101的功能性電路的互連結構。晶粒101也包括導電柱103（也稱為晶粒連接器），其提供與晶粒101的電路之電性連接。為達簡潔的目的，並未顯示出晶粒101的所有部件。
晶粒101的基底可以是經摻雜或未經摻雜的半導體基底、或絕緣體上覆矽（silicon-on-insulator；SOI）基底的主動層。通常，絕緣體上覆矽（SOI）基底包括半導體材料層，例如矽、鍺、矽鍺、絕緣體上覆矽（SOI）、絕緣體上覆矽鍺（silicon germanium on insulator；SGOI）、或前述之組合。其他可使用的基底包括多層基底、梯度（gradient）基底、或混合取向（hybrid orientation）基底。
晶粒101的電子元件包括各種主動裝置（例如，電晶體）和被動裝置（例如，電容器、電阻器、電感器）、或其類似裝置。可以使用任何合適的方法形成晶粒101的電子元件於晶粒101的基底內或基底上。晶粒101的互連結構包括形成在一個或多個介電層中的一個或多個金屬化層（例如，銅層），且用於連接各種電子元件以形成功能性電路。在一實施例中，互連結構是由介電質和導電材料（例如，銅）的交替層形成，並且可透過任何合適的製程（例如沉積、鑲嵌、雙鑲嵌等）來形成互連結構。
可形成一個或多個鈍化層於晶粒101的互連結構之上，用以為晶粒101的下層結構提供一定程度的保護。鈍化層可以由一種或多種合適的介電材料組成，例如氧化矽、氮化矽、低介電常數（low-k）介電質（例如碳摻雜的氧化物）、極低介電常數（extremely low-k）介電質（例如多孔碳摻雜的二氧化矽）、前述之組合、或類似材料。儘管可以使用任何合適的製程，但可以透過像是化學氣相沉積（chemical vapor deposition；CVD）的製程來形成鈍化層。
導電焊墊（conductive pads）可形成於鈍化層之上，並且可延伸穿過鈍化層以與晶粒101的互連結構電性接觸。導電焊墊可包括鋁，但也可使用其他材料，例如銅。
形成晶粒101的導電柱103於導電焊盤上以提供用於電性連接到晶粒101的電路之導電區域。導電柱103可為銅柱、像是微凸塊的接觸凸塊、或類似物，且導電柱103的材料可包括像是銅、錫、銀、或其他合適的材料。
關於中介片200（也可稱為工件），其包括基底211、穿孔結構（through vias）215（也稱為基底穿孔結構（through-substrate vias；TSVs））、位於基底211上表面上的導電焊墊213 、位於基底211下表面處的凸塊下金屬（under-bump-metallurgy；UBM）結構230、以及凸塊下金屬（UBM）結構230上的導電凸塊231（也可稱為凸塊、連接器、或導電柱）。第1圖也顯示出基底211的表面介電層219（例如，最低介電層）。凸塊下金屬（UBM）結構230延伸穿過表面介電層219以與中介片200的導電部件（例如，穿孔結構215）電性耦合。
基底211可為例如經摻雜或未經摻雜的半導體基底、或絕緣體上覆矽（SOI）基底的主動層。然而，基底211可替代地為玻璃基底、陶瓷基底、聚合物基底、或可提供合適的保護及/或互連功能的任何其他基底。
在一些實施例中，基底211可包括電子元件，例如電阻器、電容器、訊號分配電路、這些的組合、或其類似元件。這些電子元件可以是主動的、被動的、或前述之組合。在其他實施例中，基底211中沒有主動和被動電子元件。所有這些組合完全包含在本發明實施例範圍內。
穿孔結構215從基底211的上表面延伸到基底211的下表面，並且提供導電焊墊213和導電凸塊231之間的電性連接。穿孔結構215可由合適的導電材料形成，例如銅、鎢、鋁、合金、經摻雜的多晶矽、前述之組合、及其類似材料。可以在穿孔結構215和基底211之間形成障壁層（barrier layer）。障壁層可包括合適的材料，像是氮化鈦，但是也可以使用其他材料，像是氮化鉭、鈦、或其類似材料。
在一實施例中，凸塊下金屬（UBM）結構230包括三層導電材料，例如鈦層、銅層、和鎳層。然而，還有許多適合形成凸塊下金屬（UBM）結構230之合適的材料和層的配置，例如鉻/鉻-銅合金/銅/金的配置、鈦/鈦鎢/銅的配置、或銅/鎳/金的配置。可用於凸塊下金屬（UBM）結構230的任何合適的材料或材料層完全包含在本發明實施例的範圍內。
可透過以下步驟形成凸塊下金屬（UBM）結構230：形成開口於表面介電層219中以暴露出基底211中的導電部件（例如，電性耦合到穿孔結構215的導電焊墊）、在表面介電層219之上並沿著表面介電層219中開口的內部形成種子層、形成圖案化罩幕層（例如，光阻）於種子層之上、形成（例如，透過鍍覆(plating)）導電材料於圖案化罩幕層的開口中和種子層之上、移除罩幕層並移除其上未形成導電材料的種子層部分。用於形成凸塊下金屬（UBM）結構230的其他方法是可能的，並且完全包含在本發明實施例的範圍內。
導電凸塊231可為任何合適類型的外部接觸，例如微凸塊、銅柱、控制塌陷晶片連接（controlled collapse chip connection；C4）凸塊、銅層、鎳層、無鉛（lead free；LF）層、化鎳鈀浸金（electroless nickel electroless palladium immersion gold；ENEPIG）層、Cu/LF層、Sn/Ag層、Sn/Pb、這些的組合、或其類似物。
在一些實施例中，導電凸塊231可為或可包括金屬柱，例如透過像是鍍覆製程（例如電鍍或無電電鍍）形成的銅柱。可透過以下步驟形成導電凸塊231：形成具有暴露出凸塊下金屬（UBM）結構230的開口之圖案化罩幕層（例如，光阻）、形成（例如，透過鍍覆）導電材料於圖案化罩幕層的開口中和凸塊下金屬（UBM）結構230之上、以及移除罩幕層。用於形成導電凸塊231的其他方法是可能的，並且完全包含在本發明實施例的範圍內。在第1圖的例子中，凸塊下金屬（UBM）結構230和相應的導電凸塊231具有相同的寬度。
在一些實施例中，用於形成（例如，透過鍍覆製程）導電凸塊231的罩幕層（例如，光阻）中的開口尺寸對應於（例如，等於）（也因此決定）導電凸塊231的橫剖面積。在一些實施例中，導電凸塊231的橫剖面積指的是導電凸塊231沿著第1圖中的剖面A-A的橫剖面積。舉例而言，導電凸塊231的橫剖面可為圓形或橢圓形（參照例如第4A圖和第4B圖）。為了便於討論，用以形成（例如，透過鍍覆製程）導電凸塊231的圖案化罩幕層（例如，光阻）中的開口在下文中可稱為凸塊開口。
如第1圖所示，晶粒101的導電柱103透過例如銲錫區域105接合到中介片200的導電焊墊213。可進行回焊製程以將晶粒101接合到中介片200。
在將晶粒101接合到中介片200之後，形成底部填充材料107於晶粒101和中介片200之間。底部填充材料107可包括例如液體環氧樹脂，例如使用分注針（dispensing needle）或其他合適的分注工具將液體環氧樹脂分注在晶粒101和中介片200之間的間隙（gap）中，然後將其固化以硬化。如第1圖所示，底部填充材料107填充晶粒101和中介片200之間的間隙，並且也可以填充晶粒101的側壁之間的間隙。
接下來，形成模製（molding）材料109於中介片200之上和晶粒101周圍。模製材料109也圍繞（surrounds）底部填充材料107。做為示例，模製材料109可包括環氧樹脂、有機聚合物、添加或不添加二氧化矽類（silica-based）的填料或玻璃填料的聚合物、或其他材料。在一些實施例中，模製材料109包括液體模製化合物（liquid molding compound；LMC），其在施加時是凝膠型液體。模製材料109在施加時也可包括液體或固體。或者，模製材料109可包括其他絕緣及/或封裝材料。在一些實施例中，使用晶圓級模製製程來施加模製材料109。可使用例如壓縮模製（compression molding）、轉移模製（transfer molding）、或其他方法將模製材料109進行模製。
接下來，在一些實施例中，使用固化製程來固化模製材料109。固化製程可包括使用退火製程或其他加熱製程將模製材料109加熱至預定溫度一段預定的時間。固化製程也可包括紫外（UV）光曝光製程、紅外（IR）能量曝光製程、前述之組合、或具有加熱製程的前述之組合。或者，可使用其他方法來固化模製材料109。在一些實施例中，不包括固化製程。
在形成模製材料109之後，可進行像是化學機械平坦化（chemical and mechanical planarization；CMP）的平坦化製程以將模製材料109多餘的部分從晶粒101之上方移除，使得模製材料109和晶粒101具有一個共平面的上表面。如第1圖所示，模製材料109與基底211相接（conterminous）。
在第1圖的例子中，晶圓上晶片（CoW）結構包括中介片200、晶粒101、底部填充材料107、和模製材料109。接下來，將晶圓上晶片（CoW）結構接合到基板300以形成基板上晶圓上晶片（CoWoS）結構，所述基板300可為印刷電路板（PCB）。
關於基板300，在一些實施例中，基板300是多層電路板。例如，基板300可包括由雙馬來醯亞胺-三氮雜環（bismaleimide triazine；BT）樹脂、FR-4（由編織玻璃纖維布和具有阻燃性的環氧樹脂黏著劑構成的複合材料）、陶瓷、玻璃、塑料、膠帶、薄膜、或其他支持（supporting）材料形成的一個或多個介電層321/323/325。基板300可包括形成在基板300中/上的導電部件（例如，導線327和導孔結構（via）329）。如第1圖所示，基板300具有形成在基板300上表面上的導電焊墊326，以及形成在基板300下表面上的導電焊墊328，導電焊墊326/328電性耦合到基板300的導電部件。如第1圖所示，外部連接器331（例如焊球、銅柱、或頂部具有銲錫的銅柱）形成於導電焊墊328上。
將中介片200接合到基板300。可進行回焊製程以透過例如銲錫區域217將中介片200電性地和機械地耦合到基板300。接著，形成底部填充材料112於中介片200和基板300之間。底部填充材料112可與底部填充材料107相同或相似，並且可透過相同或類似的形成方法形成，因此不再重複細節。在將中介片200接合到基板300之後，形成第1圖中的基板上晶圓上晶片（CoWoS）結構。
隨著半導體裝置100的積體密度增加，可將更多的晶粒101附接到中介片200以在半導體封裝內實現更多功能。其結果，中介片200的尺寸可能會增加。隨著中介片200的尺寸增加，維持中介片200的導電凸塊（例如中介片200下表面處的導電凸塊231）的共平面性（例如，平坦度、水平）變得越來越困難。可透過導電凸塊231遠離基底211的端面（end surfaces）之間的最大偏移（offset）來測量導電凸塊231的共平面性。例如，可透過計算位於中介片200的中心區域和周邊區域中的導電凸塊231的最低表面之間的最大差異（例如，最大偏移）來測量導電凸塊231的共平面性。做為另一個示例，可使用商業上可獲得的設備並使用合適的測量方法，例如峰-最小均方（Peak-to-Least Mean Square；LMS）法，來測量導電凸塊231的共平面性。因此，導電凸塊的最低表面之間的較大差異表示較差的共平面性，這可能導致像是冷接合（cold-joint）或橋接（例如，導電凸塊之間的電性短路）的問題，從而降低製程的產量。本發明實施例中的各種實施例方法和結構改善了導電凸塊231的共平面性，從而提高了所形成的半導體裝置100的可靠性並提高了產量。
第2圖顯示出在一些實施例中用於第1圖的中介片200下表面上的導電凸塊231之佈局（也可稱為佈局設計或設計）。因此，第2圖是中介片200的下表面的平面圖。特別地，第2圖顯示出中介片200的下表面形成導電凸塊231的區域（例如，401、402、和403），且每一個區域可具有不同的凸塊圖案密度，關於第2圖的佈局細節（例如，如何決定不同區域的邊界）將在下文中討論。為達簡潔的目的，並未在第2圖中顯示區域（例如，401、402、和403）中的導電凸塊231，但顯示於第3圖中。
第3圖顯示出中介片200的下表面形成有導電凸塊231的區域。第3圖所示區域可以是第2圖中所示之任何區域（例如，401、402、和403）、或第2圖中所示之區域（例如，401、402、和403）的一部分。凸塊231的形狀示例顯示於第4A圖和第4B圖中。特別地，第4A圖顯示出具有直徑R的圓形剖面之凸塊231，第4B圖顯示出具有橢圓形剖面的凸塊231，其具有第一尺寸R1和第二尺寸R2，其中沿著橢圓形的縱向（例如，沿橢圓形的縱軸方向）測量第二尺寸R2，並沿著垂直於縱向的方向測量第一尺寸R1。在所示實施例中，第3圖的平面圖中之凸塊231的形狀和尺寸與凸塊231的剖面（例如，沿著第1圖中的剖面A-A）的形狀和尺寸相同。因此，在一些實施例中，如上所述，凸塊231的形狀和尺寸對應（例如，相同）於罩幕層中用於形成凸塊231的凸塊開口的形狀和尺寸。
回去參照第2圖，區域401表示具有凸塊231之第一圖案密度的區域，區域402表示具有凸塊231之第二圖案密度的區域，而區域403表示具有凸塊231之第三圖案密度的區域，其中用詞「圖案密度」是指區域（例如，中介片200的下表面區域）內的凸塊231密度。
可透過將區域中凸塊231的總面積除以所述區域的面積來計算區域中凸塊231的圖案密度。在第3圖的例子中，所示區域是具有寬度b和長度a的矩形區域，因此具有a×b的面積。所述區域中凸塊231的總面積是所述區域內凸塊231的面積（例如，第3圖的平面圖中的凸塊231之圓形或橢圓形的面積）總和。在下文的討論中，區域中凸塊231的圖案密度可被稱為區域的圖案密度、或者區域的凸塊圖案密度。在所示實施例中，區域401具有大於約25％的圖案密度，區域402具有介於約15％至約25％的圖案密度，且區域403具有小於約15％的圖案密度。在下文的討論中，區域401可被稱為高圖案密度區域，區域402可被稱為中等圖案密度區域，而區域403可被稱為低圖案密度區域。
在第2圖的例子中，區域401包括連續區域（例如，矩形區域），區域402包括四個分離的（separate）區域（例如，四個矩形區域），而區域403除了區域401和402之外還包括中介片200下表面的區域。第2圖中之區域（例如，401、402、403）的數量、區域的位置、以及區域的形狀僅用於說明而非用以限制，其他的區域數量、其他的區域位置、以及其他的區域形狀也是可能的，並且完全包含在本發明實施例的範圍內。
在先前的製程中，在沒有本發明實施例的情況下，用來在不同區域（例如，401、402、和403）中形成凸塊231之凸塊開口的尺寸是相同的，因此，形成於不同區域中的導電凸塊231具有相同的橫剖面積。然而，觀察到透過使用相同的凸塊開口尺寸，形成於具有高圖案密度的區域中之凸塊231比起形成於具有低圖案密度的區域中之凸塊231可具有較小的高度。不同圖案密度的區域中之導電凸塊231的高度差可被視為是因圖案密度變化所造成的導電凸塊231的（高度）負載效應（loading effect）。負載效應導致導電凸塊231的共平面性惡化。不受特定理論的限制，據信在形成凸塊231的鍍覆製程中，化學流體具有大致均勻的金屬離子濃度，因此，具有高圖案密度的區域中之每一個凸塊231可具有較少的金屬離子，因此，形成於高圖案密度區域中的凸塊231比起形成於低圖案密度區域中的凸塊231可具有較小的高度。
本發明實施例中的各種方法縮小了具有不同圖案密度的區域中之凸塊231的高度差，從而改善了凸塊231的共平面性。第5圖顯示出透過調整凸塊231的尺寸（例如，橫剖面積）來縮小凸塊231高度之間差異的方法，使得不同區域（例如，401、402、403）中的凸塊231尺寸是不同的。特別地，低圖案密度區域403中的凸塊231尺寸和中等圖案密度區域402中的凸塊231尺寸相對於高圖案密度區域401中的凸塊231尺寸增加（參照下述細節）。應注意的是，如上述討論的，可透過調整罩幕層中用於形成凸塊231的凸塊開口之尺寸來實現凸塊231的尺寸調整。
在一些實施例中，第5圖中所示的方法開始於接收用於導電凸塊231的第一佈局設計（例如，使用此處所揭示的方法做為改善共平面性的起點之現有設計）。第一佈局設計（也可稱為第一設計）可包括凸塊231的尺寸（例如，橫剖面積）和凸塊231的位置。在下文的討論中，假設所有區域（例如，401、402、403）中的凸塊231都具有相同的尺寸（例如，橫剖面積），第2圖的佈局設計可用做第一設計的示例。然後，修改第2圖的設計以形成第二設計，所述第二設計實現了凸塊231共平面性的改善，其細節將在下文中討論。
接下來，第5圖的方法評估（例如，計算）在中介片200下表面的不同區域中之凸塊圖案密度。基於不同區域中的凸塊231之圖案密度，第5圖的方法將凸塊231分組為高圖案密度區域401（例如，圖案密度≥25％）、中等圖案密度區域402（例如，圖案密度介於約15％至約25％）、或低圖案密度區域403（例如，圖案密度≤15％）。換句話說，所述方法將中介片200的下表面分成三個區域（參照第2圖中的401、402、403），例如高圖案密度區域401、中等圖案密度區域402、和低圖案密度區域403。
在一些實施例中，決定不同區域（例如，401、402、和403）的邊界可包括：將中介片200的下表面分為複數個未重疊的網格狀（grid-shaped）小區域（例如，尺寸為約1 mm×約0.5 mm的矩形區域）、計算每一個小區域中的凸塊圖案密度、並基於計算出來的圖案密度將每一個小區域分配給區域（例如，401、402、403）之一。在一些實施例中，第一設計可具有形成為簇（clusters）的凸塊231，且每一個凸塊簇具有不同的凸塊圖案密度，在這種情況下，每一個凸塊231簇的邊界可做為分配到所述凸塊簇的區域之邊界。這些和其他用來決定不同區域的邊界之方式完全包含在本發明實施例的範圍內。
接下來，第5圖的方法修改第一佈局設計以形成第二佈局設計（也可稱為第二設計）。特別地，在第二佈局設計中，將低圖案密度區域403中的凸塊231尺寸（例如，橫剖面積）和中等圖案密度區域402中的凸塊231尺寸（例如，橫剖面積）調整（例如，增加）為高於高圖案密度區域401中的凸塊231尺寸（例如，橫剖面積）。在所示實施例中，高圖案密度區域401中的凸塊231尺寸在第一佈局設計和第二佈局設計之間保持不變。
在一些實施例中，透過增加罩幕層的凸塊開口（例如，用於鍍覆製程以形成凸塊231）尺寸來實現低圖案密度區域和中等圖案密度區域中的凸塊231尺寸（例如，橫剖面積）之增加。特別地，假設第一佈局設計中的凸塊231在所有區域（例如，401、402、403）中都具有直徑為R的圓形，接著應用第5圖的方法，將中等圖案密度區域402中的凸塊開口（例如，圓形）之直徑R’調整為介於約1.1R至約1.25R，並且將低圖案密度區域403中的凸塊開口之直徑R’’調整為介於約1.35R至約1.55R。高圖案密度區域401中的凸塊開口之直徑保持為R。
如果第一佈局設計中的開口在所有區域（例如，401、402、403）中都具有橢圓形且具有第一尺寸R1和第二尺寸R2，則在第二設計中，將中等圖案密度區域402中的凸塊開口（例如，橢圓形）調整為具有第一尺寸R1’和第二尺寸R2’，其中R1’介於約1.1R1至約1.25R1，第二尺寸R2’介於約1.1R2至約1.25R2。另外，將低圖案密度區域403中的凸塊開口（例如，橢圓形）調整為具有第一尺寸R1’’和第二尺寸R2’’，其中R1’’介於約1.35R1至約1.55R1，且第二尺寸R2’’介於約1.35R2至約1.55R2。高圖案密度區域401中的開口仍具有第一尺寸R1和第二尺寸R2。
如上所述，將中等圖案密度區域402和低圖案密度區域403中的凸塊開口尺寸調整為大於高圖案密度區域401中凸塊開口尺寸的一預定百分比。由於凸塊開口的尺寸對應於（例如，等於）隨後形成的凸塊231之橫剖面積，因此，使用第二佈局設計形成於具有不同圖案密度的區域中之導電凸塊231具有不同的橫剖面積。 此外，上述討論之不同區域中的凸塊開口的尺寸之間的關係也適用於使用第二佈局設計形成於不同區域中的導電凸塊231之尺寸（例如，第4A圖中的圓形直徑，或第4B圖中橢圓形的第一尺寸和第二尺寸）。
第5圖的方法可包括額外的製程步驟，例如根據第二佈局設計形成導電凸塊231。在第2圖的例子中，區域401是高圖案密度區域、區域402是中等圖案密度區域、區域403是低圖案密度區域。因此，在根據第二佈局設計形成導電凸塊231之後，區域403中的導電凸塊231比起區域402中的導電凸塊231具有更大的橫剖面積，且區域402中的導電凸塊231比起區域401中的導電凸塊231具有更大的橫剖面積。
做為示例，考慮第一設計，其中，高圖案密度區域401中的凸塊231具有70 μm的第一尺寸R1和90 μm的第二尺寸R2。在調整低圖案密度區域403和中等圖案密度區域402中的凸塊尺寸之後，在第二設計中，中等圖案密度區域402中的凸塊231具有82 μm的第一尺寸和105 μm的第二尺寸，且低圖案密度區域403中的凸塊231具有98 μm的第一尺寸和125 μm的第二尺寸。
第6圖顯示出在另一個實施例中用來改善導電凸塊231共平面性的方法。在第6圖的實施例中，製程開始於接收用於導電凸塊231的第一設計，並評估中介片200的下表面上不同區域的凸塊圖案密度。基於不同區域中的凸塊圖案密度，將導電凸塊231分組為不同區域，例如高圖案密度區域401（例如，圖案密度≥25％）、中等圖案密度區域402（例如，圖案密度介於約15％至約25％）、或低圖案密度區域403（例如，圖案密度≤15％）。製程類似於上述參照第5圖所討論的製程，因此不再重複細節。在所示實施例中，在第一設計中，高圖案密度區域401中的凸塊節距P1小於中等圖案密度區域402中的凸塊節距P2，且中等圖案密度區域402中的凸塊節距P2小於低圖案密度區域403中的凸塊節距P3。
接下來，修改第一設計以產生第二設計。特別地，調整低圖案密度區域403中凸塊231的節距和中等圖案密度區域402中凸塊231的節距，以與高圖案密度區域401中凸塊231的節距匹配。在一些實施例中，添加虛設凸塊231D（參照第7B圖）於例如低圖案密度區域403和中等圖案密度區域402中現有的凸塊231之間，以調整（例如，降低）相鄰的凸塊231/231D之間的凸塊節距，使得低圖案密度區域403和中等圖案密度區域402中經調整的凸塊節距與高圖案密度區域401的凸塊節距匹配，其中虛設凸塊231D是電性隔離的導電凸塊（例如，不與其他電性導電部件電性耦合）。相反地，每一個導電凸塊231與中介片200的至少一個導電部件（例如，接觸墊、穿孔結構215、或其類似物）電性耦合。可使用與凸塊231相同的材料並在與凸塊231相同的製程步驟中形成虛設凸塊231D。應注意的是，此處的「匹配」（match）可為製造限制內節距之間的匹配，或是百分比內節距之間的匹配。例如，低圖案密度區域403和中等圖案密度區域402中的凸塊節距在高圖案密度區域401中的凸塊節距的一預定百分比內（例如，在±15％、±10％、或±5％內）。
做為示例，考慮第一設計，其中，高圖案密度區域401中的凸塊節距P1為150 μm，中等圖案密度區域402中的凸塊節距P2為180 μm，而低圖案密度區域4003中的凸塊節距P3為250 μm。在修改凸塊節距之後，所有區域（例如，401、402、403）中的凸塊231之凸塊節距具有150 μm的相同凸塊節距。
在所示實施例中，不同區域（例如，401、402、403）中的凸塊231之橫剖面積在第一設計和第二設計之間不改變。在一些實施例中，不同區域（例如，401、402、403）中的凸塊231的橫剖面積是相同的。第6圖的方法可包括額外的製程步驟，例如根據第二設計形成凸塊231和虛設凸塊231D。
第7A圖和第7B圖分別顯示出在一實施例中應用第6圖所示方法之前和之後的中介片下表面區域內之導電凸塊231。第7A圖和第7B圖中所示區域可例如為低圖案密度區域403中的區域或中等圖案密度區域402中的區域。如第7A圖所示，第一設計中的凸塊231之間的節距例如為250 μm。第7B圖顯示出形成於凸塊231之間的虛設凸塊231D。舉例而言，虛設凸塊231D可形成於同一列（row）中相鄰的凸塊231之間。此外，第7B圖也顯示出形成於兩列相鄰的凸塊231之間的一列虛設凸塊231D（虛線矩形600內）。在形成虛設凸塊231D的情況下，凸塊（例如，231和231D）的節距縮小到例如125 μm，以與高圖案密度區域401的節距密度匹配。
第8A圖利用一實施例方法顯示出用於中介片200下表面上的導電凸塊231之佈局設計。在第8A圖的例子中，接收並評估第一設計（參照例如第2圖）。計算第一設計的不同區域之圖案密度。基於所計算的圖案密度，將凸塊231分組為不同區域，例如高圖案密度區域401（例如，圖案密度≥25％）、中等圖案密度區域402（例如，圖案密度介於約15％至約25％）、或低圖案密度區域403（例如，圖案密度≤15％）。在第8A圖的實施例中，不同區域（例如，401、402、403）中的凸塊231之橫剖面積是相同的。在第8A圖中，高圖案密度區域401具有凸塊節距P1，中等圖案密度區域402具有凸塊節距P2，而低圖案密度區域403具有凸塊節距P3。在所示實施例中，凸塊節距P1小於凸塊節距P2，且凸塊節距P2小於凸塊節距P3。
為了縮小具有不同圖案密度的區域中的導電凸塊231之高度差，第8A圖的實施例方法透過添加虛設凸塊231D（參見第8B圖）於沿著中介片200的周邊200P（例如，側壁）而設置的區域404（以陰影圖案顯示於第8A圖中）中來修改第一設計以形成第二設計，使得區域404中的凸塊節距P4與高圖案密度區域401中的凸塊節距P1匹配。應注意的是，此處的「匹配」（match）可為製造限制內節距之間的匹配，或是高圖案密度區域401中凸塊節距的百分比內（例如，±15％、±10％、或±5％內）節距之間的匹配。
如第8A圖所示，區域404具有中空的矩形形狀，但是在本發明實施例的範圍內也可考慮其他合適的形狀。在第一設計中，區域404可被選擇為包括中介片200下表面上的凸塊231之最外側N列及/或最外側N欄，其中N是介於5至15的數字，例如5、10、或15。換句話說，區域404和中介片200的周邊200P之間沒有凸塊（231或231D）。因此，在第二設計中，區域404具有形成於其內的虛設凸塊231D和導電凸塊231，且第8A圖中的其他區域（例如，401、402、和403）僅具有導電凸塊231（例如，不是虛設凸塊231D）形成於其內。
在第8A圖所示的實施例中，區域404圍繞高圖案密度區域401、中等圖案密度區域402、和低圖案密度區域403。應注意的是，在第8A圖中，區域404包括先前屬於低圖案密度區域403的區域。因此，在第8A圖所示的第二設計中，區域403包括中介片200下表面之區域，其位於區域404內，但並不是區域401/402。
做為示例，考慮第一設計，其中，高圖案密度區域401中的凸塊節距P1為150 μm，中等圖案密度區域402中的凸塊節距P2為180 μm，而低圖案密度區域4003中的凸塊節距P3為250 μm。在第二設計中，虛設凸塊231D形成於區域404中，使得凸塊之間（例如，231和231D之間）的凸塊節距P4為150 μm。第8A圖的方法可包括額外的製程步驟，例如根據第二設計形成凸塊231和虛設凸塊231D。
在第8A圖的實施例中，所有區域（401、402、403）中的凸塊231之橫剖面積是相同的，且在第一設計和第二設計之間不改變。此外，在所示實施例中，區域404中的虛設凸塊231D之橫剖面積與導電凸塊231之橫剖面積相同。
第8B圖顯示出第8A圖所示區域404的部分710放大視圖。如第8B圖所示，虛設凸塊231D形成於凸塊231之間。第8B圖也顯示出形成於兩列導電凸塊231之間的一列虛設凸塊231D（虛線矩形500中）。區域404的凸塊節距（例如，231和231D之間）是P4，其中P4與高圖案密度區域401的凸塊節距P1匹配。
所揭示之實施例的變型（variations）是可能的，並且完全包含在本發明實施例的範圍內。例如，雖然各個實施例方法是調整凸塊尺寸（例如，橫剖面積）或凸塊節距，但也可透過調整凸塊尺寸和凸塊節距兩者來改善凸塊231的共平面性。例如，可在調整各個區域中的凸塊節距的同時，調整各個區域（例如，401、402、403）中的凸塊開口尺寸。此外，儘管在形成導電凸塊231於中介片200下表面上的背景下描述了本發明實施例，但是所揭示的方法可用於改善形成於其他元件及/或其他表面（例如，上表面而非下表面）上的導電凸塊之共平面性。
實施例可實現許多優點。透過在導電凸塊231的設計中調整凸塊尺寸（例如，橫剖面積）或凸塊節距，縮小了具有不同圖案密度的區域中的凸塊高度間的差異，並且改善了導電凸塊的共平面性。經改善的共平面性避免或減少了像是冷結合（例如，無法適當接合兩個裝置的導電凸塊之劣質銲錫區域）或凸塊橋接之類的問題，從而改善所形成裝置的可靠性並提高了產量。在沒有本發明實施例方法的情況下，為了滿足導電凸塊的共平面性需求，參照方法可能必須降低電鍍的速度、及/或可能必須在用於電鍍的化學流體中增加金屬離子濃度（例如，Ag的濃度），這降低了生產量並增加了製造成本。本發明實施例避免了這些問題，因此實現了生產量的增加（例如，更高的電鍍速度）和製造成本的降低。
第9、10、11圖根據一些實施例分別顯示出製造半導體裝置的方法1000、2000、和3000的流程圖。應理解的是，第9、10、11圖中所示的實施例方法僅僅是許多可能的實施例方法的示例。本技術領域具有通常知識者應可了解許多變化、替代、和修改。例如，可以添加、移除、取代、重置、和重複如第9、10、11圖所示的各種步驟。
參照第9圖，在方法1000的方框1010處，接收用於中介片的第一表面上的導電凸塊的第一設計，第一設計中的導電凸塊具有相同的橫剖面積。在方框1020處，將第一設計中的導電凸塊分組為第一表面的第一區域中的第一組導電凸塊和第一表面的第二區域中的第二組導電凸塊，其中第二區域的凸塊圖案密度小於第一區域的凸塊圖案密度。在方框1030處，透過修改第一設計來形成第二設計，其中修改第一設計包括修改第二區域中的第二組導電凸塊的橫剖面積。在方框1040處，根據第二設計形成導電凸塊於中介片的第一表面上，其中，在形成之後，第一組導電凸塊和第二組導電凸塊具有不同的橫剖面積。
參照第10圖，在方法2000的方框2010處，分析用於工件的第一表面上的導電凸塊的第一設計，其中所述分析包括將工件的第一表面分成具有第一導電凸塊的第一區域和具有第二導電凸塊的第二區域，其中第一區域中的第一導電凸塊的第一凸塊圖案密度大於第二區域中的第二導電凸塊的第二凸塊圖案密度，其中第一區域中的第一導電凸塊的第一凸塊節距小於第二區域中的第二導電凸塊的第二凸塊節距。在方框2020處，修改第一設計以產生第二設計，其中所述修改第一設計包括添加虛設凸塊於第二區域中以縮小第二凸塊節距。在方框2030處，根據第二設計，形成導電凸塊和虛設凸塊於工件的第一表面上。在方框2040處，透過導電凸塊將工件接合到基板。
參照第11圖，在方法3000的方框3010處，接收用於工件的第一表面上的導電凸塊的第一設計，第一設計中的導電凸塊具有相同的橫剖面積，其中導電凸塊包括第一表面的第一區域中的第一導電凸塊和第一表面的第二區域中的第二導電凸塊，其中第二區域圍繞第一區域，其中第二凸塊的第二凸塊節距大於第一凸塊的第一凸塊節距。在方框3020處，透過在第二區域中添加虛設凸塊來將第一設計改變為第二設計以縮小第二凸塊節距，使得第二凸塊節距大致上與第一凸塊節距匹配。在方框3030處，根據第二設計，形成導電凸塊於工件的第一表面上。
在一實施例中，一種方法包括接收用於中介片的第一表面上之複數個導電凸塊的第一設計，所述第一設計中的所述導電凸塊具有相同的橫剖面積；將所述第一設計中的所述導電凸塊分組為所述第一表面的第一區域中的第一組導電凸塊和所述第一表面的第二區域中的第二組導電凸塊，其中所述第二區域的凸塊圖案密度小於所述第一區域的凸塊圖案密度；透過修改所述第一設計來形成第二設計，其中修改所述第一設計包括修改所述第二區域中的所述第二組導電凸塊的橫剖面積；以及，根據所述第二設計形成導電凸塊於所述中介片的第一表面上，其中，在形成之後，所述第一組導電凸塊和所述第二組導電凸塊具有不同的橫剖面積。在一實施例中，第一組導電凸塊的尺寸在第一設計和第二設計中保持不變。
在一實施例中，形成所述導電凸塊包括：形成圖案化罩幕層於所述中介片的第一表面之上，所述圖案化罩幕層具有複數個凸塊開口；以及，進行電鍍製程以形成導電材料於所述圖案化罩幕層的凸塊開口中。在一實施例中，所述第一區域中之凸塊開口的尺寸小於所述第二區域中之凸塊開口的尺寸。在一實施例中，所述第一區域的凸塊圖案密度大於約25％。在一實施例中，在第二設計中，所述第一組導電凸塊具有第一剖面，所述第一剖面具有第一尺寸，所述第二組導電凸塊具有第二剖面，所述第二剖面具有相應的第二尺寸，其中如果所述第二區域的凸塊圖案密度介於約15％至約25％，則所述第二尺寸介於所述第一尺寸的約1.1倍至約1.25倍，且其中如果所述第二區域的凸塊圖案密度小於約15％，則所述第二尺寸介於所述第一尺寸的約1.35倍至約1.55倍。在一實施例中，將第一設計中的所述導電凸塊分組更包括：將所述第一表面的第三區域中的第三組導電凸塊分組，其中所述第三區域的凸塊圖案密度小於所述第二區域的凸塊圖案密度。在一實施例中，形成第二設計更包括修改所述第三區域中的第三組導電凸塊的橫剖面積。在一實施例中，所述第一區域的凸塊圖案密度大於約25％，所述第二區域的凸塊圖案密度介於約15％至約25％，且所述第三區域的凸塊圖案密度小於約15％。在一實施例中，在第二設計中，所述第一組導電凸塊具有第一剖面，所述第一剖面具有第一尺寸，所述第二組導電凸塊具有第二剖面，所述第二剖面具有相應的第二尺寸，且所述第三組導電凸塊具有第三剖面，所述第三剖面具有相應的第三尺寸，其中所述第二尺寸介於所述第一尺寸的約1.1倍至約1.25倍，且所述第三尺寸介於所述第一尺寸的約1.35倍至約1.55倍。在一實施例中，所述第一剖面、第二剖面、和第三剖面是幾何相似的形狀。在一實施例中，所述方法更包括將基板附接到所述中介片的導電凸塊。
在一實施例中，一種方法包括：分析用於工件的第一表面上之複數個導電凸塊的第一設計，其中所述分析包括將工件的第一表面分成具有複數個第一導電凸塊的第一區域和具有複數個第二導電凸塊的第二區域，其中所述第一區域中的第一導電凸塊的第一凸塊圖案密度大於所述第二區域中的第二導電凸塊的第二凸塊圖案密度，其中所述第一區域中的第一導電凸塊的第一凸塊節距小於所述第二區域中的第二導電凸塊的第二凸塊節距；修改所述第一設計以產生第二設計，其中修改所述第一設計包括添加複數個虛設凸塊於所述第二區域中以縮小所述第二凸塊節距；根據所述第二設計，形成導電凸塊和虛設凸塊於所述工件的第一表面上；以及，透過所述導電凸塊將所述工件接合到基板。在一實施例中，所述第一凸塊圖案密度大於約25％。在一實施例中，所述虛設凸塊是由與所述導電凸塊相同的材料形成，且所述虛設凸塊是電性隔離的。
在一實施例中，一種半導體裝置包括：附接至中介片的上表面之晶粒；複數個第一導電凸塊，位於所述中介片的下表面的第一區域中，所述第一區域具有第一凸塊圖案密度；複數個第二導電凸塊，位於所述中介片的下表面的第二區域中，所述第二區域具有小於所述第一凸塊圖案密度的第二凸塊圖案密度；以及，複數個虛設凸塊，位於所述中介片的下表面的周邊區域中，所述周邊區域圍繞所述第一區域和所述第二區域。在一實施例中，所述第一區域中的第一導電凸塊具有第一凸塊節距，所述第二區域中的第二導電凸塊具有大於所述第一凸塊節距的第二凸塊節距，且所述周邊區域中的虛設凸塊具有與所述第一個凸塊節距匹配的第三凸塊節距。在一實施例中，所述半導體裝置更包括：位於所述中介片下表面的第三區域中的複數個第三導電凸塊，所述第三區域具有小於所述第二凸塊圖案密度的第三凸塊圖案密度，所述第三區域具有大於所述第二凸塊節距的第四凸塊節距，其中所述周邊區域圍繞所述第一區域、第二區域、和第三區域。在一實施例中，所述第一凸塊圖案密度大於約25％。在一實施例中，所述第一導電凸塊和所述第二導電凸塊具有相同的橫剖面積。
前述內文概述了許多實施例的部件，以使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的精神與範圍。在不背離本發明的精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100:半導體裝置 101:晶粒 103:導電柱 105,217:銲錫區域 107,112:底部填充材料 109:模製材料 200:中介片 200P:周邊 211:基底 213,326,328:導電焊墊 215:穿孔結構 219:表面介電層 230:凸塊下金屬（UBM）結構 231,231D:凸塊 300:基板 321,323,325:介電層 327:導線 329:導孔結構 331:外部連接器 401,402,403,404:區域 500,600:虛線矩形 710:部分 1000,2000,3000:方法 1010,1020,1030,1040:方框 2010,2020,2030,2040:方框 3010,3020,3030:方框 a:長度 b:寬度 A-    A:剖面 R,R’,R’’,R1,R1’,R1’’,R2,R2’,R2’’:直徑 P1,P2,P3,P4:凸塊節距
本發明實施例可配合以下圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準慣例，各個部件（feature）並未按照比例繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個部件的尺寸。 ［第1圖］根據一些實施例顯示出半導體裝置的剖面圖。 ［第2圖］顯示出在一些實施例中用於中介片表面上的導電凸塊之佈局。 ［第3圖］顯示出在一些實施例中的中介片表面區域內的導電凸塊。 ［第4A和4B圖］顯示出在一些實施例中具有不同形狀的導電凸塊之俯視圖。 ［第5圖］顯示出在一實施例中改善導電凸塊的共平面性之方法。 ［第6圖］顯示出在一實施例中改善導電凸塊的共平面性之方法。 ［第7A和7B圖］顯示出在一實施例中應用第6圖所示方法之前和之後的中介片表面區域內的導電凸塊。 ［第8A圖］顯示出在一些實施例中用於中介片表面上的導電凸塊之佈局。 ［第8B圖］顯示出第8A圖所示佈局的部分放大視圖。 ［第9圖］顯示出在一些實施例中形成半導體裝置的方法流程圖。 ［第10圖］顯示出在一些實施例中形成半導體裝置的方法流程圖。 ［第11圖］顯示出在一些實施例中形成半導體裝置的方法流程圖。
無。
1000:方法
1010,1020,1030,1040:方框

Claims (20)

  1. 一種半導體裝置的形成方法，包括： 接收用於一中介片的一第一表面上之複數個導電凸塊的一第一設計，該第一設計中的該些導電凸塊具有相同的橫剖面積； 將該第一設計中的該些導電凸塊分組為該第一表面的一第一區域中的一第一組導電凸塊和該第一表面的一第二區域中的一第二組導電凸塊，其中該第二區域的一凸塊圖案密度小於該第一區域的一凸塊圖案密度； 透過修改該第一設計來形成一第二設計，其中修改該第一設計包括修改該第二區域中的該第二組導電凸塊的一橫剖面積；以及 根據該第二設計形成該些導電凸塊於該中介片的該第一表面上，其中，在形成之後，該第一組導電凸塊和該第二組導電凸塊具有不同的橫剖面積。
  2. 如請求項1之半導體裝置的形成方法，其中該第一組導電凸塊的一尺寸在該第一設計和該第二設計中保持不變。
  3. 如請求項1之半導體裝置的形成方法，其中形成該些導電凸塊包括： 形成一圖案化罩幕層於該中介片的該第一表面之上，該圖案化罩幕層具有複數個凸塊開口；以及 進行一鍍覆(plating)製程以形成一導電材料於該圖案化罩幕層的該些凸塊開口中。
  4. 如請求項3之半導體裝置的形成方法，其中該第一區域中之該些凸塊開口的一尺寸小於該第二區域中之該些凸塊開口的一尺寸。
  5. 如請求項1之半導體裝置的形成方法，其中該第一區域的一凸塊圖案密度大於約25％。
  6. 如請求項5之半導體裝置的形成方法，其中，在該第二設計中，該第一組導電凸塊具有一第一剖面，該第一剖面具有一第一尺寸，且該第二組導電凸塊具有一第二剖面，該第二剖面具有相應的一第二尺寸，其中如果該第二區域的該凸塊圖案密度介於約15％至約25％，則該第二尺寸介於該第一尺寸的約1.1倍至約1.25倍，且其中如果該第二區域的該凸塊圖案密度小於約15％，則該第二尺寸介於該第一尺寸的約1.35倍至約1.55倍。
  7. 如請求項1之半導體裝置的形成方法，其中將該第一設計中的該些導電凸塊分組更包括：將該第一表面的一第三區域中的一第三組導電凸塊分組，其中該第三區域的一凸塊圖案密度小於該第二區域的一凸塊圖案密度。
  8. 如請求項7之半導體裝置的形成方法，其中形成該第二設計更包括修改該第三區域中的該第三組導電凸塊的一橫剖面積。
  9. 如請求項8之半導體裝置的形成方法，其中該第一區域的一凸塊圖案密度大於約25％，該第二區域的該凸塊圖案密度介於約15％至約25％，且該第三區域的該凸塊圖案密度小於約15％。
  10. 如請求項9之半導體裝置的形成方法，其中，在該第二設計中，該第一組導電凸塊具有一第一剖面，該第一剖面具有一第一尺寸，該第二組導電凸塊具有一第二剖面，該第二剖面具有相應的一第二尺寸，且該第三組導電凸塊具有一第三剖面，該第三剖面具有相應的一第三尺寸，其中該第二尺寸介於該第一尺寸的約1.1倍至約1.25倍，且該第三尺寸介於該第一尺寸的約1.35倍至約1.55倍。
  11. 如請求項10之半導體裝置的形成方法，其中該第一剖面、該第二剖面、和該第三剖面是幾何相似的形狀。
  12. 如請求項1之半導體裝置的形成方法，更包括將一基板附接到該中介片的該些導電凸塊。
  13. 一種半導體裝置的形成方法，包括： 分析用於一工件的一第一表面上之複數個導電凸塊的一第一設計，其中該分析包括將該工件的該第一表面分成具有複數個第一導電凸塊的一第一區域和具有複數個第二導電凸塊的一第二區域，其中該第一區域中的該些第一導電凸塊的一第一凸塊圖案密度大於該第二區域中的該些第二導電凸塊的一第二凸塊圖案密度，其中該第一區域中的該些第一導電凸塊的一第一凸塊節距小於該第二區域中的該些第二導電凸塊的一第二凸塊節距； 修改該第一設計以產生一第二設計，其中修改該第一設計包括添加複數個虛設凸塊於該第二區域中以縮小該第二凸塊節距； 根據該第二設計，形成該些導電凸塊和該些虛設凸塊於該工件的該第一表面上；以及 透過該些導電凸塊將該工件接合到一基板。
  14. 如請求項13之半導體裝置的形成方法，其中該第一凸塊圖案密度大於約25％。
  15. 如請求項13之半導體裝置的形成方法，其中該些虛設凸塊是由與該些導電凸塊相同的材料形成，且該些虛設凸塊是電性隔離的。
  16. 一種半導體裝置，包括： 一晶粒，附接至一中介片的一上表面； 複數個第一導電凸塊，位於該中介片的一下表面的一第一區域中，該第一區域具有一第一凸塊圖案密度； 複數個第二導電凸塊，位於該中介片的該下表面的一第二區域中，該第二區域具有小於該第一凸塊圖案密度的一第二凸塊圖案密度；以及 複數個虛設凸塊，位於該中介片的該下表面的一周邊區域中，該周邊區域圍繞該第一區域和該第二區域。
  17. 如請求項16之半導體裝置，其中該第一區域中的該些第一導電凸塊具有一第一凸塊節距，該第二區域中的該些第二導電凸塊具有大於該第一凸塊節距的一第二凸塊節距，且該周邊區域中的該些虛設凸塊具有與該第一個凸塊節距匹配的一第三凸塊節距。
  18. 如請求項17之半導體裝置，其中更包括位於該中介片的該下表面的該第三區域中的複數個第三導電凸塊，該第三區域具有小於該第二凸塊圖案密度的一第三凸塊圖案密度，該第三區域具有大於該第二凸塊節距的一第四凸塊節距，其中該周邊區域圍繞該第一區域、該第二區域、和該第三區域。
  19. 如請求項16之半導體裝置，其中該第一凸塊圖案密度大於約25％。
  20. 如請求項16之半導體裝置，其中該第一導電凸塊和該第二導電凸塊具有相同的橫剖面積。
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