WO2023115633A1 - 一种基于预放大级结构的比较器及模数转换器 - Google Patents

一种基于预放大级结构的比较器及模数转换器 Download PDF

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WO2023115633A1
WO2023115633A1 PCT/CN2021/143489 CN2021143489W WO2023115633A1 WO 2023115633 A1 WO2023115633 A1 WO 2023115633A1 CN 2021143489 W CN2021143489 W CN 2021143489W WO 2023115633 A1 WO2023115633 A1 WO 2023115633A1
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nmos transistor
amplification stage
node
pmos transistor
gate
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PCT/CN2021/143489
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English (en)
French (fr)
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徐代果
蒋和全
李儒章
王健安
付东兵
陈光炳
俞宙
张正平
朱璨
高炜祺
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重庆吉芯科技有限公司
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Publication of WO2023115633A1 publication Critical patent/WO2023115633A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

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  • the invention relates to the technical field of integrated circuits, in particular to a comparator and an analog-to-digital converter based on a pre-amplification stage structure.
  • a single-stage latch structure can be used as the comparator structure.
  • the advantages of the single-stage latch structure are fast speed and low power consumption, but the disadvantages are large noise and offset.
  • the comparator in order to suppress the shortcomings of high noise and high offset of the single-stage latch structure, the comparator is usually a structure in which multiple stages of pre-amplification are cascaded and then connected to the latch stage.
  • the disadvantage of adopting the structure of multi-stage pre-amplifier cascaded and then connected to the latch stage is that during the reset process of the comparator, due to the existence of the output capacitor of the pre-amplifier stage, the reset speed of the comparator will be significantly reduced. increase the power consumption of the comparator.
  • the invention provides a comparator and an analog-to-digital converter based on a pre-amplification stage structure to solve the problem of high noise of the comparator in the prior art.
  • the present invention provides a comparator based on a pre-amplification stage structure, including:
  • the first pre-amplification stage whose input terminal is connected to a differential input signal, amplifies and outputs the differential input signal, and outputs a first differential output signal;
  • the second pre-amplification stage its input terminal is connected to the first differential output signal, the first differential output signal is amplified and output, and the second differential output signal is output, and a positive feedback is provided between its output terminal and its input terminal A unit that increases the voltage gain of the second pre-amplification stage through the positive feedback unit;
  • the input terminal of the latch is connected to the second differential output signal.
  • the comparator based on the pre-amplification stage structure further includes one pre-amplification stage, and the pre-amplification stage is connected in series between the first pre-amplification stage and the second pre-amplification stage.
  • the comparator based on the pre-amplification stage structure also includes N pre-amplification stages, N is an integer greater than or equal to 2, and the N pre-amplification stages are cascaded and connected in series to the first pre-amplifier stage and the second pre-amplification stage.
  • the structure of the N pre-amplification stages is the same as that of the second pre-amplification stage.
  • the first pre-amplification stage includes;
  • a first NMOS transistor a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
  • the source of the first NMOS transistor is grounded, the gate of the first NMOS transistor is connected to the first control signal, and the drain of the first NMOS transistor is connected to the first node;
  • the source of the second NMOS transistor is connected to the first node, the gate of the second NMOS transistor is connected to the differential input signal, and the drain of the second NMOS transistor is connected to the second node;
  • the source of the third NMOS transistor is connected to the first node, the gate of the third NMOS transistor is connected to the differential input signal, and the drain of the third NMOS transistor is connected to the third node;
  • the drain of the first PMOS transistor is connected to the second node, the gate of the first PMOS transistor is connected to the first control signal, and the source of the first PMOS transistor is connected to an operating voltage;
  • the drain of the second PMOS transistor is connected to the third node, the gate of the second PMOS transistor is connected to the first control signal, and the source of the second PMOS transistor is connected to the operating voltage;
  • the first differential output signal is output through the second node and the third node.
  • the second pre-amplification stage includes a pre-amplification stage main unit and the positive feedback unit, and the positive feedback unit includes:
  • the gate of the fourth NMOS transistor is connected to the fourth node, the source of the fourth NMOS transistor is connected to the fifth node, and the drain of the fourth NMOS transistor is connected to the gate of the seventh NMOS transistor ;
  • the source of the fifth NMOS transistor is connected to the fifth node, the gate of the fifth NMOS transistor is connected to the sixth node, the drain of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor pole connection;
  • the source of the sixth NMOS transistor is connected to the sixth node, and the drain of the sixth NMOS transistor is connected to the seventh node;
  • the source of the seventh NMOS transistor is connected to the fourth node, and the drain of the seventh NMOS transistor is connected to the eighth node.
  • the pre-amplification main body unit includes:
  • the source of the eighth NMOS transistor is grounded, and the drain of the eighth NMOS transistor is connected to the fifth node;
  • the second control signal is respectively connected to the gate of the eighth NMOS transistor, the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor, the gate of the sixth
  • the gate of the PMOS transistor is connected, and the operating voltage is respectively connected to the source of the third PMOS transistor, the source of the fourth PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor. connect;
  • the drain of the third PMOS transistor is connected to the eighth node, the drain of the fourth PMOS transistor is connected to the seventh node, and the drain of the fifth PMOS transistor is connected to the fourth NMOS transistor.
  • the drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor;
  • the first differential output signal is respectively connected to the fourth node and the sixth node, and the second differential output signal is output through the seventh node and the eighth node.
  • the latch includes a sampling unit and a holding unit;
  • the input terminals of the sampling unit are respectively connected to the sixth node and the eighth node, and the sampling unit samples the second differential output signal
  • the output terminal of the sampling unit is connected to the holding unit, and the holding unit holds the second differential output signal.
  • the first control signal and the second control signal are the same control signal.
  • the present invention provides an analog-to-digital converter, which includes the above-mentioned comparator based on the pre-amplification stage structure.
  • the comparator based on the pre-amplification stage structure in the present invention includes a first pre-amplification stage and a second pre-amplification stage, and a positive feedback unit is set between the input end and the output end of the second pre-amplification stage
  • the voltage gain of the second pre-amplification stage is increased through the positive feedback unit, especially the voltage gain of the small signal is increased, thereby effectively reducing the equivalent input noise of the comparator.
  • Figure 1 shows a schematic diagram of the principle of a multi-stage cascaded comparator
  • Figure 2 shows a circuit diagram of a conventional one-stage pre-amplification stage and a one-stage latch cascaded comparator
  • Figure 3 shows a circuit diagram of a traditional one-stage pre-amplification stage and one-stage latch cascaded high-precision comparator
  • Fig. 4 shows the comparator based on the pre-amplification stage structure among the present invention
  • Fig. 5 is shown as the second pre-amplification stage input impedance circuit diagram and its small signal circuit equivalent diagram in the present invention
  • Fig. 6 is shown as the second pre-amplification stage output impedance circuit diagram and its small signal circuit equivalent diagram in the present invention
  • Fig. 7 shows the noise equivalent circuit diagram of the first pre-amplification stage and the second pre-amplification stage half-side circuit in the present invention
  • FIG. 8 is a comparison diagram of the equivalent input noise of three comparators in the present invention as a function of temperature.
  • the comparator in the case of high precision requirements, in order to suppress the high noise and high offset shortcomings of the single-stage latch structure, the comparator is usually cascaded with multi-stage pre-amplification stages and then connected with the latch The storage stages are connected, and the pre-amplification stage provides higher gain to suppress the equivalent input noise of the comparator; the output signal of the pre-amplification stage changes slowly to suppress the offset of the comparator.
  • the first input signal Vip and the second input signal Vin are amplified by multi-stage pre-amplification stages (Preamp-1, Preamp-2, ..., Preamp-n) and then input to the latch (Latch), The large noise and large offset of the latch (Latch) will not affect the comparison accuracy of the comparator.
  • FIG. 2 shows the circuit diagram of a traditional one-stage pre-amplification stage and one-stage latch cascaded comparator, as shown in Figure 2, NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, PMOS transistor P1 and PMOS transistor P2 constitute A pre-amplification stage, wherein NMOS transistor N1 is a tail current transistor, NMOS transistor N2 and NMOS transistor N3 are input transistors, PMOS transistor P1 and PMOS transistor P2 are load transistors; NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and NMOS transistor N7, NMOS transistor N8, NMOS transistor N9, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5 and PMOS transistor P6 form a latch.
  • NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, PMOS transistor P1 and PMOS transistor P2 constitute A pre-amplification stage, wherein NMOS transistor N1 is a tail current transistor, NMOS transistor N2 and NMOS transistor N3 are
  • the control signal clk When the comparator is in the reset state, the control signal clk is 0 (low level), so that the NMOS transistor N1, NMOS transistor N4 and NMOS transistor N7 are turned off, and the entire comparator has no static power consumption; when the comparator is in the comparison state , the control signal clk is 1 (high level), and the DC gain A of the pre-amplification stage can be expressed as:
  • gm represents the transconductance of NMOS transistor N2 and NMOS transistor N3, r oN2, N3 represents the small signal equivalent output impedance of NMOS transistor N2 and NMOS transistor N3, r oP1, P2 represents the small signal of PMOS transistor P1 and PMOS transistor P2 Equivalent output impedance.
  • the dominant pole p of the pre-amplification stage can be expressed as:
  • Cp represents the load capacitance at the output terminal of the pre-amplification stage.
  • the advantages of this kind of comparator are fast speed and low power consumption, but the disadvantage is that the noise and offset are large.
  • the bandwidth of the amplification stage can reduce the equivalent input noise of the pre-amplification stage: From the formula (1), when the pre-amplification stage design is completed, the input tube transconductance gm, the input tube small-signal equivalent output impedance roN2, N3 and The small-signal equivalent output impedance roP1 and P2 of the load tube are fixed, and it is difficult to increase the DC gain A of the pre-amplification stage; at the same time, since the bandwidth of the pre-amplification stage is related to the main pole p, reducing the main pole p can reduce the corresponding Small bandwidth, therefore, if you want to reduce the equivalent input noise of the pre-amplification stage, it can be achieved by reducing the main pole p of the
  • a high-precision comparator is proposed, as shown in Figure 3, based on the structure of a cascaded comparator with one-stage pre-amplification stage and one-stage latch as shown in Figure 2, in the pre-amplification stage
  • the output terminal increases capacitance C, thus increases the load capacitance Cp of the pre-amplification stage, reduces the bandwidth of the pre-amplification stage, and plays a good role in the equivalent input noise of the pre-amplification stage inhibition.
  • the noise is no longer the main factor limiting the performance of the comparator.
  • the comparator will be significantly reduced. The reset speed increases the power consumption of the comparator.
  • a comparator based on the pre-amplification stage structure includes a first pre-amplification stage and a second pre-amplification stage, and the A positive feedback unit is set to increase the voltage gain of the second pre-amplification stage through the positive feedback unit, especially to increase the voltage gain of the small signal, so as to reduce the equivalent input noise of the comparator.
  • the present invention provides a comparator based on a pre-amplification stage structure, which includes: a first pre-amplification stage, the input terminal of which is connected to a differential input signal, amplifies and outputs the differential input signal, and outputs a first differential output signal; Two pre-amplification stages, the input end of which is connected to the first differential output signal, the first differential output signal is amplified and output, and the second differential output signal is output, and a positive feedback unit is arranged between the output end and the input end thereof, through the The positive feedback unit increases the voltage gain of the second pre-amplification stage; the latch, whose input terminal is connected to the second differential output signal.
  • the comparator based on the pre-amplification stage structure further includes a pre-amplification stage, and the pre-amplification stage is connected in series between the first pre-amplification stage and the second pre-amplification stage.
  • the structure of the pre-amplification stage is the same as that of the second pre-amplification stage.
  • the structure of the pre-amplification stage is the same as that of the first pre-amplification stage.
  • the comparator based on the pre-amplification stage structure also includes N pre-amplification stages, N is an integer greater than or equal to 2, and the N pre-amplification stages are cascaded and connected in series between the first pre-amplification stage and the second pre-amplification stage between levels.
  • N pre-amplification stages is an integer greater than or equal to 2
  • the structure of the N pre-amplification stages is the same as that of the second pre-amplification stage.
  • the structure of the N pre-amplification stages is the same as that of the first pre-amplification stage.
  • the present invention also provides an analog-to-digital converter, which includes the comparator based on the pre-amplification stage structure, and the fast and accurate comparison of the comparator based on the pre-amplification stage structure can improve the The operating efficiency of the analog-to-digital converter.
  • the first pre-amplification stage includes a first NMOS transistor M0, a second NMOS transistor M1, a third NMOS transistor M2, a first PMOS transistor M3, and a second PMOS transistor M4; the source of the first NMOS transistor M0 is grounded , the gate of the first NMOS transistor M0 is connected to the first control signal Clk, the drain of the first NMOS transistor M0 is connected to the first node a; the source of the second NMOS transistor M1 is connected to the first node a, and the second NMOS transistor M1 The gate of the second NMOS transistor M1 is connected to the positive terminal Vinp of the differential input signal, the drain of the second NMOS transistor M1 is connected to the second node b; the source of the third NMOS transistor M2 is connected to the first node a, and the gate of the third NMOS transistor M2 The pole is connected to the negative terminal Vinn of the differential input signal, the drain of the third NMOS transistor M2 is connected
  • a control signal Clk the source of the first PMOS transistor M3 is connected to the working voltage Vdd; the drain of the second PMOS transistor M4 is connected to the third node c, the gate of the second PMOS transistor M4 is connected to the first control signal Clk, and the second PMOS transistor M4
  • the source of the tube M4 is connected to the working voltage Vdd; the first differential output signal is output through the second node b and the third node c, the second node b is used as the output negative terminal of the first differential output signal, and the third node c is used as the first differential output signal The positive output terminal of the output signal.
  • the second pre-amplification stage includes a pre-amplification stage main unit and a positive feedback unit, wherein the positive feedback unit includes: a fourth NMOS transistor M6, a fifth NMOS transistor M7, a sixth NMOS transistor M8, and a seventh NMOS transistor M9; the fourth NMOS transistor The gate of M6 is connected to the fourth node d, the source of the fourth NMOS transistor M6 is connected to the fifth node e, the drain of the fourth NMOS transistor M6 is connected to the gate of the seventh NMOS transistor M9; the fifth NMOS transistor M7 The source of the fifth NMOS transistor M7 is connected to the fifth node e, the gate of the fifth NMOS transistor M7 is connected to the sixth node f, the drain of the fifth NMOS transistor M7 is connected to the gate of the sixth NMOS transistor M8; the gate of the sixth NMOS transistor M8 The source is connected to the sixth node f, the drain of the sixth NMOS transistor is connected to the seventh node
  • the main unit of the pre-amplification stage includes: the eighth NMOS transistor M5, the third PMOS transistor M10, the fourth PMOS transistor M11, the fifth PMOS transistor M12 and the sixth PMOS transistor M13; the source of the eighth NMOS transistor M5 is grounded, and the eighth NMOS transistor M5
  • the drain of the transistor M5 is connected to the fifth node e; the second control signal Clk is respectively connected to the gate of the eighth NMOS transistor M5, the gate of the third PMOS transistor M10, the gate of the fourth PMOS transistor M11, the gate of the fifth PMOS transistor
  • the gate of M12 and the gate of the sixth PMOS transistor M13 are connected, and the operating voltage Vdd is respectively connected to the source of the third PMOS transistor M10, the source of the fourth PMOS transistor M11, the source of the fifth PMOS transistor M12, and the source of the sixth PMOS transistor M13.
  • the source of the transistor M13 is connected; the drain of the third PMOS transistor M10 is connected to the eighth node h, the drain of the fourth PMOS transistor M11 is connected to the seventh node g, and the drain of the fifth PMOS transistor M12 is connected to the fourth NMOS transistor
  • the drain of M6 is connected, the drain of the sixth PMOS transistor M13 is connected to the drain of the fifth NMOS transistor; the first differential output signal is respectively connected to the fourth node d and the sixth node f, wherein the first differential output signal
  • the negative terminal Vn is connected to the sixth node f, the positive terminal Vp of the first differential output signal is connected to the fourth node d; the second differential output signal is output through the seventh node g and the eighth node h, and the positive terminal Vp of the second differential output signal is The terminal Vop is connected to the eighth node h, and the negative terminal Von of the second differential output signal is connected to the seventh node g.
  • the positive terminal Vop and the negative terminal Von of the second differential output signal are connected to the input terminal of the latch, and the latch outputs the third differential output signals Voutp and Voutn.
  • the output terminals Voutp and Voutn of the latch structure are the output terminals of the entire comparator.
  • the first control signal and the second control signal are the same control signal.
  • the latch includes a sampling unit and a holding unit; the input terminals of the sampling unit are respectively connected to the sixth node and the eighth node, and the sampling unit samples the second differential output signal; the output terminal of the sampling unit is connected to the holding unit, The holding unit holds the second differential output signal.
  • ix is the input current of this stage
  • g m9 is the gate transconductance of M9
  • v mb9 is the substrate transconductance of M9
  • v x is the input voltage
  • r o9 is the small signal output impedance of M9;
  • g m6 is the gate transconductance of M6, r o6 is;
  • the input impedance of the second preamp stage can be expressed as the small-signal output impedance of M6:
  • R in,2 is the input impedance of the second pre-amplification stage
  • a v1 is the gain of the first pre-amplification stage
  • g m2 is the gate transconductance of M2;
  • i out is the output current of this stage
  • v gs9 is the gate-source voltage of M9
  • v bs9 is the lining-source voltage of M9
  • G m,2 is the transconductance of the second stage
  • v id is the input current of this stage
  • G m,total is the total transconductance of the first pre-amplification stage and the second pre-amplification stage
  • i out, dif is the output small signal current of this stage
  • v gs6 is
  • the equivalent output impedance of the second pre-amplification stage can be expressed as:
  • R out,2 g m9 r o9 g m6 r o6 r o2 +(g m9 +g mb9 )r o9 r o2 +r o9 +r o2 (17)
  • Rout,2 is the equivalent output impedance of the second pre-amplification stage
  • the gain of the second pre-amplification stage can be expressed as:
  • a v2 is the gain of the second pre-amplification stage
  • the total gain of the first pre-amplification stage and the second pre-amplification stage can be expressed as:
  • Av,total is the total gain of the first pre-amplification stage and the second pre-amplification stage
  • the structure of the first two pre-amplification stages proposed by the present invention can provide a large small-signal voltage gain, so the pre-amplification stage of this structure can provide very high precision.
  • v n1 (I n2 +I n9 )(r o2
  • v n1 is the output noise voltage of M2
  • I n2 is the output noise current of M2
  • I n9 is the output noise current of M9
  • r o2 is the small signal output impedance of M2
  • R in,2 is the equivalent of M6 gate impedance
  • v n2 is the output noise voltage of this stage
  • I n6 is the output noise current of this stage
  • r o6 is the small signal output impedance of M6
  • g m6 is the gate transconductance of M6,
  • R in,2 is the gate of M6 The equivalent impedance;
  • v n,out is the output noise voltage of this stage
  • g m9 is the gate transconductance of M9
  • r o9 is the small signal output resistance of M9
  • g mb9 is the substrate transconductance of M9;
  • Fig. 8 Under the 180nm CMOS process, the structures of the above-mentioned Fig. 2, Fig. 3 and Fig. 4 are carefully designed, and the same input/output tube size is adopted for the above-mentioned three structures , the latch structure also adopts the same size, and the load capacitance is 10fF.
  • the clock frequency is 1.8GHz
  • the power supply voltage is 1.8V
  • the common-mode voltage is 0.9V.
  • 0.9V, the comparator is considered to complete the comparison.
  • the comparison curves of the change of the comparison time of the above three comparators with the change of the input differential signal ⁇ Vin are shown in FIG. 8 .
  • the above-mentioned comparator based on the pre-amplification stage structure introduces a positive feedback unit on the basis of the pre-amplification stage, and the voltage gain of the second pre-amplification stage is improved through the positive feedback unit, especially the voltage gain of the small signal is improved. In turn, the equivalent input noise of the comparator can be effectively reduced.
  • the present invention also provides an analog-to-digital converter, which includes the above-mentioned comparator based on the pre-amplification stage structure.
  • the present invention also provides an electronic device, which includes the above-mentioned analog-to-digital converter.
  • the comparator based on the pre-amplification stage structure of the present invention is provided with a positive feedback unit between the input terminal and the output end of the second pre-amplification stage, and the voltage gain of the second pre-amplification stage is improved through the positive feedback unit, In particular, the voltage gain of the small signal is improved, thereby effectively reducing the equivalent input noise of the comparator.

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Abstract

本发明适用于集成电路技术领域，提供了一种基于预放大级结构的比较器及模数转换器，该比较器包括：第一预放大级，其输入端接差分输入信号，对差分输入信号进行放大输出，输出第一差分输出信号；第二预放大级，其输入端连接第一差分输出信号，对第一差分输出信号进行放大输出，输出第二差分输出信号，且其输出端与其输入端之间设置有正反馈单元，通过正反馈单元提高第二预放大级的电压增益；锁存器，其输入端接第二差分输出信号；通过正反馈单元提高第二预放大级的电压增益，尤其是提高了小信号的电压增益，进而能有效降低了比较器的等效输入噪声。

Description

一种基于预放大级结构的比较器及模数转换器 技术领域
本发明涉及集成电路技术领域，特别是涉及一种基于预放大级结构的比较器及模数转换器。
背景技术
近年来，随着集成电路制造技术的不断发展，CMOS器件的特征尺寸不断减小，集成电路的工作电压也不断降低。在深亚微米工艺下，模数转换器的工作速度得到了极大的提高，同时，功耗进一步降低。但是，作为模数转换器的核心组成部分，比较器的性能成了高速低功耗设计的瓶颈。传统的几种比较器结构，很难同时满足速度、功耗和低电源电压等要求。
在精度要求较低的场合，可以采用单级锁存器结构作为比较器结构，单级锁存器该结构的优点在于速度快，功耗低，但缺点是噪声和失调较大。在精度要求较高的场合，为了抑制单级锁存器结构高噪声和高失调的缺点，比较器通常由多级预放大级级联后，再与锁存级相连的结构。但是，采用由多级预放大级级联再与锁存级相连的结构的缺点在于，在比较器的复位过程中，由于预放大级输出端电容的存在，会明显降低比较器的复位速度，增加比较器的功耗。
发明内容
本发明提供了一种基于预放大级结构的比较器及模数转换器，以解决现有技术中比较器噪声大的问题。
为实现上述目的及其他相关目的，本发明提供一种基于预放大级结构的比较器，包括：
第一预放大级，其输入端接差分输入信号，对所述差分输入信号进行放大输出，输出第一差分输出信号；
第二预放大级，其输入端连接所述第一差分输出信号，对所述第一差分输出信号进行放大输出，输出第二差分输出信号，且其输出端与其输入端之间设置有正反馈单元，通过所述正反馈单元提高所述第二预放大级的电压增益；
锁存器，其输入端接所述第二差分输出信号。
可选的，所述基于预放大级结构的比较器还包括1个预放大级，所述预放大级串接在所述第一预放大级与所述第二预放大级之间。
可选的，所述基于预放大级结构的比较器还包括N个预放大级，N为大于等2的整数，N个所述预放大级级联设置后串接在所述第一预放大级与所述第二预放大级之间。
可选的，N个所述预放大级的结构与所述第二预放大级的结构相同。
可选的，所述第一预放大级包括；
第一NMOS管、第二NMOS管、第三NMOS管、第一PMOS管以及第二PMOS管；
所述第一NMOS管的源极接地，所述第一NMOS管的栅极接第一控制信号，所述第一NMOS管的漏极接第一节点；
所述第二NMOS管的源极与所述第一节点连接，所述第二NMOS管的栅极与所述差分输入信号连接，所述第二NMOS管的漏极与第二节点连接；
所述第三NMOS管的源极与所述第一节点连接，所述第三NMOS管的栅极与所述差分输入信号连接，所述第三NMOS管的漏极与第三节点连接；
所述第一PMOS管的漏极接所述第二节点，所述第一PMOS管的栅极接所述第一控制信号，所述第一PMOS管的源极接工作电压；
所述第二PMOS管的漏极接所述第三节点，所述第二PMOS管的栅极接所述第一控制信号，所述第二PMOS管的源极接所述工作电压；
所述第一差分输出信号通过所述第二节点、所述第三节点输出。
可选的，所述第二预放大级包括预放大级主体单元和所述正反馈单元，所述正反馈单元包括：
第四NMOS管、第五NMOS管、第六NMOS管以及第七NMOS管；
所述第四NMOS管的栅极与第四节点连接，所述第四NMOS管的源极与第五节点连接，所述第四NMOS管的漏极与所述第七NMOS管的栅极连接；
所述第五NMOS管的源极与所述第五节点连接，所述第五NMOS管的栅极与第六节点连接，所述第五NMOS管的漏极与所述第六NMOS管的栅极连接；
所述第六NMOS管的源极与所述第六节点连接，所述第六NMOS管的漏极与第七节点连接；
所述第七NMOS管的源极与所述第四节点连接，第七NMOS管的漏极与第八节点连接。
可选的，所述预放大级主体单元包括：
第八NMOS管、第三PMOS管、第四PMOS管、第五PMOS管以及第六PMOS管；
所述第八NMOS管的源极接地，所述第八NMOS管的漏极与所述第五节点连接；
第二控制信号分别与所述第八NMOS管的栅极、所述第三PMOS管的栅极、所述第四PMOS管的栅极、所述第五PMOS管的栅极、所述第六PMOS管的栅极连接，工作电压分别与所述第三PMOS管的源极、所述第四PMOS管的源极、所述第五PMOS管的源极、所述第六PMOS管的源极连接；
所述第三PMOS管的漏极与所述第八节点连接，所述第四PMOS管的漏极与所述第七节点连接，所述第五PMOS管的漏极与所述第四NMOS管的漏极连接，所述第六PMOS管的漏极与所述第五NMOS管的漏极连接；
所述第一差分输出信号分别与所述第四节点、所述第六节点连接，所述第二差分输出信号通过所述第七节点、所述第八节点输出。
可选的，所述锁存器包括采样单元及保持单元；
所述采样单元的输入端分别与所述第六节点、所述第八节点连接，所述采样单元对所述第二差分输出信号进行采样；
所述采样单元的输出端接所述保持单元，所述保持单元对所述第二差分输出信号进行保持。
可选的，所述第一控制信号和所述第二控制信号为同一控制信号。
为实现上述目的及其他相关目的，本发明提供一种模数转换器，所述模数转换器包括上述基于预放大级结构的比较器。
本发明的有益效果：本发明中的基于预放大级结构的比较器包括第一预放大级和第二预放大级，通过在第二预放大级的输入端与输出端之间设置正反馈单元，通过正反馈单元提高第二预放大级的电压增益，尤其是提高了小信号的电压增益，进而能有效降低了比较器的等效输入噪声。
附图说明
图1显示为多级级联比较器的原理示意图；
图2显示为传统一级预放大级和一级锁存器级联比较器的电路图；
图3显示为传统一级预放大级和一级锁存器级联高精度比较器的电路图；
图4显示为本发明中基于预放大级结构的比较器；
图5显示为本发明中第二预放大级输入阻抗电路图及其小信号电路等效图；
图6显示为本发明中第二预放大级输出阻抗电路图及其小信号电路等效图；
图7显示为本发明中第一预放大级和第二预放大级半边电路的噪声等效电路图；
图8显示为本发明中三种比较器等效输入噪声随温度变化对比图。
具体实施方式
如前述在背景技术中所提及的，在精度要求较高的场合，为了抑制单级锁存器结构的高噪声和高失调缺点，比较器通常由多级预放大级级联后再与锁存级相连，通过预放大级提供较高的增益，对比较器的等效输入噪声进行抑制；通过预放大级输出信号较缓慢的变化，对 比较器的失调进行抑制。如图1所示，第一输入信号Vip和第二输入信号Vin经过多级预放大级(Preamp-1、Preamp-2、…、Preamp-n)的放大后再输入锁存器(Latch)，使得锁存器(Latch)的大噪声和大失调不会影响比较器的比较精度。
为了更详细的描述上述问题，以一级预放大级和一级锁存器的级联为例，分析两种传统结构比较器的工作原理和优缺点。
图2显示为传统的一级预放大级和一级锁存器级联比较器的电路图，如图2所示，NMOS管N1、NMOS管N2、NMOS管N3、PMOS管P1及PMOS管P2构成预放大级，其中，NMOS管N1为尾电流管，NMOS管N2和NMOS管N3为输入管，PMOS管P1及PMOS管P2为负载管；NMOS管N4、NMOS管N5、NMOS管N6、NMOS管N7、NMOS管N8、NMOS管N9、PMOS管P3、PMOS管P4、PMOS管P5及PMOS管P6构成锁存器。当比较器处于复位状态时，控制信号clk为0(低电平)，使得NMOS管N1、NMOS管N4及NMOS管N7被关断，整个比较器没有静态功耗；当比较器处于比较状态时，控制信号clk为1(高电平)，预放大级的直流增益A可表示为：
A＝g m·(r oN2,N3||r oP1,P2)  (1)
其中，gm表示NMOS管N2和NMOS管N3的跨导，r oN2,N3表示NMOS管N2和NMOS管N3的小信号等效输出阻抗，r oP1,P2表示PMOS管P1和PMOS管P2的小信号等效输出阻抗。
此时，预放大级的主极点p可表示为：
p＝1/((r oN2,N3||r oP1,P2)Cp)  (2)
其中，Cp表示预放大级输出端的负载电容。
这种比较器的优点在于速度快，功耗低，但缺点是噪声和失调较大，由预放大级的等效输入噪声的计算公式可知，如果增加预放大级的直流增益A或者减小预放大级的带宽，可以减小预放大级的等效输入噪声：由式(1)可知，当预放大级设计完成之后，输入管跨导gm、输入管小信号等效输出阻抗roN2,N3和负载管的小信号等效输出阻抗roP1,P2都是固定的，增加预放大级的直流增益A比较困难；同时，由于预放大级的带宽与主极点p相关，减小主极点p可相应减小带宽，因此，如果要减小预放大级的等效输入噪声，可以通过减小预放大级的主极点p来实现，由式(2)可知，需要增大预放大级的负载电容Cp。
基于上述分析，提出了一种高精度比较器，如图3所示，在如图2所示的一级预放大级和一级锁存器级联比较器结构的基础上，在预放大级的输出端(节点1和节点2处)增加了电容C，从而增大了预放大级的负载电容Cp，降低了预放大级的带宽，对预放大级的等效输入噪声起到了较好的抑制作用。但是，当预放大级的输出电压经过放大之后，噪声已经不是限 制比较器性能的主要因素，同时，在比较器的复位过程中，由于预放大级输出端电容C的存在，会明显降低比较器的复位速度，增加比较器的功耗。
因此，发明人提出了一种新的构想：一种基于预放大级结构的比较器包括第一预放大级和第二预放大级，通过在第二预放大级的输入端与输出端之间设置正反馈单元，通过正反馈单元提高第二预放大级的电压增益，尤其是要提高小信号的电压增益，以降低比较器的等效输入噪声。
具体地，本发明提供一种基于预放大级结构的比较器，其包括：第一预放大级，其输入端接差分输入信号，对差分输入信号进行放大输出，输出第一差分输出信号；第二预放大级，其输入端连接第一差分输出信号，对第一差分输出信号进行放大输出，输出第二差分输出信号，且其输出端与其输入端之间设置有正反馈单元，通过所述正反馈单元提高所述第二预放大级的电压增益；锁存器，其输入端接第二差分输出信号。
可选地，基于预放大级结构的比较器还包括1个预放大级，预放大级串接在第一预放大级与第二预放大级之间。可选地，预放大级的结构与第二预放大级的结构相同。可选地，预放大级的结构与第一预放大级的结构相同。
可选地，基于预放大级结构的比较器还包括N个预放大级，N为大于等2的整数，N个预放大级级联设置后串接在第一预放大级与第二预放大级之间。可选地，N个预放大级的结构与第二预放大级的结构相同。可选地，N个预放大级的结构与第一预放大级的结构相同。
此外，本发明还提供一种模数转换器，所述模数转换器包括所述基于预放大级结构的比较器，通过所述基于预放大级结构的比较器快速精准的比较来提高所述模数转换器的工作效率。
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
请参阅图4至图8。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条 件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
请参阅图4，第一预放大级包括第一NMOS管M0、第二NMOS管M1、第三NMOS管M2、第一PMOS管M3以及第二PMOS管M4；第一NMOS管M0的源极接地，第一NMOS管M0的栅极接第一控制信号Clk，第一NMOS管M0的漏极接第一节点a；第二NMOS管M1的源极与第一节点a连接，第二NMOS管M1的栅极与差分输入信号的正端Vinp连接，第二NMOS管M1的漏极与第二节点b连接；第三NMOS管M2的源极与第一节点a连接，第三NMOS管M2的栅极与差分输入信号的负端Vinn连接，第三NMOS管M2的漏极与第三节点c连接；第一PMOS管M3的漏极接第二节点b，第一PMOS管M3的栅极接第一控制信号Clk，第一PMOS管M3的源极接工作电压Vdd；第二PMOS管M4的漏极接第三节点c，第二PMOS管M4的栅极接第一控制信号Clk，第二PMOS管M4的源极接工作电压Vdd；第一差分输出信号通过第二节点b、第三节点c输出，第二节点b作为第一差分输出信号的输出负端，第三节点c作为第一差分输出信号的输出正端。
第二预放大级包括预放大级主体单元和正反馈单元，其中，正反馈单元包括：第四NMOS管M6、第五NMOS管M7、第六NMOS管M8以及第七NMOS管M9；第四NMOS管M6的栅极与第四节点d连接，第四NMOS管M6的源极与第五节点e连接，第四NMOS管M6的漏极与第七NMOS管M9的栅极连接；第五NMOS管M7的源极与第五节点e连接，第五NMOS管M7的栅极与第六节点f连接，第五NMOS管M7的漏极与第六NMOS管M8的栅极连接；第六NMOS管M8的源极与第六节点f连接，第六NMOS管的漏极与第七节点g连接；第七NMOS管M9的源极与第四节点d连接，第七NMOS管M9的漏极与第八节点h连接。预放大级主体单元包括：第八NMOS管M5、第三PMOS管M10、第四PMOS管M11、第五PMOS管M12以及第六PMOS管M13；第八NMOS管M5的源极接地，第八NMOS管M5的漏极与第五节点e连接；第二控制信号Clk分别与第八NMOS管M5的栅极、第三PMOS管M10的栅极、第四PMOS管M11的栅极、第五PMOS管M12的栅极、第六PMOS管M13的栅极连接，工作电压Vdd分别与第三PMOS管M10的源极、第四PMOS管M11的源极、第五PMOS管M12的源极、第六PMOS管M13的源极连接；第三PMOS管M10 的漏极与第八节点h连接，第四PMOS管M11的漏极与第七节点g连接，第五PMOS管M12的漏极与第四NMOS管M6的漏极连接，第六PMOS管M13的漏极与第五NMOS管的漏极连接；第一差分输出信号分别与第四节点d、第六节点f连接，其中，第一差分输出信号的负端Vn与第六节点f连接，第一差分输出信号的正端Vp与第四节点d连接；第二差分输出信号通过第七节点g、第八节点h输出，第二差分输出信号的正端Vop与第八节点h，第二差分输出信号的负端Von与第七节点g。第二差分输出信号的正端Vop和负端Von与锁存器的输入端连接，锁存器输出第三差分输出信号Voutp和Voutn。其中，锁存结构的输出端Voutp和Voutn为整个比较器的输出端。
可选地，第一控制信号与第二控制信号为同一控制信号。可选地，锁存器包括采样单元及保持单元；采样单元的输入端分别与第六节点、第八节点连接，采样单元对第二差分输出信号进行采样；采样单元的输出端接保持单元，保持单元对第二差分输出信号进行保持。
请参阅图5、图6和图7，首先，计算第二预放大级的输入阻抗，第二预放大级的输入级电路图和其小信号等效电路如图5所示。通过第七NMOS管M9栅极的基尔霍夫电流定律可知：
Figure PCTCN2021143489-appb-000001
其中，i x为本级输入电流，g m9为M9的栅极跨导，v mb9为M9的衬底跨导，v x为输入电压，r o9为M9的小信号输出阻抗；
Figure PCTCN2021143489-appb-000002
其中，g m6为M6的栅极跨导，r o6为；
因此，第二预放大级的输入阻抗可表示为M6的小信号输出阻抗：
Figure PCTCN2021143489-appb-000003
其中，R in,2为第二预放大级输入阻抗；
由于第一预放大级的增益可以表示为：
Figure PCTCN2021143489-appb-000004
其中，A v1为第一预放大级的增益，g m2为M2的栅极跨导；
为了计算第二预放大级的小信号电压增益，需要计算第二预放大级的跨导G m,1和输出阻抗，通过M9漏极的基尔霍夫电流定律可知：
Figure PCTCN2021143489-appb-000005
其中，i out为本级输出电流，v gs9为M9的栅源电压，v bs9为M9的衬源电压；
Figure PCTCN2021143489-appb-000006
Figure PCTCN2021143489-appb-000007
其中，G m,2为第二级的跨导；
由式(9)可知，第二预放大级的跨导非常大，通过比较式(5)和式(9)，第二预放大级的输入阻抗和跨导呈倒数关系，可表示为：
Figure PCTCN2021143489-appb-000008
接下来，需要计算第一预放大级和第二预放大级总的跨导，由图5可知：
Figure PCTCN2021143489-appb-000009
其中，v id为本级的输入电流；
Figure PCTCN2021143489-appb-000010
其中，G m,total为第一预放大级和第二预放大级总的跨导；
Figure PCTCN2021143489-appb-000011
由式(10)和式(13)可知，总的跨导可表示为：
Figure PCTCN2021143489-appb-000012
其中，i out,dif为本级的查分输出小信号电流；
为了计算第二级预放大级的等效输出阻抗，其小信号等效电路如图6所示，通过M9漏极的基尔霍夫定律可知：
Figure PCTCN2021143489-appb-000013
其中，v gs6为；
Figure PCTCN2021143489-appb-000014
从而，第二预放大级的等效输出阻抗可表示为：
R out,2＝g m9r o9g m6r o6r o2+(g m9+g mb9)r o9r o2+r o9+r o2  (17)
其中，Rout,2为第二预放大级的等效输出阻抗；
因此，第二预放大级的增益可表示为：
Figure PCTCN2021143489-appb-000015
其中，A v2为第二预放大级的增益；
可以得到，第一预放大级和第二预放大级的总增益可表示为：
Figure PCTCN2021143489-appb-000016
其中，A v,total为第一预放大级和第二预放大级的总增益；
由式(19)可知，本发明所提出的前两级预放大级结构能够提供很大的小信号电压增益，因此，该结构的预放大级可以提供很高的精度。
下面对该结构的噪声性能进行分析，以半边电路进行计算，第一预放大级和第二预放大级半边电路的噪声等效电路如图7所示。
v n1＝(I n2+I n9)(r o2||R in,2)≈(I n2+I n9)R in,2  (20)
其中，v n1为M2的输出噪声电压，I n2为M2的输出噪声电流，I n9为M9的输出噪声电流，r o2为M2的小信号输出阻抗，R in,2为M6栅极的等效阻抗；
v n2＝I n6r o6+v n1g m6r o6＝I n6r o6+(I n2+I n9)R in,2g m6r o6  (21)
其中，v n2为本级的输出噪声电压，I n6为本级的输出噪声电流，r o6为M6的小信号输出阻抗，g m6为M6的栅极跨导，R in,2为M6栅极的等效阻抗；
因此，可以得到：
v n,out＝I n9r o9+g m9r o9I n6r o6+r o9(I n2+I n9)R in,2(g m9+g mb9+g m9g m6r o6)  (22)
其中，v n,out为本级的输出噪声电压，g m9为M9的栅极跨导，r o9为M9的小信号输出电阻，g mb9为M9的衬底跨导；
将式(5)带入式(22)可得：
Figure PCTCN2021143489-appb-000017
其中，
Figure PCTCN2021143489-appb-000018
为前两级预放大级的等效输出噪声，k为玻尔兹曼常数，T为温度，γ为常数。
从而，前两级预放大级的等效输入噪声可表示为：
Figure PCTCN2021143489-appb-000019
其中，
Figure PCTCN2021143489-appb-000020
为前两级预放大级的等效输入噪声。
由式(24)可知，由于存在一个很大的小信号电压增益，该结构预放大级的等效输入噪声明显降低了。
请参阅图8，在一个具体的实施例中，在180nm CMOS工艺下，对上述图2、图3和图4的结构进行了仔细的设计，对于上述三种结构采用相同的输入/输出管尺寸，锁存器结构也采用相同的尺寸，负载电容都取10fF。时钟频率为1.8GHz，电源电压为1.8V，共模电压取0.9V，当|Dp-Dn|＝0.9V时，认为比较器完成比较。上述三种结构比较器的比较时间随输入差分信号ΔVin变化而变化的对比曲线如图8所示。时钟频率为40MHz，电源电压为1.8V，当|Dp-Dn|＝0.9V时，认为比较器完成比较，通过transient noise仿真，上述三种结构比较器的等效输入噪声随温度变化对比曲图如图8所示。从上述仿真结果可以看出，基于本发明所提出的负载调整技术的低噪声比较器和传统的几种结构相比，等效输入噪声至少降低了60％。仿真结果说明本技术实现了高速比较器的精度提升。其中，图8中[1]为图2的结构，[2]为图3的结构，本技术为图4的结构。
由此可见，上述基于预放大级结构的比较器在预放大级的基础上引入了正反馈单元，通过正反馈单元提高第二预放大级的电压增益，尤其是提高了小信号的电压增益，进而能有效降低了比较器的等效输入噪声。
本发明还提供一种模数转换器，模数转换器包括上述基于预放大级结构的比较器。
本发明还提供一种电子设备，电子设备包括上述模数转换器。
综上所述，本发明的基于预放大级结构的比较器通过在第二预放大级的输入端与输出端之间设置正反馈单元，通过正反馈单元提高第二预放大级的电压增益，尤其是提高了小信号 的电压增益，进而能有效降低了比较器的等效输入噪声。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种基于预放大级结构的比较器，其特征在于，至少包括：
    第一预放大级，其输入端接差分输入信号，对所述差分输入信号进行放大输出，输出第一差分输出信号；
    第二预放大级，其输入端连接所述第一差分输出信号，对所述第一差分输出信号进行放大输出，输出第二差分输出信号，且其输出端与其输入端之间设置有正反馈单元，通过所述正反馈单元提高所述第二预放大级的电压增益；
    锁存器，其输入端接所述第二差分输出信号。
  2. 根据权利要求1所述的基于预放大级结构的比较器，其特征在于，所述基于预放大级结构的比较器还包括1个预放大级，所述预放大级串接在所述第一预放大级与所述第二预放大级之间。
  3. 根据权利要求1所述的基于预放大级结构的比较器，其特征在于，所述基于预放大级结构的比较器还包括N个预放大级，N为大于等2的整数，N个所述预放大级级联设置后串接在所述第一预放大级与所述第二预放大级之间。
  4. 根据权利要求3所述的基于预放大级结构的比较器，其特征在于，N个所述预放大级的结构与所述第二预放大级的结构相同。
  5. 根据权利要求1所述的基于预放大级结构的比较器，其特征在于，所述第一预放大级包括；
    第一NMOS管、第二NMOS管、第三NMOS管、第一PMOS管以及第二PMOS管；
    所述第一NMOS管的源极接地，所述第一NMOS管的栅极接第一控制信号，所述第一NMOS管的漏极接第一节点；
    所述第二NMOS管的源极与所述第一节点连接，所述第二NMOS管的栅极与所述差分输入信号连接，所述第二NMOS管的漏极与第二节点连接；
    所述第三NMOS管的源极与所述第一节点连接，所述第三NMOS管的栅极与所述差分输入信号连接，所述第三NMOS管的漏极与第三节点连接；
    所述第一PMOS管的漏极接所述第二节点，所述第一PMOS管的栅极接所述第一控制信号，所述第一PMOS管的源极接工作电压；
    所述第二PMOS管的漏极接所述第三节点，所述第二PMOS管的栅极接所述第一控制信号，所述第二PMOS管的源极接所述工作电压；
    所述第一差分输出信号通过所述第二节点、所述第三节点输出。
  6. 根据权利要求1所述的基于预放大级结构的比较器，其特征在于，所述第二预放大级 包括预放大级主体单元和所述正反馈单元，所述正反馈单元包括：
    第四NMOS管、第五NMOS管、第六NMOS管以及第七NMOS管；
    所述第四NMOS管的栅极与第四节点连接，所述第四NMOS管的源极与第五节点连接，所述第四NMOS管的漏极与所述第七NMOS管的栅极连接；
    所述第五NMOS管的源极与所述第五节点连接，所述第五NMOS管的栅极与第六节点连接，所述第五NMOS管的漏极与所述第六NMOS管的栅极连接；
    所述第六NMOS管的源极与所述第六节点连接，所述第六NMOS管的漏极与第七节点连接；
    所述第七NMOS管的源极与所述第四节点连接，第七NMOS管的漏极与第八节点连接。
  7. 根据权利要求6所述的基于预放大级结构的比较器，其特征在于，所述预放大级主体单元包括：
    第八NMOS管、第三PMOS管、第四PMOS管、第五PMOS管以及第六PMOS管；
    所述第八NMOS管的源极接地，所述第八NMOS管的漏极与所述第五节点连接；
    第二控制信号分别与所述第八NMOS管的栅极、所述第三PMOS管的栅极、所述第四PMOS管的栅极、所述第五PMOS管的栅极、所述第六PMOS管的栅极连接，工作电压分别与所述第三PMOS管的源极、所述第四PMOS管的源极、所述第五PMOS管的源极、所述第六PMOS管的源极连接；
    所述第三PMOS管的漏极与所述第八节点连接，所述第四PMOS管的漏极与所述第七节点连接，所述第五PMOS管的漏极与所述第四NMOS管的漏极连接，所述第六PMOS管的漏极与所述第五NMOS管的漏极连接；
    所述第一差分输出信号分别与所述第四节点、所述第六节点连接，所述第二差分输出信号通过所述第七节点、所述第八节点输出。
  8. 根据权利要求7所述的基于预放大级结构的比较器，其特征在于，所述锁存器包括采样单元及保持单元；
    所述采样单元的输入端分别与所述第六节点、所述第八节点连接，所述采样单元对所述第二差分输出信号进行采样；
    所述采样单元的输出端接所述保持单元，所述保持单元对所述第二差分输出信号进行保持。
  9. 根据权利要求5或7所述基于预放大级结构的比较器，其特征在于，所述第一控制信号和所述第二控制信号为同一控制信号。
  10. 一种模数转换器，其特征在于，所述模数转换器包括权利要求1-9中任一项所述的基于预放大级结构的比较器。
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