WO2023109087A1 - 芯片封装结构和芯片封装方法 - Google Patents

芯片封装结构和芯片封装方法 Download PDF

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Publication number
WO2023109087A1
WO2023109087A1 PCT/CN2022/102420 CN2022102420W WO2023109087A1 WO 2023109087 A1 WO2023109087 A1 WO 2023109087A1 CN 2022102420 W CN2022102420 W CN 2022102420W WO 2023109087 A1 WO2023109087 A1 WO 2023109087A1
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Prior art keywords
layer
insulating layer
wafer
top surface
metal
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PCT/CN2022/102420
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English (en)
French (fr)
Inventor
蔡小虎
叶红波
温建新
史海军
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上海集成电路装备材料产业创新中心有限公司
上海集成电路研发中心有限公司
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Publication of WO2023109087A1 publication Critical patent/WO2023109087A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/805—Coatings
    • H10F39/8057—Optical shielding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/024—Manufacture or treatment of image sensors covered by group H10F39/12 of coatings or optical elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/805—Coatings

Definitions

  • the invention relates to the field of semiconductor packaging, in particular to a chip packaging structure and a chip packaging method.
  • CMOS Image Sensor CIS
  • CMOS Image Sensor CIS
  • the current chip packaging is to have balls on the back of the chip, but the more complex the chip, the more difficult it is to etch on the back.
  • the object of the present invention is to provide a chip packaging structure and a chip packaging method, so as to simplify the process of chip packaging and enhance the overall bonding force of the packaging structure.
  • the present invention provides a chip packaging structure in a first aspect, including a wafer, a light-shielding layer, a bottom protection layer, an insulating layer, a wiring layer, a light-transmitting layer, pads and solder balls.
  • the top surface of the wafer is a photosensitive surface
  • the light-shielding layer covers the bottom surface of the wafer
  • the bottom protection layer covers the bottom surface of the light-shielding layer
  • the insulating layer covers part of the top surface of the wafer to Exposing the middle top surface of the wafer as a photosensitive area
  • the insulating layer has a groove structure
  • the insulating layer also has a stepped lower insulating layer
  • the wiring layer is arranged in the groove structure
  • Metal wiring is arranged in the wiring layer
  • the light-transmitting layer is arranged across the middle top surface of the wafer, and covers the top surface of the lower insulating layer
  • the pad is arranged on the top surface of the wiring layer.
  • the surface is in electrical contact with the metal connection, and the solder ball is disposed on the pad and in electrical contact with the pad.
  • the beneficial effect of the chip packaging structure of the present invention is that: the light-shielding layer covers the bottom surface of the wafer, so that the wafer can be protected from stray light interference, and at the same time prevent stress from causing the wafer to fail.
  • the protective layer covers the bottom surface of the light-shielding layer, which can further prevent stress from causing the wafer to fail.
  • the photosensitive surface of the wafer avoids the complicated etching process on the bottom surface of the wafer, simplifies the chip packaging process and enhances the bonding force of the chip packaging structure.
  • the surface of the lower insulating layer has several convex structures, so as to diffusely reflect light incident on the photosensitive region by increasing surface roughness, and prevent stray light interference.
  • the beneficial effect is that: the several convex structures on the surface of the lower insulating layer can increase the surface roughness of the lower insulating layer, thereby diffusely reflecting the light incident on the photosensitive region and preventing stray light interference.
  • the insulating layer further has a remaining initial insulating layer, and the sidewall of the remaining initial insulating layer connecting with the lower insulating layer has several convex structures.
  • the several convex structures of the sidewalls of the remaining initial insulating layer and the lower insulating layer can increase the number of sidewalls of the remaining initial insulating layer and the lower insulating layer.
  • the surface roughness of the surface can diffusely reflect the light incident on the photosensitive area and prevent the interference of stray light.
  • the metal wiring has a width of 30-50 microns.
  • the beneficial effect is to prevent the metal connection from exposing the wiring layer and protect the metal connection at the same time.
  • the width of the lower insulating layer is less than or equal to 0.5 mm.
  • the beneficial effect is that the transparent layer can be attached to the top surface of the lower insulating layer without affecting the layout of the wiring layer.
  • the number of layers of the metal connection is at least 2, and different metal layers are electrically insulated.
  • the beneficial effect is that the metal connection wires can have sufficient space for wiring, and at the same time, the short circuit between the metal connection wires can be prevented.
  • the chip package structure further includes a top protection layer covering the wiring layer, and the top protection layer and the bottom protection layer have the same composition material.
  • the beneficial effect is to protect the wiring layer and the inner metal wiring layer, and prevent the metal wiring from being exposed or short-circuited.
  • the present invention also provides a chip packaging method, which includes the following steps:
  • S1 providing a wafer whose top surface is a photosensitive surface, and depositing a light-shielding layer on the bottom surface of the wafer;
  • the beneficial effect of the chip packaging method of the present invention is that: depositing and forming a light-shielding layer on the bottom surface of the wafer can prevent stray light interference and preventing stress from causing the wafer to fail, and depositing and forming a bottom protective layer on the bottom surface of the light-shielding layer can To further prevent stress from causing the wafer to fail, the insulating layer, the wiring layer, the light-transmitting layer, the pad and the solder ball are all arranged on the photosensitive surface of the wafer, avoiding damage to all
  • the complex etching process performed on the bottom surface of the wafer simplifies the chip packaging process and enhances the bonding force of the chip packaging structure.
  • the step of forming a wiring layer in the groove structure includes:
  • S31 Depositing a metal layer in the groove structure to form the metal wiring covering the bottom of the groove structure, and then forming a metal protection layer covering the metal layer;
  • the removing part of the top surface of the initial insulating layer close to the middle of the wafer to form a stepped lower insulating layer includes:
  • S42 Control the width of the lower insulating layer to be less than or equal to 0.5 mm.
  • the beneficial effect is that: the several convex structures formed on the surface of the lower insulating layer and the sidewalls of the remaining initial insulating layer and the lower insulating layer can increase the The surface roughness of the sidewall of the remaining initial insulating layer in contact with the lower insulating layer can diffusely reflect the light incident on the photosensitive area, prevent stray light interference, and control the width of the lower insulating layer Less than or equal to 0.5 mm, the transparent layer can be attached to the top surface of the lower insulating layer without affecting the layout of the wiring layer.
  • step S3 also includes:
  • the width of the metal connection is controlled to be 30-50 microns. The beneficial effect is that the metal connection can be protected from exposure and short circuit can be prevented.
  • FIG. 1 is a schematic structural view of a chip packaging structure according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram obtained after forming an insulating layer and a raised structure on the top surface of the wafer according to an embodiment of the present invention
  • FIG 3 is a top view of the structure obtained after forming the lower insulating layer, the remaining initial insulating layer and the first metal layer on the top surface of the wafer according to the embodiment of the present invention
  • FIG. 4 is a schematic flow diagram of a chip packaging method according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the structure obtained after forming a light-shielding layer on the bottom surface of the wafer according to an embodiment of the present invention.
  • Fig. 6 is a schematic diagram of the structure obtained after depositing the first insulating layer on the basis of the structure shown in Fig. 5;
  • Fig. 7 is a schematic diagram of the structure obtained after removing part of the first insulating layer on the basis of the structure shown in Fig. 6;
  • FIG. 8 is a schematic diagram of the structure obtained after etching the second insulating layer on the basis of the structure shown in FIG. 7;
  • Fig. 9 is a schematic diagram of the structure obtained after step S31 of the embodiment of the present invention.
  • Fig. 10 is a schematic diagram of the structure obtained after step S32 of the embodiment of the present invention.
  • Fig. 11 is a schematic diagram of the structure obtained after step S34 of the embodiment of the present invention.
  • Fig. 12 is a schematic diagram of the structure obtained after forming pads on the basis of the structure shown in Fig. 11;
  • Fig. 13 is a schematic diagram of the structure obtained after step S4 of the embodiment of the present invention.
  • Fig. 14 is a schematic diagram of the structure obtained after step S5 of the embodiment of the present invention.
  • Fig. 15 is a schematic diagram of the structure obtained after step S6 of the embodiment of the present invention.
  • an embodiment of the present invention provides a chip packaging structure and a chip packaging method to simplify the chip packaging process, and at the same time enhance the overall bonding force of the packaging structure, reduce stray light interference and improve the overall module heat dissipation.
  • the chip packaging structure of the embodiment of the present invention includes a wafer, a light-shielding layer, a bottom protection layer, an insulating layer, a wiring layer, a light-transmitting layer, solder pads, and solder balls.
  • FIG. 1 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present invention.
  • the chip packaging structure includes a wafer 11, a light shielding layer 12, a bottom protective layer 123, an insulating layer 51, a wiring layer 151, a light-transmitting layer 111, a pad 91 and a solder ball 121.
  • the wiring layer 151 , the insulating layer 51 , the welding pad 91 and the solder ball 121 are arranged around the middle of the wafer 11
  • the top surface of the wafer 11 is a photosensitive surface.
  • the wiring layer 151 is a ring structure.
  • the wiring layer 151 has two layers.
  • the insulating layer 51 is a ring structure.
  • the number of layers of the insulating layer 51 is two.
  • the number of the pads 91 is at least two.
  • the number of solder balls 121 is at least two.
  • the light shielding layer 12 covers the bottom surface of the wafer 11; the bottom protective layer 123 covers the bottom surface of the light shielding layer 12; the insulating layer 51 covers part of the top surface of the wafer 11 so that The middle top surface of the wafer 11 is exposed as a photosensitive region 110, the insulating layer 51 has a groove structure, and the insulating layer 51 also has a stepped lower insulating layer 61; the wiring layer 151 is arranged on the In the groove structure, metal wiring is arranged in the wiring layer 151; the light-transmitting layer 111 is arranged across the middle top surface of the wafer 11, and covers the top surface of the lower insulating layer 61; The welding pad 91 is disposed on the top surface of the wiring layer 151 and is in electrical contact with the metal connection; the solder ball 121 is disposed on the welding pad 91 and is in electrical contact with the welding pad 91 .
  • the wafer 11 is a vehicle-mounted back-illuminated (Back Side Illumination, BSI) chip.
  • BSI Back Side Illumination
  • the thickness of the wafer 11 is above 180 microns.
  • the thickness of the light-shielding layer 12 is more than 5 microns.
  • the material of the light shielding layer 12 is metal, such as Al.
  • the transparent layer 111 is glass.
  • FIG. 2 is a schematic structural diagram obtained after forming an insulating layer and a raised structure on the top surface of a wafer according to an embodiment of the present invention.
  • the surface of the lower insulating layer 61 has several convex structures 22 to diffusely reflect light incident on the photosensitive region by increasing the surface roughness to prevent stray light interference.
  • the insulating layer further has a remaining initial insulating layer, and the sidewall of the remaining initial insulating layer connecting with the lower insulating layer has several convex structures.
  • the lower insulating layer 61 and the remaining initial insulating layer 413 together constitute the insulating layer 51
  • the height of the lower insulating layer 61 is the first height h1
  • the remaining The height of the initial insulating layer 413 is the second height h2
  • the first height h1 is smaller than the second height h2
  • the sidewall of the remaining initial insulating layer 413 connected to the lower insulating layer 61 has several protrusions. from structure 22.
  • the shape of the protruding structure 22 is hemisphere, pyramid, cone and so on.
  • FIG. 3 is a top view of the structure obtained after forming the lower insulating layer, the remaining initial insulating layer and the first metal layer on the top surface of the wafer according to the embodiment of the present invention.
  • the metal wiring has a width of 30-50 microns.
  • the metal wiring (not shown) in the first metal layer 71 has a width of a first width d1, and the first width d1 is 30-50 microns.
  • the metal wiring has a width of 40 microns.
  • the width of the lower insulating layer 61 is a second width d2, and the second width d2 is less than or equal to 0.5 mm.
  • the number of layers of the metal wiring is at least 2, and the metal wirings are electrically insulated.
  • epoxy resin is filled between the metal wirings to achieve electrical insulation between the metal wirings.
  • the chip package structure further includes a top protection layer (not marked in the figure) covering the wiring layer 151 .
  • the top protection layer (not shown in the figure) and the bottom protection layer 123 have the same composition material.
  • both the top protective layer and the bottom protective layer are made of epoxy resin.
  • the present invention also provides a chip packaging method.
  • FIG. 4 is a schematic flowchart of a chip packaging method according to an embodiment of the present invention. Referring to Fig. 4, described chip packaging method comprises the following steps:
  • S1 providing a wafer whose top surface is a photosensitive surface, and depositing a light-shielding layer on the bottom surface of the wafer;
  • FIG. 5 is a schematic diagram of a structure obtained after forming a light-shielding layer on the bottom surface of the wafer according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a structure obtained after depositing a first insulating layer on the basis of the structure shown in FIG. 5 .
  • the light shielding layer 12 covering the bottom surface of the wafer 11 is formed on the bottom surface of the wafer 11 .
  • a first insulating layer 41 is formed on the top surface of the wafer 11 .
  • the thickness of the first insulating layer is 20-30 microns.
  • the constituent material of the first insulating layer is epoxy resin.
  • FIG. 7 is a schematic diagram of a structure obtained after removing part of the first insulating layer on the basis of the structure shown in FIG. 6 .
  • step S2 referring to FIG. 6 and FIG. 7, part of the first insulating layer 41 on the top surface of the wafer 11 is removed so that the middle top surface of the wafer 11 is exposed as the photosensitive region 110, so that A second insulating layer 411 is formed, and the second insulating layer 411 surrounds the middle of the wafer 11 .
  • FIG. 8 is a schematic diagram of the structure obtained after etching the second insulating layer on the basis of the structure shown in FIG. 7 .
  • step S2 referring to FIG. 7, a part of the top of the second insulating layer 411 is etched, further, referring to FIG. is a ring structure.
  • the step of forming a wiring layer in the groove structure includes:
  • S31 Depositing a metal layer in the groove structure to form the metal wiring covering the bottom of the groove structure, and then forming a metal protection layer covering the metal layer;
  • FIG. 9 is a schematic diagram of the structure obtained after step S31 of the embodiment of the present invention.
  • the first metal layer 71 is deposited in the groove structure 112, the metal wiring is formed in the first metal layer 71, and then the covering The first metal protection layer 701 of the first metal layer 71 .
  • the first metal layer 71 is a ring structure.
  • the step S3 also includes:
  • the width of the metal connection is controlled to be 30-50 microns.
  • the width of the metal wiring is a first width d1, and the first width d1 is controlled to be 30-50 microns.
  • the metal wiring has a width of 40 microns.
  • FIG. 10 is a schematic diagram of the structure obtained after step S32 of the embodiment of the present invention.
  • an insulating isolation layer 81 is deposited on the top surface of the first metal protection layer 701 .
  • FIG. 11 is a schematic diagram of the structure obtained after step S34 of the embodiment of the present invention.
  • step S33 referring to FIG. 11 , if the metal wiring formed in the first metal layer 71 does not meet the wiring requirements, a second metal is deposited on the top surface of the insulating isolation layer 81. layer 161, and then form a second metal protective layer 702 covering the second metal layer 161.
  • step S34 if the metal wiring formed in the second metal layer 161 meets the wiring requirements, the A top protection layer 703 is deposited on the top surface of the second metal protection layer 702 .
  • the first metal protection layer 701 , the second metal protection layer 702 and the top protection layer 703 are all made of epoxy resin.
  • FIG. 12 is a schematic diagram of a structure obtained after forming pads on the basis of the structure shown in FIG. 11 .
  • a pad 91 is formed on the top surface of the top protective layer 703 , and the pad 91 is in a ring structure.
  • the pad 91 covers part of the top surface of the initial insulating layer 412 .
  • the pad covers the top surface of the top protection layer, and the pad is not in contact with the initial insulating layer.
  • the removing part of the top surface of the initial insulating layer close to the middle of the wafer to form a stepped lower insulating layer includes:
  • S42 Control the width of the lower insulating layer to be less than or equal to 0.5 mm.
  • Fig. 13 is a schematic diagram of the structure obtained after step S4 of the embodiment of the present invention.
  • step S41 referring to FIG. 12 and FIG. 13 , part of the top surface of the initial insulating layer 412 close to the middle of the wafer 11 is removed to form a stepped lower insulating layer 61, the The lower insulating layer 61 and the remaining initial insulating layer 413 together constitute the insulating layer 51, and then several raised structures 22 are formed on the surface of the lower insulating layer 61, and then the remaining initial insulating layer 413 and the A plurality of protruding structures 22 are formed on the sidewalls adjoining the lower insulating layer 61 .
  • the width of the lower insulating layer 61 is the second width d2, and the second width d2 is controlled to be less than or equal to 0.5 mm.
  • Fig. 14 is a schematic diagram of the structure obtained after step S5 of the embodiment of the present invention.
  • the transparent layer 111 covering the top surface of the lower insulating layer 61 is pasted across the middle top surface of the wafer 11 .
  • Fig. 15 is a schematic diagram of the structure obtained after step S6 of the embodiment of the present invention.
  • the bottom protective layer 123 is formed on the bottom surface of the light shielding layer 12 . Further, solder ball planting on the surface of the pad 91 to form a solder ball 121 , and the solder ball 121 is arranged around the middle of the wafer 11 , but it is not limited thereto.
  • the solder balls are formed on the top surface of the wafer, and at the same time, the step-shaped lower insulating layer is formed on the top surface of the wafer, so as to Simplify the process of chip packaging, while enhancing the overall bonding force and heat dissipation capacity of the packaging structure, the surface of the lower insulating layer and the side wall of the insulating layer connected to the lower insulating layer are provided with several convex structures , can reduce stray light interference.

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Abstract

本发明提供了一种芯片封装结构，包括晶圆、遮光层、底部保护层、绝缘层、布线层、透光层、焊盘和焊球。所述晶圆的顶面为感光面，所述遮光层覆盖所述晶圆的底面，所述底部保护层覆盖所述遮光层的底面，所述布线层、所述绝缘层、所述透光层、所述焊盘以及所述焊球均设置于所述晶圆的顶部，避免了对所述晶圆底面进行的复杂刻蚀工艺，简化了芯片的封装工艺，同时增强了封装结构整体的结合力、减少杂光干扰。本发明还提供了一种芯片封装方法。

Description

芯片封装结构和芯片封装方法
交叉引用
本申请要求2021年12月14日提交的申请号为202111525671.6的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及半导体封装领域，尤其涉及芯片封装结构和芯片封装方法。
技术背景
目前大多数车载CMOS图像传感器(CMOS Image Sensor，CIS)为了满足芯片的可靠性和苛刻的应用场景，一般在感光区周围会有大量的保护控制电路，且感光区面积不大。目前的芯片封装均为在芯片背面出球，然而芯片越复杂，在其背面刻蚀越困难。
因此，有必要开发一种新型的芯片封装结构和芯片封装方法以解决现有技术中存在的上述问题。
发明概要
本发明的目的在于提供一种芯片封装结构和芯片封装方法，以简化芯片封装的工艺，同时增强封装结构整体的结合力。
为实现上述目的，第一方面本发明提供了一种芯片封装结构，包括晶圆、遮光层、底部保护层、绝缘层、布线层、透光层、焊盘和焊球。所述晶圆的顶面为感光面，所述遮光层覆盖所述晶圆的底面，所述底部保护层覆盖所述遮光层的底面，所述绝缘层覆盖所述晶圆的部分顶面以使所述晶圆的中部顶面露出作为感光区域，所述绝缘层具有凹槽结构，所述绝缘层还具有台阶状的低部绝缘层，所述布线层设置于所述凹槽结构内，所述布线层内设置有金 属连线，所述透光层跨所述晶圆的中部顶面设置，并覆盖所述低部绝缘层的顶面，所述焊盘设置于所述布线层顶面并与所述金属连线电接触，所述焊球设置于所述焊盘上，并与所述焊盘电接触。
本发明的所述芯片封装结构的有益效果在于：所述遮光层覆盖所述晶圆的底面，使得所述晶圆可以免受杂光干扰，同时防止应力造成所述晶圆失效，所述底部保护层覆盖所述遮光层的底面，可以进一步防止应力造成所述晶圆失效，所述绝缘层、所述布线层、所述透光层、所述焊盘以及所述焊球均设置于所述晶圆的感光面，避免了对所述晶圆底面进行的复杂刻蚀工艺，简化了芯片封装工艺且增强了所述芯片封装结构的结合力。
可选的，所述低部绝缘层的表面具有若干凸起结构，以通过增加表面粗糙度对入射所述感光区域的光进行漫反射，防止杂光干扰。其有益效果在于：所述低部绝缘层表面的若干凸起结构能够增加所述低部绝缘层的表面粗糙度，从而能够对入射所述感光区域的光进行漫反射，防止杂光干扰。
可选的，所述绝缘层还具有剩余的初始绝缘层，所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁具有若干凸起结构。其有益效果在于：所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁的若干凸起结构能够增加所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁的表面粗糙度，从而能够对入射所述感光区域的光进行漫反射，防止杂光干扰。
可选的，所述金属连线的宽度为30-50微米。其有益效果在于：防止金属连线露出布线层，同时保护金属连线。
可选的，所述低部绝缘层的宽度小于或等于0.5毫米。其有益效果在于：能够使得所述透光层贴合所述低部绝缘层的顶面，同时不影响所述布线层的布局。
可选的，所述金属连线的层数至少为2，不同所述金属层之间电绝缘。其有益效果在于：可使金属连线有充足的空间布线，同时防止金属连线之间发生短路。
可选的，所述芯片封装结构还包括覆盖所述布线层的顶部保护层，所述 顶部保护层和所述底部保护层具有相同的组成材料。其有益效果在于：保护布线层及其内部的金属连线层，防止金属连线露出或者发生短路。
第二方面本发明还提供了一种芯片封装方法，所述芯片封装方法包括以下步骤：
S1：提供顶面为感光面的晶圆，在所述晶圆的底面沉积形成遮光层；
S2：在所述晶圆顶面形成初始绝缘层，使所述晶圆的中部顶面露出作为所述感光区域，所述初始绝缘层具有凹槽结构；
S3：在所述凹槽结构内形成布线层，在所述布线层顶面形成与所述布线层内的金属连线电接触的焊盘，再检测所述金属连线是否满足布线要求；
S4：去除所述初始绝缘层靠近所述晶圆中部的部分顶面，形成台阶状的低部绝缘层，所述低部绝缘层和剩余的所述初始绝缘层共同构成绝缘层；
S5：跨所述晶圆的中部顶面形成覆盖所述低部绝缘层的顶面的透光层；
S6：在所述遮光层底面沉积形成底部保护层后，对所述焊盘进行植球。
本发明的所述芯片封装方法的有益效果在于：在所述晶圆底面沉积形成遮光层可以防止杂光干扰和防止应力作用使晶圆失效，在所述遮光层底面沉积形成底部保护层，可以进一步防止应力造成所述晶圆失效，所述绝缘层、所述布线层、所述透光层、所述焊盘以及所述焊球均设置于所述晶圆的感光面，避免了对所述晶圆底面进行的复杂刻蚀工艺，简化了芯片封装工艺且增强了所述芯片封装结构的结合力。
可选的，所述步骤S3中，在所述凹槽结构内形成布线层的步骤包括：
S31：在所述凹槽结构内沉积金属层以形成覆盖所述凹槽结构底部的所述金属连线，然后形成覆盖所述金属层的金属保护层；
S32：在所述金属保护层顶面沉积绝缘隔离层；
S33：所述金属连线未满足布线要求的情况下，在所述绝缘隔离层顶面再沉积所述金属层，然后形成覆盖所述金属层的金属保护层；
S34：所述金属连线满足布线要求的情况下，形成覆盖所述布线层的顶部保护层。其有益效果在于：防止金属连线露出，同时对金属连线起保护作 用。
可选的，所述去除所述初始绝缘层靠近所述晶圆中部的部分顶面，形成台阶状的低部绝缘层包括：
S41：在所述低部绝缘层的表面形成若干凸起结构，然后在所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁形成若干凸起结构；
S42：控制所述低部绝缘层的宽度小于或等于0.5毫米。其有益效果在于：在所述低部绝缘层的表面以及所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁形成的若干凸起结构，能够增加所述低部绝缘层和所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁的表面粗糙度，从而能够对入射感光区的光进行漫反射，防止杂光干扰，控制所述低部绝缘层的宽度小于或等于0.5毫米，能够使得所述透光层贴合所述低部绝缘层的顶面，同时不影响所述布线层的布局。
可选的，所述步骤S3还包括：
控制所述金属连线的宽度为30-50微米。其有益效果在于：可以保护金属连线不露出，防止短路。
附图说明
图1为本发明实施例的芯片封装结构的结构示意图；
图2为本发明实施例在晶圆顶面形成绝缘层和凸起结构后得到的结构示意图；
图3为本发明实施例在晶圆顶面形成低部绝缘层、剩余的初始绝缘层和第一金属层后得到的结构的俯视图；
图4为本发明实施例的芯片封装方法的流程示意图；
图5为本发明实施例在晶圆底面形成遮光层后得到结构的示意图；
图6为在图5所示的结构基础上沉积第一绝缘层后得到结构的示意图；
图7为在图6所示的结构基础上去除部分第一绝缘层后得到结构的示意图；
图8为在图7所示的结构基础上刻蚀第二绝缘层后得到结构的示意图；
图9为经本发明实施例的步骤S31后得到结构的示意图；
图10为经本发明实施例的步骤S32后得到结构的示意图；
图11为经本发明实施例的步骤S34后得到结构的示意图；
图12为在图11所示的结构基础上形成焊盘后得到结构的示意图；
图13为经本发明实施例的步骤S4后得到结构的示意图；
图14为经本发明实施例的步骤S5后得到结构的示意图；
图15为经本发明实施例的步骤S6后得到结构的示意图。
发明内容
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。除非另外定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本文中使用的“包括”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
为解决现有技术存在的问题，本发明实施例提供了一种芯片封装结构和芯片封装方法，以简化芯片封装的工艺，同时增强封装结构整体的结合力、减少杂光干扰并提高整体模组的散热性。
本发明实施例的芯片封装结构包括晶圆、遮光层、底部保护层、绝缘层、布线层、透光层、焊盘和焊球。
图1为本发明实施例的芯片封装结构的结构示意图。
本发明实施例中，参照图1，所述的芯片封装结构包括晶圆11、遮光层12、底部保护层123、绝缘层51、布线层151、透光层111、焊盘91和焊球121。其中：所述布线层151、所述绝缘层51、所述焊盘91和所述焊球121环绕所述晶圆11的中部设置，所述晶圆11的顶面为感光面。
一些实施例中，所述布线层151为环形结构。
一些实施例中，所述布线层151的层数为2。
一些实施例中，所述绝缘层51为环形结构。
一些实施例中，所述绝缘层51的层数为2。
一些实施例中，所述焊盘91的数目至少为2。
一些实施例中，所述焊球121的数目至少为2。
参照图1，所述遮光层12覆盖所述晶圆11的底面；所述底部保护层123覆盖所述遮光层12的底面；所述绝缘层51覆盖所述晶圆11的部分顶面以使所述晶圆11的中部顶面露出作为感光区域110，所述绝缘层51具有凹槽结构，所述绝缘层51还具有台阶状的低部绝缘层61；所述布线层151设置于所述凹槽结构内，所述布线层151内设置有金属连线；所述透光层111跨所述晶圆11的中部顶面设置，并覆盖所述低部绝缘层61的顶面；所述焊盘91设置于所述布线层151顶面并与所述金属连线电接触；所述焊球121设置于所述焊盘91上，并与所述焊盘91电接触。
一些实施例中，所述晶圆11为车载背照式(Back Side Illumination,BSI)芯片。
一些实施例中，所述晶圆11的厚度在180微米以上。
一些实施例中，所述遮光层12的厚度在5微米以上。
一些实施例中，所述遮光层12的材料为金属，如Al。
一些实施例中，所述透光层111为玻璃。
图2为本发明实施例在晶圆顶面形成绝缘层和凸起结构后得到的结构示意图。
一些实施例中，参照图2，所述低部绝缘层61的表面具有若干凸起结构22，以通过增加表面粗糙度对入射所述感光区域的光进行漫反射，防止杂光干扰。
一些实施例中，所述绝缘层还具有剩余的初始绝缘层，所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁具有若干凸起结构。
一些实施例中，参照图2，所述低部绝缘层61和剩余的初始绝缘层413共同构成所述绝缘层51，所述低部绝缘层61的高度为第一高度h1，所述剩余的初始绝缘层413的高度为第二高度h2，所述第一高度h1小于所述第二高度h2，所述剩余的初始绝缘层413与所述低部绝缘层61相接的侧壁具有若干凸起结构22。
一些实施例中，所述凸起结构22的形状为半球体、棱锥体、圆锥体等。
图3为本发明实施例在晶圆顶面形成低部绝缘层、剩余的初始绝缘层和第一金属层后得到的结构的俯视图。
一些实施例中，所述金属连线的宽度为30-50微米。
一些实施例中，参照图3，所述第一金属层71内的所述金属连线(图中未标示)的宽度为第一宽度d1，所述第一宽度d1为30-50微米。
一些实施例中，所述金属连线的宽度为40微米。
一些实施例中，参照图3，所述低部绝缘层61的宽度为第二宽度d2，所述第二宽度d2小于或等于0.5毫米。
一些实施例中，所述金属连线的层数至少为2，所述金属连线之间电绝缘。
一些实施例中，所述金属连线之间填充有环氧树脂以实现所述金属连线之间的电绝缘。
一些实施例中，参照图1，所述芯片封装结构还包括覆盖所述布线层151的顶部保护层(图中未标示)。所述顶部保护层(图中未标示)和所述底部保护层123具有相同的组成材料。
一些实施例中，所述顶部保护层和所述底部保护层的组成材料均为环氧 树脂。
一些实施例中，本发明还提供了一种芯片封装方法。
图4为本发明实施例的芯片封装方法的流程示意图。参照图4，所述芯片封装方法包括以下步骤：
S1：提供顶面为感光面的晶圆，在所述晶圆的底面沉积形成遮光层；
S2：在所述晶圆顶面形成初始绝缘层，使所述晶圆的中部顶面露出作为所述感光区域，所述初始绝缘层具有凹槽结构；
S3：在所述凹槽结构内形成布线层，在所述布线层顶面形成与所述布线层内的金属连线电接触的焊盘，再检测所述金属连线是否满足布线要求；
S4：去除所述初始绝缘层靠近所述晶圆中部的部分顶面，形成台阶状的低部绝缘层，所述低部绝缘层和剩余的所述初始绝缘层共同构成绝缘层；
S5：跨所述晶圆的中部顶面形成覆盖所述低部绝缘层的顶面的透光层；
S6：在所述遮光层底面沉积形成底部保护层后，对所述焊盘进行植球。
图5为本发明实施例在晶圆底面形成遮光层后得到结构的示意图。图6为在图5所示的结构基础上沉积第一绝缘层后得到结构的示意图。
在所述步骤S1中，参照图5，在所述晶圆11底面形成覆盖所述晶圆11底面的所述遮光层12。进一步的，在所述步骤S2中，参照图6，在所述晶圆11顶面形成第一绝缘层41。
一些实施例中，所述第一绝缘层的厚度为20-30微米。
一些实施例中，所述第一绝缘层的组成材料为环氧树脂。
图7为在图6所示的结构基础上去除部分第一绝缘层后得到结构的示意图。
在所述步骤S2中，参照图6和图7，去除所述晶圆11顶面的部分所述第一绝缘层41使得所述晶圆11的中部顶面露出作为所述感光区域110，以形成第二绝缘层411，所述第二绝缘层411环绕所述晶圆11中部。
图8为在图7所示的结构基础上刻蚀第二绝缘层后得到结构的示意图。
在所述步骤S2中，参照图7，刻蚀所述第二绝缘层411的部分顶部，进 一步的，参照图8，以形成包括凹槽结构112的初始绝缘层412，所述凹槽结构112为环形结构。
一些实施例中，所述步骤S3中，在所述凹槽结构内形成布线层的步骤包括：
S31：在所述凹槽结构内沉积金属层以形成覆盖所述凹槽结构底部的所述金属连线，然后形成覆盖所述金属层的金属保护层；
S32：在所述金属保护层顶面沉积绝缘隔离层；
S33：所述金属连线未满足布线要求的情况下，在所述绝缘隔离层顶面再沉积所述金属层，然后形成覆盖所述金属层的金属保护层；
S34：所述金属连线满足布线要求的情况下，形成覆盖所述布线层的顶部保护层。
图9为经本发明实施例的步骤S31后得到结构的示意图。
一些实施例中，在所述步骤S3中，参照图8和图9，在所述凹槽结构112内沉积第一金属层71，所述第一金属层71内形成金属连线，然后形成覆盖所述第一金属层71的第一金属保护层701。
一些实施例中，所述第一金属层71为环形结构。
一些实施例中，所述步骤S3还包括：
控制所述金属连线的宽度为30-50微米。
一些实施例中，参照图3，所述金属连线的宽度为第一宽度d1，控制所述第一宽度d1为30-50微米。
一些实施例中，所述金属连线的宽度为40微米。
图10为经本发明实施例的步骤S32后得到结构的示意图。
一些实施例中，在所述步骤S3中，参照图9和图10，在所述第一金属保护层701的顶面沉积绝缘隔离层81。
图11为经本发明实施例的步骤S34后得到结构的示意图。
一些实施例中，在所述步骤S33中，参照图11，所述第一金属层71内形成的金属连线未满足布线要求的情况下，在所述绝缘隔离层81顶面沉积 第二金属层161，然后形成覆盖所述第二金属层161的第二金属保护层702，在所述步骤S34中，所述第二金属层161内形成的金属连线满足布线要求的情况下，在所述第二金属保护层702顶面沉积顶部保护层703。
一些实施例中，所述第一金属保护层701、所述第二金属保护层702和所述顶部保护层703的材料均为环氧树脂。
图12为在图11所示的结构基础上形成焊盘后得到结构的示意图。
一些实施例中，在所述步骤S3中，参照图11和图12，在所述顶部保护层703的顶面形成焊盘91，所述焊盘91为环形结构。
一些实施例中，参照图12，所述焊盘91覆盖所述初始绝缘层412的部分顶面。
一些实施例中，所述焊盘覆盖所述顶部保护层的顶面，且所述焊盘与所述初始绝缘层不接触。
一些实施例中，所述去除所述初始绝缘层靠近所述晶圆中部的部分顶面，形成台阶状的低部绝缘层包括：
S41：在所述低部绝缘层的表面形成若干凸起结构，然后在所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁形成若干凸起结构；
S42：控制所述低部绝缘层的宽度小于或等于0.5毫米。
图13为经本发明实施例的步骤S4后得到结构的示意图。
一些实施例中，在所述步骤S41中，参照图12和图13，去除所述初始绝缘层412靠近所述晶圆11中部的部分顶面，形成台阶状的低部绝缘层61，所述低部绝缘层61和剩余的初始绝缘层413共同构成所述绝缘层51，然后在所述低部绝缘层61的表面形成若干凸起结构22，然后在所述剩余的初始绝缘层413与所述低部绝缘层61相接的侧壁形成若干凸起结构22。
一些实施例中，在所述步骤S42中，参照图3，所述低部绝缘层61的宽度为第二宽度d2，控制所述第二宽度d2小于或等于0.5毫米。
图14为经本发明实施例的步骤S5后得到结构的示意图。
一些实施例中，在所述步骤S5中，参照图13和图14，跨所述晶圆11 的中部顶面贴合覆盖所述低部绝缘层61的顶面的透光层111。
图15为经本发明实施例的步骤S6后得到结构的示意图。
一些实施例中，在所述步骤S6中，参照图15，在所述遮光层12的底面形成所述底部保护层123。进一步的，在所述焊盘91表面焊接植球，形成焊球121，所述焊球121环绕所述晶圆11中部设置，但又不限于此。
综上所述，本发明的芯片封装结构和芯片封装方法，通过在所述晶圆顶面形成所述焊球，同时在所述晶圆顶面形成台阶状的所述低部绝缘层，以简化芯片封装的工艺，同时增强封装结构整体的结合力和散热能力，所述低部绝缘层的表面和所述绝缘层中与所述低部绝缘层相接的侧壁设有若干凸起结构，能够减少杂光干扰。
虽然在上文中详细说明了本发明的实施方式，但是对于本领域的技术人员来说显而易见的是，能够对这些实施方式进行各种修改和变化。但是，应理解，这种修改和变化都属于权利要求书中所述的本发明的范围和精神之内。而且，在此说明的本发明可有其它的实施方式，并且可通过多种方式实施或实现。

Claims (10)

  1. 一种芯片封装结构，其特征在于，包括：
    晶圆，所述晶圆的顶面为感光面；
    遮光层，覆盖所述晶圆的底面；
    底部保护层，覆盖所述遮光层的底面；
    绝缘层，覆盖所述晶圆的部分顶面以使所述晶圆的中部顶面露出作为感光区域，所述绝缘层具有凹槽结构，所述绝缘层还具有台阶状的低部绝缘层；
    布线层，设置于所述凹槽结构内，所述布线层内设置有金属连线；
    透光层，跨所述晶圆的中部顶面设置，并覆盖所述低部绝缘层的顶面；
    焊盘，设置于所述布线层顶面并与所述金属连线电接触；
    焊球，设置于所述焊盘上，并与所述焊盘电接触。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述低部绝缘层的表面具有若干凸起结构，以通过增加表面粗糙度对入射所述感光区域的光进行漫反射，防止杂光干扰。
  3. 根据权利要求2所述的芯片封装结构，其特征在于，所述绝缘层还具有剩余的初始绝缘层，所述剩余的初始绝缘层与所述低部绝缘层相接的侧壁具有若干凸起结构。
  4. 根据权利要求1所述的芯片封装结构，其特征在于，所述金属连线的宽度为30-50微米，所述低部绝缘层的宽度小于或等于0.5毫米。
  5. 根据权利要求1所述的芯片封装结构，其特征在于，所述金属连线的层数至少为2，不同所述金属层之间电绝缘。
  6. 根据权利要求1所述的芯片封装结构，其特征在于，还包括覆盖所述布线层的顶部保护层，所述顶部保护层和所述底部保护层具有相同的组成材料。
  7. 一种芯片封装方法，其特征在于，包括以下步骤：
    S1：提供顶面为感光面的晶圆，在所述晶圆的底面沉积形成遮光层；
    S2：在所述晶圆顶面形成初始绝缘层，使所述晶圆的中部顶面露出作为所述感光区域，所述初始绝缘层具有凹槽结构；
    S3：在所述凹槽结构内形成布线层，在所述布线层顶面形成与所述布线层内的金属连线电接触的焊盘，再检测所述金属连线是否满足布线要求；
    S4：去除所述初始绝缘层靠近所述晶圆中部的部分顶面，形成台阶状的低部绝缘层，所述低部绝缘层和剩余的所述初始绝缘层共同构成绝缘层；
    S5：跨所述晶圆的中部顶面形成覆盖所述低部绝缘层的顶面的透光层；
    S6：在所述遮光层底面沉积形成底部保护层后，对所述焊盘进行植球。
  8. 根据权利要求7所述的芯片封装方法，其特征在于，所述步骤S3中，在所述凹槽结构内形成布线层的步骤包括：
    S31：在所述凹槽结构内沉积金属层以形成覆盖所述凹槽结构底部的所述金属连线，然后形成覆盖所述金属层的金属保护层；
    S32：在所述金属保护层顶面沉积绝缘隔离层；
    S33：所述金属连线未满足布线要求的情况下，在所述绝缘隔离层顶面再沉积所述金属层，然后形成覆盖所述金属层的金属保护层；
    S34：所述金属连线满足布线要求的情况下，形成覆盖所述布线层的顶部保护层。
  9. 根据权利要求7所述的芯片封装方法，其特征在于，所述去除所述初始绝缘层靠近所述晶圆中部的部分顶面，形成台阶状的低部绝缘层包括：
    S41：在所述低部绝缘层的表面形成若干凸起结构，然后在所述剩余 的初始绝缘层与所述低部绝缘层相接的侧壁形成若干凸起结构；
    S42：控制所述低部绝缘层的宽度小于或等于0.5毫米。
  10. 根据权利要求7所述的芯片封装方法，其特征在于，所述步骤S3还包括：
    控制所述金属连线的宽度为30-50微米。
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