TWI437699B - And a solid-state imaging device having a through-electrode - Google Patents

And a solid-state imaging device having a through-electrode Download PDF

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TWI437699B
TWI437699B TW099105507A TW99105507A TWI437699B TW I437699 B TWI437699 B TW I437699B TW 099105507 A TW099105507 A TW 099105507A TW 99105507 A TW99105507 A TW 99105507A TW I437699 B TWI437699 B TW I437699B
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electrode
semiconductor substrate
insulating film
main surface
solid
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TW201101471A (en
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Ikuko Inoue
Kenichiro Hagiwara
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Toshiba Kk
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Description

具有貫穿電極的固態攝像裝置
本發明基於日本申請案JP2009-100068(申請日：2009/04/16)，內容亦引用該申請案之內容。
本發明關於形成於半導體基板的具有貫穿電極之固態攝像裝置，關於例如相機模組。
伴隨電子機器之小型化，搭載之半導體裝置亦需要小型化、高集積化。1990年後半晶圓等級CSP(Wafer Level Chip Scale Package)之實用化檢討開始(例如參照日經Micro Devices 1998年4月號p28,p164,p176)。在廢棄引線的覆晶(flip chip)方式中，係使半導體晶片朝下藉由凸塊接合基板與半導體晶片之方式。
另外，以三維方式積層複數個半導體晶片，而可以大幅實現小型化之積層型封裝(multi-chip package(多晶片封裝))之開發亦於1990年代後期被進行，使用貫穿電極之封裝被提案(例如，特開平10-223833號公報)。光學元件之晶圓等級CSP之檢討約於2000前後開始。
另外，於International Electron Devices Meeting 1999 Technical Digest pp. 879-882揭示有，小柳等實際作成之玻璃+接著層+影像感測器+貫穿電極之構造的斷面照片。另外，同樣，美國專利第6489675號說明書及特開2007-53149號公報亦揭示，具備貫穿電極、透光性支撐基板的光學元件之斷面構造。
但是，彼等文獻揭示之貫穿電極係被形成於矽半導體基板內，貫穿電極與矽半導體基板之耦合、或者貫穿電極周邊之接地電阻變高等，會導致由焊墊介由貫穿電極供給之電源之劣化，或相反地，基於矽半導體基板側產生之電源雜訊等，而無法形成所要之良好電壓波形之問題。
 (用以解決課題的手段)
由第1側面看之本發明之固態攝像裝置，係具備：攝像元件，形成於半導體基板之第1主面；外部端子，形成於上述半導體基板之和上述第1主面呈對向的第2主面；絕緣膜，形成於上述半導體基板被挖空之貫穿孔內；貫穿電極，形成於上述貫穿孔內之上述絕緣膜上，電連接於上述外部端子；及第1電極，形成於上述半導體基板之上述第1主面之上述貫穿電極上；由和上述半導體基板之第1主面呈垂直之方向看時，上述絕緣膜與上述半導體基板相接連之外形，係大於上述第1電極之外形。
由第2側面看之本發明之固態攝像裝置，係具備：攝像元件，形成於半導體基板之第1主面；外部端子，形成於上述半導體基板之和上述第1主面呈對向的第2主面上；貫穿電極，形成於上述半導體基板被挖空之貫穿孔內，電連接於上述外部端子；第1電極，形成於上述半導體基板之上述第1主面之上述貫穿電極上；半導體區域，以包圍上述貫穿電極之外周之至少一部分的方式，被形成於上述半導體基板；及配線，形成於上述半導體區域上，電連接於上述半導體區域；於上述半導體區域，係介由上述配線被供給接地電位。
由第3側面看之本發明之相機模組，係具備：固態攝像裝置；透光性基板，配置於上述固態攝像裝置上；紅外光截止濾鏡，配置於上述透光性基板上；及攝像透鏡，配置於上述紅外光截止濾鏡上。上述固態攝像裝置，係具備：攝像元件，形成於半導體基板之第1主面；外部端子，形成於上述半導體基板之和上述第1主面呈對向的第2主面；絕緣膜，形成於上述半導體基板被挖空之貫穿孔內；貫穿電極，形成於上述貫穿孔內之上述絕緣膜上，電連接於上述外部端子；及第1電極，形成於上述半導體基板之上述第1主面之上述貫穿電極上；由和上述半導體基板之第1主面呈垂直之方向看時，上述絕緣膜與上述半導體基板相接連之外形，係大於上述第1電極之外形。
以下參照圖面說明本發明之實施形態。其中，固態攝像裝置係說明相機模組之例。說明之全圖中，共通部分附加共通之參照符號。
(第1實施形態)
首先，說明本發明第1實施形態之相機模組。
圖1為第1實施形態之相機模組之構成斷面圖。在形成有攝像元件(未圖示)之矽半導體基板(攝像元件晶片)10之第1主面上，介由接著劑11形成透光性支撐基板例如玻璃基板12。於玻璃基板12上介由接著劑13配置紅外光截止濾鏡(IR cut filter)14。於紅外光截止濾鏡14上介由接著劑15配置包含攝像透鏡16的透鏡支撐部17。
另外，於矽半導體基板10之和第1主面呈對向之第2主面上，形成外部端子(電極)例如錫球18。於矽半導體基板10及玻璃基板12之周圍，配置遮光兼蔽磁構件19。該遮光兼蔽磁構件19，係藉由接著劑20接著於透鏡支撐部17。藉由該構造而形成相機模組100。
相機模組100，係於例如樹脂或陶瓷構成之裝配基板200上，介由錫球18被直接裝配(COB：Chip On Board)。
以下詳細說明圖1之矽半導體基板10與玻璃基板12之斷面構造。
圖2為第1實施形態之相機模組中之矽半導體基板與玻璃基板之部分擴大斷面圖。相機模組，係具有：形成有攝像元件21的攝像畫素部；及周邊電路部，用於處理該攝像畫素部輸出之信號。
相機模組之攝像畫素部具有以下構成。
於矽半導體基板10之第1主面被配置：元件分離絕緣層(例如STI(Shallow Trench Isolation))22，及被該元件分離絕緣層22分離之元件區域。於元件區域形成包含光二極體及電晶體的攝像元件21。
在形成有攝像元件21的第1主面上，形成層間絕緣膜23，於層間絕緣膜23形成層間絕緣膜24。另外，於層間絕緣膜24中形成配線25。
於層間絕緣膜24上形成鈍化膜26，於鈍化膜26上形成基底層27。於基底層27上分別和攝像元件21呈對應而配置彩色濾光片28。
於彩色濾光片28上形成覆蓋層(overcoat)29，於覆蓋層29上和攝像元件21(或彩色濾光片28)呈對應而分別形成微透鏡30。另外，微透鏡30上係成為空洞31，於該空洞31上配置透光性支撐基板(透明基板)例如玻璃基板12。
於相機模組之周邊電路部，形成以下之貫穿電極及電極焊墊。於矽半導體基板10之第1主面上形成層間絕緣膜23，於層間絕緣膜23上形成內部電極(第1電極)32。
由矽半導體基板10之第2主面介由第1主面直至層間絕緣膜23被形成貫穿孔。於貫穿孔之側面上及底面上形成絕緣膜35。於矽半導體基板10之第2主面上形成絕緣膜36。
於貫穿孔之內面上(絕緣膜35上及內部電極32之貫穿孔側之面上)，及絕緣膜36上，形成貫穿電極(導電體層)37。內部電極32，係電連接於攝像元件21或周邊電路部所形成之周邊電路(未圖示)。
又，於貫穿電極37上及第2主面上之絕緣膜36上，形成保護膜例如焊錫阻劑38。另外，於第2主面上，在貫穿電極37上之焊錫阻劑38之一部分形成開口，於露出之貫穿電極37上形成錫球18。形成於貫穿孔內之貫穿電極37，係電連接於錫球18、攝像元件21或周邊電路。
又，焊錫阻劑38，係由例如酚系樹脂或聚醯亞胺系樹脂、胺系樹脂等構成。錫球18係使用例如Sn-Pb(共晶)或95Pb-Sn(高鉛高融點焊錫)，無鉛焊錫係使用Sn-Ag、Sn-Cu、Sn-Ag-Cu等。
於內部電極32上，介由層間絕緣膜24被形成元件面電極(第2電極)33。在內部電極32與元件面電極33間之層間絕緣膜24內，形成連接彼等電極間的接觸栓塞34。元件面電極33，例如係介由接觸栓塞34及內部電極32，使用於電壓施加及信號之讀出等。特別是，晶粒篩選測試(die sort test)時，於元件面電極33觸接測試用探針。
另外，於元件面電極33上被形成鈍化膜26。於鈍化膜26上被形成基底層27，於基底層27上被形成覆蓋層29。另外，於覆蓋層29上被形成苯乙烯系樹脂層39。
於元件面電極33上被配置的彼等鈍化膜26、基底層27、覆蓋層29、及苯乙烯系樹脂層39設置開口而形成焊墊開口部40。於苯乙烯系樹脂層39上及元件面電極33上，介由接著劑11形成玻璃基板12。接著劑11被圖案化，未被配置於攝像元件21上(或微透鏡30上)。
圖3為圖2之周邊電路部由焊墊開口部側看到之圖，係表示絕緣膜35、內部電極32及貫穿電極37之佈局平面圖。如圖所示，於絕緣膜35內側配置內部電極32，於內部電極32內側配置貫穿電極37。
於貫穿孔，配置於貫穿電極37與矽半導體基板10之間的絕緣膜35，係用於絕緣貫穿電極37與矽半導體基板10者。如圖2、3所示，於矽半導體基板10之第1主面之平行方向，絕緣膜35之膜厚約為300～1000nm，其外形係位於內部電極32之外形之外側。
由圖2所示斷面看時，存在於矽半導體基板10之第1主面的絕緣膜35，係大於內部電極32。另外，由圖3所示平面看時，絕緣膜35係大於內部電極32之矩形，包圍內部電極32。於圖3之例，內部電極32雖為矩形狀，但不限定於矩形，亦可為圓形或多角形。
藉由此構造，和膜厚薄的絕緣膜被配置於貫穿電極與半導體基板間的習知側比較，可以減少貫穿電極37與矽半導體基板10間之容量，縮小貫穿電極37之時間常數。如此則，可防止由錫球18供給之電源之劣化，進而可減少矽半導體基板10側產生之電源雜訊之影響。如此則，可將所要之良好電源電壓供給至攝像元件21及周邊電路。
以下說明第1實施形態之貫穿電極37之製造方法。
圖4、5係表示第1實施形態之相機模組中之貫穿電極之製造方法之圖。
首先，如圖4所示，於矽半導體基板10加工形成貫穿孔，之後，於貫穿孔內形成絕緣膜35。另外，於矽半導體基板10之第2主面上形成絕緣膜36。
之後，如圖5所示，於絕緣膜36、35、23內挖空形成到達內部電極32之貫穿孔41。另外，如圖2所示，於貫穿孔41之側面上及底面上，及基板10之第2主面上形成貫穿電極37。如此則，可將內部電極32與貫穿電極37電連接。之後，形成焊錫阻劑38及錫球18。
如上述說明，依據第1實施形態，在貫穿電極與矽半導體基板之間形成膜厚厚的絕緣膜，如此則，可以減少貫穿電極與矽半導體基板間之容量。如此則，可以縮小貫穿電極之時間常數，可以顯著減少外部端子所供給之電源電壓之劣化，或反之，可以減少半導體基板側產生之電源雜訊之影響。如此則，可提供信賴性高的固態攝像裝置。
(第2實施形態)
說明本發明第2實施形態之相機模組。於第2實施形態，係包圍貫穿電極37之外周，而使連接於接地電位的半導體區域被形成於矽半導體基板10。
圖6為第2實施形態之相機模組之構成斷面圖。圖7為圖6之周邊電路部由焊墊開口部側看到之圖，係表示接地區域(半導體區域)42、內部電極32及貫穿電極37之佈局平面圖。
相機模組之攝像畫素部，係和第1實施形態同樣。以下說明周邊電路部之構造。
如圖6所示，於矽半導體基板10之第1主面上形成層間絕緣膜23，於層間絕緣膜23上形成內部電極(第1電極)32。由矽半導體基板10之第2主面介由第1主面直至層間絕緣膜23被挖空形成貫穿孔。於貫穿孔側面上，及矽半導體基板10之第2主面上形成絕緣膜45。
另外，於貫穿孔內面上(絕緣膜45上及內部電極32之貫穿孔側之面上)，及第2主面之絕緣膜45上，形成貫穿電極(導電體層)37。內部電極32係電連接於攝像元件21或周邊電路部上被形成之周邊電路(未圖示)。
又，以包圍貫穿電極37之外周的方式，於矽半導體基板10之第1主面形成接地區域42。接地區域42係由雜質濃度高的擴散層構成，配置於貫穿電極37之近旁，例如貫穿電極37起數μm～數10μm之位置。圖7之例，係以包圍貫穿電極37之外周全體的方式形成接地區域42，但亦可僅於貫穿電極37之外周之一部分形成接地區域42。
另外，於接地區域42上之層間絕緣膜23、24內，被形成連接於接地區域42的配線43、接觸栓塞44。於接地區域42被供給接地電位等之基準電位。因此，接地區域42，例如係介由配線43及接觸栓塞44，連接於具有接地電位的錫球18。
於未具有接地區域42的習知構造，貫穿電極37周邊之矽半導體基板係具有高的接地電阻、亦即以高電阻被連接於接地，但於第2實施形態中，貫穿電極37周邊之矽半導體基板係具有低的接地電阻，電位呈現穩定。
因此，和第1實施形態同樣，可防止錫球18所供給之電源之劣化，進而可減少矽半導體基板10側產生之電源雜訊之影響。如此則，可將所要之良好電源電壓供給至攝像元件21及周邊電路。
依據上述說明之第2實施形態，藉由減低貫穿電極周邊之接地電阻，可以減小貫穿電極之時間常數，可以顯著減低外部端子所供給之電源電壓之劣化，或減少相反地由半導體基板側產生之電源雜訊之影響。如此則，可提供高信賴性之固態攝像裝置。
(第3實施形態)
說明本發明第3實施形態之相機模組。第3實施形態，係將第1實施形態與第2實施形態之特徵部予以組合者。於第3實施形態，係於貫穿電極37與矽半導體基板10間形成膜厚厚的絕緣膜之同時，以包圍貫穿電極37的方式，使連接於接地電位的接地區域42被形成。
圖8為第3實施形態之相機模組之構成斷面圖。圖9為圖8之周邊電路部由焊墊開口部側看到之圖，係表示接地區域42、絕緣膜35、內部電極32及貫穿電極37之佈局平面圖。
如圖所示，於貫穿電極37與矽半導體基板10間形成膜厚厚的絕緣膜35。另外，以包圍貫穿電極37的方式，於矽半導體基板10之第1主面，使連接於接地電位的接地區域42被形成。其他構成則和第1及第2實施形態之構成同樣。
依據第3實施形態，具有較第1及第2實施形態更大之效果，較較第1及第2實施形態能提供更高信賴性之固態攝像裝置。
本發明之實施形態可以提供固態攝像裝置，其可以減低由具有貫穿電極之半導體基板之電極所供給之電源之劣化，或者半導體基板側產生之電源雜訊之影響。
另外，依據上述各實施形態，不僅可以單獨實施，亦可以適當組合而實施。另外，於上述各實施形態包含各種階段之發明，藉由各實施形態中揭示之複數個構成要件之適當組合，可以抽出各種階段之發明。
以上係依據實施形態具體說明本發明，但本發明並不限定於上述實施形態，在不脫離其要旨情況下可做各種變更實施。
10．．．矽半導體基板
11．．．接著劑
12．．．玻璃基板
13．．．接著劑
14．．．紅外光截止濾鏡
15．．．接著劑
16．．．攝像透鏡
17．．．透鏡支撐部
18．．．錫球
20．．．接著劑
21．．．攝像元件
22．．．元件分離絕緣層
23‧‧‧層間絕緣膜
24‧‧‧層間絕緣膜
25‧‧‧配線
26‧‧‧鈍化膜
27‧‧‧基底層
28‧‧‧彩色濾光片
29‧‧‧覆蓋層
30‧‧‧微透鏡
31‧‧‧空洞
32‧‧‧內部電極
33‧‧‧元件面電極
34‧‧‧接觸栓塞
35‧‧‧絕緣膜
36‧‧‧絕緣膜
37‧‧‧貫穿電極
38‧‧‧焊錫阻劑
39‧‧‧苯乙烯系樹脂層
40‧‧‧焊墊開口部
41‧‧‧貫穿孔
42‧‧‧接地區域
43‧‧‧配線
44‧‧‧接觸栓塞
100‧‧‧相機模組
200‧‧‧裝配基板
圖1為本發明第1實施形態之相機模組之構成斷面圖。
圖2為第1實施形態之相機模組中之矽半導體基板與玻璃基板之部分擴大斷面圖。
圖3為圖2之周邊電路部由焊墊開口部側看到之圖。
圖4為第1實施形態之相機模組中之貫穿電極之製造方法之圖。
圖5為第1實施形態之相機模組中之貫穿電極之製造方法之圖。
圖6為本發明第2實施形態之相機模組之構成斷面圖。
圖7為圖6之周邊電路部由焊墊開口部側看到之圖。
圖8為本發明第3實施形態之相機模組之構成斷面圖。
圖9為圖8之周邊電路部由焊墊開口部側看到之圖。
10．．．矽半導體基板
11．．．接著劑
12．．．玻璃基板
18．．．錫球
21．．．攝像元件
22．．．元件分離絕緣層
23．．．層間絕緣膜
24．．．層間絕緣膜
25．．．配線
26．．．鈍化膜
27．．．基底層
28．．．彩色濾光片
29．．．覆蓋層
30．．．微透鏡
31．．．空洞
32．．．內部電極
33．．．元件面電極
34．．．接觸栓塞
35．．．絕緣膜
36．．．絕緣膜
37．．．貫穿電極
38．．．焊錫阻劑
39．．．苯乙烯系樹脂層
40．．．焊墊開口部

Claims (3)

  1. 一種固態攝像裝置，係包含：攝像元件，形成於包括半導體基板之第1主面的區域內；外部端子，形成於上述半導體基板之和上述第1主面呈對向的第2主面上；貫穿電極，形成於上述半導體基板被挖空之貫穿孔內，電連接於上述外部端子；第1電極，形成於上述半導體基板之上述第1主面之上述貫穿電極上；半導體區域，以包圍上述貫穿電極之外周之至少一部分的方式，被形成於上述半導體基板內，上述半導體區域係由雜質濃度高的擴散層構成，配置於上述貫穿電極之近旁；及配線，形成於上述半導體區域上，電連接於上述半導體區域；其中於上述半導體區域，係介由上述配線被供給接地電位。
  2. 如申請專利範圍第1項之固態攝像裝置，其中另包含：層間絕緣膜，形成於上述第1電極上及上述半導體基板之上述第1主面上；第2電極，形成於上述層間絕緣膜上；鈍化膜，形成於上述第2電極上及上述層間絕緣膜 上，具有使上述第2電極之一部分露出的開口部；及接觸栓塞，連接、形成於上述第2電極與上述第1電極之間。
  3. 如申請專利範圍第1項之固態攝像裝置，其中另包含：彩色濾光片，和上述攝像元件對應而配置於上述攝像元件上；及微透鏡，配置於上述彩色濾光片上。
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009645A (ja) * 2009-06-29 2011-01-13 Toshiba Corp 半導体装置及びその製造方法
US8532449B2 (en) * 2010-05-06 2013-09-10 Intel Corporation Wafer integrated optical sub-modules
JP2012018993A (ja) * 2010-07-06 2012-01-26 Toshiba Corp カメラモジュールおよびその製造方法
JP5832852B2 (ja) 2011-10-21 2015-12-16 浜松ホトニクス株式会社 光検出装置
JP5791461B2 (ja) * 2011-10-21 2015-10-07 浜松ホトニクス株式会社 光検出装置
KR20130106619A (ko) * 2012-03-20 2013-09-30 삼성전자주식회사 이미지 센서 및 그 제조 방법
US9570398B2 (en) 2012-05-18 2017-02-14 Xintec Inc. Chip package and method for forming the same
JP2014022402A (ja) * 2012-07-12 2014-02-03 Toshiba Corp 固体撮像装置
EP2889901B1 (en) * 2013-12-27 2021-02-03 ams AG Semiconductor device with through-substrate via and corresponding method
TWI616692B (zh) * 2014-12-29 2018-03-01 鴻海精密工業股份有限公司 光纖連接器及光耦合透鏡
WO2016143288A1 (en) * 2015-03-12 2016-09-15 Sony Corporation Imaging device, manufacturing method, and electronic device
JP6693068B2 (ja) * 2015-03-12 2020-05-13 ソニー株式会社 固体撮像装置および製造方法、並びに電子機器
TWI600125B (zh) 2015-05-01 2017-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
US10986281B2 (en) 2015-07-31 2021-04-20 Sony Corporation Pinhole camera, electronic apparatus and manufacturing method
JP6743035B2 (ja) * 2015-10-05 2020-08-19 ソニーセミコンダクタソリューションズ株式会社 撮像装置、製造方法
TWI826965B (zh) * 2016-06-03 2023-12-21 日商大日本印刷股份有限公司 貫通電極基板及其製造方法、以及安裝基板
JP7378923B2 (ja) 2018-10-31 2023-11-14 キヤノン株式会社 半導体装置、モジュール、カメラおよび機器
WO2023074233A1 (ja) 2021-10-26 2023-05-04 ソニーセミコンダクタソリューションズ株式会社 半導体装置及びその製造方法並びに電子機器

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
JP4011695B2 (ja) 1996-12-02 2007-11-21 株式会社東芝 マルチチップ半導体装置用チップおよびその形成方法
DE19916572A1 (de) 1999-04-13 2000-10-26 Siemens Ag Optisches Halbleiterbauelement mit optisch transparenter Schutzschicht
US6960837B2 (en) * 2002-02-26 2005-11-01 International Business Machines Corporation Method of connecting core I/O pins to backside chip I/O pads
TWI227050B (en) * 2002-10-11 2005-01-21 Sanyo Electric Co Semiconductor device and method for manufacturing the same
JP2005101711A (ja) 2003-09-22 2005-04-14 Renesas Technology Corp 固体撮像装置およびその製造方法
JP2005234038A (ja) * 2004-02-17 2005-09-02 Seiko Epson Corp 誘電体多層膜フィルタ及びその製造方法並びに固体撮像デバイス
JP4365750B2 (ja) * 2004-08-20 2009-11-18 ローム株式会社 半導体チップの製造方法、および半導体装置の製造方法
JP4694305B2 (ja) 2005-08-16 2011-06-08 ルネサスエレクトロニクス株式会社 半導体ウエハの製造方法
DE102005053494A1 (de) * 2005-11-09 2007-05-16 Fraunhofer Ges Forschung Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate
JP4951989B2 (ja) * 2006-02-09 2012-06-13 富士通セミコンダクター株式会社 半導体装置
TW200739894A (en) 2006-04-10 2007-10-16 United Microelectronics Corp Semiconductor image sensor and method for fabricating the same
US7629249B2 (en) * 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
JP4403424B2 (ja) * 2006-11-30 2010-01-27 ソニー株式会社 固体撮像装置
JP4742057B2 (ja) * 2007-02-21 2011-08-10 富士フイルム株式会社 裏面照射型固体撮像素子
JP2009065055A (ja) * 2007-09-07 2009-03-26 Fujifilm Corp 固体撮像装置及び固体撮像装置の製造方法

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CN101866897A (zh) 2010-10-20
US20100264503A1 (en) 2010-10-21

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