WO2023108738A1 - 一种阵列基板及显示终端 - Google Patents

一种阵列基板及显示终端 Download PDF

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Publication number
WO2023108738A1
WO2023108738A1 PCT/CN2021/140273 CN2021140273W WO2023108738A1 WO 2023108738 A1 WO2023108738 A1 WO 2023108738A1 CN 2021140273 W CN2021140273 W CN 2021140273W WO 2023108738 A1 WO2023108738 A1 WO 2023108738A1
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WO
WIPO (PCT)
Prior art keywords
area
array substrate
region
thin film
film transistor
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Application number
PCT/CN2021/140273
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English (en)
French (fr)
Inventor
高蓉
Original Assignee
Tcl华星光电技术有限公司
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Priority to US17/622,847 priority Critical patent/US20240038774A1/en
Publication of WO2023108738A1 publication Critical patent/WO2023108738A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display terminal.
  • the scan lines are generally arranged in the wiring areas of multiple pixel units, and the scan lines are connected with multiple thin film transistors (Thin Film Transistor, TFT) in the wiring areas.
  • TFT Thin Film Transistor
  • the aperture ratio of the display panel is reduced, which further leads to the problem that the light transmittance of the display panel is not high.
  • the display panel Due to the opacity of the scanning lines and the connection structure between the scanning lines and the thin film transistors in the current display panel, the display panel has the problems of decreased aperture ratio and low light transmittance.
  • the present application provides an array substrate and a display terminal to improve the current liquid crystal display panel due to the opacity of the scanning lines and thin film transistors in the wiring area, which leads to the decrease of the aperture ratio of the display panel, which in turn leads to the technical problem of low light transmittance .
  • the present application provides an array substrate, including a plurality of sub-pixel units, each of which includes a routing area and a pixel electrode area located on at least one side of the routing area;
  • the wiring area includes a first area and a second area
  • the first area is provided with at least one thin film transistor
  • the aperture ratio of the second area is greater than that of the first area
  • the pixel electrode region extends toward the second region.
  • the pixel electrode region includes an extension region overlapping with the second region.
  • the pixel electrode area includes a main electrode area and an auxiliary electrode area respectively located on two sides of the wiring area.
  • the extension region includes a first extension region where the main electrode region extends toward the second region and a second extension region where the secondary electrode region extends toward the second region.
  • a main pixel electrode is disposed in the main electrode region, and a sub-pixel electrode is disposed in the sub-electrode region.
  • a first thin film transistor connected to the main pixel electrode and a second thin film transistor connected to the sub pixel electrode are arranged in the first region.
  • the first thin film transistor and the second thin film transistor are connected in parallel.
  • a third thin film transistor connected to the sub-pixel electrode is further arranged in the first region.
  • the second thin film transistor is connected in series with the third thin film transistor.
  • the sub-pixel electrode is connected to a series circuit of the second thin film transistor and the third thin film transistor.
  • the array substrate further includes a main pixel capacitor corresponding to the main pixel electrode, a sub pixel capacitor corresponding to the sub pixel electrode, and a common connection between the second thin film transistor and the Auxiliary capacitance of the third thin film transistor.
  • the array substrate further includes data lines disposed on both sides of the pixel unit and a shared electrode line located between two adjacent data lines.
  • the shared electrode line is connected to the third thin film transistor.
  • the shared electrode line divides the wiring area into the first area and the second area, and the area of the second area is greater than or equal to the area of the first area .
  • the array substrate further includes a plurality of scan lines, and the plurality of scan lines intersect with the data lines.
  • the scan lines are arranged in the routing area along the line connecting the first area and the second area.
  • the width of the scan lines in the second area is smaller than the width of the scan lines in the first area.
  • the width of the first extending region is smaller than or equal to the width of the second extending region.
  • the present application also proposes a display terminal, which includes a terminal body and the above-mentioned array substrate, and the terminal body and the array substrate are combined into one.
  • the wiring area is set as the first area and the second area, and the thin film transistors are concentrated in the first area, so that no thin film transistors are set in the second area, so that the second area can be reduced.
  • the proportion of the opaque area in the region increases the aperture ratio in the second region, thereby increasing the light transmittance of the display panel and improving the display effect.
  • FIG. 1 is a schematic structural diagram of a sub-pixel in the background technology of the present application.
  • FIG. 2 is a schematic structural diagram of a sub-pixel unit in the array substrate described in the present application.
  • FIG. 3 is a driving circuit diagram of the sub-pixel unit described in the present application.
  • Sub-pixel unit 101 wiring area 100, first area 110, second area 120, pixel electrode area 200, main electrode area 210, first extension area 211, sub-electrode area 220, second extension area 221, thin film transistor 300 , first thin film transistor 310, second thin film transistor 320, third thin film transistor 330, data line 400, scan line 500, main pixel capacitor 600, main pixel storage capacitor 610, sub pixel capacitor 700, auxiliary capacitor 710, shared electrode line 800.
  • the scanning line 500 is generally arranged in the wiring area 100 between the main pixel area and the sub-pixel area, and the widened scanning line 500 and a plurality of thin film transistors 300 (Thin Film Transistor, TFT) are arranged in the wiring area. 100 are connected through via holes, as shown in FIG. 1 .
  • TFT Thin Film Transistor
  • this pixel design structure has the following disadvantages: the widened scan line 500 and multiple thin film transistors 300 and via hole structures are generally opaque structures, and the multiple thin film transistors 300 and via holes scattered in the wiring area 100
  • the hole structure will occupy most of the area of the wiring area 100, resulting in a non-light-transmitting area with a relatively large area ratio in the wiring area 100.
  • the aperture ratio of the pixel is not the same. It has not been improved or even decreased, resulting in the problem that the light transmittance of the large-size display panel is not improved, and the advantage of increasing the pixel size brought by the large-size display panel is wasted.
  • the present application proposes the following solutions based on the above technical problems.
  • the present application provides an array substrate, including a plurality of sub-pixel units 101 , each of which includes a routing area 100 and a pixel electrode located on at least one side of the routing area 100 District 200;
  • the wiring area 100 includes a first area 110 and a second area 120, the first area 110 is provided with at least one thin film transistor 300, and the opening ratio of the second area 120 is larger than that of the first area 110 opening rate.
  • the wiring area 100 is set as the first area 110 and the second area 120, and the thin film transistors 300 are concentrated in the first area 110, so that no thin film transistors 300 are set in the second area 120, Therefore, the proportion of the opaque area in the second region 120 can be reduced, and the aperture ratio in the second region 120 can be increased, thereby increasing the light transmittance of the display panel and improving the display effect.
  • FIG. 2 is a schematic structural diagram of the sub-pixel unit 101 in the array substrate of the present application.
  • the array substrate of the present application a plurality of sub-pixel units 101 are arranged in an array, and the array substrate also includes a plurality of horizontal and vertical
  • the data lines 400 and the scan lines 500 are intersected.
  • one data line 400 corresponds to a column of sub-pixel units 101 , that is, one data line 400 is electrically connected to a column of sub-pixel units 101 and is located at one side of the column of sub-pixel units 101 .
  • One scan line 500 corresponds to one row of sub-pixel units 101 , that is, one scan line 500 is arranged in the routing area 100 of a row of sub-pixel units 101 along a direction perpendicular to the data line 400 .
  • the scan line 500 is connected to the gate of the thin film transistor 300 through a via hole, and the data line 400 is connected to the source of the thin film transistor 300 (or drain), the pixel electrode in the pixel electrode area 200 is electrically connected to the drain (or source) of the thin film transistor 300, so as to realize the array driving of the sub-pixel unit 101 by the array substrate.
  • each sub-pixel unit 101 may only include one pixel electrode region 200, and one pixel electrode may be arranged in one pixel electrode region 200, and the wiring region 100 It is disposed on one side of the pixel electrode region 200 .
  • each sub-pixel of the array substrate has a single-pixel electrode structure, the design of the pixel structure is simple, and the process difficulty and cost are lower.
  • each of the sub-pixel units 101 may also include two pixel electrode regions 200, and correspondingly, a pixel electrode may be respectively arranged in the two pixel electrode regions 200, and the wiring The region 100 is disposed between two pixel electrode regions 200 .
  • each sub-pixel of the array substrate has a dual-pixel electrode structure, one of which is a main pixel electrode and the other is a sub-pixel electrode, so that by setting the main pixel electrode and the sub-pixel electrode in one sub-pixel unit 101 Sub) pixel electrodes to improve the color shift/contrast of large-size display panels.
  • the pixel electrode region 200 extends toward the second region 120 , and the pixel electrode region 200 includes an extension region overlapping with the second region 120 .
  • the pixel electrode region 200 extends toward the second region 120, that is, the pixel electrode disposed in the pixel electrode region 200 also extends into the second region 120, which is equivalent to making the The aperture area of the sub-pixel (coinciding with the pixel electrode area 200 ) extends toward the second area 120 , thereby increasing the aperture ratio of each sub-pixel, thereby increasing the overall light transmittance of the display panel and improving the display effect.
  • the pixel electrode area 200 includes a main electrode area 210 and a secondary electrode area 220 respectively located on both sides of the wiring area 100 , and the main electrode area 210 is provided with The main pixel electrode, the sub-pixel electrode is arranged in the sub-electrode region 220 .
  • the extension region includes a first extension region 211 where the main electrode region 210 extends toward the second region 120 and a second extension region where the secondary electrode region 220 extends toward the second region 120 District 221. That is to say, in this embodiment, the main pixel electrode may extend into the first extension region 211, and the sub-pixel electrode may extend into the second extension region 221, so that the main electrode Both the opening area of the region 210 and the secondary electrode region 220 can be enlarged to a certain extent, that is, the opening ratios of the main electrode region 210 and the secondary electrode region 220 can be correspondingly increased, and the main electrode region can be maintained The aperture ratios of the region 210 and the secondary electrode region 220 are kept adapted to better improve the display effect of the display panel.
  • FIG. 3 is a driving circuit diagram of the sub-pixel unit 101 of the present application.
  • the first region 110 is provided with a first The thin film transistor 310 and the second thin film transistor 320 connected to the sub-pixel electrode, the first thin film transistor 310 and the second thin film transistor 320 are connected in parallel.
  • the gate of the first thin film transistor 310 is connected to the scanning line 500 through a via hole, the source (or drain) of the first thin film transistor 310 is connected to the main pixel electrode, The drain (or source) of the first TFT 310 is connected to the data line 400 .
  • the gate of the second thin film transistor 320 is connected to the scanning line 500 through a via hole, the source (or drain) of the second thin film transistor 320 is connected to the sub-pixel electrode, and the second thin film transistor The drain (or source) of 320 is connected to the data line 400 .
  • the same scanning line 500 can be used to control the switch, and the same data line 400 can be used to control the switching of the main
  • the same voltage signal is input to the pixel electrode and the sub-pixel electrode to realize synchronous operation of the main electrode area 210 and the sub-electrode area 220 , which can avoid or reduce problems such as flicker.
  • a third thin film transistor 330 connected to the sub-pixel electrode is also provided in the first region 110 , and the second thin film transistor 320 is connected to the third thin film transistor.
  • the transistors 330 are connected in series, and the sub-pixel electrode is connected to the series circuit of the second thin film transistor 320 and the third thin film transistor 330 .
  • the gate of the third thin film transistor 330 is connected to the scan line 500 , the source (or drain) of the third thin film transistor 330 is connected to the drain of the second thin film transistor 320 (or source) connection, and the drain (or source) of the third thin film transistor 330 is grounded.
  • the third thin film transistor 330 and the second thin film transistor 320 are connected in series, and the sub-pixel electrode is connected to the series connection between the second thin film transistor 320 and the third thin film transistor 330.
  • the second thin film transistor 320 and the third thin film transistor 330 can jointly control the sub-pixel electrode, so that The working state between the sub-pixel electrode and the main pixel electrode is more stable, reducing display abnormalities.
  • the array substrate further includes a main pixel capacitor 600 corresponding to the main pixel electrode, a sub pixel capacitor 700 corresponding to the sub pixel electrode, and a common connection to the The auxiliary capacitor 710 of the second thin film transistor 320 and the third thin film transistor 330 .
  • the first end of the main pixel capacitor 600 is connected to the drain (or source) of the first thin film transistor 310 , and the second end of the main pixel capacitor 600 is connected to a common voltage end.
  • the main pixel capacitor 600 can also be connected in parallel with a main pixel storage capacitor 610, so as to continuously discharge the main pixel electrode within a certain period of time after the first thin film transistor 310 is turned off, and maintain the display image until the next frame is refreshed.
  • the first end of the sub-pixel capacitor 700 is connected to the drain (or source) of the second thin film transistor 320 , and the second end of the sub-pixel capacitor 700 is connected to a common voltage end.
  • the auxiliary capacitor 710 can be used as the auxiliary capacitor 710 of the sub-pixel electrode.
  • the first end of the auxiliary capacitor 710 may be connected to the drain (or source) of the second thin film transistor 320 and the source (or drain) of the third thin film transistor 330, and the auxiliary capacitor 710
  • the second terminal can be connected to a common voltage terminal on the color filter substrate (not shown in the figure).
  • the storage capacitors in the sub-pixel unit 101 can be used to control the pixel electrodes within a certain period of time after the scanning signal is turned off. Discharge, so that the sub-pixel unit 101 maintains the display image until the next frame of image refresh, thereby reducing display abnormalities such as flickering and flickering.
  • the auxiliary capacitor 710 can cause a voltage difference between the main electrode region 210 and the secondary electrode region 220 in the sub-pixel unit 101, so that the main electrode region 210 and the The deflection angles of the liquid crystal molecules in the sub-electrode region 220 are different, so as to improve the problem of large viewing angle deflection.
  • the array substrate further includes data lines 400 arranged on both sides of the pixel unit and a shared electrode between two adjacent data lines 400 line 800 , the shared electrode line 800 is connected to the third thin film transistor 330 , so that the third thin film transistor 330 can be grounded through the shared electrode line 800 .
  • the shared electrode line 800 may be arranged parallel to the data line 400, and the shared electrode line 800 divides the routing area 100 into the first area 110 and the second area 110. Zone 120 , the area of the second zone 120 is greater than or equal to the area of the first zone 110 .
  • the area of the second region 120 may be equal to the area of the first region 110 , and at this time, the shared electrode line 800 is just on the central symmetrical line of two adjacent data lines 400 .
  • the shared electrode line 800 is arranged on the central symmetrical line of two adjacent data lines 400, and the routing area 100 is divided into the first area 110 and the first area 110 by the shared electrode line 800.
  • the second area 120 can not only accurately divide the wiring area 100, so as to extend the pixel electrode area 200 into the wiring area 100, but also divide the common electrode line 800 in the conventional pixel structure into
  • the curved winding design in the wiring area 100 is changed to a straight design, which not only reduces the difficulty of manufacturing the shared electrode line 800, but also saves the material of the shared electrode line 800, which is beneficial to reduce the cost.
  • the area of the second area 120 may also be greater than the area of the first area 110 , at this time, the shared electrode line 800 may flow to the first area 100 when passing through the wiring area 100 .
  • One side of the region 110 is offset, so as to further enlarge the area of the second region 120 and further increase the aperture ratio of the sub-pixel unit 101 .
  • the arrangement of the first thin film transistor 310 , the second thin film transistor 320 and the third thin film transistor 330 in the first region 110 is more concentrated, and the manufacturing difficulty is correspondingly increased.
  • the scanning lines 500 are arranged in the In the routing area 100 , and in the extending direction of the data lines 400 , the width of the scanning lines 500 in the second area 120 is smaller than the width of the scanning lines 500 in the first area 110 .
  • the first thin film transistor 310, the second thin film transistor 320, and the third thin film transistor 330 are collectively arranged in the first region 110, so that there is no need to arrange a thin film in the second region 120.
  • Transistor 300 and vias, etc. so as to reduce the width of the scanning line 500 in the second region 120, reduce the proportion of the opaque area in the second region 120, and further improve the opening rate.
  • the width d1 of the first extension region 211 is smaller than or equal to the width d2 of the second extension region 221 .
  • the area of the main electrode region 210 may be smaller than or equal to the area of the secondary electrode region 220, that is, in the extending direction of the data line 400, the The length of the main electrode region 210 may be less than or equal to the length of the secondary electrode region 220 .
  • the width d1 of the first extending region 211 is less than or equal to the width d2 of the second extending region 221, which can also be described as: the first extending The area of the region 211 is smaller than or equal to the area of the second extension region 221 .
  • the width d1 of the first extension region 211 is smaller than the width d2 of the second extension region 221 .
  • the width d1 of the first extension region 211 may be 10.33 microns
  • the width d2 of the second extension region 221 may be 21.52 microns.
  • the width d1 of the first extension region 211 and the width d2 of the second extension region 221 can be adjusted according to the actual situation, and this embodiment only uses the above values as an example.
  • the widths of the first extension region 211 and the second extension region 221 are not specifically limited.
  • the area of the first extension region 211 can be adapted to the area of the main electrode region 210
  • the area of the second extension region 221 can be adapted to the area of the secondary electrode region 220. matching, so that the opening ratio of the main electrode region 210 is increased by the same or close to that of the secondary electrode region 220, and the gap between the main electrode region 210 and the secondary electrode region 220 is reduced as much as possible.
  • the aperture ratio improves the difference, and further reduces the display defects such as color cast and uneven brightness and darkness.
  • An embodiment of the present application further provides a display terminal, where the display terminal includes a terminal body and the aforementioned array substrate, and the terminal body and the array substrate are combined into one body.
  • the display terminal may be an intelligent terminal such as a mobile phone, a computer, a television, or a watch.
  • the aperture ratio of the display panel can be increased by at least 3.4%, that is, the light transmittance of the display panel can be increased by at least 3.4%.

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Abstract

本申请提出了一种阵列基板及显示终端；该阵列基板包括多个子像素单元，每一子像素单元包括走线区和位于走线区至少一侧的像素电极区，其中，走线区包括第一区和第二区，第一区内设置有至少一薄膜晶体管，第二区的开口率大于第一区的开口率。

Description

一种阵列基板及显示终端 技术领域
本申请涉及显示技术的领域，具体涉及一种阵列基板及显示终端。
 背景技术
在液晶显示面板中，扫描线一般设置在多个像素单元的走线区内，扫描线与多个薄膜晶体管（Thin Film Transistor，TFT）在走线区内进行连接。
但是，由于扫描线及扫描线与薄膜晶体管连接结构的不透光性，会使显示面板的开口率下降，进而导致显示面板透光率不高的问题。
 技术问题
目前的显示面板因扫描线及扫描线与薄膜晶体管连接结构的不透光性，导致显示面板存在开口率下降、透光率不高的问题。
 技术解决方案
本申请提供一种阵列基板及显示终端，以改善当前液晶显示面板因走线区内扫描线和薄膜晶体管的不透光性导致显示面板的开口率下降，进而导致透光率较低的技术问题。
为解决上述技术问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括多个子像素单元，每一所述子像素单元包括走线区和位于所述走线区至少一侧的像素电极区；
其中，所述走线区包括第一区和第二区，所述第一区内设置有至少一薄膜晶体管，所述第二区的开口率大于所述第一区的开口率。
在本申请的阵列基板中，所述像素电极区向所述第二区延伸。
在本申请的阵列基板中，所述像素电极区包括与所述第二区重叠的延伸区。
在本申请的阵列基板中，所述像素电极区包括分别位于所述走线区两侧的主电极区和副电极区。
在本申请的阵列基板中，所述延伸区包括所述主电极区向所述第二区延伸的第一延伸区和所述副电极区向所述第二区延伸的第二延伸区。
在本申请的阵列基板中，所述主电极区内设置有主像素电极，所述副电极区内设置有副像素电极。
在本申请的阵列基板中，所述第一区内设置有与所述主像素电极连接的第一薄膜晶体管以及与所述副像素电极连接的第二薄膜晶体管。
在本申请的阵列基板中，所述第一薄膜晶体管与所述第二薄膜晶体管并联。
在本申请的阵列基板中，所述第一区内还设置有与所述副像素电极连接的第三薄膜晶体管。
在本申请的阵列基板中，所述第二薄膜晶体管与所述第三薄膜晶体管串联。
在本申请的阵列基板中，所述副像素电极连接于所述第二薄膜晶体管和所述第三薄膜晶体管的串联电路上。
在本申请的阵列基板中，所述阵列基板还包括与所述主像素电极对应的主像素电容、与所述副像素电极对应的副像素电容，以及共同连接所述第二薄膜晶体管和所述第三薄膜晶体管的辅助电容。
在本申请的阵列基板中，所述阵列基板还包括设置于所述像素单元两侧的数据线及位于相邻两条所述数据线之间的共享电极线。
在本申请的阵列基板中，所述共享电极线与所述第三薄膜晶体管连接。
在本申请的阵列基板中，所述共享电极线将所述走线区分割成所述第一区和所述第二区，所述第二区的面积大于或等于所述第一区的面积。
在本申请的阵列基板中，所述阵列基板还包括多条扫描线，多条所述扫描线与所述数据线交叉设置。
在本申请的阵列基板中，所述扫描线沿所述第一区与所述第二区的连线方向设置于所述走线区内。
在本申请的阵列基板中，在所述数据线的延伸方向上，所述第二区内的扫描线的宽度小于所述第一区内的扫描线的宽度。
在本申请的阵列基板中，在所述数据线的延伸方向上，所述第一延伸区的宽度小于或等于所述第二延伸区的宽度。
本申请还提出了一种显示终端，包括终端主体和上述阵列基板，所述终端主体和所述阵列基板组合为一体。
 有益效果
本申请通过将走线区设置为第一区和第二区，并将薄膜晶体管集中设置在所述第一区内，使所述第二区内未设置薄膜晶体管，从而可以减少所述第二区内的不透光区域占比，提高所述第二区内的开口率，进而提高显示面板的透光率，改善显示效果。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请背景技术中子像素的结构示意图；
图2是本申请所述阵列基板中子像素单元的结构示意图；
图3是本申请所述子像素单元的驱动电路图。
附图标记说明：
子像素单元101、走线区100、第一区110、第二区120、像素电极区200、主电极区210、第一延伸区211、副电极区220、第二延伸区221、薄膜晶体管300、第一薄膜晶体管310、第二薄膜晶体管320、第三薄膜晶体管330、数据线400、扫描线500、主像素电容600、主像素存储电容610、副像素电容700、辅助电容710、共享电极线800。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
在大尺寸超（高）清液晶显示面板中，通常会采用加宽数据线400、加宽扫描线500、加宽黑矩阵等牺牲开口率的像素设计方法来解决充电不足和其他光学品味问题。其中，扫描线500一般设置在主像素区和次（副）像素区之间的走线区100内，加宽的扫描线500与多个薄膜晶体管300（Thin Film Transistor，TFT）在走线区100内通过过孔进行连接，如图1所示。
目前，这种像素设计结构存在以下弊端：加宽的扫描线500与多个薄膜晶体管300及过孔结构一般为不透光结构，在走线区100内分散设置的多个薄膜晶体管300及过孔结构会占用走线区100的大部分面积，造成走线区100内存在较大面积占比的非透光区域，这样虽然大尺寸显示面板的像素尺寸增大了，但像素的开口率并未提升甚至还有所降低，导致既未提升大尺寸显示面板的透光率，也浪费了大尺寸显示面板带来的像素尺寸增大的优势的问题。本申请基于上述技术问题提出了以下方案。
请参阅图2至图3，本申请提供一种阵列基板，包括多个子像素单元101，每一所述子像素单元101包括走线区100和位于所述走线区100至少一侧的像素电极区200；
其中，所述走线区100包括第一区110和第二区120，所述第一区110内设置有至少一薄膜晶体管300，所述第二区120的开口率大于所述第一区110的开口率。
本申请通过将走线区100设置为第一区110和第二区120，并将薄膜晶体管300集中设置在所述第一区110内，使所述第二区120内未设置薄膜晶体管300，从而可以减少所述第二区120内的不透光区域占比，提高所述第二区120内的开口率，进而提高显示面板的透光率，改善显示效果。
现结合具体实施例对本申请的技术方案进行描述。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图2，图2为本申请所述阵列基板中子像素单元101的结构示意图，在本申请的阵列基板中，多个子像素单元101阵列排布，所述阵列基板还包括多条横纵交叉设置的数据线400和扫描线500。其中，一条所述数据线400对应一列所述子像素单元101，即一条所述数据线400与一列所述子像素单元101电连接且位于该列子像素单元101的一侧。一条所述扫描线500对应一行所述子像素单元101，即一条所述扫描线500沿垂直于所述数据线400的方向设置在一行所述子像素单元101的走线区100内。
在本实施例中，在所述走线区100内，所述扫描线500与所述薄膜晶体管300的栅极通过过孔连接，所述数据线400与所述薄膜晶体管300的源极（或漏极）连接，所述像素电极区200内的像素电极与所述薄膜晶体管300的漏极（或源极）电连接，以实现所述阵列基板对所述子像素单元101的阵列驱动。
请参阅图2，在本申请的阵列基板中，每个所述子像素单元101可以仅包括一个像素电极区200，一个所述像素电极区200内可以设置一个像素电极，所述走线区100设置于所述像素电极区200的一侧。此时，所述阵列基板的每个子像素为单像素电极结构，像素结构设计简单，制程难度和成本更低。
在本实施例中，每个所述子像素单元101也可以包括两个像素电极区200，与此对应地，两个所述像素电极区200内可以分别设置有一个像素电极，所述走线区100设置于两个像素电极区200之间。此时，所述阵列基板的每个子像素为双像素电极结构，其中一个为主像素电极，另一个为副（次）像素电极，从而通过在一个子像素单元101内设置主像素电极和副（次）像素电极来改善大尺寸显示面板的色偏/对比度等问题。
请参阅图2，在本申请的阵列基板中，所述像素电极区200向所述第二区120延伸，以及，所述像素电极区200包括与所述第二区120重叠的延伸区。
在本实施例中，所述像素电极区200向所述第二区120延伸，即，设置在所述像素电极区200内的像素电极也延伸至所述第二区120内，相当于使所述子像素的开口区（与像素电极区200重合）向第二区120延伸，从而提升每个子像素的开口率，进而提升显示面板的整体透光率，改善显示效果。
请参阅图2，在本申请的阵列基板中，所述像素电极区200包括分别位于所述走线区100两侧的主电极区210和副电极区220，所述主电极区210内设置有主像素电极，所述副电极区220内设置有副像素电极。
在本实施例中，所述延伸区包括所述主电极区210向所述第二区120延伸的第一延伸区211和所述副电极区220向所述第二区120延伸的第二延伸区221。也就是说，在本实施例中，所述主像素电极可以延伸至所述第一延伸区211内，所述副像素电极可以延伸至所述第二延伸区221内，从而使所述主电极区210和所述副电极区220的开口区均可以得到一定程度的扩大，即所述主电极区210和所述副电极区220的开口率均能得到相应提升，且能够保持所述主电极区210和所述副电极区220的开口率保持适配，更好地改善显示面板的显示效果。
请参阅图2和图3，图3是本申请所述子像素单元101的驱动电路图，在本申请的阵列基板中，所述第一区110内设置有与所述主像素电极连接的第一薄膜晶体管310以及与所述副像素电极连接的第二薄膜晶体管320，所述第一薄膜晶体管310与所述第二薄膜晶体管320并联。
在本实施例中，所述第一薄膜晶体管310的栅极通过过孔与所述扫描线500连接，所述第一薄膜晶体管310的源极（或漏极）与所述主像素电极连接，所述第一薄膜晶体管310的漏极（或源极）与所述数据线400连接。所述第二薄膜晶体管320的栅极通过过孔与所述扫描线500连接，所述第二薄膜晶体管320的源极（或漏极）与所述副像素电极连接，所述第二薄膜晶体管320的漏极（或源极）与所述数据线400连接。
在本实施例中，由于所述第一薄膜晶体管310和所述第二薄膜晶体管320是并联，因此可由同一条所述扫描线500控制开关，并由同一所述数据线400分别向所述主像素电极和所述副像素电极输入相同的电压信号，实现所述主电极区210和所述副电极区220的同步工作，可避免或减少闪烁等问题。
请参阅图3，在本申请的阵列基板中，所述第一区110内还设置有与所述副像素电极连接的第三薄膜晶体管330，所述第二薄膜晶体管320与所述第三薄膜晶体管330串联，以及，所述副像素电极连接于所述第二薄膜晶体管320和所述第三薄膜晶体管330的串联电路上。
在本实施例中，所述第三薄膜晶体管330的栅极与所述扫描线500连接，所述第三薄膜晶体管330的源极（或漏极）与所述第二薄膜晶体管320的漏极（或源极）连接，所述第三薄膜晶体管330的漏极（或源极）接地。
本实施例通过将所述第三薄膜晶体管330和所述第二薄膜晶体管320串联，并使所述副像素电极连接于所述第二薄膜晶体管320和所述第三薄膜晶体管330之间的串联电路上，通过将所述第三薄膜晶体管330连接其他电学元器件（如电容等），可以使所述第二薄膜晶体管320和所述第三薄膜晶体管330共同控制所述副像素电极，从而使所述副像素电极与所述主像素电极之间的工作状态更加稳定，减少显示异常现象。
请参阅图3，在本申请的阵列基板中，所述阵列基板还包括与所述主像素电极对应的主像素电容600、与所述副像素电极对应的副像素电容700，以及共同连接所述第二薄膜晶体管320和所述第三薄膜晶体管330的辅助电容710。
在本实施例中，所述主像素电容600的第一端与所述第一薄膜晶体管310的漏极（或源极）连接，所述主像素电容600的第二端接公共电压端。所述主像素电容600还可以并联一个主像素存储电容610，以在所述第一薄膜晶体管310关闭后一定时间内可以持续对所述主像素电极放电，维持显示画面直至下一帧画面刷新。
在本实施例中，所述副像素电容700的第一端与所述第二薄膜晶体管320的漏极（或源极）连接，所述副像素电容700的第二端连接公共电压端。
在本实施例中，所述辅助电容710可以作为所述副像素电极的辅助电容710。所述辅助电容710的第一端可以与所述第二薄膜晶体管320的漏极（或源极）及所述第三薄膜晶体管330的源极（或漏极）连接，所述辅助电容710的第二端可以连接至彩膜基板（图中未示出）上的公共电压端。
本实施例通过对所述主像素电极、所述副像素电极设置像素电容和存储电容，可以使所述子像素单元101内的存储电容在扫描信号关闭后的一定时间内对所述像素电极进行放电，以使所述子像素单元101维持显示画面至下一帧画面刷新，进而减少频闪、画面闪烁等显示异常。
在本实施例中，所述辅助电容710可以使所述子像素单元101内的所述主电极区210和所述副电极区220之间具有电压差，从而使所述主电极区210和所述副电极区220的液晶分子偏转角度有所差异，以改善大视角色偏的问题。
请参阅图2和图3，在本申请的阵列基板中，所述阵列基板还包括设置于所述像素单元两侧的数据线400及位于相邻两条所述数据线400之间的共享电极线800，所述共享电极线800与所述第三薄膜晶体管330连接，以使所述第三薄膜晶体管330可以通过所述共享电极线800实现接地。
在本实施例中，所述共享电极线800可以与所述数据线400平行设置，以及，所述共享电极线800将所述走线区100分割成所述第一区110和所述第二区120，所述第二区120的面积大于或等于所述第一区110的面积。
在本实施例中，所述第二区120的面积可以与所述第一区110的面积相等，此时，所述共享电极线800正好处于相邻两条数据线400的中心对称线上。本实施例通过将所述共享电极线800设置在相邻两条数据线400的中心对称线上，并将所述走线区100通过所述共享电极线800分割成所述第一区110和所述第二区120，既可将所述走线区100进行准确划分，便于将所述像素电极区200向所述走线区100内延伸，也可将常规像素结构中共享电极线800在走线区100内的弯折绕线设计改为直线设计，不仅降低共享电极线800的制程难度，也可节省共享电极线800的材料，有利于压缩成本。
在本实施例中，所述第二区120的面积还可以大于所述第一区110的面积，此时，所述共享电极线800在经过所述走线区100时可以向所述第一区110的一侧偏移，从而进一步扩大所述第二区120的面积，进一步提升所述子像素单元101的开口率。此时，所述第一区110内的所述第一薄膜晶体管310、所述第二薄膜晶体管320和所述第三薄膜晶体管330的排布更加集中，制程难度也相应地增大。
请参阅图2，在本申请的阵列基板中，所述扫描线500沿所述第一区110与所述第二区120的连线方向（即所述子像素单元101的行方向）设置于所述走线区100内，以及，在所述数据线400的延伸方向上，所述第二区120内的扫描线500的宽度小于所述第一区110内的扫描线500的宽度。
本实施例通过将所述第一薄膜晶体管310、所述第二薄膜晶体管320和所述第三薄膜晶体管330集中设置于所述第一区110内，使所述第二区120内无需设置薄膜晶体管300和过孔等结构，从而可以减小所述第二区120内的扫描线500的宽度，减小所述第二区120内的不透明区域占比，进一步提升所述第二区120内的开口率。
请参阅图2，在本申请的阵列基板中，在所述数据线400的延伸方向上，所述第一延伸区211的宽度d1小于或等于所述第二延伸区221的宽度d2。
在本实施例中，在所述像素电极区200内，所述主电极区210的面积可以小于或等于所述副电极区220的面积，即在所述数据线400的延伸方向上，所述主电极区210的长度可以小于或等于所述副电极区220的长度。与此对应的，在所述数据线400的延伸方向上，所述第一延伸区211的宽度d1小于或等于所述第二延伸区221的宽度d2，也可描述为：所述第一延伸区211的面积小于或等于所述第二延伸区221的面积。
作为优选地，在本实施例中，在所述数据线400的延伸方向上，所述第一延伸区211的宽度d1小于所述第二延伸区221的宽度d2。例如，如图2所示，在所述数据线400的延伸方向上，所述第一延伸区211的宽度d1可以为10.33微米，所述第二延伸区221的宽度可以d2为21.52微米。需要说明的是，本实施例中所述第一延伸区211的宽度d1及所述第二延伸区221的宽度d2可以根据实际情况进行调整，本实施例仅以上述数值进行示例，本实施例对所述第一延伸区211和所述第二延伸区221的宽度不作具体限制。
本实施例通过以上设置，可以使所述第一延伸区211的面积与所述主电极区210的面积适配，使所述第二延伸区221的面积与所述副电极区220的面积适配，从而使所述主电极区210的开口率提升幅度与所述副电极区220的开口率提升幅度相同或相近，尽可能地减小所述主电极区210和所述副电极区220的开口率提升差异，进一步减少色偏、亮暗不均等显示不良现象。
本申请实施例还提供一种显示终端，所述显示终端包括终端主体和上述阵列基板，所述终端主体和所述阵列基板组合为一体。在本实施例中，所述显示终端可以为手机、电脑、电视、手表等智能终端。
本申请实施例通过将走线区100设置为第一区110和第二区120，并将薄膜晶体管300集中设置在所述第一区110内，使所述第二区120内未设置薄膜晶体管300，从而可以减少所述第二区120内的不透光区域占比，提高所述第二区120内的开口率，进而提高显示面板的透光率，改善显示效果。采用本申请上述技术方案之后，显示面板的开口率至少可以提升3.4%，即显示面板的透光率至少可以提升3.4%。
以上对本申请实施例所提供的一种阵列基板及显示终端进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，包括多个子像素单元，每一所述子像素单元包括走线区和位于所述走线区至少一侧的像素电极区；
    其中，所述走线区包括第一区和第二区，所述第一区内设置有至少一薄膜晶体管，所述第二区的开口率大于所述第一区的开口率。
  2. 根据权利要求1所述的阵列基板，其中，所述像素电极区向所述第二区延伸。
  3. 根据权利要求2所述的阵列基板，其中，所述像素电极区包括与所述第二区重叠的延伸区。
  4. 根据权利要求3所述的阵列基板，其中，所述像素电极区包括分别位于所述走线区两侧的主电极区和副电极区。
  5. 根据权利要求4所述的阵列基板，其中，所述延伸区包括所述主电极区向所述第二区延伸的第一延伸区和所述副电极区向所述第二区延伸的第二延伸区。
  6. 根据权利要求5所述的阵列基板，其中，所述主电极区内设置有主像素电极，所述副电极区内设置有副像素电极。
  7. 根据权利要求6所述的阵列基板，其中，所述第一区内设置有与所述主像素电极连接的第一薄膜晶体管以及与所述副像素电极连接的第二薄膜晶体管。
  8. 根据权利要求7所述的阵列基板，其中，所述第一薄膜晶体管与所述第二薄膜晶体管并联。
  9. 根据权利要求7所述的阵列基板，其中，所述第一区内还设置有与所述副像素电极连接的第三薄膜晶体管。
  10. 根据权利要求9所述的阵列基板，其中，所述第二薄膜晶体管与所述第三薄膜晶体管串联。
  11. 根据权利要求10所述的阵列基板，其中，所述副像素电极连接于所述第二薄膜晶体管和所述第三薄膜晶体管的串联电路上。
  12. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括与所述主像素电极对应的主像素电容、与所述副像素电极对应的副像素电容，以及共同连接所述第二薄膜晶体管和所述第三薄膜晶体管的辅助电容。
  13. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括设置于所述像素单元两侧的数据线及位于相邻两条所述数据线之间的共享电极线。
  14. 根据权利要求13所述的阵列基板，其中，所述共享电极线与所述第三薄膜晶体管连接。
  15. 根据权利要求14所述的阵列基板，其中，所述共享电极线将所述走线区分割成所述第一区和所述第二区，所述第二区的面积大于或等于所述第一区的面积。
  16. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括多条扫描线，多条所述扫描线与所述数据线交叉设置。
  17. 根据权利要求16所述的阵列基板，其中，所述扫描线沿所述第一区与所述第二区的连线方向设置于所述走线区内。
  18. 根据权利要求17所述的阵列基板，其中，在所述数据线的延伸方向上，所述第二区内的扫描线的宽度小于所述第一区内的扫描线的宽度。
  19. 根据权利要求16所述的阵列基板，其中，在所述数据线的延伸方向上，所述第一延伸区的宽度小于或等于所述第二延伸区的宽度。
  20. 一种显示终端，包括终端主体和如权利要求1所述的阵列基板，所述终端主体和所述阵列基板组合为一体。
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