WO2023108729A1 - 显示面板、显示面板的制作方法以及制作显示面板的机台 - Google Patents

显示面板、显示面板的制作方法以及制作显示面板的机台 Download PDF

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Publication number
WO2023108729A1
WO2023108729A1 PCT/CN2021/140173 CN2021140173W WO2023108729A1 WO 2023108729 A1 WO2023108729 A1 WO 2023108729A1 CN 2021140173 W CN2021140173 W CN 2021140173W WO 2023108729 A1 WO2023108729 A1 WO 2023108729A1
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Prior art keywords
display panel
layer
organic electronic
cathode
electronic functional
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PCT/CN2021/140173
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English (en)
French (fr)
Inventor
万之君
魏锋
李金川
曹蔚然
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to JP2021576634A priority Critical patent/JP2024508054A/ja
Priority to US17/622,812 priority patent/US20240032331A1/en
Publication of WO2023108729A1 publication Critical patent/WO2023108729A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24—Vacuum evaporation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/173—Passive-matrix OLED displays comprising banks or shadow masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask

Definitions

  • the present application relates to the technical field of display panels, in particular to a display panel, a method for manufacturing a display panel, and a machine for manufacturing a display panel.
  • IJP Ink Jet Printing
  • OLED Organic Light Emitting Diode
  • IJP Ink Jet Printing
  • evaporation process EV
  • SPT sputtering process
  • OLED panels use the IJP process to deposit OLED functional layers such as HIL (hole injection layer), HTL (hole transport layer), EML (light emitting layer), and use EV/SPT process to deposit ETL (electron transport layer), EIL (electron injection layer). layer), CAT (cathode) and other OLED functional layers.
  • HIL hole injection layer
  • HTL hole transport layer
  • EML light emitting layer
  • EV/SPT process to deposit ETL (electron transport layer), EIL (electron injection layer). layer
  • CAT cathode
  • the CAT needs to be connected to the metal wiring on the substrate to realize the driving circuit to control the OLED to emit light.
  • One way is that the CAT film layer is directly overlapped with the metal wiring. Therefore, the size of the mask opening required to deposit CAT is different from that required to deposit ETL and EIL, so as to realize the difference in the film formation area to avoid the ETL and EIL films with poor conductivity covering the metal lines and affecting CAT. Bond conduction to metal traces.
  • Embodiments of the present application provide a display panel, a manufacturing method of the display panel, and a machine for manufacturing the display panel, so as to solve the problems of simplification of the manufacturing process of the display panel and overlapping of the cathode film layer and the metal wiring in the prior art.
  • An embodiment of the present application provides a display panel, which is divided into a display area and a pad area, wherein the display panel includes:
  • a pad pattern disposed on the substrate and located in the pad area
  • an anode disposed on the substrate and located in the display area
  • a light-emitting layer disposed on the anode
  • the organic electronic functional layer includes a stacked electron transport layer and an electron injection layer.
  • the organic electronic functional layer extends from the display area to the pad area
  • the cathode extends from the display area to the pad area
  • the display panel described in some embodiments of the present application further includes a driving circuit layer disposed on the substrate, a planarization layer covering the driving circuit layer, an anode disposed on the planarization layer, disposed on the The pixel definition layer on the planarization layer and covering part of the anode, wherein the pixel definition layer forms an opening, the hole injection layer and the hole transport layer are stacked in the opening, and the light emitting layer is arranged in the on the hole transport layer.
  • the organic electronic functional layer includes an electron transport layer covering the light emitting layer, the pixel definition layer and part of the driving circuit layer and contacting the pad pattern, And the electron injection layer covers the electron transport layer, contacts the pad pattern and covers part of the pad pattern, wherein the cathode covers the electron injection layer and another part of the pad pattern.
  • the present application provides a method for manufacturing a display panel, comprising the steps of:
  • a substrate is provided, wherein the substrate area is divided into a display area and a pad area, and the substrate includes a pad pattern disposed on the pad area and a light emitting layer disposed on the display area;
  • a deposited cathode covers the organic electronic functional layer and another part of the pad pattern.
  • the step of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern and the step of depositing the The cathode covers the organic electronic functional layer and another part of the pad pattern step.
  • the step of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern includes depositing the organic electronic functional layer by vapor deposition.
  • the step of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern it also includes adding an evaporation source and The distance between the substrates is to reduce the overspray area of the organic electronic functional layer.
  • the step of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern it also includes changing the evaporation source Evaporating corners to reduce the overspray area of the organic electronic functional layer.
  • the step of depositing the cathode covering the organic electronic functional layer and another part of the pad pattern includes depositing the cathode by evaporation, wherein, The overspray area of the cathode covers the overspray area of the organic electronic functional layer and the other part of the pad pattern.
  • the step of depositing the cathode covering the organic electronic functional layer and another part of the pad pattern it also includes changing the evaporation source Evaporate corners to increase the overspray area of the cathode.
  • the step of depositing the cathode covering the organic electronic functional layer and another part of the pad pattern it also includes adding an evaporation source and distance from the substrate to increase the overspray area of the cathode.
  • the step of depositing the cathode covering the organic electronic functional layer and another part of the contact pad pattern it also includes adding a mask and the distance from the substrate to increase the overspray area of the cathode.
  • the step of depositing the cathode covering the organic electronic functional layer and another part of the pad pattern includes depositing the cathode by a sputtering method, wherein, The overspray area of the cathode covers the overspray area of the organic electronic functional layer and the other part of the pad pattern.
  • the step of depositing the cathode covering the organic electronic functional layer and another part of the pad pattern it also includes adding a sputtering target distance from the substrate to increase the overspray area of the cathode.
  • the step of depositing the cathode covering the organic electronic functional layer and another part of the contact pad pattern it also includes adding a mask and the distance from the substrate to increase the overspray area of the cathode.
  • the present application provides a machine for manufacturing a display panel, which is used to perform any of the methods for manufacturing a display panel described above, including:
  • a buffer cavity used to transport and accommodate the substrate
  • a mask alignment cavity used for covering the mask on the surface of the substrate and aligning it with the substrate
  • An evaporation/sputtering chamber for performing the steps of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern and depositing the cathode covering the organic electronic functional layer on the substrate and the pad patterning step described in another section;
  • a mask separation cavity is used to remove the mask from the substrate.
  • the machine for making display panels further includes a mask rotary cavity, and the gap between the mask rotary cavity and the mask alignment cavity and the One of the buffer chambers is respectively arranged between the mask rotary chamber and the mask separation chamber, and the two buffer chambers cooperate with the mask rotary chamber to select and transfer an appropriate mask to the mask alignment chamber for masking The alignment of the mold.
  • a buffer chamber is further provided beside the mask alignment chamber, and the buffer chamber is used to receiving and accommodating the substrate on which the hole injection layer, the hole transport layer and the light-emitting layer have been printed, and transferring the substrate to the mask alignment cavity for mask alignment.
  • the beneficial effect of the present application is: the display panel, the manufacturing method of the display panel and the machine for manufacturing the display panel provided by the present application cover the part of the pads through the overspray area of the organic electronic functional layer pattern, the overspray area of the cathode covers the overspray area of the organic electronic functional layer and the other part of the pad pattern while solving the simplification of the display panel process and the overlapping of the cathode film layer and the metal wiring in the prior art And other issues.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a method for manufacturing a display panel provided in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram during the manufacturing process of the display panel provided by the embodiment of the present application.
  • Figure 4 is a partial enlarged view of Figure 3;
  • Fig. 5 is a schematic configuration diagram of the evaporation method provided by the embodiment of the present application.
  • FIG. 6 is a schematic configuration diagram of the sputtering method provided by the embodiment of the present application.
  • Fig. 7 is a schematic cross-sectional view of the configuration of the mask and the substrate provided by the embodiment of the present application;
  • Fig. 8 is a schematic configuration diagram of a machine for manufacturing a display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the curves of the deposited film thickness versus the horizontal distance of the evaporation method and the sputtering method provided in the embodiment of the present application;
  • FIG. 10 is a schematic structural diagram of a substrate provided in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display panel made of a display panel provided in an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a display panel manufactured by the display panel provided by the embodiment of the present application.
  • a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more.
  • the term “comprise” and any variations thereof, are intended to cover a non-exclusive inclusion.
  • connection should be understood in a broad sense, for example, it can be a support connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the embodiment of the present application provides a display panel 100, which is divided into a display area AA and a pad area BA, wherein the display panel 100 includes: a substrate SB; The pad pattern BP; the anode AN disposed on the substrate SB and located in the display area AA; the light-emitting layer EL disposed on the anode AN; the organic electronic functional layer OEL covering the light-emitting layer EL;
  • the cathode CA of the organic electronic functional layer OEL wherein the organic electronic functional layer OEL also covers a part of the pad pattern BP, and the cathode CA also covers another part of the pad pattern BP.
  • the pad area BA is, for example, a peripheral circuit area outside the display area AA.
  • the organic electronic functional layer OEL includes a laminated electron transport layer ETL and electron injection layer EIL.
  • the display panel 100 in some embodiments of the present application includes a driving circuit layer DCL disposed on the substrate SB, a planarization layer PLN covering the driving circuit layer DCL, an anode AN disposed on the planarization layer PLN, disposed on The pixel definition layer PDL on the planarization layer PLN and covers part of the anode AN.
  • the pixel definition layer PDL is formed with an opening, and the hole injection layer HIL and the hole transport layer HTL are stacked in the opening.
  • the light emitting layer EL is disposed on the hole transport layer HTL.
  • the electron transport layer ETL covers the light emitting layer EL, the pixel definition layer PDL and part of the driving circuit layer DCL and contacts the pad pattern BP.
  • the electron injection layer EIL covers the electron transport layer ETL, contacts the pad pattern BP and covers part of the pad pattern BP.
  • the cathode CA covers the electron injection layer EIL and another part of the pad pattern BP.
  • the driving circuit layer DCL includes driving transistors and circuit traces, and the traces are connected to the anode AN, the pad pattern BP, etc. through openings.
  • a passivation layer is also included in the driving circuit layer DCL to provide proper insulation for wiring, for example, insulation from the electron transport layer ETL.
  • the driving circuit layer DCL is not the focus of this case, so its details are not shown.
  • FIG. 9 is a schematic diagram of the curves of the deposition film thickness versus the horizontal distance of the evaporation method and the sputtering method provided by the embodiment of the present application.
  • the opening edge of the mask MK is approximately between 0 and 0.5 of the horizontal distance in the figure.
  • the deposit will slightly exceed the opening position of the mask MK and deposit toward the unopened position of the mask MK. This area is called an overspray area (Overspray).
  • the sputtering direction of the sputtering method SPT particles is random, and the evaporation method EV particles are limited by the evaporation angle. Therefore, the overspray area SOA formed by the sputtering method SPT will be greater than the overspray area EOA formed by the evaporation method EV .
  • FIG. 3 is a schematic structural diagram during the manufacturing process of the display panel provided by the embodiment of the present application
  • FIG. 4 is a partial enlarged view of FIG. 3
  • the method of forming the organic electronic functional layer OEL also covers a part of the pad pattern BP
  • the overspray area EOA of the electronic functional layer OEL covers the part of the pad pattern BP
  • the overspray area COA of the cathode CA covers the overspray area EOA and the other part of the organic electronic functional layer OEL.
  • Pad pattern BP is a schematic structural diagram during the manufacturing process of the display panel provided by the embodiment of the present application
  • FIG. 4 is a partial enlarged view of FIG. 3 .
  • the method of forming the organic electronic functional layer OEL also covers a part of the pad pattern BP
  • the cathode CA also covers another part of the pad pattern BP includes: making the organic
  • the cathode CA can directly contact the other part of the pad pattern BP through the overspray area COA, there is no space between the overspray area COA of the cathode CA and the other part of the pad pattern BP.
  • the overspray area EOA of the electronic functional layer OEL can therefore provide a good electrical connection between the cathode CA and the pad pattern BP, solving the problem of poor overlap between the cathode and the pad pattern in the prior art.
  • FIG. 2 is a schematic flowchart of a method for manufacturing a display panel provided by an embodiment of the present application.
  • the present application provides a method for manufacturing a display panel, comprising the steps of:
  • S100 Provide a substrate, wherein the substrate area is divided into a display area and a pad area, and the substrate includes a pad pattern disposed in the pad area and a light emitting layer disposed in the display area;
  • S200 Deposit organic electronics A functional layer covering the light-emitting layer and a part of the pad pattern;
  • S300 depositing a cathode to cover the organic electronic functional layer and another part of the pad pattern.
  • the substrate SB (IJP) provided in step S100 further includes a driving circuit layer DCL disposed on the substrate SB, a planarization layer PLN covering the driving circuit layer DCL, and disposed on
  • the anode AN on the planarization layer PLN is disposed on the planarization layer PLN and covers part of the pixel definition layer PDL of the anode AN.
  • the pixel definition layer PDL is formed with an opening, and the hole injection layer HIL and the hole transport layer HTL are stacked in the opening.
  • the light emitting layer EL is disposed on the hole transport layer HTL.
  • the hole injection layer HIL, the hole transport layer HTL layer and the light emitting layer EL are prepared by a printing process IJP (Ink Jet Printing).
  • step S200: depositing an organic electronic functional layer to cover the light-emitting layer and a part of the pad pattern includes: depositing an electron transport layer ETL to cover the light-emitting layer EL, pixels A definition layer PCL, a part of the driving circuit layer DCL and contacting the pad pattern BP, and an electron injection layer EIL covering the electron transport layer ETL, contacting the pad pattern BP and covering part of the pad pattern BP are deposited.
  • step S300: depositing a cathode covering the organic electronic functional layer and another part of the pad pattern includes: depositing a cathode CA covering the electron injection layer EIL and another part of the pad pattern BP.
  • FIG. 2 is a schematic flowchart of a method for manufacturing a display panel provided by an embodiment of the present application.
  • the step S200 of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern and the depositing the The cathode covers the organic electronic functional layer and another part of the pad pattern step S300.
  • the manufacturing method of the display panel utilizes the overspray area EOA of the organic electronic functional layer OEL to cover the part of the pad pattern BP, and the overspray area COA of the cathode CA covers the organic electronic functional layer OEL.
  • the step S200 of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern and depositing the cathode covering the same mask MK can be performed.
  • the step S300 of the organic electronic functional layer and the other part of the pad pattern does not need to use two masks with different opening sizes, and can provide a good electrical connection between the cathode CA and the pad pattern BP, and at the same time. The problem of poor overlap between the cathode and the pad pattern in the prior art is solved.
  • FIG. 5 is a schematic configuration diagram of the evaporation method provided by the embodiment of the present application.
  • the step S200 of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern includes depositing the organic electronic functional layer by evaporation.
  • the step S200 of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern it also includes reducing the evaporation source EM and The distance d1 of the substrate SB is to reduce the overspray area EOA of the organic electronic functional layer OEL.
  • the distance from the intersection of the surface SS of the substrate SB and the normal line NL at the center of the surface TS of the evaporation source EM to the surface TS of the evaporation source EM is d1.
  • the evaporation source EM is disposed on the heating seat EH for heating and evaporating the evaporation source EM to coat the surface of the substrate SB through the mask MK.
  • step S200 of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern it also includes changing the evaporation source EM
  • the corner EA is evaporated to reduce the overspray area EOA of the organic electronic functional layer OEL.
  • angle plates AP are arranged on both sides of the evaporation source EM for adjusting the evaporation angle EA.
  • the evaporation source EM is arranged on the heating seat EH for heating and evaporating the evaporation source EM, which is limited by the angle plate AP and coated on the surface of the substrate SB through the mask MK.
  • the angle plate AP is adjusted to make the evaporation angle EA larger, the length of the overspray area EOA is shorter.
  • the deposition of the cathode CA and the deposition of the organic electronic functional layer OEL both use the evaporation method, it can be set that when the cathode CA is deposited, the evaporation angle EA is changed to be smaller, so that the cathode CA is oversprayed.
  • the length of the area EOA is increased.
  • the evaporation angle EA is increased to reduce the length of the overspray area EOA of the organic electronic functional layer OEL.
  • FIG. 6 is a schematic configuration diagram of the sputtering method provided by the embodiment of the present application.
  • the step S300 of depositing the cathode covering the organic electronic functional layer and another part of the pad pattern includes depositing the cathode by evaporation or sputtering CA, wherein, the overspray area COA of the cathode CA covers the overspray area EOA of the organic electronic functional layer OEL and the other part of the pad pattern BP.
  • the sputtering target SM is set on the sputtering platform STP and connected to a negative charge, and positively charged argon ions Ar+ are introduced to bombard the sputtering target SM to make the sputtering material
  • the atomic groups are scattered and coated on the surface of the substrate SB through the mask MK.
  • the sputtering direction of the particles produced by the sputtering method is relatively random. Therefore, the overspray area produced by the sputtering method is larger than that of the evaporation method.
  • Fig. 2, Fig. 4 and Fig. 6 in the manufacturing method of the display panel in some embodiments of the present application, in the step of depositing the cathode covering the organic electronic functional layer and another part of the pad pattern In S300, it also includes increasing the distance d2 between the evaporation source EM or the sputtering target SM and the substrate SB to increase the overspray area of the cathode.
  • the distance between the surface TS of the sputtering target SM and the surface SS of the substrate SB is d2. Similar to the evaporation method, the longer the distance d2 is, the more chaotic the direction of the sputtered particles is, and the longer the length of the overspray area COA. On the contrary, reducing the distance d2 can reduce the length of the overspray area COA of the cathode.
  • FIG. 7 is a schematic cross-sectional view of the configuration of the mask and the substrate provided by the embodiment of the present application.
  • the step S300 of depositing the cathode covering the organic electronic functional layer and another part of the contact pad pattern it also includes adding a mask MK and the The distance MSD of the substrate SB is increased to increase the overspray area COA of the cathode CA.
  • the present application does not limit the specific manner of increasing the distance MSD between the mask MK and the substrate SB.
  • a spacer SR is provided between the mask MK and the substrate SB to increase the distance MSD.
  • the spacer SR is, for example, a protrusion formed on the mask MK by etching, stamping, soldering, etc., or a spacer disposed between the mask MK and the substrate SB.
  • the present application does not limit the method of making the protrusions or pads, nor does it limit the shape of the protrusions or pads.
  • the contact area of BP can therefore provide a good electrical connection between the cathode CA and the pad pattern BP, solving the problem of poor overlap between the cathode and the pad pattern in the prior art.
  • FIG. 8 is a schematic configuration diagram of a machine for manufacturing a display panel provided by an embodiment of the present application.
  • the present application provides a machine PM for manufacturing a display panel, which is used to execute any one of the above-mentioned display panel manufacturing methods, including: a buffer chamber BC, used to transport and accommodate the substrate SB ( IJP); mask alignment chamber AC, for covering the mask MK on the surface of the substrate SB (IJP) and facing the substrate SB (IJP); evaporation/sputtering chamber E/SC, for alignment
  • the substrate SB (IJP) performs the step S200 of depositing the organic electronic functional layer covering the light-emitting layer and a part of the pad pattern and depositing the cathode covering the organic electronic functional layer and another part of the Pad patterning step S300 ; and a mask separation chamber SC for removing the mask MK from the substrate SB(IJP).
  • the buffer cavity BC receives and accommodates the substrate SB (IJP) on which the hole injection layer HIL, the hole transport layer HTL layer and the light emitting layer EL have been printed. And the substrate SB (IJP) is transferred to the mask alignment chamber AC for alignment of the mask MK.
  • the machine PM for manufacturing the display panel also includes a mask rotary cavity TC, and a buffer cavity BC is respectively included between the mask rotary cavity TC, the mask alignment cavity AC, and the mask separation cavity SC.
  • the two buffer chambers BC cooperate with the mask rotary chamber TC to select and transfer the appropriate mask MK to the mask alignment chamber AC for alignment of the mask MK.
  • the manufacturing method of the display panel utilizes the overspray area EOA of the organic electronic functional layer OEL to cover the part of the pad pattern BP, and the overspray area COA of the cathode CA covers the organic electronic functional layer OEL.
  • the overspray area EOA of the layer OEL can therefore be deposited using the same mask MK in the evaporation/sputtering chamber E/SC.
  • the organic electronic functional layer covers the light-emitting layer and a part of the pad pattern.
  • Step S200 and step S300 of depositing the cathode covering the organic electronic functional layer and the other part of the pad pattern do not need to use two masks with different opening sizes, so there is no need for two additional production line platform layouts Circular process.
  • the manufacturing process of the display panel is simplified, the cost is reduced, and a good electrical connection between the cathode CA and the pad pattern BP can be provided, so as to solve the problem of poor overlap between the cathode and the pad pattern in the prior art.
  • the part of the pad pattern is covered by the overspray area of the organic electronic functional layer, and the overspray area of the cathode is The spraying area covers the overspraying area of the organic electronic functional layer and the other part of the pad pattern while solving the problems of simplification of the display panel manufacturing process and overlapping of the cathode film layer and the metal wiring in the prior art.
  • the display panel, the method for manufacturing the display panel, and the machine for manufacturing the display panel provided in the embodiments of the present application are described above in detail.

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  • Chemical Kinetics & Catalysis (AREA)
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  • Metallurgy (AREA)
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Abstract

一种显示面板（100）、显示面板（100）的制作方法以及制作显示面板（100）的机台（PM）。通过有机电子功能层（OEL）的过喷区（EOA）覆盖一部分接垫图案（BP），阴极（CA）的过喷区（COA）覆盖有机电子功能层（OEL）的过喷区（EOA）及另一部分接垫图案（BP），同时解决现有技术的显示面板（100）制程简化以及阴极（CA）膜层与金属走线搭接等问题。

Description

显示面板、显示面板的制作方法以及制作显示面板的机台 技术领域
本申请涉及显示面板技术领域，尤其涉及一种显示面板、显示面板的制作方法以及制作显示面板的机台。
 背景技术
近年来，打印制程IJP（Ink Jet Printing）有可能大幅降低制造成本，使有机发光二极管(Organic Light Emitting Diode, OLED)在包括电视机和平板电脑在内的产品应用中更具成本竞争力。对于OLED面板，其制作除了采用喷墨打印制程（IJP）外，仍需使用蒸镀制程（EV）或溅射制程（SPT）。由于ETM（电子传输材料）和EIM（电子注入材料）的墨水的材料限制。目前OLED面板采用IJP制程沉积HIL（空穴注入层）、HTL（空穴传输层）、EML（发光层）等OLED功能层，采用EV/SPT制程沉积ETL（电子传输层）、EIL（电子注入层）、CAT（阴极）等OLED功能层。
CAT需要与基板上的金属走线搭接导通，实现驱动电路控制OLED发光。一种方式为CAT膜层直接与金属走线搭接。因此，沉积CAT所需要的掩模开口与沉积ETL、EIL所需要的掩模开口大小不同，来实现成膜区域的不同以避免导电性较差的ETL、EIL膜覆盖于金属走线上影响CAT与金属走线的搭接导通。
对于OLED面板蒸镀产线，在站台设计上，需要根据不同的掩模而设计不同的循环流程。基于上述沉积CAT所需要的掩模开口与沉积ETL、EIL所需要的掩模开口大小不同的设计，其产线站台布局上至少需要2个循环流程，设备投资成本高。
因此，目前急需能够同时解决上述显示面板制程简化以及CAT膜层与金属走线搭接的问题。
 技术问题
本申请实施例提供一种显示面板、显示面板的制作方法以及制作显示面板的机台，以解决现有技术的显示面板制程简化以及阴极膜层与金属走线搭接等问题。
 技术解决方案
本申请实施例提供一种显示面板，区分为显示区及接垫区，其中，所述显示面板包括：
基板；
设置于所述基板上且位于所述接垫区的接垫图案；
设置于所述基板上且位于所述显示区的阳极；
设置于所述阳极上的发光层；
覆盖所述发光层的有机电子功能层；以及
覆盖所述有机电子功能层的阴极，其中，所述有机电子功能层还覆盖一部分所述接垫图案，所述阴极还覆盖另一部分所述接垫图案。
在本申请的一些实施例所述的显示面板中，所述有机电子功能层包括层叠的电子传输层及电子注入层。
在本申请的一些实施例所述的显示面板中，所述有机电子功能层从所述显示区延伸至所述接垫区，所述阴极从所述显示区延伸至所述接垫区。
在本申请的一些实施例所述的显示面板还包括设置于所述基板上的驱动电路层，覆盖所述驱动电路层的平坦化层，设置于所述平坦化层上的阳极, 设置于所述平坦化层上并覆盖部分所述阳极的像素定义层，其中所述像素定义层形成开孔，电洞注入层及电洞传输层层叠设置于所述开孔中，发光层设置于所述电洞传输层上。
在本申请的一些实施例所述的显示面板中，所述有机电子功能层包括电子传输层覆盖所述发光层、所述像素定义层及部分所述驱动电路层并接触所述接垫图案，以及电子注入层覆盖所述电子传输层、接触所述接垫图案并覆盖部分所述接垫图案，其中，所述阴极覆盖所述电子注入层及另一部分的所述接垫图案。
在另一方面，本申请提供一种显示面板的制作方法，包括步骤：
提供基板，其中，所述基板区分为显示区及接垫区，所述基板包括设置于所述接垫区的接垫图案以及设置于所述显示区的发光层；
沉积有机电子功能层覆盖所述发光层及一部分所述接垫图案；以及
沉积阴极覆盖所述有机电子功能层及另一部分所述接垫图案。
在本申请的一些实施例所述的显示面板的制作方法中，采用同一掩模进行所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案步骤及所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案步骤。
在本申请的一些实施例所述的显示面板的制作方法中，所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤包括采用蒸镀法沉积所述有机电子功能层，其中，所述有机电子功能层的过喷区覆盖所述一部分接垫图案。
在本申请的一些实施例所述的显示面板的制作方法中，在所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤中，还包括增加蒸镀源与所述基板的距离以缩小所述有机电子功能层的所述过喷区。
在本申请的一些实施例所述的显示面板的制作方法中，在所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤中，还包括改变蒸镀源的蒸镀角以缩小所述有机电子功能层的所述过喷区。
在本申请的一些实施例所述的显示面板的制作方法中，沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤包括采用蒸镀法沉积所述阴极，其中，所述阴极的过喷区覆盖所述有机电子功能层的所述过喷区及所述另一部分接垫图案。
在本申请的一些实施例所述的显示面板的制作方法中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括改变蒸镀源的蒸镀角以增加所述阴极的所述过喷区。
在本申请的一些实施例所述的显示面板的制作方法中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括增加蒸镀源与所述基板的距离以增加所述阴极的所述过喷区。
在本申请的一些实施例所述的显示面板的制作方法中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括增加掩模与所述基板的距离以增加所述阴极的所述过喷区。
在本申请的一些实施例所述的显示面板的制作方法中，沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤包括采用溅镀法沉积所述阴极，其中，所述阴极的过喷区覆盖所述有机电子功能层的所述过喷区及所述另一部分接垫图案。
在本申请的一些实施例所述的显示面板的制作方法中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括增加溅镀靶材与所述基板的距离以增加所述阴极的所述过喷区。
在本申请的一些实施例所述的显示面板的制作方法中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括增加掩模与所述基板的距离以增加所述阴极的所述过喷区。
在另一方面，本申请提供一种制作显示面板的机台，用以执行上述任一所述的显示面板的制作方法，包括：
缓冲腔，用以传送并容置所述基板；
掩模对位腔，用以将掩模覆盖于所述基板表面并对位于所述基板；
蒸镀/溅镀腔，用以对所述基板执行所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案步骤及所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案步骤；以及
掩模分离腔，用以将所述掩模从所述基板上移开。
在本申请的一些实施例所述的制作显示面板的机台中，所述制作显示面板的机台还包括掩模回转腔，所述掩模回转腔与所述掩模对位腔之间及所述掩模回转腔与所述掩模分离腔之间分别设置一个所述缓冲腔，所述两个缓冲腔配合掩模回转腔用以选择并传送适当的掩模至掩模对位腔进行掩模的对位。
在本申请的一些实施例所述的制作显示面板的机台中，所述掩模对位腔旁还设置一个所述缓冲腔，所述缓冲腔用以从所述制作显示面板的机台的外部接收并容置已完成电洞注入层、电洞传输层层及发光层打印的所述基板，并将所述基板传送至掩模对位腔进行掩模的对位。
 有益效果
本申请的有益效果为：本申请提供的所述显示面板、所述显示面板的制作方法以及所述制作显示面板的机台，通过所述有机电子功能层的过喷区覆盖所述一部分接垫图案，所述阴极的过喷区覆盖所述有机电子功能层的所述过喷区及所述另一部分接垫图案同时解决现有技术的显示面板制程简化以及阴极膜层与金属走线搭接等问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1是本申请实施例提供的显示面板的结构示意图；
图2是本申请实施例提供的显示面板的制作方法的流程示意图；
图3是本申请实施例提供的显示面板制作过程中的结构示意图；
图4是图3的局部放大图；
图5是本申请实施例提供的蒸镀法的配置示意图；
图6是本申请实施例提供的溅镀法的配置示意图；
图7是本申请实施例提供的掩模与基板的配置剖视示意图；
图8是本申请实施例提供的制作显示面板的机台的配置示意图；
图9是本申请实施例提供的蒸镀法与溅镀法的沉积膜厚对水平距离的曲线示意图；
图10是本申请实施例提供的基板的结构示意图；
图11是本申请实施例提供的显示面板制作的显示面板结构示意图；以及
图12是本申请实施例提供的显示面板制作的显示面板结构示意图。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是支撑连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和实施例对本申请作进一步说明。
请参照图1，图1是本申请实施例提供的显示面板的结构示意图。本申请实施例提供一种显示面板100，区分为显示区AA及接垫区BA，其中，所述显示面板100包括：基板SB；设置于所述基板SB上且位于所述接垫区BA的接垫图案BP；设置于所述基板SB上且位于所述显示区AA的阳极AN；设置于所述阳极AN上的发光层EL；覆盖所述发光层EL的有机电子功能层OEL；以及覆盖所述有机电子功能层OEL的阴极CA，其中，所述有机电子功能层OEL还覆盖一部分所述接垫图案BP，所述阴极CA还覆盖另一部分所述接垫图案BP。
具体的，在本申请的一些实施例的显示面板100，所述接垫区BA例如为所述显示区AA之外的外围电路区。
在本申请的一些实施例的显示面板100中，所述有机电子功能层OEL包括层叠的电子传输层ETL及电子注入层EIL。
具体的，在本申请的一些实施例的显示面板100包括设置于基板SB上的驱动电路层DCL，覆盖驱动电路层DCL的平坦化层PLN，设置于平坦化层PLN上的阳极AN, 设置于平坦化层PLN上并覆盖部分阳极AN的像素定义层PDL。其中像素定义层PDL形成有开孔，电洞注入层HIL及电洞传输层HTL层叠设置于所述开孔中。发光层EL设置于所述电洞传输层HTL上。所述电子传输层ETL覆盖发光层EL、像素定义层PDL及部分驱动电路层DCL并接触所述接垫图案BP。所述电子注入层EIL覆盖所述电子传输层ETL、接触所述接垫图案BP并覆盖部分所述接垫图案BP。阴极CA覆盖所述电子注入层EIL及另一部分的所述接垫图案BP。
具体的，驱动电路层DCL中包括驱动晶体管及电路走线，走线通过开孔连接阳极AN、接垫图案BP等。驱动电路层DCL中还包含钝化层以提供走线适当的绝缘，例如与所述电子传输层ETL绝缘。驱动电路层DCL并非本案的重点，因此并未绘示其细节。
具体的，请参照图9，图9是本申请实施例提供的蒸镀法与溅镀法的沉积膜厚对水平距离的曲线示意图。具体的，掩膜MK的开口边缘约在图中的水平距离0至0.5之间。沉积过程中，因为掩膜MK与基板SB无法完全贴紧，沉积物会稍微超过掩膜MK的开口位置而往掩膜MK未开口的位置沉积，这个区域称为过喷区(Overspray)。具体的，溅镀法SPT粒子溅射方向随机，而蒸镀法EV粒子受蒸镀角限制，因此，溅镀法SPT形成的过喷区SOA会大于蒸镀法EV所形成的过喷区EOA。
具体的，请参照图3及图4，图3是本申请实施例提供的显示面板制作过程中的结构示意图，图4是图3的局部放大图。应用在本申请实施例中，形成所述有机电子功能层OEL还覆盖一部分所述接垫图案BP，所述阴极CA还覆盖另一部分所述接垫图案BP的结构的方式包括：使所述有机电子功能层OEL的过喷区EOA覆盖所述一部分接垫图案BP，且使所述阴极CA的过喷区COA覆盖所述有机电子功能层OEL的所述过喷区EOA及所述另一部分接垫图案BP。
具体的，由于所述阴极CA能通过过喷区COA直接接触所述另一部分接垫图案BP，所述阴极CA的过喷区COA与所述另一部分接垫图案BP之间没有间隔所述有机电子功能层OEL的所述过喷区EOA，因此可以提供所述阴极CA与所述接垫图案BP之间良好的电连接，解决现有技术阴极与接垫图案搭接不良的问题。
请参照图2，图2是本申请实施例提供的显示面板的制作方法的流程示意图。在另一方面，本申请提供一种显示面板的制作方法，包括步骤：
S100：提供基板，其中，所述基板区分为显示区及接垫区，所述基板包括设置于所述接垫区的接垫图案以及设置于所述显示区的发光层；S200：沉积有机电子功能层覆盖所述发光层及一部分所述接垫图案；以及S300：沉积阴极覆盖所述有机电子功能层及另一部分所述接垫图案。
具体的，请参照图10，图10是本申请实施例提供的基板的结构示意图。在本申请的一些实施例的显示面板的制作方法中，步骤S100提供的基板SB(IJP)还包括设置于基板SB上的驱动电路层DCL，覆盖驱动电路层DCL的平坦化层PLN，设置于平坦化层PLN上的阳极AN, 设置于平坦化层PLN上并覆盖部分阳极AN的像素定义层PDL。其中像素定义层PDL形成有开孔，电洞注入层HIL及电洞传输层HTL层叠设置于所述开孔中。发光层EL设置于所述电洞传输层HTL上。
具体的，电洞注入层HIL、电洞传输层HTL层及发光层EL采用打印制程IJP（Ink Jet Printing）制备。
具体的，请参照图11及图12，图11、图12是本申请实施例提供的显示面板制作的显示面板结构示意图。在本申请的一些实施例的显示面板的制作方法中，步骤S200：沉积有机电子功能层覆盖所述发光层及一部分所述接垫图案包括：沉积电子传输层ETL覆盖所述发光层EL、像素定义层PCL、部分驱动电路层DCL并接触所述接垫图案BP，以及沉积电子注入层EIL覆盖所述电子传输层ETL、接触所述接垫图案BP并覆盖部分所述接垫图案BP。
具体的，请参照图1。在本申请的一些实施例的显示面板的制作方法中，步骤S300：沉积阴极覆盖所述有机电子功能层及另一部分所述接垫图案包括：沉积阴极CA覆盖所述电子注入层EIL及另一部分的所述接垫图案BP。
请参照图2、图3及图4，图2是本申请实施例提供的显示面板的制作方法的流程示意图。在本申请的一些实施例的显示面板的制作方法中，采用同一掩模MK进行所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案步骤S200及所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案步骤S300。
具体的，本申请实施例提供的显示面板的制作方法利用所述有机电子功能层OEL的过喷区EOA覆盖所述一部分接垫图案BP，所述阴极CA的过喷区COA覆盖所述有机电子功能层OEL的所述过喷区EOA及所述另一部分接垫图案BP。因此，所述阴极CA能通过过喷区COA直接接触所述另一部分接垫图案BP，所述阴极CA的过喷区COA与所述另一部分接垫图案BP之间没有间隔所述有机电子功能层OEL的所述过喷区EOA，因此可以采用同一掩模MK进行所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案步骤S200及所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案步骤S300，不需使用两个不同开口尺寸的掩膜，且可提供所述阴极CA与所述接垫图案BP之间良好的电连接，同时解决现有技术阴极与接垫图案搭接不良的问题。
请参照图2、图4及图5，图5是本申请实施例提供的蒸镀法的配置示意图。在本申请的一些实施例的显示面板的制作方法中，所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤S200包括采用蒸镀法沉积所述有机电子功能层OEL，其中，所述有机电子功能层OEL的过喷区EOA覆盖所述一部分接垫图案BP。
请参照图2、图4及图5。在本申请的一些实施例的显示面板的制作方法中，在所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤S200中，还包括减少蒸镀源EM与所述基板SB的距离d1以缩小所述有机电子功能层OEL的所述过喷区EOA。
具体的，基板SB的表面SS与蒸镀源EM表面TS中心的法线NL的交点至蒸镀源EM表面TS的距离为d1。蒸镀源EM设置于加热座EH上，用以将蒸镀源EM加热蒸发而通过掩膜MK涂布于基板SB表面。当距离d1越长，越不易控制蒸镀粒子的行进方向，因此较过喷区EOA的长度较长。
请参照图2、图4及图5。在本申请的一些实施例的显示面板的制作方法中，在所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤S200中，还包括改变蒸镀源EM的蒸镀角EA以缩小所述有机电子功能层OEL的所述过喷区EOA。
具体的，蒸镀源EM两侧设置有角度板AP，用以调整蒸镀角EA。蒸镀源EM设置于加热座EH上，用以将蒸镀源EM加热蒸发，经过角度板AP的限制而通过掩膜MK涂布于基板SB表面。当调整角度板AP使蒸镀角EA越大，过喷区EOA的长度越短。
具体的，若沉积所述阴极CA与沉积所述有机电子功能层OEL均使用蒸镀法，则可设置在沉积所述阴极CA时，将蒸镀角EA改小，使所述阴极CA过喷区EOA的长度增加。在沉积所述有机电子功能层OEL时，将蒸镀角EA改大，使所述有机电子功能层OEL的过喷区EOA的长度减小。
请参照图2、图4及图6，图6是本申请实施例提供的溅镀法的配置示意图。在本申请的一些实施例的显示面板的制作方法中，沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤S300包括采用蒸镀法或溅镀法沉积所述阴极CA，其中，所述阴极CA的过喷区COA覆盖所述有机电子功能层OEL的所述过喷区EOA及所述另一部分接垫图案BP。
具体的，以溅镀法沉积所述阴极CA为例，溅镀靶材SM设置于溅镀平台STP上并接负电，引入带正电的氩离子Ar+轰击溅镀靶材SM使溅镀材料中的原子团飞散而通过掩膜MK涂布于基板SB表面。溅镀法产生的粒子溅射方向较随机。因此与蒸镀法相比，溅镀法产生的过喷区较大。
请参照图2、图4及图6，在本申请的一些实施例的显示面板的制作方法中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤S300中，还包括增加蒸镀源EM或溅镀靶材SM与所述基板SB的距离d2以增加所述阴极的所述过喷区。
具体的，以溅镀法沉积所述阴极CA为例，溅镀靶材SM表面TS与基板SB表面SS的距离为d2。与蒸镀法类似，距离d2越长，溅镀粒子的行进方向越混乱，过喷区COA的长度越长。相反的，减少距离d2，可以减少所述阴极的过喷区COA的长度。
请参照图2、图4及图7，图7是本申请实施例提供的掩模与基板的配置剖视示意图。在本申请的一些实施例的显示面板的制作方法中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤S300中，还包括增加掩模MK与所述基板SB的距离MSD以增加所述阴极CA的所述过喷区COA。本申请不限制增加掩模MK与所述基板SB的距离MSD的具体方式。
具体的，在本申请的一些实施例的显示面板的制作方法中，在所述掩模MK与所述基板SB之间设置间隔物SR以增加距离MSD。所述间隔物SR例如为利用蚀刻、冲压、焊铸等方式在所述掩模MK形成的凸起物，或是设置于所述掩模MK与所述基板SB之间的垫片。本申请不限制凸起物或垫片的制作方式，也不限制凸起物或垫片的形状。
具体的，增加所述阴极CA的所述过喷区COA及/或缩小所述有机电子功能层OEL的所述过喷区EOA可以增加所述阴极CA的所述过喷区COA与接垫图案BP的接触面积，因此可以提供所述阴极CA与所述接垫图案BP之间良好的电连接，解决现有技术阴极与接垫图案搭接不良的问题。
请参照图2及图8，图8是本申请实施例提供的制作显示面板的机台的配置示意图。在另一方面，本申请提供一种制作显示面板的机台PM，用以执行上述任一所述的显示面板的制作方法，包括：缓冲腔BC，用以传送并容置所述基板SB(IJP)；掩模对位腔AC，用以将掩模MK覆盖于所述基板SB(IJP)表面并对位于所述基板SB(IJP)；蒸镀/溅镀腔E/SC，用以对所述基板SB(IJP)执行所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案步骤S200及所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案步骤S300；以及掩模分离腔SC，用以将所述掩模MK从所述基板SB(IJP)上移开。
具体的，所述缓冲腔BC，接收并容置已完成电洞注入层HIL、电洞传输层HTL层及发光层EL打印的所述基板SB(IJP)。并将所述基板SB(IJP)传送至掩模对位腔AC进行掩模MK的对位。
具体的，所述制作显示面板的机台PM还包括掩模回转腔TC，所述掩模回转腔TC与掩模对位腔AC及掩模分离腔SC之间各包括一个缓冲腔BC，这两个缓冲腔BC配合掩模回转腔TC用以选择并传送适当的掩模MK至掩模对位腔AC进行掩模MK的对位。
具体的，本申请实施例提供的显示面板的制作方法利用所述有机电子功能层OEL的过喷区EOA覆盖所述一部分接垫图案BP，所述阴极CA的过喷区COA覆盖所述有机电子功能层OEL的所述过喷区EOA及所述另一部分接垫图案BP。因此，所述阴极CA能通过过喷区COA直接接触所述另一部分接垫图案BP，所述阴极CA的过喷区COA与所述另一部分接垫图案BP之间没有间隔所述有机电子功能层OEL的所述过喷区EOA，因此可以在蒸镀/溅镀腔E/SC中采用同一掩模MK进行所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案步骤S200及所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案步骤S300，不需使用两个不同开口尺寸的掩膜，因此不需要额外的产线站台布局2个循环流程。简化显示面板制程、降低成本且可提供所述阴极CA与所述接垫图案BP之间良好的电连接，解决现有技术阴极与接垫图案搭接不良的问题。
本申请提供的所述显示面板、所述显示面板的制作方法以及所述制作显示面板的机台，通过所述有机电子功能层的过喷区覆盖所述一部分接垫图案，所述阴极的过喷区覆盖所述有机电子功能层的所述过喷区及所述另一部分接垫图案同时解决现有技术的显示面板制程简化以及阴极膜层与金属走线搭接等问题。
以上对本申请实施例所提供的所述显示面板、所述显示面板的制作方法以及所述制作显示面板的机台进行了详细介绍。
以上各个操作的具体实施可参见前面的实施例，在此不再赘述。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，区分为显示区及接垫区，其中，所述显示面板包括：
    基板；
    设置于所述基板上且位于所述接垫区的接垫图案；
    设置于所述基板上且位于所述显示区的阳极；
    设置于所述阳极上的发光层；
    覆盖所述发光层的有机电子功能层；以及
    覆盖所述有机电子功能层的阴极，其中，所述有机电子功能层还覆盖一部分所述接垫图案，所述阴极还覆盖另一部分所述接垫图案。
  2. 根据权利要求1所述的显示面板，其中，所述有机电子功能层包括层叠的电子传输层及电子注入层。
  3. 根据权利要求1所述的显示面板，其中，所述有机电子功能层从所述显示区延伸至所述接垫区，所述阴极从所述显示区延伸至所述接垫区。
  4. 根据权利要求1所述的显示面板，还包括设置于所述基板上的驱动电路层，覆盖所述驱动电路层的平坦化层，设置于所述平坦化层上的阳极, 设置于所述平坦化层上并覆盖部分所述阳极的像素定义层，其中所述像素定义层形成开孔，电洞注入层及电洞传输层层叠设置于所述开孔中，发光层设置于所述电洞传输层上。
  5. 根据权利要求4所述的显示面板，其中，所述有机电子功能层包括电子传输层覆盖所述发光层、所述像素定义层及部分所述驱动电路层并接触所述接垫图案，以及电子注入层覆盖所述电子传输层、接触所述接垫图案并覆盖部分所述接垫图案，其中，所述阴极覆盖所述电子注入层及另一部分的所述接垫图案。
  6. 一种显示面板的制作方法，包括步骤：
    提供基板，其中，所述基板区分为显示区及接垫区，所述基板包括设置于所述接垫区的接垫图案以及设置于所述显示区的发光层；
    沉积有机电子功能层覆盖所述发光层及一部分所述接垫图案；以及
    沉积阴极覆盖所述有机电子功能层及另一部分所述接垫图案。
  7. 根据权利要求6所述的显示面板的制作方法，其中，采用同一掩模进行所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案步骤及所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案步骤。
  8. 根据权利要求6所述的显示面板的制作方法，其中，所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤包括采用蒸镀法沉积所述有机电子功能层，其中，所述有机电子功能层的过喷区覆盖所述一部分接垫图案。
  9. 根据权利要求8所述的显示面板的制作方法，其中，在所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤中，还包括增加蒸镀源与所述基板的距离以缩小所述有机电子功能层的所述过喷区。
  10. 根据权利要求8所述的显示面板的制作方法，其中，在所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案的步骤中，还包括改变蒸镀源的蒸镀角以缩小所述有机电子功能层的所述过喷区。
  11. 根据权利要求6所述的显示面板的制作方法，其中，沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤包括采用蒸镀法沉积所述阴极，其中，所述阴极的过喷区覆盖所述有机电子功能层的所述过喷区及所述另一部分接垫图案。
  12. 根据权利要求11所述的显示面板的制作方法，其中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括改变蒸镀源的蒸镀角以增加所述阴极的所述过喷区。
  13. 根据权利要求11所述的显示面板的制作方法，其中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括增加蒸镀源与所述基板的距离以增加所述阴极的所述过喷区。
  14. 根据权利要求11所述的显示面板的制作方法，其中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括增加掩模与所述基板的距离以增加所述阴极的所述过喷区。
  15. 根据权利要求6所述的显示面板的制作方法，其中，沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤包括采用溅镀法沉积所述阴极，其中，所述阴极的过喷区覆盖所述有机电子功能层的所述过喷区及所述另一部分接垫图案。
  16. 根据权利要求15所述的显示面板的制作方法，其中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括增加溅镀靶材与所述基板的距离以增加所述阴极的所述过喷区。
  17. 根据权利要求15所述的显示面板的制作方法，其中，在所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案的步骤中，还包括增加掩模与所述基板的距离以增加所述阴极的所述过喷区。
  18. 一种制作显示面板的机台，用以执行权利要求6的显示面板的制作方法，包括：
    缓冲腔，用以传送并容置所述基板；
    掩模对位腔，用以将掩模覆盖于所述基板表面并对位于所述基板；
    蒸镀/溅镀腔，用以对所述基板执行所述沉积所述有机电子功能层覆盖所述发光层及一部分所述接垫图案步骤及所述沉积所述阴极覆盖所述有机电子功能层及另一部分所述接垫图案步骤；以及
    掩模分离腔，用以将所述掩模从所述基板上移开。
  19. 根据权利要求18所述的制作显示面板的机台，其中，所述制作显示面板的机台还包括掩模回转腔，所述掩模回转腔与所述掩模对位腔之间及所述掩模回转腔与所述掩模分离腔之间分别设置一个所述缓冲腔，所述两个缓冲腔配合掩模回转腔用以选择并传送适当的掩模至掩模对位腔进行掩模的对位。
  20. 根据权利要求19所述的制作显示面板的机台，其中，所述掩模对位腔旁还设置一个所述缓冲腔，所述缓冲腔用以从所述制作显示面板的机台的外部接收并容置已完成电洞注入层、电洞传输层层及发光层打印的所述基板，并将所述基板传送至掩模对位腔进行掩模的对位。
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