WO2023108612A1 - 像素电路、显示装置及其驱动方法 - Google Patents

像素电路、显示装置及其驱动方法 Download PDF

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Publication number
WO2023108612A1
WO2023108612A1 PCT/CN2021/139163 CN2021139163W WO2023108612A1 WO 2023108612 A1 WO2023108612 A1 WO 2023108612A1 CN 2021139163 W CN2021139163 W CN 2021139163W WO 2023108612 A1 WO2023108612 A1 WO 2023108612A1
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Prior art keywords
transistor
electrically connected
drain
gate
source
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PCT/CN2021/139163
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English (en)
French (fr)
Inventor
曾勉
孙亮
Original Assignee
武汉华星光电半导体显示技术有限公司
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Priority to US17/622,785 priority Critical patent/US20240038161A1/en
Publication of WO2023108612A1 publication Critical patent/WO2023108612A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the present application relates to the field of display technology, in particular to a pixel circuit, a display device and a driving method thereof.
  • the display device may include pixel circuits.
  • Each pixel circuit may include a transistor, a light emitting element electrically connected to the transistor, and a capacitor.
  • the transistors may be turned on in response to corresponding signals provided through the lines, and a predetermined driving current may be generated by the turned-on transistors.
  • the light emitting element can emit light in response to a driving current.
  • the present application provides a pixel circuit, a display device and a driving method thereof, which can reset and compensate the pixel circuit under low-frequency driving, improve the driving efficiency of the display device, and minimize the power consumption of the display device.
  • the present application provides a pixel circuit, which includes:
  • the first transistor, the first transistor and the light-emitting element are connected in series between the first power supply and the second power supply, and the first transistor controls the light-emitting element flowing through the light-emitting element based on the voltage of the gate of the first transistor. drive current of the element;
  • the second transistor is electrically connected to the first transistor, and the second transistor is turned off during the display scanning period of a frame period in response to the timing voltage signal provided by the timing voltage line, and is turned off during the display scanning period of a frame period. turned on during the self-scanning period to reset the first transistor during the self-scanning period of one frame period.
  • the gate of the second transistor is electrically connected to the timing voltage line
  • the source of the second transistor is electrically connected to the reset power supply
  • the drain of the second transistor is electrically connected to the The source of the first transistor or the drain of the first transistor is electrically connected.
  • the pixel circuit includes:
  • a third transistor the gate of the third transistor is electrically connected to the first scan line, the source of the third transistor is electrically connected to the drain of the first transistor, and the drain of the third transistor is electrically connected to the first scanning line.
  • the gate of the first transistor is electrically connected;
  • a fourth transistor the gate of the fourth transistor is electrically connected to the second scanning line, the source of the fourth transistor is electrically connected to the first initialization power supply, and the drain of the fourth transistor is electrically connected to the first transistor The drain electrical connection.
  • the pixel circuit further includes:
  • a fifth transistor the gate of the fifth transistor is electrically connected to the third scan line, the source of the fifth transistor is electrically connected to the data line, the drain of the fifth transistor is electrically connected to the source of the first transistor pole electrical connection;
  • a sixth transistor the gate of the sixth transistor is electrically connected to the third scanning line, the source of the sixth transistor is electrically connected to the second initialization power supply, and the drain of the sixth transistor is electrically connected to the light emitting
  • the anode of the element is electrically connected; the cathode of the light emitting element is electrically connected to the second power supply;
  • a seventh transistor the gate of the seventh transistor is electrically connected to the light-emitting control line, the source of the seventh transistor is electrically connected to the first power supply, and the drain of the seventh transistor is electrically connected to the first transistor The source electrical connection;
  • An eighth transistor the gate of the eighth transistor is electrically connected to the light-emitting control line, the source of the eighth transistor is electrically connected to the drain of the first transistor, and the drain of the eighth transistor is electrically connected to the an electrical connection to the anode of the light emitting element;
  • a capacitor the first end of the capacitor is electrically connected to the first power supply, and the second end of the capacitor is electrically connected to the gate of the first transistor.
  • the first scanning line, the second scanning line and the third scanning line provide scanning signals during the display scanning period to control the corresponding transistors to be turned on.
  • a scan line, the second scan line and the third scan line do not provide the scan signal during the self-scan period.
  • the first scan signal provided by the first scan line, the second scan signal provided by the second scan line, and the third scan signal provided by the third scan line have the same frequency.
  • the pixel circuit further includes:
  • a ninth transistor the gate of the ninth transistor is electrically connected to the timing voltage line, the source of the ninth transistor is electrically connected to the second initialization power supply, and the drain of the ninth transistor is electrically connected to the The anode of the light emitting element is electrically connected.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor , the eighth transistor and the ninth transistor are low temperature polysilicon transistors.
  • the present application further provides a display device, which includes a pixel circuit, and the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor , an eighth transistor, a capacitor, and a light-emitting element, wherein the first transistor and the light-emitting element are connected in series between the first power supply and the second power supply, and the gate of the second transistor is electrically connected to the timing voltage line connected, the source of the second transistor is electrically connected to the reset power supply, the drain of the second transistor is electrically connected to the source of the first transistor or the drain of the first transistor, and the third transistor The gate of the third transistor is electrically connected to the first scan line, the source of the third transistor is electrically connected to the drain of the first transistor, and the drain of the third transistor is electrically connected to the gate of the first transistor , the gate of the fourth transistor is electrically connected to the second scan line, the source of the fourth transistor is electrically connected to the second scan
  • the drain of the seventh transistor is electrically connected to the source of the first transistor
  • the gate of the eighth transistor is electrically connected to the light-emitting control line
  • the source of the eighth transistor is electrically connected to the The drain of the first transistor is electrically connected
  • the drain of the eighth transistor is electrically connected to the anode of the light-emitting element
  • the first end of the capacitor is electrically connected to the first power supply
  • the second end of the capacitor It is electrically connected with the gate of the first transistor.
  • the first scanning line, the second scanning line and the third scanning line provide scanning signals during the display scanning period to control the conduction of corresponding transistors, and the first scanning line A scan line, the second scan line and the third scan line do not provide the scan signal during the self-scan period.
  • the first scan signal provided by the first scan line, the second scan signal provided by the second scan line, and the third scan signal provided by the third scan line have the same frequency.
  • the pixel circuit further includes:
  • a ninth transistor the gate of the ninth transistor is electrically connected to the timing voltage line, the source of the ninth transistor is electrically connected to the second initialization power supply, and the drain of the ninth transistor is electrically connected to the The anode of the light emitting element is electrically connected.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor , the eighth transistor and the ninth transistor are transistors of the same type.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor , the eighth transistor and the ninth transistor are low temperature polysilicon transistors.
  • the present application further provides a driving method of a display device, the driving method is used to drive the above-mentioned display device, and the driving method includes:
  • the first initialization power supply supplies a first initialization signal to the gate of the first transistor
  • the second initialization power supply supplies a second initialization signal to the anode of the light-emitting element, and the data line supplies a data signal to the source of the first transistor;
  • the second transistor responds to the timing voltage signal provided by the timing voltage line, and is turned off during the display scanning period of one frame period, and turned on during the self-scanning period of one frame period. is turned on to reset the first transistor during the self-scanning period of one frame period, so that the pixel circuit can be reset and compensated in the case of low-frequency driving, improving the driving efficiency of the display device and minimizing the power consumption of the display device.
  • FIG. 1 is a first equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application
  • FIG. 2 is a driving timing diagram of the pixel circuit shown in FIG. 1 during a display scanning period
  • FIG. 3 is a driving timing diagram of the pixel circuit shown in FIG. 1 during a self-scanning period
  • FIG. 4 is a schematic diagram of a method for driving a display device according to an image frame rate according to an embodiment of the present application
  • FIG. 5 is a second equivalent schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a third equivalent schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 7 is a fourth equivalent schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a driving method of the display device shown in FIG. 8 .
  • the source and drain of the transistor used in this application are symmetrical, the source and drain can be interchanged.
  • one pole is called the source, and the other pole is called the drain.
  • the middle terminal of the transistor is the gate, the signal input terminal is the source terminal, and the output terminal is the drain terminal.
  • FIG. 1 is a first equivalent circuit diagram of the pixel circuit provided by the embodiment of the present application.
  • the data line DA may be located or disposed on the i-th horizontal row (wherein, "i" is a natural number) and may be electrically connected to the j-th data line DA (wherein, "j" is a natural number) pixel circuit.
  • the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a capacitor Cst and light emitting element DL.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may all be low temperature polysilicon thin film transistor.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the embodiment of the present application are of the same type
  • the transistor can not only avoid the impact of the difference between different types of transistors on the pixel circuit, but also make the structure and process of the pixel circuit simpler.
  • the anode of the light emitting element DL can be electrically connected to the third node C, and the cathode of the light emitting element DL can be electrically connected to the second power supply VSS.
  • the light emitting element DL may generate light having a predetermined brightness according to the amount of current supplied from the first transistor T1.
  • the light-emitting element DL may be an organic light-emitting diode including an organic light-emitting layer, or may be an inorganic light-emitting element DL formed of inorganic materials.
  • the gate of the first transistor T1 (or driving transistor) can be electrically connected to the fourth node Q
  • the source of the first transistor T1 can be electrically connected to the first node A
  • the drain of the first transistor T1 can be electrically connected to Second node B.
  • the first transistor T1 may control the amount of current flowing from the first power supply VDD into the second power supply VSS through the light emitting element DL according to the voltage of the fourth node Q.
  • the voltage of the first power supply VDD may be set to a higher voltage than that of the second power supply VSS.
  • the gate of the second transistor T2 can be electrically connected to the timing voltage line RST
  • the source of the second transistor T2 can be electrically connected to the reset power supply VEH
  • the drain of the second transistor T2 can be electrically connected to the first node A.
  • the timing voltage signal is supplied through the timing voltage line RST
  • the second transistor T2 may be turned on.
  • the second transistor T2 can be turned on by the timing voltage signal supplied by the timing voltage line RST, and at this time, the voltage of the reset power supply VEH is supplied to the first node A (ie, the source of the first transistor T1 ).
  • the gate of the third transistor T3 may be electrically connected to the i-th first scan line B(i)
  • the source of the third transistor T3 may be electrically connected to the second node B
  • the drain of the third transistor T3 may be electrically connected to Connect to fourth node Q.
  • a scan signal eg, a first scan signal
  • the third transistor T3 may be turned on.
  • the third transistor T3 can be turned on by the scan signal supplied by the ith first scan line B(i), at this time, the second node B can be electrically connected with the fourth node Q, that is, the first transistor
  • the drain and gate of T1 are electrically connected, and the first transistor T1 may be electrically connected in a diode configuration.
  • the gate of the fourth transistor T4 may be electrically connected to the i-1th second scanning line A (i-1), the source of the fourth transistor T4 may be electrically connected to the first initialization power supply V1, and the fourth transistor T4 The drain of can be electrically connected to the second node B.
  • a scan signal eg, a second scan signal
  • the fourth transistor T4 may be turned on.
  • the fourth transistor T4 can be turned on by the scan signal supplied by the i-1th second scan line A (i-1), at this time, the voltage of the first initialization power supply V1 is supplied to the second node B (that is, the drain of a transistor T1).
  • the gate of the fifth transistor T5 can be electrically connected to the third scan line (or the i-th second scan line A(i)), the source of the fifth transistor T5 can be electrically connected to the data line DA, and the fifth transistor T5 The drain of T5 may be electrically connected to the first node A.
  • a scan signal eg, a second scan signal
  • the fifth transistor T5 may be turned on.
  • the fifth transistor T5 may be turned on by the scanning signal supplied by the i-th second scanning line A(i), and at this time, the data line DA may be electrically connected to the first node A.
  • the gate of the sixth transistor T6 may be electrically connected to the third scan line (or the i-th second scan line A(i)), the source of the sixth transistor T6 may be electrically connected to the second initialization power supply V2, and the sixth transistor T6 may be electrically connected to the second initialization power supply V2.
  • the drain of the six transistor T6 may be electrically connected to the anode of the light emitting element DL.
  • a scan signal eg, a second scan signal
  • the sixth transistor T6 may be turned on.
  • the sixth transistor T6 can be turned on by the scanning signal supplied by the i-th second scanning line A(i), at this time, the voltage of the second initialization power supply V2 is supplied to the third node C (that is, the anode of the light emitting element DL ).
  • the gate of the seventh transistor T7 can be electrically connected to the ith light emission control line EM(i), the source of the seventh transistor T7 can be electrically connected to the first power supply VDD, and the drain of the seventh transistor T7 can be electrically connected to to the first node A.
  • the seventh transistor T7 may be turned off when the light emission control signal is supplied through the i-th light emission control line EM(i), and may be turned on in the rest of the cases. Specifically, the seventh transistor T7 may be turned off by the light emission control signal supplied by the i-th light emission control line EM(i).
  • the gate of the eighth transistor T8 can be electrically connected to the ith light emission control line EM(i)
  • the source of the seventh transistor T7 can be electrically connected to the second node B
  • the drain of the eighth transistor T8 can be electrically connected to to the third node C.
  • the eighth transistor T8 may be turned off when the light emission control signal is supplied through the i-th light emission control line EM(i), and may be turned on in the rest of the cases. Specifically, the eighth transistor T8 may be turned off by the light emission control signal supplied by the i-th light emission control line EM(i).
  • the first initialization power V1 , the second initialization power V2 and the reset power VEH may generate different voltages.
  • a voltage for initializing the first node A, a voltage for initializing the third node C, and a voltage for initializing the fourth node Q may be set to different voltages.
  • the pixel circuit and the display device having the pixel circuit according to the embodiment may periodically apply the reset power VEH as a constant voltage to the source electrode of the first transistor T1 using the second transistor T2. Therefore, hysteresis deviation due to a difference in gradation between adjacent pixel circuits can be removed, and thus image blur due to hysteresis deviation can be reduced (or eliminated). That is, the second transistor T2 is turned off during the display scan period of one frame period in response to the timing voltage signal provided by the timing voltage line RST, and is turned on during the self-scanning period of one frame period, so as to realize the self-scanning period of one frame period. The first transistor T1 is reset during the period.
  • the embodiments of the present application do not need to design an additional set of high-frequency driving scanning signals, so that the driving efficiency of the display device can be improved and the power consumption of the display device can be minimized.
  • FIG. 2 is a driving timing diagram of the pixel circuit shown in FIG. 1 during the display scanning period.
  • FIG. 3 is a driving timing diagram of the pixel circuit shown in FIG. 1 during a self-scan period.
  • the i-th light emission control line can be used as the light emission control line
  • the i-th first scanning line B(i) can be used as the first scanning line
  • the scan line A(i ⁇ 1) may be used as the previous second scan line
  • the i-th second scan line A(i) may be used as the second scan line.
  • the first scan signal supplied by the first scan line may have a pulse width of 2 horizontal periods (2H).
  • the second scan signal supplied by the second scan line may have a pulse width of 1 horizontal period (1H).
  • the first scan signal supplied through the first scan line, the second scan signal supplied through the second scan line, and the sequence voltage signal supplied through the sequence voltage line RST may be defined as a logic low voltage, and used to make the seventh transistor T7
  • the light emission control signal for turning off the eighth transistor T8 may be defined as a logic high voltage.
  • pulse widths and logic levels of scan signals and light emission control signals are not limited thereto, and may vary according to pixel circuit structures, types of transistors, etc. within the spirit and scope of the disclosure.
  • the driving timing of the pixel circuit includes a display scanning period t1 and a self-scanning period t2 .
  • the display scan period t1 includes a first display scan period t11 , a second display scan period t12 and a third display scan period t13 .
  • the self-scanning period t2 includes a first self-scanning period t21 and a second self-scanning period t22.
  • the first scan line supplies the scan signal
  • the next second scan line supplies the scan signal
  • the third transistor T3 and the fourth transistor T4 are turned on.
  • the voltage of the first initialization power supply V1 is supplied to the fourth node Q (the gate of the first transistor T1 ) through the third transistor T3 and the fourth transistor T4 .
  • the gate of the first transistor T1 may be initialized during the first display scan period.
  • the second display scan period t12 the first scan line supplies the scan signal, the second scan line supplies the scan signal, and the third transistor T3 , the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the first transistor T1 When the third transistor T3 is turned on, the first transistor T1 may be electrically connected in a diode configuration.
  • the data line DA is electrically connected to the first node A when the fifth transistor T5 is turned on. Therefore, writing data into the first transistor T1 and compensating the threshold voltage can be performed together.
  • the sixth transistor T6 when the sixth transistor T6 is turned on, the voltage of the second initialization power supply V2 is supplied to the anode of the light emitting element DL (ie, the third node C).
  • the parasitic capacitance Cst of the light emitting element DL When the voltage of the second initialization power source V2 is supplied to the anode of the light emitting element DL, the parasitic capacitance Cst of the light emitting element DL may be discharged.
  • the supply of the light emission control signal may be stopped, and the seventh transistor T7 and the eighth transistor T8 may be turned on.
  • the driving current generated based on the data signal may be supplied to the light emitting element DL, and the light emitting element DL may emit light with brightness corresponding to the driving current.
  • the light emission control signal continues to be supplied, and the seventh transistor T7 and the eighth transistor T8 are turned off, and the pixel circuit enters a blank period.
  • the second transistor T2 when the timing voltage line RST supplies the timing voltage signal, the second transistor T2 is turned on.
  • the voltage of the reset power supply VEH is supplied to the first node A (ie, the source of the first transistor T1 ) through the second transistor T2 .
  • the second transistor T2 is turned off during the display scanning period t1 of one frame period, and is turned on during the self-scanning period t2 of one frame period, so as to reset the first transistor T1 during the self-scanning period t2 of one frame period .
  • the embodiments of the present application do not need to design an additional set of high-frequency driving scanning signals, so that the driving efficiency of the display device can be improved and the power consumption of the display device can be minimized.
  • the single frame may include at least one self-scanning period t2 according to the image frame rate.
  • the image frame rate may be the frequency at which data signals are actually written to the drive transistors of each pixel circuit.
  • an image frame rate may also be referred to as a scan rate or a screen display frequency, and may represent the frequency at which a displayed image is refreshed per second.
  • scan signals need to be supplied to the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 and the sixth transistor T6 .
  • the scan signal need not be supplied to the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.
  • FIG. 4 is a schematic diagram of a method for driving a display device according to an image frame rate according to an embodiment of the present application.
  • one frame period may only include one display scan period t1; when the display device is driven at an image frame rate of 120 Hz, one frame period may include one A display scan period t1 and a self-scan period t2; when the display device is driven at an image frame rate of 80Hz, a frame cycle may include a display scan period t1 and two consecutive self-scan periods t2;
  • a frame period may include a display scanning period t1 and three consecutive self-scanning periods t2; when the display device is driven at an image frame rate of 48 Hz, a frame period may include a display A scan period during t1 and four consecutive self-scan periods during t2.
  • one frame period may include one display scan period t1 and seven consecutive self-scan periods t2.
  • one frame period may include one display scan period t1 and nine consecutive self-scan periods t2.
  • a turn-on bias having a predetermined magnitude may be periodically applied to each of the first transistors T1 included in the pixel circuit. Reduced brightness, flicker, or image blur that occurs when driving at low frequencies can be improved.
  • connection mode and driving sequence setting of the third transistor T3 and the fourth transistor T4 in the embodiment of the present application can reduce the leakage path of the potential of the fourth node Q.
  • FIG. 5 is a second equivalent schematic diagram of the pixel circuit provided by the embodiment of the present application. As shown in Figure 1 and Figure 5, the difference between the pixel circuit shown in Figure 5 and the pixel circuit shown in Figure 1 is that the drain of the second transistor T2 in the pixel circuit shown in Figure 5 is connected to the second node B ; The drain of the second transistor T2 in the pixel circuit shown in FIG. 1 is connected to the first node A.
  • the pixel circuit shown in FIG. 5 connects the drain of the second transistor T2 to the second node B, and as the frame rate decreases, the number of self-scanning periods increases, so a turn-on bias with a predetermined magnitude can be applied periodically to each first transistor T1 included in the pixel circuit. Therefore, reduction in luminance, flicker, or image blur that occurs at the time of low-frequency driving can be improved.
  • the connection mode and driving sequence setting of the third transistor T3 and the fourth transistor T4 in the pixel circuit shown in FIG. 5 can reduce the leakage path of the potential of the fourth node Q.
  • FIG. 6 is a third equivalent schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • the difference between the pixel circuit shown in FIG. 6 and the pixel circuit shown in FIG. 1 is that the pixel circuit shown in FIG. 6 further includes a ninth transistor T9 .
  • the gate of the ninth transistor T9 is electrically connected to the timing voltage line RST, the source of the ninth transistor T9 is electrically connected to the second initialization power supply V2, and the drain of the ninth transistor T9 is electrically connected to the anode of the light emitting element DL.
  • the pixel circuit shown in FIG. 6 connects the drain of the second transistor T2 to the first node A, and as the frame rate decreases, the number of self-scanning periods increases, so a turn-on bias with a predetermined magnitude can be applied periodically to each first transistor T1 included in the pixel circuit. Therefore, reduction in luminance, flicker, or image blur that occurs at the time of low-frequency driving can be improved.
  • the connection mode and driving sequence setting of the third transistor T3 and the fourth transistor T4 in the pixel circuit shown in FIG. 5 can reduce the leakage path of the potential of the fourth node Q.
  • the pixel circuit shown in FIG. 6 can also respond to the timing voltage signal provided by the timing voltage line RST through the ninth transistor T9, which is turned off during the display scanning period t1 of a frame period and turned on during the self-scanning period t2 of a frame period. , to reset the anode of the light emitting element DL during the self-scanning period t2 of one frame period.
  • FIG. 7 is a third equivalent schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • the difference between the pixel circuit shown in Figure 7 and the pixel circuit shown in Figure 1 is that the drain of the second transistor T2 in the pixel circuit shown in Figure 7 is connected to the second node B ;
  • the drain of the second transistor T2 in the pixel circuit shown in FIG. 1 is connected to the first node A; in addition, the pixel circuit shown in FIG. 7 also includes a ninth transistor T9.
  • the gate of the ninth transistor T9 is electrically connected to the timing voltage line RST, the source of the ninth transistor T9 is electrically connected to the second initialization power supply V2, and the drain of the ninth transistor T9 is electrically connected to the anode of the light emitting element DL.
  • the pixel circuit shown in FIG. 7 connects the drain of the second transistor T2 to the second node B, and as the frame rate decreases, the number of self-scanning periods increases, so a turn-on bias with a predetermined magnitude can be applied periodically to each first transistor T1 included in the pixel circuit. Therefore, reduction in luminance, flicker, or image blurring occurring at the time of low-frequency driving can be improved.
  • the connection mode and driving sequence setting of the third transistor T3 and the fourth transistor T4 in the pixel circuit shown in FIG. 5 can reduce the leakage path of the potential of the fourth node Q.
  • the pixel circuit shown in FIG. 7 can also respond to the timing voltage signal provided by the timing voltage line RST through the ninth transistor T9, which is turned off during the display scanning period t1 of one frame period and turned on during the self-scanning period t2 of one frame period. , to reset the anode of the light emitting element DL during the self-scanning period t2 of one frame period.
  • FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 100 provided by the embodiment of the present application includes a plurality of pixel circuits 10 arranged in an array.
  • pixel circuits 10 for the pixel circuit 10 arranged in the i-th horizontal row, specific reference may be made to the pixel circuits shown above.
  • the pixel circuit 10 arranged in the i-th horizontal row includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the capacitor Cst and the light-emitting element DL, wherein the first transistor T1 and the light-emitting element DL are connected in series between the first power supply VDD and the second power supply VSS, and the gate of the second transistor T2 pole is electrically connected to the timing voltage line RST, the source of the second transistor T2 is electrically connected to the reset power supply VEH, the drain of the second transistor T2 is electrically connected to the source of the first transistor T1 or the drain of the first transistor T1, and the second transistor T2 is electrically connected to the source of the first transistor T1 or the drain of the first transistor T1.
  • the gate of the third transistor T3 is electrically connected to the first scanning line
  • the source of the third transistor T3 is electrically connected to the drain of the first transistor T1
  • the drain of the third transistor T3 is electrically connected to the gate of the first transistor T1
  • the gate of the fourth transistor T4 is electrically connected to the second scanning line
  • the source of the fourth transistor T4 is electrically connected to the first initialization power supply V1
  • the drain of the fourth transistor T4 is electrically connected to the drain of the first transistor T1
  • the drain of the fourth transistor T4 is electrically connected to the drain of the first transistor T1.
  • the gate of the fifth transistor T5 is electrically connected to the third scanning line, the source of the fifth transistor T5 is electrically connected to the data line DA, the drain of the fifth transistor T5 is electrically connected to the source of the first transistor T1, and the sixth transistor T6
  • the gate of the sixth transistor T6 is electrically connected to the third scanning line, the source of the sixth transistor T6 is electrically connected to the second initialization power supply V2, the drain of the sixth transistor T6 is electrically connected to the anode of the light-emitting element DL; the cathode of the light-emitting element DL is electrically connected to the first
  • the two power sources VSS are electrically connected, the gate of the seventh transistor T7 is electrically connected to the light-emitting control line, the source of the seventh transistor T7 is electrically connected to the first power source VDD, and the drain of the seventh transistor T7 is electrically connected to the source of the first transistor T1.
  • the gate of the eighth transistor T8 is electrically connected to the light-emitting control line
  • the source of the eighth transistor T8 is electrically connected to the drain of the first transistor T1
  • the drain of the eighth transistor T8 is electrically connected to the anode of the light-emitting element DL
  • the first end of the capacitor Cst is electrically connected to the first power supply VDD
  • the second end of the capacitor Cst is electrically connected to the gate of the first transistor T1.
  • FIG. 9 is a schematic diagram of a driving method of the display device shown in FIG. 8 .
  • the driving method of the display device includes:
  • the first initialization power supply supplies a first initialization signal to the gate of the first transistor
  • the second initialization power supply supplies a second initialization signal to the anode of the light-emitting element, and the data line supplies a data signal to the source of the first transistor;
  • the second transistor T2 responds to the timing voltage signal provided by the timing voltage line RST, and is turned off during the display scanning period of one frame period, and during the self-scanning period of one frame period During the period of conduction, the first transistor T1 is reset during the self-scanning period of one frame period, so that the pixel circuit can be reset and compensated in the case of low-frequency driving, and the driving efficiency of the display device is improved and the power consumption of the display device is reduced. minimize.

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Abstract

一种像素电路（10）、显示装置（100）及其驱动方法。像素电路（10）包括发光元件（DL）、第一晶体管（T1）以及第二晶体管（T2），第二晶体管（T2）响应于时序电压线（RST）提供的时序电压信号，在一帧周期的显示扫描时段期间（t1）截止，在一帧周期的自扫描时段期间（t2）导通，以在一帧周期的自扫描时段期间（t2）对第一晶体管（T1）进行复位。

Description

像素电路、显示装置及其驱动方法 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路、显示装置及其驱动方法。
 背景技术
显示装置可以包括像素电路。每个像素电路可以包括晶体管、电连接到晶体管的发光元件以及电容。晶体管可以响应于通过线提供的相应信号而导通，并且可以由导通的晶体管产生预定驱动电流。发光元件可以响应于驱动电流而发光。
近来，正在开发以低频驱动显示装置的方法，以提高显示装置的驱动效率并使显示装置的功耗最小化。
 技术问题
本申请提供一种像素电路、显示装置及其驱动方法，可以在低频驱动的情况下对像素电路进行复位补偿，提高显示装置的驱动效率并使显示装置的功耗最小化。
 技术解决方案
第一方面，本申请提供一种像素电路，其包括：
发光元件；
第一晶体管，所述第一晶体管与所述发光元件串接于第一电源与第二电源之间，所述第一晶体管基于所述第一晶体管的栅极的电压来控制流经所述发光元件的驱动电流；及
第二晶体管，所述第二晶体管与所述第一晶体管电连接，所述第二晶体管响应于时序电压线提供的时序电压信号，在一帧周期的显示扫描时段期间截止，在一帧周期的自扫描时段期间导通，以在一帧周期的自扫描时段期间对所述第一晶体管进行复位。
在本申请提供的像素电路中，所述第二晶体管的栅极与所述时序电压线电连接，所述第二晶体管的源极与复位电源电连接，所述第二晶体管的漏极与所述第一晶体管的源极或者所述第一晶体管的漏极电连接。
在本申请提供的像素电路中，所述像素电路包括：
第三晶体管，所述第三晶体管的栅极与第一扫描线电连接，所述第三晶体管的源极与所述第一晶体管的漏极电连接，所述第三晶体管的漏极与所述第一晶体管的栅极电连接；
第四晶体管，所述第四晶体管的栅极与第二扫描线电连接，所述第四晶体管的源极与第一初始化电源电连接，所述第四晶体管的漏极与所述第一晶体管的漏极电连接。
在本申请提供的像素电路中，所述像素电路还包括：
第五晶体管，所述第五晶体管的栅极与第三扫描线电连接，所述第五晶体管的源极与数据线电连接，所述第五晶体管的漏极与所述第一晶体管的源极电连接；
第六晶体管，所述第六晶体管的栅极与所述第三扫描线电连接，所述第六晶体管的源极与第二初始化电源电连接，所述第六晶体管的漏极与所述发光元件的阳极电连接；所述发光元件的阴极与所述第二电源电连接；
第七晶体管，所述第七晶体管的栅极与发光控制线电连接，所述第七晶体管的源极与所述第一电源电连接，所述第七晶体管的漏极与所述第一晶体管的源极电连接；
第八晶体管，所述第八晶体管的栅极与所述发光控制线电连接，所述第八晶体管的源极与所述第一晶体管的漏极电连接，所述第八晶体管的漏极与所述发光元件的阳极电连接；及
电容，所述电容的第一端与所述第一电源电连接，所述电容的第二端与所述第一晶体管的栅极电连接。
在本申请提供的像素电路中，所述第一扫描线、所述第二扫描线及所述第三扫描线在所述显示扫描时段期间提供扫描信号，以控制相应晶体管导通，所述第一扫描线、所述第二扫描线及所述第三扫描线在所述自扫描时段期间不提供所述扫描信号。
在本申请提供的像素电路中，所述第一扫描线提供的第一扫描信号、所述第二扫描线提供的第二扫描信号及所述第三扫描线提供的第三扫描信号具有相同的频率。
在本申请提供的像素电路中，所述像素电路还包括：
第九晶体管，所述第九晶体管的栅极与所述时序电压线电连接，所述第九晶体管的源极与所述第二初始化电源电连接，所述第九晶体管的漏极与所述发光元件的阳极电连接。
在本申请提供的像素电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管及所述第九晶体管均为低温多晶硅晶体管。
第二方面，本申请还提供一种显示装置，其包括像素电路，所述像素电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、电容及发光元件，其中，所述第一晶体管与所述发光元件串接于第一电源与第二电源之间，所述第二晶体管的栅极与所述时序电压线电连接，所述第二晶体管的源极与复位电源电连接，所述第二晶体管的漏极与所述第一晶体管的源极或者所述第一晶体管的漏极电连接，所述第三晶体管的栅极与第一扫描线电连接，所述第三晶体管的源极与所述第一晶体管的漏极电连接，所述第三晶体管的漏极与所述第一晶体管的栅极电连接，所述第四晶体管的栅极与第二扫描线电连接，所述第四晶体管的源极与第一初始化电源电连接，所述第四晶体管的漏极与所述第一晶体管的漏极电连接，所述第五晶体管的栅极与第三扫描线电连接，所述第五晶体管的源极与数据线电连接，所述第五晶体管的漏极与所述第一晶体管的源极电连接，所述第六晶体管的栅极与所述第三扫描线电连接，所述第六晶体管的源极与第二初始化电源电连接，所述第六晶体管的漏极与所述发光元件的阳极电连接；所述发光元件的阴极与所述第二电源电连接，所述第七晶体管的栅极与发光控制线电连接，所述第七晶体管的源极与所述第一电源电连接，所述第七晶体管的漏极与所述第一晶体管的源极电连接，所述第八晶体管的栅极与所述发光控制线电连接，所述第八晶体管的源极与所述第一晶体管的漏极电连接，所述第八晶体管的漏极与所述发光元件的阳极电连接，所述电容的第一端与所述第一电源电连接，所述电容的第二端与所述第一晶体管的栅极电连接。
在本申请提供的显示装置中，所述第一扫描线、所述第二扫描线及所述第三扫描线在所述显示扫描时段期间提供扫描信号，以控制相应晶体管导通，所述第一扫描线、所述第二扫描线及所述第三扫描线在所述自扫描时段期间不提供所述扫描信号。
在本申请提供的显示装置中，所述第一扫描线提供的第一扫描信号、所述第二扫描线提供的第二扫描信号及所述第三扫描线提供的第三扫描信号具有相同的频率。
在本申请提供的显示装置中，所述像素电路还包括：
第九晶体管，所述第九晶体管的栅极与所述时序电压线电连接，所述第九晶体管的源极与所述第二初始化电源电连接，所述第九晶体管的漏极与所述发光元件的阳极电连接。
在本申请提供的显示装置中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管及所述第九晶体管均为同种类型晶体管。
在本申请提供的显示装置中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管及所述第九晶体管均为低温多晶硅晶体管。
第三方面，本申请还提供一种显示装置的驱动方法，所述驱动方法用于驱动以上所述的显示装置，所述驱动方法包括：
同时控制所述第二晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管及所述第八晶体管截止，及控制所述第三晶体管及所述第四晶体管导通，所述第一初始化电源供应第一初始化信号至所述第一晶体管的栅极；
同时控制所述第二晶体管、所述第四晶体管、所述第七晶体管及所述第八晶体管截止，及控制所述第三晶体管、所述第五晶体管及所述第六晶体管导通，所述第二初始化电源供应第二初始化信号至所述发光元件的阳极，所述数据线供应数据信号至所述第一晶体管的源极；
同时控制所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管及所述第六晶体管截止，及控制所述第七晶体管及所述第八晶体管导通，所述发光元件发光；
同时控制所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管及所述第八晶体管截止；
控制所述第二晶体管导通，以对所述第一晶体管进行复位。
 有益效果
本申请提供的像素电路、显示装置及其驱动方法，通过第二晶体管响应于时序电压线提供的时序电压信号，在一帧周期的显示扫描时段期间截止，在一帧周期的自扫描时段期间导通，以在一帧周期的自扫描时段期间对第一晶体管进行复位，从而可以在低频驱动的情况下对像素电路进行复位补偿，提高显示装置的驱动效率并使显示装置的功耗最小化。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素电路的第一种等效电路图；
图2为图1所示的像素电路在显示扫描时段期间的驱动时序图；
图3为图1所示的像素电路在自扫描时段期间的驱动时序图；
图4为本申请实施例根据图像帧速率驱动显示装置的方法的示意图；
图5为本申请实施例提供的像素电路的第二种等效示意图；
图6为本申请实施例提供的像素电路的第三种等效示意图；
图7为本申请实施例提供的像素电路的第四种等效示意图；
图8为本申请实施例提供的显示装置的结构示意图；
图9为图8所示的显示装置的驱动方法示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
此外，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”、“第五”、“第六”、“第七”、“第八”、“第九”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。
需要说明的是，由于本申请采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。
请参阅图1，图1为本申请实施例提供的像素电路的第一种等效电路图。在图1中，为了便于描述，示出了可以位于或设置在第i水平行(其中，“i”是自然数)上并且可以电连接到第j数据线DA (其中，“j”是自然数)的像素电路。
如图1所示，像素电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、电容Cst及发光元件DL。
在本申请实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8可以均为低温多晶硅薄膜晶体管。本申请实施例中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8为同一种类型的晶体管，不仅可以避免不同类型的晶体管之间的差异性对像素电路造成的影响，还可以使得像素电路的结构和工艺更加简单。
其中，发光元件DL的阳极可以电连接到第三节点C，发光元件DL的阴极可以电连接到第二电源VSS。发光元件DL可以根据从第一晶体管T1供应的电流量产生具有预定亮度的光。在本申请实施例中，发光元件DL可以是包括有机发光层的有机发光二极管，也可以是由无机材料形成的无机发光元件DL。
其中，第一晶体管T1（或驱动晶体管）的栅极可以电连接到第四节点Q，第一晶体管T1的源极可以电连接到第一节点A，第一晶体管T1的漏极可以电连接到第二节点B。第一晶体管T1可以根据第四节点Q的电压来控制从第一电源VDD经由发光元件DL流入第二电源VSS的电流量。第一电源VDD的电压可以被设定为比第二电源VSS的电压高的电压。
其中，第二晶体管T2的栅极可以电连接到时序电压线RST，第二晶体管T2的源极可以电连接到复位电源VEH，第二晶体管T2的漏极可以电连接到第一节点A。当通过时序电压线RST供应时序电压信号时，第二晶体管T2可以导通。具体的，第二晶体管T2可以通过时序电压线RST供应的时序电压信号导通，此时，复位电源VEH的电压供应到第一节点A（即，第一晶体管T1的源极）。
其中，第三晶体管T3的栅极可以电连接到第i条第一扫描线B（i），第三晶体管T3的源极可以电连接到第二节点B，第三晶体管T3的漏极可以电连接到第四节点Q。当通过第i条第一扫描线B（i）供应扫描信号（例如，第一扫描信号）时，第三晶体管T3可以导通。具体的，第三晶体管T3可以通过第i条第一扫描线B（i）供应的扫描信号导通，此时，可以将第二节点B与第四节点Q电连接，即，将第一晶体管T1的漏极和栅极电连接，第一晶体管T1可以以二极管配置电连接。
其中，第四晶体管T4的栅极可以电连接到第i-1条第二扫描线A（i-1），第四晶体管T4的源极可以电连接到第一初始化电源V1，第四晶体管T4的漏极可以电连接到第二节点B。当通过第i-1条第二扫描线A（i-1）供应扫描信号（例如，第二扫描信号）时，第四晶体管T4可以导通。具体的，第四晶体管T4可以通过第i-1条第二扫描线A（i-1）供应的扫描信号导通，此时，第一初始化电源V1的电压供应到第二节点B（即第一晶体管T1的漏极）。
其中，第五晶体管T5的栅极可以电连接到第三扫描线（或第i条第二扫描线A（i）），第五晶体管T5的源极可以电连接到数据线DA，第五晶体管T5的漏极可以电连接到第一节点A。当通过第i条第二扫描线A（i）供应扫描信号（例如，第二扫描信号）时，第五晶体管T5可以导通。具体的，第五晶体管T5可以通过第i条第二扫描线A（i）供应的扫描信号导通，此时，数据线DA可以电连接到第一节点A。
其中，第六晶体管T6的栅极可以电连接到第三扫描线（或第i条第二扫描线A（i）），第六晶体管T6的源极可以电连接到第二初始化电源V2，第六晶体管T6的漏极可以电连接到发光元件DL的阳极。当通过第i条第二扫描线A（i）供应扫描信号（例如，第二扫描信号）时，第六晶体管T6可以导通。具体的，第六晶体管T6可以通过第i条第二扫描线A（i）供应的扫描信号导通，此时，第二初始化电源V2的电压供应到第三节点C（即发光元件DL的阳极）。
其中，第七晶体管T7的栅极可以电连接到第i条发光控制线EM（i），第七晶体管T7的源极可以电连接到第一电源VDD，第七晶体管T7的漏极可以电连接到第一节点A。当通过第i条发光控制线EM（i）供应发光控制信号时，第七晶体管T7可以截止，并且可以在其余情况下导通。具体的，第七晶体管T7可以通过第i条发光控制线EM（i）供应的发光控制信号截止。
其中，第八晶体管T8的栅极可以电连接到第i条发光控制线EM（i），第七晶体管T7的源极可以电连接到第二节点B，第八晶体管T8的漏极可以电连接到第三节点C。当通过第i条发光控制线EM（i）供应发光控制信号时，第八晶体管T8可以截止，并且可以在其余情况下导通。具体的，第八晶体管T8可以通过第i条发光控制线EM（i）供应的发光控制信号截止。
在本申请实施例中，第一初始化电源V1、第二初始化电源V2和复位电源VEH可以产生不同的电压。例如，用于使第一节点A初始化的电压、用于使第三节点C初始化的电压以及用于使第四节点Q初始化的电压可以被设定为不同的电压。
当将要供应到第四节点Q的第一初始化电源V1的电压在一帧周期的长度增加的低频驱动期间过低时，第一晶体管T1在对应帧周期中的迟滞的变化可能恶化。这样的迟滞可能在低频驱动时导致闪烁现象。因此，在以低频驱动的显示装置中，可能需要第一初始化电源V1的电压高于第二电源VSS的电压。
在低频驱动期间，当使用可以通过第五晶体管T5的导通操作经由数据线DA供应的信号将导通偏置施加到第一晶体管T1时(即，当第一晶体管T1偏置导通时)，可能发生归因于相邻像素电路的灰度值之间的差异导致的迟滞的严重偏差。因此，在相邻像素电路中的驱动晶体管的阈值电压的偏移量之间出现差异，并且因此可以感知到由这样的差异导致的运动模糊(即，重影现象)。
为了解决该问题，根据实施例的像素电路和具有像素电路的显示装置可以使用第二晶体管T2周期性地将作为恒定电压的复位电源VEH施加到第一晶体管T1的源电极。因此，可以去除归因于相邻像素电路之间的灰度差异的迟滞偏差，并且因此可减少(或消除)归因于迟滞偏差的图像模糊。也即，第二晶体管T2响应于时序电压线RST提供的时序电压信号，在一帧周期的显示扫描时段期间截止，在一帧周期的自扫描时段期间导通，以在一帧周期的自扫描时段期间对第一晶体管T1进行复位。相较于现有技术，本申请实施例不需要额外再设计一组高频率驱动扫描信号，从而可以提高显示装置的驱动效率并使显示装置的功耗最小化。
请参阅图2、图3，图2为图1所示的像素电路在显示扫描时段期间的驱动时序图。图3为图1所示的像素电路在自扫描时段期间的驱动时序图。在下文中，为了便于描述，可以进行如下描述：第i发光控制线可以用作发光控制线，第i条第一扫描线B（i）可以用作第一扫描线，第i-1条第二扫描线A（i-1）可以用作前一第二扫描线，并且第i条第二扫描线A（i）可以用作第二扫描线。
在本申请实施例中，第一扫描线供应的第一扫描信号可以具有2个水平时段(2H)的脉冲宽度。第二扫描线供应的第二扫描信号可以具有1个水平时段（1H）的脉冲宽度。通过第一扫描线供应的第一扫描信号、通过第二扫描线供应的第二扫描信号以及通过时序电压线RST供应的时序电压信号可以被定义为逻辑低电压，并且用于使第七晶体管T7和第八晶体管T8截止的发光控制信号可以被定义为逻辑高电压。然而，这仅是示例性的，因此扫描信号和发光控制信号的脉冲宽度和逻辑电平不限于此，并且可以在公开的精神和范围内根据像素电路结构、晶体管的类型等而改变。
需要说明的是，本申请实施例提供的像素电路的驱动时序包括显示扫描时段期间t1以及自扫描时段期间t2。其中，显示扫描时段期间t1包括第一显示扫描时段t11、第二显示扫描时段t12以及第三显示扫描时段t13。自扫描时段期间t2包括第一自扫描时段t21以及第二自扫描时段t22。
具体的，在第一显示扫描时段t11，第一扫描线供应扫描信号，上一第二扫描线供应扫描信号，第三晶体管T3以及第四晶体管T4导通。第一初始化电源V1的电压经第三晶体管T3和第四晶体管T4供应到第四节点Q（第一晶体管T1的栅极）。因此，第一晶体管T1的栅极可以在第一显示扫描时段被初始化。在第二显示扫描时段t12，第一扫描线供应扫描信号，第二扫描线供应扫描信号，第三晶体管T3、第五晶体管T5以及第六晶体管T6导通。当第三晶体管T3导通时，第一晶体管T1可以以二极管配置电连接。当第五晶体管T5导通时，数据线DA电连接到第一节点A。因此，将数据写入第一晶体管T1和阈值电压的补偿可以一起执行。同时，当第六晶体管T6导通，第二初始化电源V2的电压供应到发光元件DL阳极(即，第三节点C)。当第二初始化电源V2的电压被供应到发光元件DL的阳极时，发光元件DL的寄生电容Cst器可以被放电。当寄生电容Cst器中充入的残余电压被放电(消除)时，可以防止非预期的细小的发光。因此，可以改善像素电路的黑色表现能力。在第三显示扫描时段t13，可以停止供应发光控制信号，并且第七晶体管T7和第八晶体管T8可以导通。当第七晶体管T7和第八晶体管T8导通时，基于数据信号产生的驱动电流可以被供应到发光元件DL，并且发光元件DL可以以与驱动电流对应的亮度发光。
具体的，在第一自扫描时段t21，继续供应发光控制信号，并且第七晶体管T7和第八晶体管T8截止，像素电路进入空白时段。在第二自扫描时段t22，时序电压线RST供应时序电压信号时，第二晶体管T2导通。复位电源VEH的电压经第二晶体管T2供应到第一节点A（即，第一晶体管T1的源极）。也即，第二晶体管T2在一帧周期的显示扫描时段期间t1截止，在一帧周期的自扫描时段期间t2导通，以在一帧周期的自扫描时段期间t2对第一晶体管T1进行复位。相较于现有技术，本申请实施例不需要额外再设计一组高频率驱动扫描信号，从而可以提高显示装置的驱动效率并使显示装置的功耗最小化。
需要说明的是，在一帧周期内可以仅仅包括显示扫描时段t1。在一帧周期内可以包括显示扫描时段t1以及至少一个自扫描时段t2。也即，单个帧可以根据图像帧速率单个帧可以根据图像帧速率包括至少一个自扫描时段t2。图像帧速率可以是将数据信号实际写入每个像素电路的驱动晶体管的频率。例如，图像帧速率也可以被称为扫描速率或屏幕显示频率，并且可以表示每秒刷新显示图像的频率。
特别的，在本申请实施例中，在显示扫描时段期间t1，扫描信号需要被供应到第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6。在自扫描时段期间t2，扫描信号不需被供应到第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6。
请参阅图4，图4为本申请实施例根据图像帧速率驱动显示装置的方法的示意图。如图4所示，当以约240Hz的图像帧速率驱动显示装置时，一帧周期可以仅仅包括一个显示扫描时段期间t1；当以120Hz的图像帧速率驱动显示装置时，一帧周期可以包括一个显示扫描时段期间t1以及一个自扫描时段期间t2；当以80Hz的图像帧速率驱动显示装置时，一帧周期可以包括一个显示扫描时段期间t1以及两个连续的自扫描时段期间t2；当以60Hz的图像帧速率驱动显示装置时，一帧周期可以包括一个显示扫描时段期间t1以及三个连续的自扫描时段期间t2；当以48Hz的图像帧速率驱动显示装置时，一帧周期可以包括一个显示扫描时段期间t1以及四个连续的自扫描时段期间t2。当以30Hz的图像帧速率驱动显示装置时，一帧周期可以包括一个显示扫描时段期间t1以及七个连续的自扫描时段期间t2。当以24Hz的图像帧速率驱动显示装置时，一帧周期可以包括一个显示扫描时段期间t1以及九个连续的自扫描时段期间t2。随着帧速降低，自扫描时段期间t2的数目增加，因此具有预定大小的导通偏置可以周期性地施加到包括在像素电路中的每个第一晶体管T1。可以改善在低频驱动时发生的亮度降低、闪烁或图像模糊。
此外，本申请实施例中的第三晶体管T3以及第四晶体管T4的连接方式以及驱动时序设置，可以减少第四节点Q的电位的漏电途径。
请参阅图5，图5为本申请实施例提供的像素电路的第二种等效示意图。如图1、图5所示，图5所示的像素电路与图1所示的像素电路的区别在于：图5所示的像素电路中的第二晶体管T2的漏极与第二节点B连接；图1所示的像素电路中的第二晶体管T2的漏极与第一节点A连接。
图5所示的像素电路将第二晶体管T2的漏极与第二节点B连接，随着帧速降低，自扫描时段期间的数目增加，因此具有预定大小的导通偏置可以周期性地施加到包括在像素电路中的每个第一晶体管T1。因此，可以改善在低频驱动时发生的亮度降低、闪烁或图像模糊。此外，图5所示的像素电路中的第三晶体管T3以及第四晶体管T4的连接方式以及驱动时序设置，可以减少第四节点Q的电位的漏电途径。
请参阅图6，图6为本申请实施例提供的像素电路的第三种等效示意图。如图1、图6所示，图6所示的像素电路与图1所示的像素电路的区别在于，图6所示的像素电路还包括第九晶体管T9。第九晶体管T9的栅极与时序电压线RST电连接，第九晶体管T9的源极与第二初始化电源V2电连接，第九晶体管T9的漏极与发光元件DL的阳极电连接。
图6所示的像素电路将第二晶体管T2的漏极与第一节点A连接，随着帧速降低，自扫描时段期间的数目增加，因此具有预定大小的导通偏置可以周期性地施加到包括在像素电路中的每个第一晶体管T1。因此，可以改善在低频驱动时发生的亮度降低、闪烁或图像模糊。此外，图5所示的像素电路中的第三晶体管T3以及第四晶体管T4的连接方式以及驱动时序设置，可以减少第四节点Q的电位的漏电途径。
图6所示的像素电路还可以通过第九晶体管T9响应于时序电压线RST提供的时序电压信号，在一帧周期的显示扫描时段期间t1截止，在一帧周期的自扫描时段期间t2导通，以在一帧周期的自扫描时段期间t2对发光元件DL的阳极进行复位。
请参阅图7，图7为本申请实施例提供的像素电路的第三种等效示意图。如图1、图7所示，图7所示的像素电路与图1所示的像素电路的区别在于：图7所示的像素电路中的第二晶体管T2的漏极与第二节点B连接；图1所示的像素电路中的第二晶体管T2的漏极与第一节点A连接；此外，图7所示的像素电路还包括第九晶体管T9。第九晶体管T9的栅极与时序电压线RST电连接，第九晶体管T9的源极与第二初始化电源V2电连接，第九晶体管T9的漏极与发光元件DL的阳极电连接。
图7所示的像素电路将第二晶体管T2的漏极与第二节点B连接，随着帧速降低，自扫描时段期间的数目增加，因此具有预定大小的导通偏置可以周期性地施加到包括在像素电路中的每个第一晶体管T1。因此，可以改善在低频驱动时发生的亮度降低、闪烁或图像模糊。此外，图5所示的像素电路中的第三晶体管T3以及第四晶体管T4的连接方式以及驱动时序设置，可以减少第四节点Q的电位的漏电途径。
图7所示的像素电路还可以通过第九晶体管T9响应于时序电压线RST提供的时序电压信号，在一帧周期的显示扫描时段期间t1截止，在一帧周期的自扫描时段期间t2导通，以在一帧周期的自扫描时段期间t2对发光元件DL的阳极进行复位。
请参阅图8，图8为本申请实施例提供的显示装置的结构示意图。本申请实施例提供的显示装置100包括多个呈阵列排布设置的像素电路10。其中，在像素电路10之中，设置在第i水平行中的像素电路10具体可参照以上所示的像素电路。
特别的，在一种实施方式中，设置在第i水平行中的像素电路10包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、电容Cst及发光元件DL，其中，第一晶体管T1与发光元件DL串接于第一电源VDD与第二电源VSS之间，第二晶体管T2的栅极与时序电压线RST电连接，第二晶体管T2的源极与复位电源VEH电连接，第二晶体管T2的漏极与第一晶体管T1的源极或者第一晶体管T1的漏极电连接，第三晶体管T3的栅极与第一扫描线电连接，第三晶体管T3的源极与第一晶体管T1的漏极电连接，第三晶体管T3的漏极与第一晶体管T1的栅极电连接，第四晶体管T4的栅极与第二扫描线电连接，第四晶体管T4的源极与第一初始化电源V1电连接，第四晶体管T4的漏极与第一晶体管T1的漏极电连接，第五晶体管T5的栅极与第三扫描线电连接，第五晶体管T5的源极与数据线DA电连接，第五晶体管T5的漏极与第一晶体管T1的源极电连接，第六晶体管T6的栅极与第三扫描线电连接，第六晶体管T6的源极与第二初始化电源V2电连接，第六晶体管T6的漏极与发光元件DL的阳极电连接；发光元件DL的阴极与第二电源VSS电连接，第七晶体管T7的栅极与发光控制线电连接，第七晶体管T7的源极与第一电源VDD电连接，第七晶体管T7的漏极与第一晶体管T1的源极电连接，第八晶体管T8的栅极与发光控制线电连接，第八晶体管T8的源极与第一晶体管T1的漏极电连接，第八晶体管T8的漏极与发光元件DL的阳极电连接，电容Cst的第一端与第一电源VDD电连接，电容Cst的第二端与第一晶体管T1的栅极电连接。
请参阅图9，图9为图8所示的显示装置的驱动方法示意图。如图9所示，显示装置的驱动方法，包括：
S1、同时控制所述第二晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管及所述第八晶体管截止，及控制所述第三晶体管及所述第四晶体管导通，所述第一初始化电源供应第一初始化信号至所述第一晶体管的栅极；
S2、同时控制所述第二晶体管、所述第四晶体管、所述第七晶体管及所述第八晶体管截止，及控制所述第三晶体管、所述第五晶体管及所述第六晶体管导通，所述第二初始化电源供应第二初始化信号至所述发光元件的阳极，所述数据线供应数据信号至所述第一晶体管的源极；
S3、同时控制所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管及所述第六晶体管截止，及控制所述第七晶体管及所述第八晶体管导通，所述发光元件发光；
S4、同时控制所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管及所述第八晶体管截止；
S5、控制所述第二晶体管导通，以对所述第一晶体管进行复位。
本申请提供的像素电路、显示装置及其驱动方法，通过第二晶体管T2响应于时序电压线RST提供的时序电压信号，在一帧周期的显示扫描时段期间截止，在一帧周期的自扫描时段期间导通，以在一帧周期的自扫描时段期间对第一晶体管T1进行复位，从而可以在低频驱动的情况下对像素电路进行复位补偿，提高显示装置的驱动效率并使显示装置的功耗最小化。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (15)

  1. 一种像素电路，其包括：
    发光元件；
    第一晶体管，所述第一晶体管与所述发光元件串接于第一电源与第二电源之间，所述第一晶体管基于所述第一晶体管的栅极的电压来控制流经所述发光元件的驱动电流；及
    第二晶体管，所述第二晶体管与所述第一晶体管电连接，所述第二晶体管响应于时序电压线提供的时序电压信号，在一帧周期的显示扫描时段期间截止，在一帧周期的自扫描时段期间导通，以在一帧周期的自扫描时段期间对所述第一晶体管进行复位。
  2. 根据权利要求1所述的像素电路，其中，所述第二晶体管的栅极与所述时序电压线电连接，所述第二晶体管的源极与复位电源电连接，所述第二晶体管的漏极与所述第一晶体管的源极或者所述第一晶体管的漏极电连接。
  3. 根据权利要求2所述的像素电路，其中，所述像素电路包括：
    第三晶体管，所述第三晶体管的栅极与第一扫描线电连接，所述第三晶体管的源极与所述第一晶体管的漏极电连接，所述第三晶体管的漏极与所述第一晶体管的栅极电连接；
    第四晶体管，所述第四晶体管的栅极与第二扫描线电连接，所述第四晶体管的源极与第一初始化电源电连接，所述第四晶体管的漏极与所述第一晶体管的漏极电连接。
  4. 根据权利要求3所述的像素电路，其中，所述像素电路还包括：
    第五晶体管，所述第五晶体管的栅极与第三扫描线电连接，所述第五晶体管的源极与数据线电连接，所述第五晶体管的漏极与所述第一晶体管的源极电连接；
    第六晶体管，所述第六晶体管的栅极与所述第三扫描线电连接，所述第六晶体管的源极与第二初始化电源电连接，所述第六晶体管的漏极与所述发光元件的阳极电连接；所述发光元件的阴极与所述第二电源电连接；
    第七晶体管，所述第七晶体管的栅极与发光控制线电连接，所述第七晶体管的源极与所述第一电源电连接，所述第七晶体管的漏极与所述第一晶体管的源极电连接；
    第八晶体管，所述第八晶体管的栅极与所述发光控制线电连接，所述第八晶体管的源极与所述第一晶体管的漏极电连接，所述第八晶体管的漏极与所述发光元件的阳极电连接；及
    电容，所述电容的第一端与所述第一电源电连接，所述电容的第二端与所述第一晶体管的栅极电连接。
  5. 根据权利要求4所述的像素电路，其中，所述第一扫描线、所述第二扫描线及所述第三扫描线在所述显示扫描时段期间提供扫描信号，以控制相应晶体管导通，所述第一扫描线、所述第二扫描线及所述第三扫描线在所述自扫描时段期间不提供所述扫描信号。
  6. 根据权利要求4所述的像素电路，其中，所述第一扫描线提供的第一扫描信号、所述第二扫描线提供的第二扫描信号及所述第三扫描线提供的第三扫描信号具有相同的频率。
  7. 根据权利要求4所述的像素电路，其中，所述像素电路还包括：
    第九晶体管，所述第九晶体管的栅极与所述时序电压线电连接，所述第九晶体管的源极与所述第二初始化电源电连接，所述第九晶体管的漏极与所述发光元件的阳极电连接。
  8. 根据权利要求7所述的像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管及所述第九晶体管均为低温多晶硅晶体管。
  9. 一种显示装置，其包括像素电路；所述像素电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、电容及发光元件，其中，所述第一晶体管与所述发光元件串接于第一电源与第二电源之间，所述第二晶体管的栅极与所述时序电压线电连接，所述第二晶体管的源极与复位电源电连接，所述第二晶体管的漏极与所述第一晶体管的源极或者所述第一晶体管的漏极电连接，所述第三晶体管的栅极与第一扫描线电连接，所述第三晶体管的源极与所述第一晶体管的漏极电连接，所述第三晶体管的漏极与所述第一晶体管的栅极电连接，所述第四晶体管的栅极与第二扫描线电连接，所述第四晶体管的源极与第一初始化电源电连接，所述第四晶体管的漏极与所述第一晶体管的漏极电连接，所述第五晶体管的栅极与第三扫描线电连接，所述第五晶体管的源极与数据线电连接，所述第五晶体管的漏极与所述第一晶体管的源极电连接，所述第六晶体管的栅极与所述第三扫描线电连接，所述第六晶体管的源极与第二初始化电源电连接，所述第六晶体管的漏极与所述发光元件的阳极电连接；所述发光元件的阴极与所述第二电源电连接，所述第七晶体管的栅极与发光控制线电连接，所述第七晶体管的源极与所述第一电源电连接，所述第七晶体管的漏极与所述第一晶体管的源极电连接，所述第八晶体管的栅极与所述发光控制线电连接，所述第八晶体管的源极与所述第一晶体管的漏极电连接，所述第八晶体管的漏极与所述发光元件的阳极电连接，所述电容的第一端与所述第一电源电连接，所述电容的第二端与所述第一晶体管的栅极电连接。
  10. 根据权利要求9所述的显示装置，其中，所述第一扫描线、所述第二扫描线及所述第三扫描线在所述显示扫描时段期间提供扫描信号，以控制相应晶体管导通，所述第一扫描线、所述第二扫描线及所述第三扫描线在所述自扫描时段期间不提供所述扫描信号。
  11. 根据权利要求9所述的显示装置，其中，所述第一扫描线提供的第一扫描信号、所述第二扫描线提供的第二扫描信号及所述第三扫描线提供的第三扫描信号具有相同的频率。
  12. 根据权利要求9所述的显示装置，其中，所述像素电路还包括：
    第九晶体管，所述第九晶体管的栅极与所述时序电压线电连接，所述第九晶体管的源极与所述第二初始化电源电连接，所述第九晶体管的漏极与所述发光元件的阳极电连接。
  13. 根据权利要求12所述的显示装置，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管及所述第九晶体管均为同种类型晶体管。
  14. 根据权利要求12所述的显示装置，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管及所述第九晶体管均为低温多晶硅晶体管。
  15. 一种显示装置的驱动方法，其中，所述驱动方法用于驱动权利要求9所述的显示装置，所述驱动方法包括：
    同时控制所述第二晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管及所述第八晶体管截止，及控制所述第三晶体管及所述第四晶体管导通，所述第一初始化电源供应第一初始化信号至所述第一晶体管的栅极；
    同时控制所述第二晶体管、所述第四晶体管、所述第七晶体管及所述第八晶体管截止，及控制所述第三晶体管、所述第五晶体管及所述第六晶体管导通，所述第二初始化电源供应第二初始化信号至所述发光元件的阳极，所述数据线供应数据信号至所述第一晶体管的源极；
    同时控制所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管及所述第六晶体管截止，及控制所述第七晶体管及所述第八晶体管导通，所述发光元件发光；
    同时控制所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管及所述第八晶体管截止；
    控制所述第二晶体管导通，以对所述第一晶体管进行复位。
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