WO2023100808A1 - 絶縁チップおよび信号伝達装置 - Google Patents

絶縁チップおよび信号伝達装置 Download PDF

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Publication number
WO2023100808A1
WO2023100808A1 PCT/JP2022/043766 JP2022043766W WO2023100808A1 WO 2023100808 A1 WO2023100808 A1 WO 2023100808A1 JP 2022043766 W JP2022043766 W JP 2022043766W WO 2023100808 A1 WO2023100808 A1 WO 2023100808A1
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Prior art keywords
electrode plate
side electrode
chip
insulating layer
insulating
Prior art date
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Ceased
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PCT/JP2022/043766
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English (en)
French (fr)
Japanese (ja)
Inventor
文悟 田中
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Rohm Co Ltd
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Rohm Co Ltd
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Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to DE112022005675.4T priority Critical patent/DE112022005675B4/de
Priority to CN202280078999.4A priority patent/CN118339655A/zh
Priority to JP2023564963A priority patent/JPWO2023100808A1/ja
Publication of WO2023100808A1 publication Critical patent/WO2023100808A1/ja
Priority to US18/675,658 priority patent/US20240313043A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to insulating tips and signal transmission devices.
  • an insulated gate driver that applies a gate voltage to the gate of a switching element such as a transistor is known (see Patent Document 1, for example).
  • the gate driver has an insulating element such as a transformer or a capacitor that is used to insulate the primary side circuit and the secondary side circuit.
  • a gate driver may be required to have an improved withstand voltage.
  • Such a problem is not limited to the gate driver, but can similarly occur in a signal transmission device and an insulation chip that insulates the primary side circuit and the secondary side circuit and transmits a signal.
  • An insulating chip that solves the above problems includes an element insulating layer having a front surface and a back surface, and a first capacitor and a second capacitor formed in the element insulating layer, wherein the first capacitor is formed on the element insulating layer.
  • the second capacitor has a first surface-side electrode plate and a first back-side electrode plate that face each other in the thickness direction, and the second capacitor has the first surface-side electrode plate when viewed from the thickness direction of the element insulating layer. and a second back electrode plate formed to surround the first back electrode plate when viewed from the thickness direction of the element insulating layer.
  • the second front-side electrode plate and the second back-side electrode plate face each other in the thickness direction of the element insulating layer, and the first back-side electrode plate and the second back-side electrode plate are arranged in the element insulating layer; It is electrically connected to the side electrode plate.
  • a signal transmission device for solving the above problems is configured to perform at least one of transmission and reception of a signal to and from the first circuit through a first chip including a first circuit, an insulation chip, and the insulation chip.
  • a second chip including a second circuit the insulating chip including an element insulating layer having a front surface and a back surface; a first capacitor and a second capacitor formed in the element insulating layer;
  • the first capacitor has a first front-side electrode plate and a first back-side electrode plate that are arranged to face each other in the thickness direction of the element insulating layer, and the second capacitor has a structure when viewed from the thickness direction of the element insulating layer.
  • a second front electrode plate formed to surround the first front electrode plate and a second front electrode plate formed to surround the first rear electrode plate when viewed from the thickness direction of the element insulating layer.
  • a back-side electrode plate wherein the second front-side electrode plate and the second back-side electrode plate are opposed to each other in the thickness direction of the element insulating layer, and the first The backside electrode plate and the second backside electrode plate are electrically connected.
  • the insulating chip and the signal transmission device it is possible to improve the withstand voltage.
  • FIG. 1 is a circuit diagram schematically showing the circuit configuration in one embodiment of the signal transmission device.
  • FIG. 2 is a cross-sectional view schematically showing the cross-sectional structure of the signal transmission device of FIG. 3 is a plan view schematically showing a planar structure of an insulating chip in the signal transmission device of FIG. 2.
  • FIG. 4 is a cross-sectional view schematically showing the cross-sectional structure of the insulating chip of FIG. 3 taken along a plane perpendicular to its thickness direction.
  • FIG. 7 is a plan view schematically showing a planar structure of part of an insulating chip of a comparative example.
  • 8 is a cross-sectional view schematically showing the cross-sectional structure of the insulating chip of the comparative example of FIG. 7 taken along line F8-F8.
  • FIG. 9 is a cross-sectional view schematically showing the cross-sectional structure of the signal transmission device of the modification.
  • FIG. 10 is a plan view schematically showing the planar structure of the insulating chip of the modification.
  • FIG. 11 is a plan view schematically showing the planar structure of the insulating chip of the modified example.
  • FIG. 12 is a plan view schematically showing the planar structure of the insulating chip of the modification.
  • FIG. 13 is a cross-sectional view schematically showing the cross-sectional structure of the insulating chip of the modified example of FIG. 12 taken along a plane perpendicular to the thickness direction thereof.
  • FIG. 14 is a cross-sectional view schematically showing the cross-sectional structure of the insulating tip of the modification.
  • FIG. 15 is a cross-sectional view schematically showing the cross-sectional structure of the insulating tip of the modification.
  • FIG. 1 shows a simplified example of the circuit configuration of the signal transmission device 10. As shown in FIG.
  • the signal transmission device 10 is a device that transmits a pulse signal while electrically insulating a primary terminal 11 and a secondary terminal 12 from each other.
  • the signal transfer device 10 is a digital isolator, an example of which is an AC/DC converter or gate driver or electronic components contained therein.
  • the signal transmission device 10 includes a primary circuit 13 electrically connected to a primary terminal 11, a secondary circuit 14 electrically connected to a secondary terminal 12, and a primary circuit 13.
  • a signal transmission circuit 10A having a capacitor 15 electrically connected to the secondary side circuit 14 is provided.
  • the primary side circuit 13 corresponds to the "first circuit”
  • the secondary side circuit 14 corresponds to the "second circuit”.
  • the primary side circuit 13 is a circuit configured to operate when a first voltage is applied.
  • the primary circuit 13 is electrically connected, for example, to an external control device (not shown).
  • the secondary circuit 14 is a circuit configured to operate when a second voltage different from the first voltage is applied.
  • the second voltage is higher than the first voltage, for example.
  • the first voltage and the second voltage are DC voltages.
  • Secondary circuit 14 is electrically connected to, for example, a drive circuit to be controlled by the control device.
  • a drive circuit is a switching circuit.
  • the signal transmission device 10 transmits the signal from the primary circuit 13 to the secondary circuit 14 via the capacitor 15 . is transmitted and a signal is output from the secondary side circuit 14 to the drive circuit via the secondary side terminal 12 .
  • the signal transmission device 10 transmits a signal from a primary side circuit 13 to a secondary side circuit 14 via a capacitor 15 .
  • the primary side circuit 13 and the secondary side circuit 14 are electrically insulated by the capacitor 15 . More specifically, while the capacitor 15 restricts the transmission of the DC voltage between the primary circuit 13 and the secondary circuit 14, it allows the transmission of the pulse signal.
  • the state in which the primary side circuit 13 and the secondary side circuit 14 are insulated means the state in which the transmission of the DC voltage is interrupted between the primary side circuit 13 and the secondary side circuit 14. This means that the transmission of the pulse signal from the primary side circuit 13 to the secondary side circuit 14 is permitted.
  • the secondary circuit 14 is configured to receive the signal of the primary circuit 13 .
  • the dielectric strength of the signal transmission device 10 is, for example, 2500 Vrms or more and 7500 Vrms or less.
  • the dielectric breakdown voltage of the signal transmission device 10 of this embodiment is about 5700 Vrms.
  • the specific numerical value of the withstand voltage of the signal transmission device 10 is not limited to this and is arbitrary. Further, in this embodiment, as shown in FIG. 1, the ground of the primary circuit 13 and the ground of the secondary circuit 14 are provided independently.
  • the signal transmission device 10 of this embodiment includes two capacitors 15 for transmitting two types of signals from the primary circuit 13 to the secondary circuit 14 . More specifically, the signal transmission device 10 includes a capacitor 15 used to transmit a first signal from the primary circuit 13 to the secondary circuit 14 and a second signal from the primary circuit 13 to the secondary circuit 14 . and a capacitor 15 used for transmitting two signals.
  • the first signal is a signal containing rise information of the external signal input to the signal transmission device 10
  • the second signal is a signal containing fall information of the external signal.
  • a pulse signal is generated by the first signal and the second signal.
  • the capacitor 15 used for transmitting the first signal is referred to as "capacitor 15A”
  • the capacitor 15 used for transmitting the second signal is referred to as "capacitor 15B".
  • the signal transmission device 10 includes primary signal lines 16A, 16B and secondary signal lines 17A, 17B.
  • the primary signal line 16A is a signal line that connects the primary circuit 13 and the capacitor 15A, and is a signal line that transmits the first signal from the primary circuit 13 to the capacitor 15A.
  • the primary side signal line 16B is a signal line that connects the primary side circuit 13 and the capacitor 15B, and is a signal line that transmits the second signal from the primary side circuit 13 to the capacitor 15B.
  • the secondary signal line 17A is a signal line that connects the capacitor 15A and the secondary circuit 14, and is a signal line that transmits the first signal from the capacitor 15A to the secondary circuit 14.
  • the secondary signal line 17B is a signal line that connects the capacitor 15B and the secondary circuit 14, and is a signal line that transmits the second signal from the capacitor 15B to the secondary circuit 14.
  • the first signal is transmitted from the primary circuit 13 to the secondary circuit 14 through the primary signal line 16A, the capacitor 15A, and the secondary signal line 17A in this order.
  • the second signal is transmitted from primary circuit 13 to secondary circuit 14 via primary signal line 16B, capacitor 15B, and secondary signal line 17B in this order.
  • the capacitor 15A transmits the first signal from the primary circuit 13 to the secondary circuit 14 and electrically insulates the primary circuit 13 and the secondary circuit 14 from each other.
  • the capacitor 15A has a first capacitor 21A and a second capacitor 22A connected in series.
  • the first capacitor 21A is connected to the primary signal line 16A
  • the second capacitor 22A is connected to the secondary signal line 17A.
  • the first capacitor 21A and the second capacitor 22A correspond to the "first signal capacitor".
  • the first capacitor 21A has a first electrode 23A and a second electrode 24A.
  • the first electrode 23A is connected to the primary signal line 16A.
  • the second capacitor 22A has a first electrode 25A and a second electrode 26A.
  • a second electrode 24A of the first capacitor 21A and a first electrode 25A of the second capacitor 22A are connected to each other by a connection signal line 18A.
  • the second electrode 26A is connected to the secondary signal line 17A.
  • the capacitor 15B transmits the second signal from the primary circuit 13 to the secondary circuit 14 and electrically insulates the primary circuit 13 and the secondary circuit 14 from each other.
  • Capacitor 15B has a first capacitor 21B and a second capacitor 22B that are connected in series with each other.
  • the first capacitor 21B is connected to the primary signal line 16B
  • the second capacitor 22B is connected to the secondary signal line 17B.
  • the first capacitor 21B and the second capacitor 22B correspond to "second signal capacitors".
  • the first capacitor 21B has a first electrode 23B and a second electrode 24B.
  • the first electrode 23B is connected to the primary signal line 16B.
  • the second capacitor 22B has a first electrode 25B and a second electrode 26B.
  • a second electrode 24B of the first capacitor 21B and a first electrode 25B of the second capacitor 22B are connected to each other by a connection signal line 18B.
  • the second electrode 26B is connected to the secondary signal line 17B.
  • the dielectric breakdown voltage of the capacitors 15A and 15B in this embodiment is, for example, 2500 Vrms or more and 7500 Vrms or less.
  • the dielectric strength of the capacitors 15A and 15B may be 2500 Vrms or more and 5700 Vrms or less.
  • the specific numerical value of the dielectric strength voltage of the capacitors 15A and 15B is not limited to this and is arbitrary.
  • FIG. 2 shows an example of a cross-sectional structure schematically showing a part of the internal configuration of the signal transmission device 10.
  • the signal transmission device 10 is a semiconductor device in which a plurality of semiconductor chips are packaged.
  • the package format of the signal transmission device 10 is, for example, an SO (Small Outline) system, and in this embodiment, it is an SOP (Small Outline Package). Note that the package format of the signal transmission device 10 can be arbitrarily changed.
  • the signal transmission device 10 includes a first chip 30, a second chip 40, and an insulating chip 50 as a plurality of semiconductor chips.
  • the signal transmission device 10 also includes a primary die pad 60 on which the first chip 30 is mounted, a secondary die pad 70 on which the second chip 40 is mounted, the die pads 60 and 70 and the chips 30, 40, . and a sealing resin 80 that seals 50 .
  • the primary die pad 60 corresponds to the "first mounting frame”
  • the secondary die pad 70 corresponds to the "mounting frame” or the "second mounting frame”.
  • the sealing resin 80 is made of an electrically insulating resin material, such as a black epoxy resin.
  • the sealing resin 80 is formed in a rectangular plate shape having a thickness direction in the z direction.
  • each die pad 60, 70 is made of a material containing Cu (copper).
  • the die pads 60 and 70 may be made of other metal material such as Al (aluminum).
  • the material forming each die pad 60, 70 is not limited to a conductive material.
  • each die pad 60, 70 may be made of ceramics such as alumina. That is, each of the die pads 60 and 70 may be made of an electrically insulating material. The die pads 60 and 70 are not exposed from the sealing resin 80 in this embodiment.
  • the primary die pad 60 and the secondary die pad 70 When viewed from the z-direction, the primary die pad 60 and the secondary die pad 70 are arranged side by side while being separated from each other.
  • the arrangement direction of the primary die pads 60 and the secondary die pads 70 when viewed from the z direction is defined as the x direction.
  • a direction perpendicular to the x direction when viewed from the z direction is the y direction.
  • Both the primary die pad 60 and the secondary die pad 70 are formed in a flat plate shape.
  • the x-direction length of the secondary die pad 70 is longer than the x-direction length of the primary die pad 60 .
  • the insulating chip 50 is mounted on the secondary die pad 70 . That is, both the insulating chip 50 and the second chip 40 are mounted on the secondary die pad 70 .
  • the second chip 40 and the insulating chip 50 are arranged apart from each other in the x direction. Therefore, the chips 30, 40, 50 are arranged apart from each other in the x-direction.
  • the chips 30, 40, 50 are arranged in the order of the first chip 30, the insulating chip 50, and the second chip 40 from the primary die pad 60 toward the secondary die pad 70 in the x direction. ing. That is, the insulating chip 50 is arranged between the first chip 30 and the second chip 40 in the x direction.
  • the distance between the primary die pad 60 and the secondary die pad 70 is greater than the distance between the second chip 40 and the insulating chip 50 in the x direction when viewed in the z direction. Therefore, when viewed from the z direction, the distance between the first tip 30 and the insulating tip 50 in the x direction is greater than the distance between the second tip 40 and the insulating tip 50 in the x direction. In other words, the insulating chip 50 is arranged closer to the second chip 40 than to the first chip 30 .
  • the first chip 30 has a first substrate 33 on which the primary circuit 13 is formed.
  • the first substrate 33 is, for example, a semiconductor substrate.
  • An example of a semiconductor substrate is a substrate made of a material containing Si (silicon).
  • a wiring layer 34 is formed on the first substrate 33 .
  • the wiring layer 34 includes a plurality of insulating films stacked in the z-direction, metal layers provided between insulating films adjacent in the z-direction, and vias connecting metal layers positioned at different positions in the z-direction. have.
  • the metal layers and vias constitute the wiring pattern of the first chip 30 .
  • the metal layers and vias are electrically connected to, for example, primary circuit 13 .
  • a protective film 35 is formed on the wiring layer 34 to protect the wiring layer 34 .
  • the protective film 35 is made of an electrically insulating material.
  • the first chip 30 has a chip front surface 30s and a chip rear surface 30r facing opposite sides in the z direction.
  • the first substrate 33 constitutes the chip rear surface 30r
  • the protective film 35 constitutes the chip front surface 30s.
  • the chip back surface 30 r faces the primary die pad 60 .
  • a plurality of first electrode pads 31 and a plurality of second electrode pads 32 are provided in a portion of the first chip 30 near the chip surface 30s. More specifically, each electrode pad 31, 32 is provided so as to be exposed from the chip surface 30s.
  • a protective film 35 covers the electrode pads 31 and 32 .
  • the protection film 35 has openings that expose the electrode pads 31 and 32 .
  • Each of the electrode pads 31 and 32 is electrically connected to the primary circuit 13 by a wiring layer 34, for example.
  • a plurality of first electrode pads 31 and a plurality of second electrode pads 32 are formed on the surface of the wiring layer 34 .
  • the surface of the wiring layer 34 is the surface of the wiring layer 34 facing the same side as the chip surface 30s.
  • the plurality of first electrode pads 31 are arranged on the opposite side of the chip surface 30s from the insulating chip 50 with respect to the center of the chip surface 30s in the x-direction.
  • the plurality of electrode pads 31 are arranged apart from each other in the y direction.
  • the plurality of second electrode pads 32 are arranged closer to the insulating chip 50 with respect to the center of the chip surface 30s in the x direction in the chip surface 30s.
  • the plurality of second electrode pads 32 are arranged apart from each other in the y direction.
  • the first chip 30 is bonded to the primary die pad 60 with the first bonding material 101.
  • the first bonding material 101 is interposed between the chip back surface 30 r of the first chip 30 and the primary die pad 60 .
  • the first bonding material 101 is a conductive bonding material such as solder paste or Ag (silver) paste.
  • the primary circuit 13 is electrically connected to the primary die pad 60 via the first bonding material 101 .
  • the primary die pad 60 constitutes a ground. Therefore, it can be said that the primary side circuit 13 is electrically connected to the ground.
  • the material of the first bonding material 101 can be arbitrarily changed, and may be an insulating bonding material, for example.
  • the primary side circuit 13 may be electrically connected to the primary side die pad 60 by a structure other than the first bonding material 101 (for example, a wire).
  • the second chip 40 has a second substrate 43 on which the secondary circuit 14 is formed.
  • the second substrate 43 is, for example, a semiconductor substrate.
  • An example of a semiconductor substrate is a substrate made of a material containing Si.
  • a wiring layer 44 is formed on the second substrate 43 .
  • the wiring layer 44 includes insulating films stacked in the z-direction, metal layers provided between insulating films adjacent in the z-direction, and vias connecting metal layers positioned at different positions in the z-direction. ing.
  • the metal layers and vias constitute the wiring pattern of the second chip 40 .
  • the metal layers and vias are electrically connected to, for example, the secondary circuit 14 .
  • a protective film 45 is formed on the wiring layer 44 to protect the wiring layer 44 .
  • the protective film 45 is made of an electrically insulating material.
  • the second chip 40 has a chip front surface 40s and a chip rear surface 40r facing opposite sides in the z direction.
  • the second substrate 43 constitutes the chip rear surface 40r
  • the protective film 45 constitutes the chip front surface 40s.
  • the chip rear surface 40 r faces the secondary die pad 70 .
  • the chip rear surface 40 r faces the same side as the chip rear surface 30 r of the first chip 30
  • the chip front surface 40 s faces the same side as the chip front surface 30 s of the first chip 30 .
  • a plurality of first electrode pads 41 and a plurality of second electrode pads 42 are provided in a portion of the second chip 40 near the chip surface 40s. More specifically, each electrode pad 41, 42 is provided so as to be exposed from the chip surface 40s.
  • a protective film 45 covers the electrode pads 41 and 42 .
  • the protective film 45 has openings that expose the electrode pads 41 and 42 .
  • Each electrode pad 41 , 42 is electrically connected to the secondary circuit 14 by a wiring layer 44 , for example.
  • a plurality of first electrode pads 41 and a plurality of second electrode pads 42 are formed on the surface of wiring layer 44 .
  • the surface of the wiring layer 44 is the surface of the wiring layer 44 facing the same side as the chip surface 40s.
  • the plurality of first electrode pads 41 are arranged closer to the insulating chip 50 with respect to the center of the chip surface 40s in the x direction than the chip surface 40s when viewed from the z direction. Although not shown, the plurality of first electrode pads 41 are arranged apart from each other in the y direction.
  • the plurality of second electrode pads 42 are arranged on the opposite side of the chip surface 40s from the insulating chip 50 with respect to the center of the chip surface 40s in the x direction. Although not shown, the plurality of second electrode pads 42 are arranged apart from each other in the y direction.
  • the second chip 40 is bonded to the secondary die pad 70 with the second bonding material 102 . More specifically, the second bonding material 102 is interposed between the chip rear surface 40 r and the secondary die pad 70 . The second bonding material 102 bonds the chip rear surface 40 r and the secondary die pad 70 .
  • the second bonding material 102 is a conductive bonding material such as solder paste or Ag paste. In this embodiment, the second bonding material 102 is made of the same material as the first bonding material 101, for example.
  • the material of the second bonding material 102 can be arbitrarily changed, and may be a conductive bonding material different from the material of the first bonding material 101, for example. Also, the second bonding material 102 may be an insulating bonding material. In this case, the secondary circuit 14 may be electrically connected to the secondary die pad 70 by means of a structure other than the second bonding material 102 (for example, a wire).
  • the insulating chip 50 has capacitors 15A and 15B (see FIG. 1). As shown in FIG. 3, the shape of the insulating tip 50 viewed from the z-direction is a rectangle having short sides and long sides. In the present embodiment, the insulating chip 50 is mounted on the secondary die pad 70 so that the long side extends along the y direction and the short side extends along the x direction when viewed from the z direction.
  • the insulating chip 50 has a chip front surface 50s and a chip rear surface 50r facing opposite sides in the z direction.
  • the chip rear surface 50r faces the secondary die pad 70 side. That is, the chip rear surface 50r faces the same side as the chip rear surface 40r of the second chip 40, and the chip front surface 50s faces the same side as the chip front surface 40s of the second chip 40.
  • the insulating chip 50 includes a plurality of (two in this embodiment) first electrode pads 51 and a plurality of (two in this embodiment) second electrode pads 52 .
  • Each of the electrode pads 51 and 52 is provided at a portion closer to the chip surface 50s. More specifically, the electrode pads 51 and 52 are provided so as to be exposed from the chip surface 50s when viewed in the z direction.
  • the plurality of first electrode pads 51 are arranged closer to the first chip 30 with respect to the center of the chip surface 50s in the x direction than the chip surface 50s.
  • the plurality of second electrode pads 52 are arranged closer to the second chip 40 with respect to the center of the chip surface 50s in the x direction in the chip surface 50s.
  • a plurality of wires W are connected to each of the first chip 30, the second chip 40, and the insulating chip 50.
  • a wire W electrically connects the first chip 30 and the insulating chip 50
  • a wire W electrically connects the second chip 40 and the insulating chip 50 .
  • Each wire W is a bonding wire formed by a wire bonding apparatus, and is made of a conductor such as Au (gold), Al, Cu, or the like.
  • a plurality of first electrode pads 31 of the first chip 30 are individually connected by a plurality of wires W to a plurality of primary leads (not shown).
  • the primary lead is a component that constitutes the primary terminal 11 in FIG. Thereby, the primary side circuit 13 and the primary side terminal 11 are electrically connected.
  • the primary side lead is made of the same material as the primary side die pad 60 .
  • the primary side lead and primary side die pad 60 may be integrally formed.
  • the primary leads are spaced apart from the primary die pad 60 on the side opposite to the secondary die pad 70 .
  • the primary lead has a portion protruding outward from the sealing resin 80 .
  • a portion of the primary lead that protrudes outward from the sealing resin 80 constitutes an external terminal of the signal transmission device 10 .
  • the plurality of second electrode pads 32 of the first chip 30 are individually connected to the plurality of first electrode pads 51 of the insulating chip 50 by a plurality of wires W. Thereby, the primary side circuit 13 and the capacitors 15A and 15B (see FIG. 1) are electrically connected. That is, the wiring layer 34 of the first chip 30, the plurality of second electrode pads 32, the plurality of wires W, and the plurality of first electrode pads 51 respectively constitute the primary side signal lines 16A and 16B (see FIG. 1). are doing.
  • the plurality of second electrode pads 52 of the insulating chip 50 are individually connected to the plurality of first electrode pads 41 of the second chip 40 by a plurality of wires W. Thereby, the capacitors 15A and 15B and the secondary circuit 14 are electrically connected. That is, the plurality of second electrode pads 52, the plurality of wires W, the first electrode pads 41 of the second chip 40, and the wiring layer 44 respectively constitute the secondary signal lines 17A and 17B (see FIG. 1). there is
  • a plurality of second electrode pads 42 of the second chip 40 are individually connected by a plurality of wires W to a plurality of secondary leads (not shown).
  • the secondary lead is a component that constitutes the secondary terminal 12 in FIG. Thereby, the secondary circuit 14 and the secondary terminal 12 are electrically connected.
  • the secondary lead is made of the same material as the secondary die pad 70 .
  • the secondary lead and secondary die pad 70 may be integrally formed.
  • the primary lead, primary die pad 60, secondary lead, and secondary die pad 70 may be integrally formed.
  • the secondary leads are spaced apart from the secondary die pad 70 on the side opposite to the primary die pad 60 .
  • the secondary lead has a portion that protrudes outward from the sealing resin 80 .
  • a portion of the secondary lead protruding outward from the sealing resin 80 constitutes an external terminal of the signal transmission device 10 .
  • FIG. 1 A detailed configuration of insulation chip
  • FIG. 2 A detailed configuration of the insulating tip 50 will be described with reference to FIGS. 2 to 6.
  • FIG. 1 the two first electrode pads 51 are referred to as the first electrode pad 51A and the first electrode pad 51B for convenience, and the two second electrode pads 52 are referred to as the second electrode pad 52A and the second electrode pad for convenience. 52B.
  • FIG. 3 is a plan view schematically showing the planar structure of the insulating chip 50.
  • FIG. 4 is a cross-sectional view schematically showing the cross-sectional structure of the insulating chip 50 taken along a plane orthogonal to the thickness direction of the insulating chip 50.
  • FIG. 5 and 6 are cross-sectional views schematically showing cross-sectional structures taken along the cross-section indicating lines in FIG. 3.
  • FIG. 4 to 6 hatching lines of some components are omitted from the viewpoint of visibility of the drawings.
  • the direction from the chip rear surface 50r to the chip front surface 50s of the insulating chip 50 is defined as upward, and the direction from the chip front surface 50s to the chip rear surface 50r is defined as downward.
  • the insulating chip 50 is obtained by integrating both capacitors 15A and 15B into one chip.
  • the insulating chip 50 is a chip dedicated to both the capacitors 15A and 15B, separate from the first chip 30 and the second chip 40 (see FIG. 2 for both).
  • Both capacitors 15A and 15B are arranged apart from each other in the y direction. In other words, both capacitors 15A and 15B are arranged apart from each other in the longitudinal direction of the insulating chip 50 when viewed from the z direction.
  • the first capacitor 21A has a first front-side electrode plate 53A and a first back-side electrode plate 54A that are arranged facing each other in the z-direction.
  • the first front-side electrode plate 53A and the first back-side electrode plate 54A are arranged concentrically.
  • the first front electrode plate 53A corresponds to the first electrode 23A (see FIG. 1) of the first capacitor 21A
  • the first back electrode plate 54A corresponds to the second electrode 24A (see FIG. 1) of the first capacitor 21A. are doing.
  • the shape of the first surface-side electrode plate 53A viewed from the z direction is circular.
  • the shape of the first backside electrode plate 54A viewed from the z direction is circular.
  • the area of the first front electrode plate 53A viewed from the z direction is equal to the area of the first back electrode plate 54A viewed from the z direction.
  • the difference between the area of the first front electrode plate 53A viewed from the z direction and the area of the first back electrode plate 54A viewed from the z direction is, for example, the area of the first front electrode plate 53A viewed from the z direction.
  • Within 10% of the area it can be said that the area of the first front electrode plate 53A viewed from the z direction is equal to the area of the first back electrode plate 54A viewed from the z direction.
  • the second capacitor 22A has a second front-side electrode plate 55A and a second back-side electrode plate 56A that are arranged facing each other in the z-direction.
  • the second front electrode plate 55A and the second back electrode plate 56A are arranged concentrically.
  • the second front electrode plate 55A corresponds to the second electrode 26A (see FIG. 1) of the second capacitor 22A
  • the second back electrode plate 56A corresponds to the first electrode 25A (see FIG. 1) of the second capacitor 22A. are doing.
  • the shape of the second surface-side electrode plate 55A viewed from the z-direction is a closed annular shape.
  • the second front electrode plate 55A has an inner diameter larger than the diameter of the first front electrode plate 53A.
  • the shape of the second backside electrode plate 56A viewed from the z-direction is a closed annular shape.
  • the second backside electrode plate 56A has an inner diameter larger than the diameter of the first backside electrode plate 54A.
  • the area of the second front electrode plate 55A viewed from the z direction is equal to the area of the second back electrode plate 56A viewed from the z direction.
  • the difference between the area of the second front electrode plate 55A viewed from the z direction and the area of the second back electrode plate 56A viewed from the z direction is, for example, the area of the second front electrode plate 55A viewed from the z direction.
  • the area of the second front electrode plate 55A viewed from the z direction is equal to the area of the second back electrode plate 56A viewed from the z direction.
  • the second surface-side electrode plate 55A is formed so as to surround the first surface-side electrode plate 53A when viewed from the z direction.
  • the second front electrode plate 55A is provided so that its center coincides with the center of the first front electrode plate 53A. That is, the first surface-side electrode plate 53A and the second surface-side electrode plate 55A are arranged concentrically. In other words, the first surface-side electrode plate 53A and the second surface-side electrode plate 55A are formed concentrically.
  • the second surface-side electrode plate 55A is provided at a position aligned with the first surface-side electrode plate 53A in the z-direction.
  • the second surface-side electrode plate 55A When viewed from the z-direction, the second surface-side electrode plate 55A is arranged with a gap from the first surface-side electrode plate 53A.
  • a distance G1 between the first surface-side electrode plate 53A and the second surface-side electrode plate 55A as viewed in the z-direction is constant over the entire circumference of the first surface-side electrode plate 53A.
  • the distance G1 is greater than or equal to the distance D1 (see FIG. 5) between the first front electrode plate 53A and the first back electrode plate 54A in the z direction. Since the distance G1 is constant over the entire circumference of the first front electrode plate 53A, it can be said that it is the shortest distance between the first front electrode plate 53A and the second front electrode plate 55A when viewed from the z direction. .
  • the distance D1 is the distance between the region of the first front electrode plate 53A facing the first rear electrode plate 54A and the region of the first rear electrode plate 54A facing the first front electrode plate 53A. constant throughout each. Therefore, it can be said that the distance D1 is the shortest distance between the first front-side electrode plate 53A and the first back-side electrode plate 54A. Therefore, the shortest distance between the first front-side electrode plate 53A and the second front-side electrode plate 55A as viewed in the z-direction is the distance between the first front-side electrode plate 53A and the first back-side electrode plate 54A. It can be said that it is more than the shortest distance. In this embodiment, distance G1 is equal to distance D1.
  • the second capacitor 22A has an electrode pad portion 55AA electrically connected to the second surface-side electrode plate 55A.
  • the electrode pad portion 55AA is formed at a different position from the second surface-side electrode plate 55A.
  • the electrode pad portion 55AA is provided closer to the second chip 40 than the second surface-side electrode plate 55A.
  • the electrode pad portion 55AA and the second surface-side electrode plate 55A are connected by a connection portion 55AB.
  • the second surface-side electrode plate 55A, the electrode pad portion 55AA, and the connection portion 55AB are integrally formed.
  • the second surface-side electrode plate 55A, the electrode pad portion 55AA, and the connection portion 55AB are provided at positions aligned with each other in the z direction.
  • the electrode pad portion 55AA corresponds to "a region formed at a position different from that of the second surface-side electrode plate and integrally formed with the second surface-side electrode plate".
  • the electrode pad portion 55AA is formed at a position separated from the second front electrode plate 55A in the x direction, the first front electrode plate 53A and the second front electrode plate 55A are insulated. It is arranged offset in the x direction with respect to the chip 50 .
  • the first front-side electrode plate 53A and the second front-side electrode plate 55A are arranged closer to the first chip 30 with respect to the center of the insulating chip 50 in the x direction.
  • the first rear electrode plate 54A and the second rear electrode plate 56A are arranged closer to the first chip 30 with respect to the center of the insulating chip 50 in the x direction.
  • the second backside electrode plate 56A is formed so as to surround the first backside electrode plate 54A when viewed from the z direction.
  • the second backside electrode plate 56A is provided so that its center coincides with the center of the first backside electrode plate 54A. That is, the first rear electrode plate 54A and the second rear electrode plate 56A are formed concentrically.
  • the second backside electrode plate 56A is provided at a position aligned with the first backside electrode plate 54A in the z-direction.
  • the second backside electrode plate 56A When viewed from the z-direction, the second backside electrode plate 56A is arranged with a gap from the first backside electrode plate 54A.
  • a distance G2 between the first rear electrode plate 54A and the second rear electrode plate 56A as viewed in the z-direction is constant over the entire circumference of the first rear electrode plate 54A.
  • the distance G2 is greater than or equal to the distance D3 (see FIG. 5) between the second front electrode plate 55A and the second back electrode plate 56A in the z direction. Since the distance G2 is constant over the entire circumference of the first back electrode plate 54A, it can be said that it is the shortest distance between the first back electrode plate 54A and the second back electrode plate 56A when viewed from the z direction. .
  • the distance D3 is the distance between the area of the second front electrode plate 55A that faces the second back electrode plate 56A and the area of the second back electrode plate 56A that faces the second front electrode plate 55A. constant throughout each. Therefore, it can be said that the distance D3 is the shortest distance between the second front electrode plate 55A and the second rear electrode plate 56A. Therefore, the shortest distance between the first back electrode plate 54A and the second back electrode plate 56A when viewed in the z direction is the distance between the second back electrode plate 55A and the second back electrode plate 56A. It can be said that it is more than the shortest distance.
  • distance G2 is equal to distance D3.
  • distance D3 is equal to distance D1.
  • the difference between the distance D3 and the distance D1 is, for example, within 10% of the distance D1, it can be said that the distance D3 is equal to the distance D1.
  • the area of the second back electrode plate 56A viewed from the z direction is equal to the area of the first back electrode plate 54A viewed from the z direction.
  • the difference between the area of the second back electrode plate 56A viewed from the z direction and the area of the first back electrode plate 54A viewed from the z direction is, for example, the first back electrode plate 54A viewed from the z direction.
  • the area of the second rear electrode plate 56A viewed from the z direction is equal to the area of the first rear electrode plate 54A viewed from the z direction.
  • the area of the first surface-side electrode plate 53A and the area of the second surface-side electrode plate 55A are equal to each other.
  • the area of the first back side electrode plate 54A and the area of the second back side electrode plate 56A are equal to each other.
  • Distance D1 and distance D3 are equal to each other. From these, it can be said that the capacitance of the first capacitor 21A and the capacitance of the second capacitor 22A are equal to each other.
  • the first back-side electrode plate 54A and the second back-side electrode plate 56A are connected by a connection wiring 56AB.
  • the connection wiring 56AB is provided at a position aligned with the back-side electrode plates 54A and 56A in the z-direction. In the present embodiment, the connection wiring 56AB extends along the x-direction from the end of the first backside electrode plate 54A near the second chip 40 (see FIG. 2).
  • the connection wiring 56AB can be positioned at any position in the circumferential direction of the first back electrode plate 54A as long as it connects the first back electrode plate 54A and the second back electrode plate 56A. It can also be said that the connection wiring 56AB extends along the radial direction of the first back side electrode plate 54A. In this manner, the first backside electrode plate 54A and the second backside electrode plate 56A are electrically connected within the element insulating layer 58 .
  • the first capacitor 21B has a first front-side electrode plate 53B and a first back-side electrode plate 54B that are arranged facing each other in the z-direction.
  • the second capacitor 22B has a second front-side electrode plate 55B and a second back-side electrode plate 56B that are opposed to each other in the z-direction.
  • the second capacitor 22B has an electrode pad portion 55BA and a connecting portion 55BB.
  • the first back-side electrode plate 54B and the second back-side electrode plate 56B are connected by a connection wiring 56BB.
  • the capacitor 15B has the same configuration as the capacitor 15A, so detailed description thereof will be omitted.
  • the first front-side electrode plates 53A, 53B, the first back-side electrode plates 54A, 54B, the second front-side electrode plates 55A, 55B, and the second back-side electrode plates 56A, 56B contain Al. made of material. Therefore, it can be said that the first electrode pads 51A and 51B and the second electrode pads 52A and 52B are made of a material containing Al.
  • the material constituting each electrode plate 53A, 53B, 54A, 54B, 55A, 55B, 56A, 56B can be arbitrarily changed, and for example, a material containing Cu, W, or the like may be used.
  • each of the electrode plates 53A, 53B, 54A, 54B, 55A, 55B, 56A, and 56B should be made of a material containing at least one of Cu, Al, and W. Further, each electrode plate 53A, 53B, 54A, 54B, 55A, 55B, 56A, 56B may be made of a material containing Ti.
  • the insulating chip 50 has a substrate 57 and an element insulating layer 58 formed on the substrate 57 .
  • Substrate 57 is formed of, for example, a semiconductor substrate.
  • the substrate 57 is a semiconductor substrate made of a material containing Si.
  • the substrate 57 may use a wide bandgap semiconductor or a compound semiconductor as a semiconductor substrate.
  • the substrate 57 may be an insulating substrate made of a material containing glass or an insulating substrate made of a material containing ceramics such as alumina.
  • a wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more.
  • the wide bandgap semiconductor may be SiC (silicon carbide).
  • the compound semiconductor may be a III-V compound semiconductor.
  • the compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).
  • the substrate 57 has a substrate front surface 57s and a substrate rear surface 57r facing opposite sides in the z-direction.
  • a plurality of insulating films 58M are laminated in the z direction on the substrate surface 57s.
  • the element insulating layer 58 of this embodiment is composed of a plurality of laminated insulating films 58M. Therefore, the z direction can also be said to be the thickness direction of the element insulating layer 58 . Also, "viewed from the z-direction" includes the meaning of "viewed from the thickness direction of the element insulating layer 58".
  • Each insulating film 58M is an interlayer insulating film, for example, and is an oxide film formed of a material containing SiO 2 (silicon oxide).
  • the thickness of each insulating film 58M may be, for example, 500 nm or more and 5000 nm or less. In this embodiment, the thickness of each insulating film 58M is, for example, about 2000 nm.
  • the element insulating layer 58 has a front surface 58s and a rear surface 58r.
  • the front surface 58 s faces the same side as the substrate front surface 57 s of the substrate 57
  • the rear surface 58 r faces the same side as the substrate rear surface 57 r of the substrate 57 .
  • the surface 58s of the element insulating layer 58 is the surface of the uppermost insulating film 58M among the plurality of insulating films 58M stacked in the z direction.
  • the rear surface 58r of the element insulating layer 58 is the rear surface of the lowermost insulating film 58M among the plurality of insulating films 58M stacked in the z direction.
  • a rear surface 58 r of the element insulating layer 58 faces a substrate surface 57 s of the substrate 57 . More specifically, the back surface 58 r of the element insulating layer 58 is in contact with the substrate surface 57 s of the substrate 57 .
  • the surface 58s of the element insulating layer 58 is provided with first surface-side electrode plates 53A and 53B and second surface-side electrode plates 55A and 55B.
  • first front-side electrode plates 53A and 53B and the second front-side electrode plates 55A and 55B are provided on the element insulating layer 58 respectively.
  • the insulating chip 50 has a surface protective layer 59 formed on the surface 58s of the element insulating layer 58 .
  • the surface protective layer 59 is a protective layer that constitutes the chip surface 50 s of the insulating chip 50 and protects the element insulating layer 58 .
  • the surface protective layer 59 has a protective film 59A and a passivation film 59B formed on the protective film 59A.
  • Protective film 59A is made of a material containing SiO 2 , for example.
  • Passivation film 59B is made of a material containing, for example, SiN.
  • the passivation film 59B constitutes the chip surface 50s of the insulating chip 50. As shown in FIG.
  • the surface protective layer 59 covers the surface 58s of the element insulating layer 58 and the second surface-side electrode plates 55A and 55B.
  • the surface protective layer 59 covers the first surface-side electrode plate 53A while exposing a portion of the surface of the first surface-side electrode plate 53A.
  • the electrode pad portions 55AA and 55BA are exposed without being covered with the surface protection layer 59.
  • the connection portions 55AB and 55BB are covered with a surface protection layer 59.
  • the first front-side electrode plates 53A, 53B and the second front-side electrode plates 55A, 55B are covered with a protective film 59A and a passivation film 59B.
  • both the protective film 59A and the passivation film 59B are provided with four openings that expose parts of the surfaces of the first front-side electrode plates 53A and 53B and the electrode pad portions 55AA and 55BA.
  • the four openings are a first opening exposing the central region of the first surface-side electrode plate 53A, a second opening exposing the central region of the first surface-side electrode plate 53B, and exposing the electrode pad portion 55AA. and a fourth opening exposing the electrode pad portion 55BA. Therefore, exposed surfaces for connecting the wires W are formed on the first surface side electrode plates 53A, 53B and the electrode pad portions 55AA, 55BA through the respective openings.
  • the exposed surfaces of the first surface-side electrode plates 53A and 53B constitute first electrode pads 51A and 51B, and the electrode pad portions 55AA and 55BA constitute second electrode pads 52A and 52B.
  • regions other than the central regions of the first front-side electrode plates 53A and 53B are covered with a protective film 59A and a passivation film 59B.
  • the second surface-side electrode plates 55A, 55B and the connection portions 55AB, 55BB are covered with a protective film 59A and a passivation film 59B.
  • the first rear electrode plates 54A, 54B and the second rear electrode plates 56A, 56B are provided within the element insulating layer 58, respectively.
  • the first backside electrode plate 54A is embedded in the element insulating layer 58.
  • the first rear electrode plate 54A is provided so as to penetrate the one-layer insulating film 58M in the z-direction.
  • a conductive member made of a material containing Al, for example, is embedded in the opening to form the first back side electrode plate 54A.
  • One or more insulating films 58M are interposed between the first front-side electrode plate 53A and the first back-side electrode plate 54A in the z-direction. That is, the element insulating layer 58 has a portion (inter-electrode insulating film) sandwiched between the first front-side electrode plate 53A and the first back-side electrode plate 54A in the z direction. In other words, the first front-side electrode plate 53A and the first back-side electrode plate 54A are opposed to each other with the element insulating layer 58 (inter-electrode insulating film) interposed therebetween.
  • the first backside electrode plate 54A is insulated from the substrate 57 by the element insulating layer 58 .
  • the element insulating layer 58 is also provided between the first rear electrode plate 54A and the substrate 57 .
  • the distance D1 between the first front electrode plate 53A and the first rear electrode plate 54A in the z direction is the distance D2 between the first rear electrode plate 54A and the rear surface 58r of the element insulating layer 58 in the z direction. bigger than As a result, the distance D1 can be increased while suppressing the thickness TA of the element insulating layer 58 from increasing.
  • the second back side electrode plate 56A is embedded in the element insulating layer 58.
  • the second backside electrode plate 56A is also formed by embedding a conductive member in an opening of a single-layer insulating film 58M, like the first backside electrode plate 54A.
  • the first rear electrode plate 54A, the second rear electrode plate 56A, and the connection wiring 56AB are integrally formed.
  • one insulating film 58M of the element insulating layers 58 is provided with openings corresponding to the first rear-side electrode plate 54A, the second rear-side electrode plate 56A, and the connection wiring 56AB. .
  • a conductive member (Al) By embedding a conductive member (Al) in this opening, the first rear electrode plate 54A, the second rear electrode plate 56A, and the connection wiring 56AB are integrally formed.
  • One or more insulating films 58M are interposed between the second front electrode plate 55A and the second back electrode plate 56A in the z direction. That is, the element insulating layer 58 has a portion (interelectrode insulating film) sandwiched between the second front electrode plate 55A and the second rear electrode plate 56A in the z direction. In other words, the second front-side electrode plate 55A and the second back-side electrode plate 56A are arranged to face each other with the element insulating layer 58 (inter-electrode insulating film) interposed therebetween.
  • the second backside electrode plate 56A is insulated from the substrate 57 by the element insulating layer 58 .
  • the element insulating layer 58 is also provided between the second backside electrode plate 56A and the substrate 57 .
  • the distance D3 between the second front electrode plate 55A and the second rear electrode plate 56A in the z direction is the distance D4 between the second rear electrode plate 56A and the rear surface 58r of the element insulating layer 58 in the z direction. bigger than As a result, the distance D3 can be increased while suppressing the thickness TA of the element insulating layer 58 from increasing.
  • distance D3 is equal to distance D1 and distance D4 is equal to distance D2.
  • Both D3 can be arbitrarily changed according to the required dielectric strength of the capacitor 15A.
  • the required withstand voltage of the capacitor 15A depends on the distances D1 and D3.
  • the distance between the electrodes corresponding to the required dielectric strength of the capacitor 15A is used as the reference distance.
  • the ratio of the total distance of the distance D1 and the distance D3 to the reference distance is, for example, 1.0 or more and 2.0 or less. This ratio is preferably 1.6, for example.
  • the total distance of the distance D1 and the distance D3 is set larger than the reference distance in consideration of the safety margin. It should be noted that increasing the total distance of the distance D1 and the distance D3 invites a decrease in the capacity of the capacitor 15A. Further, when the total distance of the distance D1 and the distance D3 is increased, the distance to the first front electrode plate 53A, the first rear electrode plate 54A, the second front electrode plate 55A, or the second rear electrode plate 56A is increased. There is concern that the influence of the conductive member outside the insulating chip 50 will increase. If this effect is considered, the chip size of the insulating chip 50 becomes large. Therefore, in order to suppress both a decrease in the capacity of capacitor 15A and an increase in the chip size of insulating chip 50, it is preferable to set the total distance of distance D1 and distance D3 close to the reference distance.
  • the insulating chip 50 is mounted on the secondary die pad 70. As shown in FIG. More specifically, the insulating chip 50 is mounted on the secondary die pad 70 via the insulating substrate 90 . It can be said that the insulating substrate 90 is interposed between the insulating chip 50 and the secondary die pad 70 .
  • the insulating substrate 90 is bonded to the secondary die pad 70 with a third bonding material 103 .
  • the insulating chip 50 is bonded to the insulating substrate 90 with the fourth bonding material 104 .
  • Both the third bonding material 103 and the fourth bonding material 104 are, for example, insulating bonding materials.
  • the insulating substrate 90 corresponds to the "insulating member”.
  • the third bonding material 103 corresponds to the "first insulating bonding material”
  • the fourth bonding material 104 corresponds to the "second insulating bonding material”.
  • the insulating substrate 90 is formed of an insulating substrate containing alumina or an insulating substrate containing glass. Alternatively, the insulating substrate 90 may be made of a resin material.
  • the insulating substrate 90 has a front surface 90s and a rear surface 90r facing opposite sides in the z-direction. The front surface 90s is the surface with which the fourth bonding material 104 is in contact, and the back surface 90r is the surface with which the third bonding material 103 is in contact.
  • the thickness TS of the insulating substrate 90 is thicker than the distance D2 between the first back-side electrode plate 54A and the back surface 58r of the element insulating layer 58.
  • the thickness TS of the insulating substrate 90 can be defined by the distance between the front surface 90s and the rear surface 90r of the insulating substrate 90 in the z direction.
  • the insulating chip 50 is mounted on the secondary die pad 70 via the insulating substrate 90, so that the first back electrode plate 54A (54B) of the capacitor 15A (15B) and the secondary die pad 70 is greater than the distance D1.
  • the distance D5 is equal to or greater than the thickness TA of the element insulating layer 58 .
  • the distance D5 is greater than the thickness TA of the element insulating layer 58.
  • the distance D6 between the second back side electrode plate 56A (56B) of the capacitor 15A (15B) and the secondary side die pad 70 is longer than the distance D3.
  • the distance D6 is equal to the distance D5.
  • Thickness TS of insulating substrate 90 may be, for example, less than distance D2 (D4) or greater than distance D1 (D3).
  • the distances D5 and D6 may be less than the distance D1 (D3) or may be smaller than the thickness TA of the element insulating layer 58 .
  • the distance between the secondary die pad 70 and the substrate 57 of the insulating chip 50 in the z direction is , the distance between the secondary die pad 70 and the second substrate 43 of the second chip 40 in the z direction. Also, the distance between the secondary die pad 70 and the substrate 57 of the insulating chip 50 in the z direction is greater than the distance between the primary die pad 60 and the first substrate 33 of the first chip 30 in the z direction.
  • Method for manufacturing insulating chip and signal transmission device An outline of an example of a method for manufacturing the insulating chip 50 and an example of a method for manufacturing the signal transmission device 10 of this embodiment will be described. Hereinafter, the case of forming a plurality of insulating chips 50 at the same time will be described.
  • the manufacturing method of the insulation chip 50 includes a wafer preparation process, a first insulation layer and capacitor formation process, a second insulation layer formation process, and a singulation process.
  • a semiconductor wafer forming the substrate 57 is prepared.
  • a semiconductor wafer is made of a material containing Si, for example.
  • the semiconductor wafer is large enough to form a plurality of insulating chips 50 .
  • an element insulating layer is formed on the semiconductor wafer. More specifically, the element insulating layer is formed by laminating a plurality of insulating films made of a material containing SiO2 . This insulating film is an insulating film forming the insulating film 58M (see FIG. 5). The element insulating layer is formed, for example, over the entire surface of the semiconductor wafer. This element insulating layer is an insulating layer forming the element insulating layer 58 (see FIG. 5).
  • the insulating film on which the first back electrode plate 54A (54B) and the second back electrode plate 56A (56B) are formed has the first back electrode plate 54A (54B) and the second back electrode plate 54A (54B).
  • An opening corresponding to 56A (56B) is provided.
  • the first rear electrode plate 54A (54B) and the second rear electrode plate 56A (56B) are formed.
  • a material containing Al, for example, is used as the conductive material.
  • the first surface-side electrode plate 53A (53B) and the second surface-side electrode plate 55A (55B) are formed on the surface of the element insulating layer.
  • the first surface-side electrode plate 53A (53B) and the second surface-side electrode plate 55A (55B) are made of a material containing Al, for example.
  • Other conductive materials such as W, Ti, and Cu may be used as materials for forming the electrode plates 53A (53B), 54A (54B), 55A (55B), and 56A (56B).
  • the protective film is an insulating film forming the protective film 59A (see FIG. 5), and is formed over the entire surface of the element insulating layer.
  • the protective film is made of a material containing SiO2 , for example.
  • a passivation film is formed.
  • the passivation film is an oxide film forming the passivation film 59B (see FIG. 5) and is formed over the entire surface of the protective film.
  • the passivation film is made of a material containing SiN, for example.
  • a part including the center of the first surface-side electrode plate 53A (53B) and the openings of the electrode pad portions 55AA (55BA) of the second surface-side electrode plate 55A (55B) are covered with a protective film and a protective film. It is formed on both sides of the passivation film.
  • the portion of the first surface-side electrode plate 53A (53B) exposed from both the protective film and the passivation film forms the first electrode pad 51A (51B), and the electrode pad portion 55AA (55BA) forms the second electrode.
  • a pad 52A (52B) is configured.
  • a mask or the like is used to separate a portion including the center of the first front-side electrode plate 53A (53B) from the electrode pad portion 55AA of the second front-side electrode plate 55A (55B). (55BA) may be formed to expose each of them.
  • the semiconductor wafer on which the element insulating layer is formed is cut into the size of the insulating chip 50 . Thereby, the insulating chip 50 is singulated. Through the above steps, the insulating chip 50 is manufactured.
  • the method of manufacturing the signal transmission device 10 includes a frame preparation process, a chip mounting process, a wire forming process, a resin layer forming process, a separating process, and a terminal forming process.
  • a frame is prepared for forming the primary side lead, the secondary side lead, the primary side die pad 60, and the secondary side die pad 70 (see FIG. 2 for both).
  • the primary side lead, the secondary side lead, the primary side die pad 60 and the secondary side die pad 70 are formed by pressing or etching a single plate frame made of a material containing Cu.
  • the primary side lead, the secondary side lead, the primary side die pad 60, and the secondary side die pad 70 are each connected to the frame.
  • the first chip 30 is mounted on the primary die pad 60 by die bonding, and both the second chip 40 and the insulating chip 50 are mounted on the secondary die pad 70 .
  • the first bonding material 101 is applied to the portion of the primary die pad 60 where the first chip 30 is to be mounted, and the portion of the secondary die pad 70 to be mounted with the second chip 40 is coated with the first bonding material 101 .
  • a second bonding material 102 is applied.
  • the first bonding material 101 and the second bonding material 102 are conductive bonding materials.
  • the first chip 30 is placed on the first bonding material 101 and the second chip 40 is placed on the second bonding material 102 .
  • the first bonding material 101 and the second bonding material 102 are solidified. For example, when solder paste is used for both bonding materials 101 and 102, both bonding materials 101 and 102 are solidified by cooling both bonding materials 101 and 102, respectively.
  • the third bonding material 103 is applied to the portion of the secondary die pad 70 where the insulating chip 50 is to be mounted.
  • the third bonding material 103 is an insulating bonding material.
  • the insulating substrate 90 is placed on the third bonding material 103 .
  • the fourth bonding material 104 is applied onto the insulating substrate 90 .
  • the fourth bonding material 104 is an insulating bonding material.
  • the insulating chip 50 is placed on the fourth bonding material 104 .
  • both bonding materials 103 and 104 are solidified.
  • both bonding materials 103 and 104 are made of a material containing epoxy resin
  • both bonding materials 103 and 104 are solidified by mixing the epoxy resin with a curing agent.
  • wires W connecting the chips 30, 40 and 50, a plurality of wires W connecting the first chip 30 and the primary leads, and the second chip 40 and the secondary leads are formed.
  • a plurality of connecting wires W are formed. These wires W are formed, for example, by a wire bonding apparatus.
  • a resin layer is formed to seal the chips 30, 40, 50, the wires W, and the die pads 60, 70.
  • the resin layer is a layer that constitutes the sealing resin 80, and is made of, for example, a black epoxy resin.
  • the resin layer is formed by transfer molding or compression molding, for example.
  • part of the primary lead and part of the secondary lead each protrude from the resin layer.
  • the resin layer is cut and the primary lead, secondary lead, primary die pad 60, and secondary die pad 70 are separated from the frame.
  • a dicing blade is used to cut both the resin layer and the frame.
  • the primary side lead and the secondary side lead are cut from the frame so as to have a portion protruding from the resin layer.
  • both the primary side lead and the secondary side lead protruding from the resin layer are bent into a predetermined shape by bending. Through the above steps, the signal transmission device 10 is manufactured.
  • FIG. 7 schematically shows a part of the planar structure of the insulating tip 50X of the comparative example
  • FIG. 8 schematically shows the cross-sectional structure of the insulating tip 50X of the comparative example.
  • FIG. 8 schematically shows cross-sectional structures of the first capacitor 21AX and the second capacitor 22AX.
  • the insulating chip 50X of the comparative example differs from the insulating chip 50 of the present embodiment only in the capacitor structure, so common components are denoted by the same reference numerals and descriptions thereof are omitted.
  • the insulation chip 50X has a package structure in which the first capacitor 21AX and the second capacitor 22AX are integrated into one chip.
  • the first capacitor 21AX has a first front-side electrode plate 53AX and a first back-side electrode plate 54AX
  • the second capacitor 22AX has a second front-side electrode plate 55AX and a second back-side electrode plate 55AX. 56AX.
  • the first front-side electrode plate 53AX and the first back-side electrode plate 54AX are arranged to face each other in the z-direction, and the second front-side electrode plate 55AX and the second back-side electrode plate 56AX are arranged to face each other in the z-direction.
  • the first front electrode plate 53AX and the second front electrode plate 55AX are arranged apart from each other in the x direction, and the first rear electrode plate 54AX and the second rear electrode plate 56AX are arranged apart from each other in the x direction. spaced apart.
  • the first rear electrode plate 54AX and the second rear electrode plate 56AX are electrically connected within the element insulating layer 58 .
  • each electrode plate 53AX, 54AX, 55AX, 56AX viewed from the z direction is rectangular. Therefore, electric field concentration is likely to occur at the corner portions of the electrode plates 53AX, 54AX, 55AX, and 56AX. Due to electric field concentration at the corner portions of the electrode plates 53AX, 54AX, 55AX, and 56AX, the withstand voltage of the capacitors 21AX and 22AX may be lowered.
  • the first front-side electrode plate 53A (53B) and the first back-side electrode plate 54A (54B) are circular when viewed from the z direction.
  • the second front electrode plate 55A (55B) and the second back electrode plate 56A (56B) are larger in diameter than the first front electrode plate 53A (53B) and the first back electrode plate 54A (54B). It is circular with an inner diameter.
  • a second front-side electrode plate 55A is formed so as to surround the first front-side electrode plate 53A and is provided so as to be concentric with the first front-side electrode plate 53A. It is formed so as to surround the back side electrode plate 54A and is provided so as to be concentric with the first back side electrode plate 54A.
  • the electrode plates 53A (53B), 54A (54B), 55A (55B), and 56A (56B) do not have corner portions that cause electric field concentration when viewed from the z direction.
  • the distance G1 between the first front-side electrode plate 53A (53B) and the second front-side electrode plate 55A (55B) becomes constant, and the first back-side electrode plate 54A (54B) and the second back-side electrode Since the distance G2 between the plates 56A (56B) is constant, electric field concentration is less likely to occur. Therefore, a decrease in dielectric strength of the insulating chip 50 can be suppressed.
  • the insulating chip 50 includes an element insulating layer 58 having a front surface 58s and a back surface 58r, and a first capacitor 21A (21B) and a second capacitor 22A (22B) formed on the element insulating layer 58. .
  • the first capacitor 21A (21B) has a first front-side electrode plate 53A (53B) and a first back-side electrode plate 54A (54B) that are opposed to each other in the z direction, which is the thickness direction of the element insulating layer 58. ing.
  • the second capacitor 22A (22B) includes a second front-side electrode plate 55A (55B) formed so as to surround the first front-side electrode plate 53A (53B) when viewed in the z-direction, and a first front-side electrode plate 55A (55B) when viewed in the z-direction. and a second back electrode plate 56A (56B) formed to surround the back electrode plate 54A (54B).
  • the second front side electrode plate 55A (55B) and the second back side electrode plate 56A (56B) face each other in the z direction.
  • the first backside electrode plate 54A (54B) and the second backside electrode plate 56A (56B) are electrically connected.
  • the withstand voltage of the insulating chip is improved by increasing the distance between the front-side electrode plate and the back-side electrode plate in the z direction.
  • the thickness of the element insulating layer also increases. If the thickness of the element insulating layer is increased, warpage of the semiconductor wafer increases during the manufacturing process of the insulating chip, making it difficult to manufacture the insulating chip.
  • the first capacitor 21A (21B) and the second capacitor 22A (22B) are connected in series, and the second capacitor 22A (22B) is connected to the first capacitor 21A (21B). It is arranged in the direction perpendicular to the direction. Therefore, it is possible to improve the withstand voltage of the insulating chip 50 without increasing the thickness TA of the element insulating layer 58 . Therefore, it is possible to improve the dielectric strength of the insulating chip 50 and to easily manufacture the insulating chip 50 .
  • the second front electrode plate 55A (55B) is formed so as to surround the first front electrode plate 53A (53B) when viewed from the z direction
  • the second rear electrode plate 56A (56B) is formed when viewed from the z direction.
  • the front side electrode plates 53A (53B) and 55A ( 55B) and the rear electrode plates 54A (54B) and 56A (56B) in the x direction can be reduced. Therefore, it is possible to reduce the size of the insulating chip 50 in the x direction.
  • the shape of the first surface-side electrode plate 53A (53B) viewed from the z-direction is circular.
  • the second front-side electrode plate 55A (55B) has an annular shape with an inner diameter larger than the diameter of the first front-side electrode plate 53A (53B).
  • the first surface-side electrode plate 53A (53B) and the second surface-side electrode plate 55A (55B) are arranged concentrically.
  • the shape of the first back side electrode plate 54A (54B) when viewed in the z direction is circular.
  • the second backside electrode plate 56A (56B) has an annular shape with an inner diameter larger than the diameter of the first backside electrode plate 54A (54B).
  • the first rear electrode plate 54A (54B) and the second rear electrode plate 56A (56B) are arranged concentrically.
  • the distance G1 between the first surface-side electrode plate 53A (53B) and the second surface-side electrode plate 55A (55B) is constant in the circumferential direction of the first surface-side electrode plate 53A (53B).
  • the distance G2 between the first back electrode plate 54A (54B) and the second back electrode plate 56A (56B) is constant in the circumferential direction of the first back electrode plate 54A (54B).
  • the shortest distance G1 between the first front electrode plate 53A (53B) and the second front electrode plate 55A (55B) is the distance between the first front electrode plate 53A (53B) and the first rear electrode. It is the shortest distance to the plate 54A (54B) and is greater than or equal to the distance D1.
  • the withstand voltage between the first front electrode plate 53A (53B) and the second front electrode plate 55A (55B) is equal to that of the first front electrode plate 53A (53B) and the first rear electrode. Since it is equal to or higher than the dielectric strength voltage between the plate 54A (54B), a decrease in the dielectric strength voltage of the insulating chip 50 can be suppressed.
  • the insulating chip 50 has a surface protective layer 59 that covers the surface 58s of the element insulating layer 58, the first surface-side electrode plate 53A (53B), and the second surface-side electrode plate 55A (55B).
  • the surface protective layer 59 exposes a portion of the first surface-side electrode plate 53A (53B).
  • the exposed surface of the first surface-side electrode plate 53A (53B) exposed from the surface protective layer 59 can be formed as the first electrode pad 51A (51B).
  • one or more insulating films 58M need to be interposed between the first surface-side electrode plate 53A and the electrode pad. There is As a result, the thickness TA of the device insulating layer 58 is increased.
  • the first surface-side electrode plate 53A (53B) also serves as an electrode pad, it is possible to prevent the thickness TA of the element insulating layer 58 from increasing. Further, for example, in the case of a configuration in which an electrode pad is formed at a position separated from the first surface-side electrode plate 53A (53B) in the direction orthogonal to the z-direction, the first surface-side electrode plate 53A (53B) and the electrode pad Since a conductive path is formed between , an inductance is generated due to the conductive path. In this regard, in the present embodiment, since the conductive path is not formed, it is possible to avoid the occurrence of inductance due to the conductive path.
  • the signal transmission device 10 is configured to receive signals from the primary circuit 13 via the first chip 30 including the primary circuit 13, the insulating chip 50, and the insulating chip 50. and a second chip 40 including the secondary circuit 14 .
  • the insulating chip 50 includes an element insulating layer 58 having a front surface 58s and a back surface 58r, and a first capacitor 21A (21B) and a second capacitor 22A (22B) formed on the element insulating layer 58.
  • the first capacitor 21A (21B) has a first front-side electrode plate 53A (53B) and a first back-side electrode plate 54A (54B) that are opposed to each other in the z direction, which is the thickness direction of the element insulating layer 58. ing.
  • the second capacitor 22A (22B) includes a second front-side electrode plate 55A (55B) formed so as to surround the first front-side electrode plate 53A (53B) when viewed in the z-direction, and a first front-side electrode plate 55A (55B) when viewed in the z-direction. and a second back electrode plate 56A (56B) formed to surround the back electrode plate 54A (54B).
  • the second front side electrode plate 55A (55B) and the second back side electrode plate 56A (56B) face each other in the z direction.
  • the first backside electrode plate 54A (54B) and the second backside electrode plate 56A (56B) are electrically connected.
  • the same effect as the effect (1) above can be obtained.
  • the dielectric strength of the insulating chip 50 can be improved, the dielectric strength of the signal transmission device 10 can be improved.
  • An insulating substrate 90 is interposed between the insulating chip 50 and the secondary die pad 70 .
  • the distances D5 and D6 between the first rear electrode plate 54A (54B) and the second rear electrode plate 56A (56B) and the secondary die pad 70 in the z direction can be increased. . Therefore, it is possible to improve the withstand voltage between the first back side electrode plate 54A (54B) and the second back side electrode plate 56A (56B) and the secondary side die pad .
  • the insulating substrate 90 is bonded to the secondary die pad 70 with the third bonding material 103 .
  • An insulating bonding material is used for the third bonding material 103 . According to this configuration, the dielectric breakdown voltage between the first capacitor 21A (21B) and the second capacitor 22A (22B) and the secondary die pad 70 can be improved.
  • the insulating substrate 90 is formed of an insulating substrate containing alumina or an insulating substrate containing glass. According to this configuration, the insulating substrate 90 having a large thickness can be easily formed as compared with the case where the insulating substrate 90 is made of an insulating film.
  • substrate 57 can be changed arbitrarily.
  • an SOI substrate may be used as the substrate 57 .
  • One of the protective film 59A and the passivation film 59B may be omitted from the surface protective layer 59 .
  • the surface protective layer 59 may be omitted.
  • each front side electrode plate 53A, 53B, 55A, 55B and each thickness of each back side electrode plate 54A, 54B, 56A, 56B can be changed arbitrarily. In one example, the thickness of each of the front electrode plates 53A, 53B, 55A, 55B may be thicker than the thickness of each of the back electrode plates 54A, 54B, 56A, 56B.
  • the second surface-side electrode plates 55A, 55B and the second electrode pads 52A, 52B may be formed separately.
  • the insulating chip 50 may have second electrode pads 52A and 52B electrically connected to the second front electrode plates 55A and 55B.
  • the second electrode pads 52A and 52B are formed at positions separated from the second surface-side electrode plates 55A and 55B when viewed in the z direction.
  • the surface protection layer 59 exposes the surfaces of the second electrode pads 52A and 52B.
  • the second surface-side electrode plates 55A, 55B and the second electrode pads 52A, 52B may be connected by wires, for example. Further, in this case, the second electrode pads 52A, 52B may be made of a material different from that of the second front-side electrode plates 55A, 55B.
  • both the first surface-side electrode plates 53A, 53B and the second surface-side electrode plates 55A, 55B are formed on the surface 58s of the element insulating layer 58, but this is not the only option.
  • the first surface-side electrode plates 53A and 53B may be embedded in the element insulating layer 58.
  • first electrode pads 51A and 51B are provided separately from the first front-side electrode plates 53A and 53B on the surface 58s of the element insulating layer 58 above the first front-side electrode plates 53A and 53B. there is The first surface-side electrode plate 53A and the first electrode pads 51A are connected by connection vias.
  • the first surface-side electrode plate 53B and the first electrode pads 51B are connected by connection vias.
  • the second front-side electrode plates 55A and 55B may be embedded in the element insulating layer 58 .
  • second electrode pads 52A and 52B are provided separately from the second front electrode plates 55A and 55B on the surface 58s of the element insulating layer 58 above the second front electrode plates 55A and 55B.
  • the second surface-side electrode plate 55A and the second electrode pads 52A are connected by connection vias.
  • the second surface-side electrode plate 55B and the second electrode pads 52B are connected by connection vias.
  • the first electrode pads 51A, 51B and the second electrode pads 52A, 52B are made of a material containing Al like the first front electrode plates 53A, 53B and the second front electrode plates 55A, 55B.
  • the materials forming the first electrode pads 51A, 51B and the second electrode pads 52A, 52B can be changed arbitrarily.
  • the first electrode pads 51A, 51B may be made of a material different from that of the first surface-side electrode plates 53A, 53B.
  • the second electrode pads 52A, 52B may be made of a material different from that of the second surface-side electrode plates 55A, 55B.
  • the area of the first front electrode plate 53A and the area of the second front electrode plate 55A are equal to each other, and the area of the first rear electrode plate 54A and the area of the second rear electrode plate 56A are equal to each other. were equal to each other, but are not limited to this.
  • the area of the first front-side electrode plate 53A may be larger than the area of the second front-side electrode plate 55A, and the area of the first back-side electrode plate 54A may be larger than the area of the second back-side electrode plate 56A. That is, the capacity of the first capacitor 21A may be larger than the capacity of the second capacitor 22A.
  • the area of the second front electrode plate 55A may be larger than the area of the first front electrode plate 53A, and the area of the second rear electrode plate 56A may be larger than the area of the first rear electrode plate 54A. . That is, the capacity of the second capacitor 22A may be larger than the capacity of the first capacitor 21A.
  • the first front-side electrode plate 53B, the first back-side electrode plate 54B, the second front-side electrode plate 55B, and the second back-side electrode plate 56B may also be changed in the same manner.
  • the insulating chip 50 may be mounted on the primary die pad 60 instead of the secondary die pad 70 .
  • both the first chip 30 and the insulating chip 50 are mounted on the primary die pad 60 .
  • the mounting structure of the insulating chip 50 to the primary side die pad 60 is the same as the mounting structure of the insulating chip 50 to the secondary side die pad 70 of the above embodiment.
  • the insulating chip 50 may be mounted on an intermediate die pad 110 different from the primary die pad 60 and the secondary die pad 70 .
  • Intermediate die pad 110 is electrically floating with respect to primary die pad 60 and secondary die pad 70 .
  • the insulating chip 50 is mounted on the mounting frame (intermediate die pad 110) in an electrically floating state.
  • the intermediate die pad 110 corresponds to the "mounting frame” and the "third mounting frame”.
  • the intermediate die pad 110 may be formed simultaneously with the die pads 60 and 70 from the same material as the die pads 60 and 70, for example. Note that the material forming the intermediate die pad 110 can be arbitrarily changed, and may be formed of a material different from that of the die pads 60 and 70, for example. In one example, the intermediate die pad 110 may be made of an insulating material such as ceramics such as alumina or glass. Also, the intermediate die pad 110 may be made of a resin material.
  • the insulating substrate 90 is bonded to the intermediate die pad 110 by the third bonding material 103.
  • the insulating chip 50 is bonded to the insulating substrate 90 with the fourth bonding material 104 .
  • the third bonding material 103 and the fourth bonding material 104 may be conductive bonding materials.
  • a semiconductor substrate may be used instead of the insulating substrate 90 interposed between the intermediate die pad 110 and the insulating chip 50 .
  • the insulating substrate 90 may be omitted. That is, the insulating chip 50 may be bonded to the intermediate die pad 110 with the third bonding material 103 .
  • the third bonding material 103 may be a conductive bonding material or an insulating bonding material.
  • the shape of the second surface side electrode plates 55A and 55B of the capacitors 15A and 15B as viewed from the z direction can be arbitrarily changed.
  • the shape of the second front electrode plates 55A and 55B viewed from the z-direction may be an open annular shape with openings 55AD and 55BD.
  • the openings 55AD and 55BD are formed on the side opposite to the second electrode pads 52A and 52B with respect to the first electrode pads 51A and 51B.
  • the side opposite to the second electrode pads 52A and 52B with respect to the first electrode pads 51A and 51B means that the electrode passes through both the first electrode pads 51A (51B) and the second electrode pads 52A (52B).
  • the second electrode pad 52A (52B) is opposite to the first electrode pad 51A (51B).
  • the openings 55AD and 55BD of the second front electrode plates 55A and 55B are closer to the first chip 30 than the first electrode pads 51A and 51B of the second front electrode plates 55A and 55B. 2) It is formed in a near portion.
  • the first electrode pads 51A, 51B are opposite to the second electrode pads 52A, 52B. pulled out to the side. Since the openings 55AD and 55BD are formed on the side opposite to the second electrode pads 52A and 52B with respect to the first electrode pads 51A and 51B, the openings 55AD and 55BD are the first electrode pads 55AD and 55BD when viewed from the z direction. It can be said that they are provided at positions overlapping the wires W connected to the electrode pads 51A and 51B. In other words, the second surface side electrode plates 55A and 55B are provided at positions different from the wires W connected to the first electrode pads 51A and 51B when viewed in the z direction.
  • the tip portions 55AE and 55BE that define the openings 55AD and 55BD in the second front electrode plates 55A and 55B have convex curved surfaces when viewed from the z direction.
  • the wire W connected to the first surface-side electrode plate 53A (53B) is not arranged at a position overlapping the second surface-side electrode plate 55A (55B) when viewed from the z direction, It is possible to reduce the risk of short-circuiting between the wire W having a large potential difference and the second front electrode plate 55A (55B).
  • the tip portion 55AE (55BE) of the second front-side electrode plate 55A (55B) has a curved surface, it is possible to suppress the occurrence of electric field concentration at the tip portion 55AE (55BE).
  • the shape of the tip portions 55AE and 55BE of the second surface-side electrode plates 55A and 55B can be arbitrarily changed.
  • the tip surfaces of the tip portions 55AE and 55BE may be flat surfaces.
  • the shape of the second back side electrode plates 56A and 56B as viewed in the z direction may be formed into an open annular shape to match the shape of the second front side electrode plates 55A and 55B.
  • the shape of the first front-side electrode plates 53A, 53B and the first back-side electrode plates 54A, 54B of the capacitors 15A, 15B as viewed in the z-direction is not limited to a circle, and can be arbitrarily changed.
  • the shape of the second front electrode plates 55A, 55B and the second back electrode plates 56A, 56B of the capacitors 15A, 15B as viewed in the z-direction is not limited to an annular shape, and can be arbitrarily changed.
  • the shape of the first surface-side electrode plates 53A and 53B viewed from the z direction may be rectangular.
  • the four corner portions of the first front electrode plates 53A and 53B are chamfered and curved.
  • the shape of the second surface-side electrode plates 55A and 55B as viewed from the z-direction may be a rectangular frame shape.
  • the four corner portions of the second front electrode plates 55A and 55B are chamfered and curved.
  • the shape of the first surface-side electrode plates 53A and 53B viewed from the z-direction may be a polygon of pentagon or more.
  • the shape of the first back side electrode plates 54A and 54B as viewed in the z direction may be a polygon of pentagon or more.
  • the shape of the second front-side electrode plates 55A and 55B as viewed in the z-direction may be a frame shape that is a polygon of pentagons or more.
  • the shape of the second backside electrode plates 56A and 56B when viewed in the z direction may be a frame shape that is a polygon with pentagons or more.
  • the shape of the first surface-side electrode plates 53A and 53B viewed from the z direction may be circular.
  • the shape of the first back side electrode plates 54A and 54B viewed from the z direction is circular.
  • the shape of the second surface-side electrode plates 55A and 55B viewed from the z-direction may be a closed annular shape.
  • the shape of the second backside electrode plates 56A and 56B as viewed in the z direction is a closed annular shape.
  • the shape of the second surface side electrode plates 55A and 55B as viewed in the z direction may be an open annular shape with an opening 55AD.
  • capacitors 15A and 15B have a double insulation structure in which the first capacitors 21A and 21B and the second capacitors 22A and 22B are connected in series
  • the structure is not limited to this.
  • capacitor 15A may have a structure in which first capacitor 21A, second capacitor 22A, and third capacitor 140 are connected in series.
  • the configuration of the first capacitor 21A is the same as in the above embodiment.
  • the configuration of the second capacitor 22A differs from that of the above-described embodiment in the configuration of the second front electrode plate 55A.
  • the second surface-side electrode plate 55A does not have the electrode pad portion 55AA and the connection portion 55AB of the above embodiment. Therefore, as shown in FIG. 12, the shape of the second surface side electrode plate 55A viewed from the z direction is a closed ring.
  • the third capacitor 140 has a third front-side electrode plate 141 and a third back-side electrode plate 142 .
  • the third front electrode plate 141 and the third rear electrode plate 142 are made of the same material as the electrode plates 53A, 54A, 55A and 56A, for example.
  • the third surface-side electrode plate 141 has an inner diameter larger than the diameter of the second surface-side electrode plate 55A.
  • the shape of the third surface-side electrode plate 141 viewed from the z-direction is a closed ring.
  • the third front electrode plate 141 When viewed from the z-direction, the third front electrode plate 141 is formed so as to surround the second front electrode plate 55A.
  • the third front electrode plate 141 is provided so that its center coincides with the center of the first front electrode plate 53A.
  • the third front electrode plate 141 is arranged concentrically with the first front electrode plate 53A. That is, the third front-side electrode plate 141 is formed concentrically with both the first front-side electrode plate 53A and the second front-side electrode plate 55A.
  • the third front electrode plate 141 is provided at a position aligned with both the first front electrode plate 53A and the second front electrode plate 55A in the z-direction.
  • the area of the third front electrode plate 141 viewed from the z direction may be larger than the area of the second front electrode plate 55A viewed from the z direction.
  • the area of the third front electrode plate 141 viewed from the z-direction can be arbitrarily changed.
  • the area of the third front electrode plate 141 viewed in the z direction may be smaller than the area of the second front electrode plate 55A viewed in the z direction.
  • the area of the third front electrode plate 141 viewed from the z direction may be equal to the area of the second front electrode plate 55A viewed from the z direction.
  • the difference between the area of the third front electrode plate 141 viewed from the z direction and the second front electrode plate 55A viewed from the z direction is 10% of the second front electrode plate 55A viewed from the z direction.
  • the area of the third front electrode plate 141 viewed from the z direction is equal to the area of the second front electrode plate 55A viewed from the z direction.
  • the third surface-side electrode plate 141 is electrically connected to the second surface-side electrode plate 55A by a connection wiring 143.
  • the connection wiring 143 is provided on the opposite side of the second front electrode plate 55A to the second electrode pad 52A.
  • the connection wiring 143 can be arbitrarily changed in the circumferential direction of the second surface side electrode plate 55A.
  • the third backside electrode plate 142 has an inner diameter larger than the diameter of the second backside electrode plate 56A.
  • the shape of the third backside electrode plate 142 as viewed in the z-direction is a closed ring.
  • the third backside electrode plate 142 When viewed from the z-direction, the third backside electrode plate 142 is formed so as to surround the second backside electrode plate 56A.
  • the third backside electrode plate 142 is provided so that its center coincides with the center of the first backside electrode plate 54A.
  • the third backside electrode plate 142 is arranged so as to be concentric with the first backside electrode plate 54A. That is, the third back electrode plate 142 is formed concentrically with both the first back electrode plate 54A and the second back electrode plate 56A.
  • the third back electrode plate 142 is provided at a position aligned with both the first back electrode plate 54A and the second back electrode plate 56A in the z-direction.
  • the area of the third backside electrode plate 142 viewed from the z direction may be larger than the area of the second backside electrode plate 56A viewed from the z direction.
  • the area of the third back electrode plate 142 viewed from the z-direction can be arbitrarily changed.
  • the area of the third back electrode plate 142 viewed in the z direction may be smaller than the area of the second back electrode plate 56A viewed in the z direction.
  • the area of the third backside electrode plate 142 viewed from the z direction may be equal to the area of the second backside electrode plate 56A viewed from the z direction.
  • the difference between the area of the third back electrode plate 142 seen in the z direction and the second back electrode plate 56A seen in the z direction is 10% of the second back electrode plate 56A seen in the z direction, for example.
  • the area of the third back electrode plate 142 viewed from the z direction is equal to the area of the second back electrode plate 56A viewed from the z direction.
  • the area of the third back side electrode plate 142 is equal to the area of the third front side electrode plate 141 .
  • the difference between the area of the third back electrode plate 142 and the area of the third front electrode plate 141 is, for example, within 10% of the area of the third front electrode plate 141, the third back electrode plate It can be said that the area of 142 is equal to the area of the third front electrode plate 141 .
  • the third back side electrode plate 142 is electrically connected to the second electrode pad 52A by a connection wiring 144.
  • the connection wiring 144 has a wiring portion 144A connected to the third back side electrode plate 142 and a connection via 144B connecting the wiring portion 144A and the second electrode pad 52A.
  • the wiring portion 144A is connected to the third back side electrode plate 142 .
  • the wiring portion 144A extends from the third back side electrode plate 142 to a position where the second electrode pad 52A is formed when viewed in the z direction.
  • the wiring portion 144A is formed integrally with the third back side electrode plate 142 .
  • connection via 144B is provided in the element insulating layer 58 (see FIG. 5) so as to connect the second electrode pad 52A and the wiring portion 144A.
  • a third capacitor 140 electrically connected to the second electrode pad 52A is electrically connected to the secondary circuit 14 (see FIG. 1).
  • the dielectric breakdown voltage of the insulation chip 50 can be improved as compared with the insulation structure by two capacitors connected in series with each other. can be planned.
  • the dielectric strength of the insulating chip 50 is the same, the distance between the front-side electrode plate and the back-side electrode plate in the z direction can be reduced, so the thickness TA of the element insulating layer 58 is reduced. be able to.
  • the structure of the insulating chip 50 near the back surface 50r of the chip may be changed as in the first and second examples shown in FIGS. 14 and 15, for example. 14 and 15, the first electrode pads 51A and 51B, the second electrode pads 52A and 52B, the electrode plates 53A, 53B, 54A, 54B, 55A, 55B, 56A and 56B, the element insulating layer 58, the protective
  • the structures of the film 59A and the passivation film 59B are the same as in the above embodiments. 14 and 15, the insulating substrate 90 and the fourth bonding material 104 (both of which are shown in FIG. 5) are not provided between the insulating chip 50 and the secondary die pad . In other words, the insulating chip 50 is directly bonded to the secondary die pad 70 by the third bonding material 103 .
  • the insulating chip 50 includes a back surface insulating layer 120 provided on the substrate back surface 57r of the substrate 57.
  • the back insulating layer 120 is made of an electrically insulating material.
  • back insulating layer 120 is formed of a layer containing SiO, for example.
  • the back surface insulating layer 120 is formed by applying, for example, a thermosetting organic siloxane polymer solution having Si--O--Si as a main chain to the back surface 57r of the substrate.
  • Back insulating layer 120 may be formed of a layer containing resin, for example. Examples of resins are epoxy resins, phenolic resins, and polyimide resins.
  • the back surface insulating layer 120 is formed over the entire surface of the substrate back surface 57r.
  • the back insulating layer 120 has a front surface 120s and a back surface 120r facing opposite sides in the z-direction.
  • a surface 120s of the back surface insulating layer 120 is in contact with the substrate back surface 57r.
  • the back surface 120 r of the back insulating layer 120 constitutes the chip back surface 50 r of the insulating chip 50 .
  • the insulating chip 50 is bonded to the secondary die pad 70 with the third bonding material 103.
  • the insulating substrate 90 is not interposed between the insulating chip 50 and the secondary die pad 70 .
  • the third bonding material 103 bonds the rear surface 120 r (chip rear surface 50 r ) of the rear insulating layer 120 and the secondary die pad 70 .
  • An insulating bonding material is used for the third bonding material 103 as in the above-described embodiment.
  • the thickness TR of the back insulating layer 120 is thicker than the thickness TB of the insulating film 58M and thinner than the thickness TA of the element insulating layer 58 .
  • the thickness TR of the back insulating layer 120 is thicker than the thickness TC of the protective film 59A and thicker than the thickness TD of the passivation film 59B.
  • the thickness TR of the back insulating layer 120 is thicker than the distance D2 between the first back electrode plate 54A and the back surface 58r of the element insulating layer 58 in the z direction.
  • the thickness TR of the back insulating layer 120 is thicker than the distance D4 between the second back electrode plate 56A and the back surface 58r of the element insulating layer 58 in the z direction.
  • the thickness TR of the back insulating layer 120 is greater than the thickness TE of the third bonding material 103 .
  • the thickness TR of the back insulating layer 120 is 5 ⁇ m or more and 100 ⁇ m or less.
  • the thickness TE of the third bonding material 103 is less than 10 ⁇ m (about several ⁇ m) on the premise that it is thinner than the thickness TR of the back insulating layer 120 .
  • the thickness TR of the back insulating layer 120 can be defined by the distance between the front surface 120s and the back surface 120r of the back insulating layer 120 in the z direction.
  • the thickness TB of the insulating film 58M can be defined by the distance between the front surface and the back surface of the insulating film 58M in the z direction.
  • the insulating film 58M is composed of a first insulating film 58A and a second insulating film 58B, and the thickness TB of the insulating film 58M is the same as the back surface of the first insulating film 58A and the second insulating film 58M.
  • the thickness TC of the protective film 59A can be defined by the distance between the front surface and the rear surface of the protective film 59A in the z direction.
  • the surface of the protective film 59A is the surface in contact with the passivation film 59B, and the back surface of the protective film 59A is the surface in contact with the element insulating layer 58.
  • the thickness TD of the passivation film 59B can be defined by the distance between the front surface and the back surface of the passivation film 59B in the z direction.
  • the surface of the passivation film 59B constitutes the chip surface 50s of the insulating chip 50, and the back surface of the passivation film 59B is the surface in contact with the protective film 59A.
  • the z direction between the secondary die pad 70 and the capacitor 15A is reduced. can be increased. Therefore, it is possible to improve the dielectric strength voltage between the insulating chip 50 and the secondary die pad 70, so that the dielectric strength voltage of the signal transmission device 10 can be improved.
  • the volume of the third bonding material 103 needs to be increased.
  • the third bonding material 103 applied to the secondary die pad 70 wets and spreads, if the thickness TE of the third bonding material 103 is increased, the area of the third bonding material 103 viewed from the z-direction becomes large. As a result, there is a possibility that the secondary side die pad 70 is protruded.
  • the thickness TR of the back insulating layer 120 is set to the thickness TE of the third bonding material 103. can be made thicker easily. Therefore, it becomes easier to increase the distances D5 and D6 between the capacitor 15A and the secondary die pad 70 in the z direction.
  • back insulating layer 120 contains resin, thickness TR of back insulating layer 120 can be easily increased compared to the case where back insulating layer 120 is formed of, for example, an oxide film.
  • the thickness TR of the back insulating layer 120 is determined by the distance D2 between the first back electrode plate 54A and the back surface 58r of the element insulating layer 58 in the z direction and the z distance between the second back electrode plate 56A and the back surface 58r. greater than the distance D4 between the directions. Therefore, the distances D5 and D6 between the capacitor 15A and the secondary die pad 70 in the z direction can be increased without increasing the distances D3 and D4.
  • the thickness TR of the back insulating layer 120 can be arbitrarily changed. In one example, the thickness TR of the back insulating layer 120 may be greater than or equal to the thickness TA of the element insulating layer 58 . Also, the thickness TR of the back insulating layer 120 may be equal to or less than the thickness TE of the third bonding material 103, or may be equal to or less than the distances D2 and D4.
  • the insulating chip 50 includes a back surface insulating layer 130 provided on the substrate back surface 57r of the substrate 57.
  • the back insulating layer 130 has an oxide film 131 and an insulating layer 132 .
  • the back insulating layer 130 has a front surface 130s and a back surface 130r facing opposite sides. The surface 130s is in contact with the substrate rear surface 57r.
  • the rear surface 130r constitutes a chip rear surface 50r of the insulating chip 50. As shown in FIG.
  • the oxide film 131 is provided on the substrate rear surface 57 r of the substrate 57 .
  • Oxide film 131 is made of a material containing SiO 2 , for example.
  • the oxide film 131 is provided over the entire surface of the substrate rear surface 57r.
  • the insulating layer 132 is provided on the side opposite to the substrate 57 with respect to the oxide film 131 .
  • the insulating layer 132 may be formed by coating the oxide film 131 with a thermosetting organic siloxane polymer solution having Si--O--Si as the main chain.
  • the insulating layer 132 is formed of a layer containing SiO.
  • the insulating layer 132 is formed over the entire back surface of the oxide film 131 facing away from the surface in contact with the substrate 57 .
  • the oxide film 131 is interposed between the substrate 57 and the insulating layer 132 in the z-direction. Therefore, oxide film 131 constitutes surface 130 s of back insulating layer 130 .
  • the insulating layer 132 is a layer forming the rear surface 130 r of the rear insulating layer 130 , and can be said to be a layer forming the chip rear surface 50 r of the insulating chip 50 .
  • the insulating layer 132 may be made of a material containing resin. In this case, the insulating layer 132 can also be said to be a resin layer. Insulating layer 132 (resin layer) may be made of a material including, for example, any one of epoxy resin, phenol resin, and polyimide resin.
  • the thickness TRA of the back insulating layer 130 is the total thickness of the thickness TF of the oxide film 131 and the thickness TG of the insulating layer 132 .
  • the thickness TRA of the back insulating layer 130 is greater than the thickness TE of the third bonding material 103 . More specifically, thickness TG of insulating layer 132 is greater than thickness TF of oxide film 131 .
  • the thickness TF of the oxide film 131 is thinner than the thickness TE of the third bonding material 103 .
  • the thickness TG of the insulating layer 132 is equal to the thickness TE of the third bonding material 103 . Therefore, the total thickness of the thickness TF of the oxide film 131 and the thickness TG of the insulating layer 132 (thickness TRA of the back insulating layer 130) is thicker than the thickness TE of the third bonding material 103.
  • the thickness TF of the oxide film 131 is defined by the distance between the surface (surface) of the oxide film 131 in contact with the substrate back surface 57r of the substrate 57 (front surface) and the surface (back surface) in contact with the insulating layer 132 in the z direction. can.
  • the thickness TG of the insulating layer 132 can be defined by the distance between the surface (front surface) of the insulating layer 132 in contact with the oxide film 131 and the surface (back surface) facing in the opposite direction to the z-direction. .
  • the rear surface of the insulating layer 132 constitutes the rear surface 130r of the rear insulating layer 130 (the chip rear surface 50r of the insulating chip 50).
  • the thickness TRA of the back insulating layer 130 is thicker than the thickness TC of the protective film 59A and thicker than the thickness TD of the passivation film 59B.
  • the thickness TRA of the back insulating layer 130 is thicker than the thickness TB of the insulating film 58M and thinner than the thickness TA of the element insulating layer 58 .
  • the thickness TRA of the back insulating layer 130 is thicker than the distance D2 between the first back electrode plate 54A and the back surface 58r of the element insulating layer 58 in the z direction. Also, the thickness TRA of the back insulating layer 130 is thicker than the distance D4 between the second back electrode plate 56A and the back surface 58r of the element insulating layer 58 in the z direction.
  • Thickness TF of oxide film 131 is thinner than distances D2 and D4.
  • the thickness TF of the oxide film 131 may be equal to the thickness TB of the insulating film 58M.
  • the thickness TG of the insulating layer 132 is thicker than the thickness TC of the protective film 59A.
  • the thickness TG of the insulating layer 132 is equal to or greater than the thickness TD of the passivation film 59B.
  • the thickness TF of the oxide film 131 may be equal to or greater than the thickness TC of the protective film 59A. Note that the thickness TF of the oxide film 131 and the thickness TG of the insulating layer 132 can be changed arbitrarily.
  • the secondary side die pad 70 and the capacitor 15A are separated from each other.
  • the distance D5, D6 between the z-directions can be increased. Therefore, it is possible to improve the dielectric strength voltage between the insulating chip 50 and the secondary die pad 70, so that the dielectric strength voltage of the signal transmission device 10 can be improved.
  • the thickness TG of the insulating layer 132 which tends to be thicker than the oxide film 131, is made thicker than the thickness TF of the oxide film 131, the distance D5 between the secondary die pad 70 and the capacitor 15A in the z direction is , D6 can be increased.
  • the back insulating layer 130 including the oxide film 131 and the insulating layer 132 can be easily formed.
  • an insulating substrate 90 may be interposed between the insulating chip 50 and the secondary die pad 70 .
  • the mounting structure of the insulating chip 50 to the secondary die pad 70 via the insulating substrate 90 is the same as in the above embodiment.
  • each insulating film 58M constituting the element insulating layer 58 can be arbitrarily changed.
  • each insulating film 58M has a first insulating film 58A and a second insulating film 58B formed on the first insulating film 58A.
  • each electrode plate 53A, 53B, 54A, 54B, 55A, 55B, 56A, 56B may be made of a material containing Cu.
  • the first insulating film 58A is, for example, an etching stopper film, and is made of a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-added silicon carbide), or the like. Further, the first insulating film 58A has a function of preventing diffusion of Cu, for example. That is, it can be said that the first insulating film 58A is a Cu diffusion prevention film. In addition, the first insulating film 58A has a function of suppressing warpage, for example. More specifically, the first insulating film 58A is configured to warp in a direction opposite to the direction in which the second insulating film 58B warps. In the modification shown in FIGS.
  • the first insulating film 58A is made of a material containing SiN.
  • the second insulating film 58B is an interlayer insulating film, for example, and is an oxide film made of a material containing SiO 2 .
  • the second insulating film 58B is thicker than the first insulating film 58A.
  • the thickness of the first insulating film 58A may be 50 nm or more and 1000 nm or less.
  • the thickness of the second insulating film 58B may be 500 nm or more and 5000 nm or less. In one example, the thickness of the first insulating film 58A is, for example, approximately 300 nm, and the thickness of the second insulating film 58B is, for example, approximately 2000 nm.
  • the insulating chip 50 may have a resin layer composed of one or more layers instead of the plurality of insulating films 58M as the configuration of the element insulating layer 58 .
  • a material containing any one of polyimide resin, phenol resin, and epoxy resin may be used as the resin layer.
  • the insulating chip 50 can be applied to a device other than the signal transmission device 10 of the above embodiment.
  • the insulating chip 50 may be applied to the primary side circuit module.
  • the primary circuit module includes a first chip 30, an insulating chip 50, and a sealing resin that seals these chips 30 and 50.
  • the primary side circuit module also includes a primary side die pad 60 on which both the first chip 30 and the insulating chip 50 are mounted.
  • the first chip 30 is bonded to the primary die pad 60 with the first bonding material 101
  • the insulating chip 50 is bonded to the primary die pad 60 with the third bonding material 103 .
  • the primary side circuit module may have an intermediate die pad provided separately from the primary side die pad 60 .
  • An insulating chip 50 is bonded to the intermediate die pad with a third bonding material 103 .
  • a first chip 30 is bonded to the primary die pad 60 with a first bonding material 101 .
  • the insulating chip 50 may be applied to the secondary circuit module.
  • the secondary circuit module includes a second chip 40, an insulating chip 50, and a sealing resin that seals these chips 40,50.
  • the secondary circuit module also includes a secondary die pad 70 on which both the second chip 40 and the insulating chip 50 are mounted.
  • the second chip 40 is bonded to the secondary die pad 70 with the second bonding material 102
  • the insulating chip 50 is bonded to the secondary die pad 70 with the third bonding material 103 .
  • the secondary circuit module may have an intermediate die pad provided separately from the secondary die pad 70 .
  • An insulating chip 50 is bonded to the intermediate die pad with a third bonding material 103 .
  • a second chip 40 is bonded to the secondary die pad 70 with a second bonding material 102 .
  • the configuration of the signal transmission device 10 can be arbitrarily changed.
  • the signal transmission device 10 may include the primary circuit module and the second chip 40 .
  • the second chip 40 may be mounted on the secondary die pad 70, and both the secondary die pad 70 and the second chip 40 may be configured by a module sealed with sealing resin.
  • the secondary circuit 14 (see FIG. 1) included in the second chip 40 corresponds to the "signal transmission circuit”
  • the second chip 40 corresponds to the "circuit chip”.
  • the signal transmission device 10 corresponds to the "insulation module”.
  • the signal transmission device 10 may include the secondary circuit module and the first chip 30 .
  • the first chip 30 may be mounted on the primary side die pad 60, and both the primary side die pad 60 and the first chip 30 may be configured by a module sealed with a sealing resin.
  • the primary side circuit 13 (see FIG. 1) included in the first chip 30 corresponds to the "signal transmission circuit”
  • the first chip 30 corresponds to the "circuit chip”.
  • the signal transmission device 10 corresponds to the "insulation module”.
  • the signal transmission device 10 may be configured to transmit a signal from the secondary side circuit 14 to the primary side circuit 13 via the capacitor 15 . More specifically, when a signal (e.g., a feedback signal) from a drive circuit electrically connected to secondary circuit 14 via secondary terminal 12 is input to secondary terminal 12, the secondary circuit A signal is transmitted from the circuit 14 to the primary side circuit 13 via the capacitor 15 . A signal of the primary circuit 13 is output to the control device electrically connected to the primary circuit 13 via the primary terminal 11 . Further, the signal transmission device 10 may be configured to transmit signals bidirectionally between the primary side circuit 13 and the secondary side circuit 14 . In short, the signal transmission device 10 includes a primary circuit 13 and a secondary circuit 14 configured to at least one of transmit and receive signals to and from the primary circuit 13 via the capacitor 15. may contain.
  • a signal e.g., a feedback signal
  • a first member is formed on a second member means that in some embodiments the first member may be placed directly on the second member in contact with the second member, but in other implementations the first member may be disposed directly on the second member. It is contemplated that the configuration allows the first member to be positioned over the second member without contacting the second member. That is, the term “on” does not exclude structures in which another member is formed between the first member and the second member.
  • the z-direction used in the present disclosure does not necessarily have to be the vertical direction, nor does it have to match the vertical direction perfectly.
  • the various structures according to this disclosure are not limited to the z-direction "top” and “bottom” described herein being the vertical “top” and “bottom”.
  • the x-direction may be vertical, or the y-direction may be vertical.
  • the first capacitors (21A, 21B) are composed of first surface-side electrode plates (53A, 53B) and first back-side electrode plates (53A, 53B) and a first back-side electrode plate ( 54A, 54B),
  • the second capacitors (22A, 22B) are formed so as to surround the first surface-side electrode plates (53A, 53B) when viewed from the thickness direction (z direction) of the element insulating layer (58).
  • the second surface-side electrode plates (55A, 55B) are annular having an inner diameter larger than the diameter of the first surface-side electrode plates (53A, 53B), The first surface-side electrode plates (53A, 53B) and the second surface-side electrode plates (55A, 55B) are arranged concentrically,
  • the second back electrode plate (56A, 56B) is an annular ring having an inner diameter larger than the diameter of the first back electrode plate (54A, 54B),
  • the insulating chip according to appendix 2 wherein the first back electrode plate (54A, 54B) and the second back electrode plate (56A, 56B) are arranged concentrically.
  • the second surface-side electrode plates (55A, 55B) have an open annular shape with openings (55AD, 55BD) when viewed from the thickness direction (z direction) of the element insulating layer (58). 4.
  • the shortest distance (G1) between the first surface-side electrode plates (53A, 53B) and the second surface-side electrode plates (55A, 55B) is the distance between the first surface-side electrode plates (53A, 53B) and the 10.
  • the surface protective layer (59) covers the first surface-side electrode plates (53A, 53B) with part of the surfaces of the first surface-side electrode plates (53A, 53B) exposed.
  • the insulating tip according to any one of 10.
  • the second capacitors (22A, 22B) have regions (55AA, 55BA) integrally formed with the second surface-side electrode plates (55A, 55B), The regions (55AA, 55BA) are formed at different positions from the second surface-side electrode plates (55A, 55B) when viewed from the thickness direction (z direction) of the element insulating layer (58), 12.
  • the insulating tip according to any one of 1 to 13.
  • the insulating tip (50) comprises: a device insulating layer (58) having a front surface (58s) and a back surface (58r); a first capacitor (21A, 21B) and a second capacitor (22A, 22B) formed in the element insulating layer (58);
  • the first capacitors (21A, 21B) are composed of first surface-side electrode plates (53A, 53B) and first back-side electrode plates (53A, 53B) and a first back-side electrode plate ( 54A, 54B),
  • the second capacitors (22A, 22B) are formed so as to surround the first surface-side electrode plates (53A, 53B) when viewed from the thickness direction (z direction) of the element insulating layer (58).
  • (Appendix 16) a first mounting frame (60) on which the first chip (30) is mounted; a second mounting frame (70) on which the second chip (40) is mounted; 16.
  • FIG. 17 a first mounting frame (60) on which the first chip (30) is mounted; a second mounting frame (70) on which the second chip (40) is mounted; a third mounting frame (110) on which the insulating chip (50) is mounted; 16.
  • said third mounting frame (110) is electrically floating with respect to both said first mounting frame (60) and said second mounting frame (70).
  • the signal transmission device (10) transmits the signal from the first circuit to the second circuit via the first capacitors (21A, 21B) and the second capacitors (22A, 22B).
  • both the first capacitor and the second capacitor include first signal capacitors (21A, 22A) and second signal capacitors (21B, 22B);
  • the signals transmitted through the first capacitors (21A, 21B) and the second capacitors (22A, 22B) include a first signal and a second signal;
  • the first signal is transmitted from the first circuit (13) to the second circuit (14) through the first signal capacitors (21A, 22A);
  • the second signal is transmitted from the first circuit (13) to the second circuit (14) through the second signal capacitors (21B, 22B).
  • the signal transmission device according to .
  • the insulating member (90) is a mounting frame (60) or the second mounting frame (70) on which the insulating chip (50) is mounted by a first insulating bonding material (103). 70), and 17.
  • the substrate (57) has a substrate surface (57s) facing the element insulating layer (58) and a substrate rear surface (57r) opposite to the substrate surface (57s), 15.
  • the back surface insulating layer (130) comprises an oxide film (131) provided on the substrate back surface (57r) and an insulating layer provided on the opposite side of the substrate (57) with respect to the oxide film (131). (132) and the insulating tip of clause 20.
  • Appendix 24 the insulating tip (50) according to any one of Appendices 1 to 14 and 20 to 23; a circuit chip (30/40) including a signal transmission circuit (13/14) electrically connected to said insulating chip (50); an isolation module.
  • first Electrodes 26A, 26B Second electrode 30 First chip 30s Chip surface 30r Chip rear surface 31 First electrode pad 32 Second electrode pad 33 First substrate 34 Wiring layer 40 Second chip 40s Chip Front surface 40r Chip rear surface 41 First electrode pad 42 Second electrode pad 43 Second substrate 44 Wiring layer 50 Insulating chip 50s Insulating chip surface 50r Insulating chip rear surface 51, 51A, 51B First electrode pad 52, 52A, 52B... Second electrode pad 53A, 53B... First surface side electrode plate 54A, 54B... First back side electrode plate 55A, 55B... Second front side electrode plate 55AA, 55BA...

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PCT/JP2022/043766 2021-12-01 2022-11-28 絶縁チップおよび信号伝達装置 Ceased WO2023100808A1 (ja)

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JP2023564963A JPWO2023100808A1 (https=) 2021-12-01 2022-11-28
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JP2002270756A (ja) * 2001-03-08 2002-09-20 Hitachi Ltd 半導体装置及びそれを用いた通信端末装置
US20070296013A1 (en) * 2006-06-26 2007-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure for reducing mismatch effects
JP2016028407A (ja) * 2013-11-13 2016-02-25 ローム株式会社 半導体装置および半導体モジュール
JP2020036171A (ja) * 2018-08-29 2020-03-05 株式会社東芝 アイソレータ及び通信システム

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JP2002229696A (ja) * 2001-02-05 2002-08-16 Hitachi Ltd インタフェース装置及びインターフェースシステム
JP2002270756A (ja) * 2001-03-08 2002-09-20 Hitachi Ltd 半導体装置及びそれを用いた通信端末装置
US20070296013A1 (en) * 2006-06-26 2007-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure for reducing mismatch effects
JP2016028407A (ja) * 2013-11-13 2016-02-25 ローム株式会社 半導体装置および半導体モジュール
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