DE112022005675B4 - Isolationschip und signalübertragungsvorrichtung - Google Patents

Isolationschip und signalübertragungsvorrichtung

Info

Publication number
DE112022005675B4
DE112022005675B4 DE112022005675.4T DE112022005675T DE112022005675B4 DE 112022005675 B4 DE112022005675 B4 DE 112022005675B4 DE 112022005675 T DE112022005675 T DE 112022005675T DE 112022005675 B4 DE112022005675 B4 DE 112022005675B4
Authority
DE
Germany
Prior art keywords
electrode plate
chip
front electrode
insulation layer
rear electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE112022005675.4T
Other languages
German (de)
English (en)
Other versions
DE112022005675T5 (de
Inventor
Bungo Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of DE112022005675T5 publication Critical patent/DE112022005675T5/de
Application granted granted Critical
Publication of DE112022005675B4 publication Critical patent/DE112022005675B4/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
DE112022005675.4T 2021-12-01 2022-11-28 Isolationschip und signalübertragungsvorrichtung Active DE112022005675B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021-195484 2021-12-01
JP2021195484 2021-12-01
PCT/JP2022/043766 WO2023100808A1 (ja) 2021-12-01 2022-11-28 絶縁チップおよび信号伝達装置

Publications (2)

Publication Number Publication Date
DE112022005675T5 DE112022005675T5 (de) 2024-09-19
DE112022005675B4 true DE112022005675B4 (de) 2025-10-30

Family

ID=86612207

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112022005675.4T Active DE112022005675B4 (de) 2021-12-01 2022-11-28 Isolationschip und signalübertragungsvorrichtung

Country Status (5)

Country Link
US (1) US20240313043A1 (https=)
JP (1) JPWO2023100808A1 (https=)
CN (1) CN118339655A (https=)
DE (1) DE112022005675B4 (https=)
WO (1) WO2023100808A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025094846A1 (ja) * 2023-11-01 2025-05-08 ローム株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002270756A (ja) * 2001-03-08 2002-09-20 Hitachi Ltd 半導体装置及びそれを用いた通信端末装置
JP2016028407A (ja) * 2013-11-13 2016-02-25 ローム株式会社 半導体装置および半導体モジュール
JP2020036171A (ja) * 2018-08-29 2020-03-05 株式会社東芝 アイソレータ及び通信システム
US20200395353A1 (en) * 2019-06-17 2020-12-17 Rohm Co., Ltd. Chip component

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3992442B2 (ja) * 2001-02-05 2007-10-17 株式会社日立製作所 インタフェース装置及びインターフェースシステム
US8330251B2 (en) * 2006-06-26 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure for reducing mismatch effects
JP6591637B2 (ja) 2013-11-13 2019-10-16 ローム株式会社 半導体装置および半導体モジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002270756A (ja) * 2001-03-08 2002-09-20 Hitachi Ltd 半導体装置及びそれを用いた通信端末装置
JP2016028407A (ja) * 2013-11-13 2016-02-25 ローム株式会社 半導体装置および半導体モジュール
JP2020036171A (ja) * 2018-08-29 2020-03-05 株式会社東芝 アイソレータ及び通信システム
US20200395353A1 (en) * 2019-06-17 2020-12-17 Rohm Co., Ltd. Chip component

Also Published As

Publication number Publication date
JPWO2023100808A1 (https=) 2023-06-08
CN118339655A (zh) 2024-07-12
US20240313043A1 (en) 2024-09-19
DE112022005675T5 (de) 2024-09-19
WO2023100808A1 (ja) 2023-06-08

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Legal Events

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R012 Request for examination validly filed
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0027130000

Ipc: H10D0086800000

R016 Response to examination communication
R016 Response to examination communication
R018 Grant decision by examination section/examining division