WO2023093680A1 - Carte de circuit imprimé et son procédé de fabrication, architecture au niveau de la carte et dispositif électronique - Google Patents

Carte de circuit imprimé et son procédé de fabrication, architecture au niveau de la carte et dispositif électronique Download PDF

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Publication number
WO2023093680A1
WO2023093680A1 PCT/CN2022/133264 CN2022133264W WO2023093680A1 WO 2023093680 A1 WO2023093680 A1 WO 2023093680A1 CN 2022133264 W CN2022133264 W CN 2022133264W WO 2023093680 A1 WO2023093680 A1 WO 2023093680A1
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WO
WIPO (PCT)
Prior art keywords
medium
printed circuit
circuit board
dielectric
dielectric layer
Prior art date
Application number
PCT/CN2022/133264
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English (en)
Chinese (zh)
Inventor
程柳军
蔡黎
高峰
张林川
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华为技术有限公司
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Publication of WO2023093680A1 publication Critical patent/WO2023093680A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • the present application relates to the field of electronic devices, in particular to a printed circuit board and a manufacturing method thereof, a board-level structure, and an electronic device.
  • PCB Printed Circuit Board
  • the printed circuit board is a composite layer structure, and its main structure is made of insulating materials, and pads and metal traces are arranged on the outer surface and inner layer to realize the electrical connection between components.
  • the body of the component is usually made of ceramics, silicon wafers, etc., and is packaged with epoxy molding compound (EMC).
  • EMC epoxy molding compound
  • CTE coefficient of Thermal Expansion
  • the main material forms a temperature difference, resulting in inconsistent expansion and contraction between the components and the printed circuit board, and the solder joints connected between the two are subject to periodic thermal fatigue stress (creep fatigue) for a long time, which may eventually lead to soldering Point cracking fails.
  • the purpose of the present application is to provide a printed circuit board and its manufacturing method, a board-level structure including the printed circuit board, and an electronic device equipped with the board-level structure.
  • the present application provides a printed circuit board. It includes a substrate and a dielectric layer covering the surface of the substrate. There is also a pad on the side of the dielectric layer away from the substrate. The pad is used to connect and fix external devices.
  • the dielectric layer includes a first dielectric area and a second dielectric area. The pad is in the The vertical projection on the medium layer is located in the first medium area, the material of the first medium area is the first medium, the material of the second medium area is the second medium, and the Young's modulus of the first medium is smaller than that of the second medium Young's modulus, or the coefficient of thermal expansion of the first medium is less than the coefficient of thermal expansion of the second medium.
  • the printed circuit board of this application carries a dielectric layer through the substrate, and achieves soldering conduction with external devices through the pads on the dielectric layer. External devices form solder joints at the pad position, and the printed circuit board of this application can reduce the thermal fatigue of the solder joints formed at the pad position by setting the Young’s modulus or the first medium with a lower thermal expansion coefficient at the pad position stress effect. In this way, the phenomenon of crack failure at the solder joint can be avoided, and the service life of the printed circuit board can be improved.
  • the Young's modulus of the first medium is smaller than the Young's modulus of the second medium, and the thermal expansion coefficient of the first medium is smaller than the thermal expansion coefficient of the second medium.
  • the Young's modulus and thermal expansion coefficient of the first medium are lower than those of the second medium, which can further reduce the thermal fatigue stress effect of the solder joint formed at the pad position.
  • the first medium is a single material.
  • the first medium is a composite material
  • the average Young's modulus of the composite material is smaller than that of the second medium
  • the average thermal expansion coefficient of the composite material is smaller than that of the second medium coefficient of thermal expansion.
  • the vertical projection of the external device on the dielectric layer is a first projection area, and the first projection area is located within the first dielectric area.
  • the first medium area is set to completely accommodate the first projection area, so that the printed circuit board uses the material of the first medium to cooperate with the external device in the entire area corresponding to the external device. Because the temperature of the electronic equipment changes repeatedly during the working process, the use of the first medium can reduce the thermal fatigue stress at the solder joint position of the external device. On the other hand, the overall area of the external device is relatively large, and the first projected area formed by it is also relatively large, which facilitates the manufacture of the first dielectric area.
  • the minimum distance between the edge of the first projected area and the edge of the first dielectric area is greater than or equal to 50 ⁇ m.
  • controlling the distance between the edge of the first dielectric region and the edge of the first projection region can make the first dielectric region surround the periphery of the first projection region, and the outer edge of the external device is set as Young’s mode within a certain range.
  • a small amount of the first dielectric ensures that the thermal fatigue stress of the pad of the external device is also in a relatively low range.
  • the distance D between the edge of the first projection area and the edge of the first medium area satisfies the condition: 5mil ⁇ D ⁇ 50mil.
  • an intermediate dielectric layer is further included, and the intermediate dielectric layer is located between the substrate and the dielectric layer.
  • an intermediate dielectric layer may also be disposed between the dielectric layer and the substrate, so as to increase the overall thickness of the dielectric layer and the intermediate dielectric layer.
  • the introduction of the intermediate dielectric layer also reduces the thickness of the dielectric layer and reduces the usage of the first medium.
  • the material of the intermediate medium layer is the second medium.
  • a metal layer is further provided between the substrate and the dielectric layer, and/or between the substrate and the intermediate dielectric layer for signal transmission.
  • the number of dielectric layers is two, and the two dielectric layers are respectively covered on two opposite outer surfaces of the substrate.
  • a prepreg layer is provided between two adjacent substrates.
  • the Young's modulus of the first medium is less than or equal to 15 GPa.
  • the Young's modulus of the first medium is less than or equal to 3 GPa.
  • the coefficient of thermal expansion of the first medium is less than or equal to 100 ppm/°C.
  • the coefficient of thermal expansion of the first medium is less than or equal to 35 ppm/°C.
  • the thermal curing temperature of the first medium is greater than or equal to 130°C.
  • the thickness of the dielectric layer is less than or equal to 75 ⁇ m.
  • the sum of the thicknesses of the dielectric layer and the intermediate dielectric layer is less than or equal to 75 ⁇ m.
  • the present application provides a method for manufacturing a printed circuit board, comprising the following steps:
  • the first medium is used to form the first medium area
  • the second medium is used to form the second medium area
  • the Young's modulus of the first medium is smaller than the Young's modulus of the second medium
  • the coefficient of thermal expansion of the first medium is smaller than the coefficient of thermal expansion of the second medium
  • the printed circuit board manufacturing method provided in the second aspect of the present application is used to form the printed circuit board in the first aspect.
  • the first dielectric region and the second dielectric region need to be manufactured respectively, and then the dielectric layer is formed by pressing. It can be understood that the position of the first dielectric area corresponds to the position where the printed circuit board needs to be connected to external devices, so as to achieve the above-mentioned effect of improving the service life of the printed circuit board in the first aspect.
  • the first medium is used to form the first medium area on one outer surface of the substrate
  • the second medium is used to form the second medium area, including:
  • the second dielectric film layer is surface-attached on the outer surface to form the second dielectric region, and the first dielectric region is exposed through the hollow region.
  • the first dielectric region and the second dielectric film layer corresponding to the second dielectric region are formed separately, and a hollow area is opened at the position of the second dielectric film layer corresponding to the first dielectric region, so that the second dielectric film
  • the first dielectric region can be exposed through the hollow area while the second dielectric region is being formed, thereby forming a pre-stack of the first dielectric region and the second dielectric region.
  • the first dielectric region is fabricated using the first dielectric on one outer surface of the substrate, including:
  • a first medium in the form of a film is pseudo-connected at a low temperature on the outer surface of one side of the substrate, or
  • the first medium is used to form the first medium area on one outer surface of the substrate
  • the second medium is used to form the second medium area, including:
  • a film-like first medium is surface-attached to the exposed outer surface of the hollow area to form the first medium area.
  • the second dielectric region can be manufactured first, and then the first dielectric region can be manufactured to realize the pre-stacking of the two.
  • the present application provides yet another printed circuit board, including a substrate and a dielectric layer covering the substrate, and pads located on the side of the dielectric layer away from the substrate, the pads are used to connect and fix external devices, and the dielectric layer
  • the material is the first medium, and the Young's modulus of the first medium is less than or equal to 15GPa, or the coefficient of thermal expansion of the first medium is less than or equal to 100ppm/°C.
  • the Young's modulus of the first medium is less than or equal to 15 GPa, and the thermal expansion coefficient of the first medium is less than or equal to 100 ppm/°C.
  • the first medium is a single material.
  • the first medium is a composite material
  • the average Young's modulus of the composite material is smaller than that of the second medium
  • the average thermal expansion coefficient of the composite material is smaller than that of the second medium coefficient of thermal expansion.
  • an intermediate dielectric layer is further included, and the intermediate dielectric layer is located between the substrate and the dielectric layer.
  • an intermediate dielectric layer may also be disposed between the dielectric layer and the substrate, so as to increase the overall thickness of the dielectric layer and the intermediate dielectric layer.
  • the introduction of the intermediate dielectric layer also reduces the thickness of the dielectric layer and reduces the usage of the first medium.
  • the Young's modulus of the material of the intermediate dielectric layer is greater than 15 GPa, and/or the thermal expansion coefficient of the material of the intermediate dielectric layer is greater than 100 ppm/°C.
  • a metal layer is further provided between the substrate and the dielectric layer, and/or between the substrate and the intermediate dielectric layer for signal transmission.
  • the number of dielectric layers is two, and the two dielectric layers are respectively covered on two opposite outer surfaces of the substrate.
  • a prepreg layer is provided between two adjacent substrates.
  • the Young's modulus of the first medium is less than or equal to 3 GPa.
  • the coefficient of thermal expansion of the first medium is less than or equal to 35 ppm/°C.
  • the thermal curing temperature of the first medium is greater than or equal to 130°C.
  • the thickness of the dielectric layer is less than or equal to 75 ⁇ m.
  • the sum of the thicknesses of the dielectric layer and the intermediate dielectric layer is less than or equal to 75 ⁇ m.
  • the present application provides yet another method for manufacturing a printed circuit board, comprising the following steps:
  • a first medium to make a medium layer on one outer surface of the substrate, wherein the Young's modulus of the first medium is less than or equal to 15GPa, and/or the coefficient of thermal expansion of the first medium is less than or equal to 100ppm/°C;
  • all the dielectric layers of the printed circuit board are made of the first dielectric material, thereby reducing the thermal fatigue stress between the entire dielectric layer and external devices, and improving the service life of the printed circuit board.
  • the printed circuit board manufacturing method in the fourth aspect of the present application is used to form the printed circuit board provided in the third aspect.
  • the present application provides a board-level architecture, including at least one printed circuit board and at least one device mounted on the printed circuit board, wherein the printed circuit board provides The printed circuit board, or the printed circuit board is a printed circuit board manufactured by using the method for manufacturing the printed circuit board of the second aspect and the fourth aspect.
  • the present application provides an electronic device, including the above-mentioned board-level architecture.
  • the board-level architecture provided by the fifth aspect of the present application uses the printed circuit boards provided by the first to fourth aspects above, the combination between the device and the printed circuit board is more reliable, which also improves the The reliability of the board-level architecture itself can prolong the service life of the board-level architecture.
  • the electronic device provided in the sixth aspect of the present application also improves the reliability and service life of the electronic device due to the improved reliability and service life of the board-level structure of its equipment.
  • FIG. 1 is a schematic structural diagram of a board-level architecture provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a device in a board-level architecture provided by an embodiment of the present application
  • FIG. 2a is a schematic structural diagram of another device in a board-level architecture provided by an embodiment of the present application.
  • FIG. 3 is a schematic plan view of a printed circuit board in a board-level architecture provided by an embodiment of the present application
  • FIG. 4 is a schematic diagram of an exploded structure of a board-level architecture provided by an embodiment of the present application.
  • Fig. 5 is a schematic cross-sectional structure diagram of a printed circuit board provided by an embodiment of the present application.
  • FIG. 6 is a schematic plan view of a printed circuit board provided by an embodiment of the present application.
  • FIG. 7 is a schematic plan view of a board-level architecture provided by an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional structure diagram of a board-level architecture provided by an embodiment of the present application.
  • FIG. 9 is a schematic plan view of another board-level architecture provided by an embodiment of the present application.
  • FIG. 10 is a schematic cross-sectional structure diagram of another board-level architecture provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a partial plane structure of another board-level architecture provided by an embodiment of the present application.
  • FIG. 12 is a schematic cross-sectional structure diagram of another board-level architecture provided by an embodiment of the present application.
  • Fig. 13 is a schematic cross-sectional structure diagram of another board-level architecture provided by an embodiment of the present application.
  • FIG. 14 is a schematic cross-sectional structure diagram of another board-level architecture provided by an embodiment of the present application.
  • Fig. 15 is a schematic cross-sectional structure diagram of another board-level architecture provided by an embodiment of the present application.
  • 16a-16d are structural schematic diagrams of each step in a method for manufacturing a printed circuit board provided by an embodiment of the present application.
  • Fig. 17a-Fig. 17c are the structural representations of each sub-step of step S100 in a kind of printed circuit board manufacturing method provided by the embodiment of the present application;
  • FIG. 18 is a schematic flow chart of each step in a method for manufacturing a printed circuit board provided in an embodiment of the present application.
  • FIG. 19 is a schematic flow diagram of steps in another printed circuit board manufacturing method provided in the embodiment of the present application.
  • 20a-20c are structural schematic diagrams of each sub-step of step S100 in another printed circuit board manufacturing method provided by the embodiment of the present application;
  • Fig. 21 is a schematic flow chart of each step in another printed circuit board manufacturing method provided by the embodiment of the present application.
  • Fig. 22 is a schematic cross-sectional structure diagram of another printed circuit board provided by the embodiment of the present application.
  • 23a-23c are structural schematic diagrams of steps in another printed circuit board manufacturing method provided by the embodiment of the present application.
  • FIG. 1 illustrates a structure of a board-level architecture 400 provided by an embodiment of the present application.
  • the board-level architecture 400 provided in the embodiment of the present application may be assembled in the electronic device (not shown in the figure) provided in the present application.
  • the board-level architecture 400 includes at least one printed circuit board 100 and at least one device 200 .
  • the device 200 may be a wafer chip, and several devices 200 are mounted on the printed circuit board 100 to realize the preset functions of the board-level architecture 400 .
  • the device 200 shown in FIG. 1 is the external device of the printed circuit board 100 described in the claims of the present application and the summary of the invention in the specification.
  • the board-level architecture 400 can be directly assembled in electronic equipment to realize preset functions of the electronic equipment; the board-level architecture 400 can also be formed into functional devices such as capacitors, resistors, inductors, diodes, triodes, and field effect transistors through packaging, And further mounted on the printed circuit board 100 to form an upper-level board-level framework 400 , the upper-level board-level framework 400 can be equipped in an electronic device to realize preset functions.
  • the electronic devices involved in this application may include but are not limited to mobile phones, tablet computers, notebook computers, ultra-mobile personal computers (ultra-mobile personal computer, UMPC), handheld computers, walkie-talkies, netbooks, POS machines, personal digital assistants (personal digital assistant, PDA), driving recorder, security equipment, server, wireless base station, switch, router and other electronic equipment or equipment.
  • UMPC ultra-mobile personal computers
  • UMPC ultra-mobile personal computer
  • PDA personal digital assistants
  • driving recorder security equipment
  • server wireless base station
  • switch router and other electronic equipment or equipment.
  • a device 200 in the electronic device of the present application includes a plurality of signal pins 201 .
  • a plurality of signal pins 201 may be located at an outer edge of the device 200 body and extend toward a direction away from the device 200 body.
  • the device 200 may further include a signal pin 201 partially located at the bottom thereof.
  • the device 200 includes a bottom surface 202 , and when the device 200 is mounted on the printed circuit board 100 , the bottom surface 202 is an outer surface facing the printed circuit board 100 .
  • the signal legs 201 at the bottom of the device 200 can be disposed on the bottom surface 202 , so that when the device 200 is mounted on the printed circuit board 100 , the part of the signal legs 201 can be bonded and contacted with the printed circuit board 100 .
  • the legs 201 of the device 200 can be located on the side of the device 200 or on the bottom surface 202 thereof.
  • the introduced device 200 has legs 201 on its side and bottom 202 . It can be understood that for the device 200 provided with the legs 201 only on the sides, or the device 200 provided with the legs 201 only on the bottom surface 202 , corresponding explanations can also be made with reference to the descriptions of the subsequent embodiments.
  • the printed circuit board 100 of the present application includes an assembly surface 101 , on which the device 200 is mounted and bonded. Further, please understand it together with FIG. 3 .
  • the printed circuit board 100 of the present application is provided with a plurality of pads 102 on the assembly surface 101 .
  • the positions of the plurality of pads 102 may be set corresponding to the positions of the signal pins 201 of the device 200 .
  • the functional devices formed after the board-level architecture 400 is packaged, as well as the above-mentioned devices 200 using wafer chips, can be fixed and conducted on the printed circuit board 100 by soldering. As shown in FIG.
  • each signal leg 201 of the device 200 can form a one-to-one correspondence structure with each solder pad 102, so that when the device 200 is fixed on the printed circuit board 100, each signal leg 201 can be connected to a solder pad. 102 is welded and conducted, thereby realizing the signal transmission function of the device 200 on the printed circuit board 100 .
  • both the signal pins 201 of the device 200 and the pads 102 of the printed circuit board 100 are made of conductive materials (such as copper and other metals).
  • a plurality of transmission lines 103 are provided on the assembly surface 101 of the printed circuit board, and each transmission line 103 is respectively connected to a plurality of pads 102 in one-to-one correspondence, and is used to realize the transmission of signals in the device 200 in the printed circuit board 100 transmission. That is, corresponding to a signal pin 201 in the device 200 , it realizes its signal transmission function on the printed circuit board 100 through a pad 102 and a transmission line 103 successively.
  • FIG. 5 illustrates a cross-sectional view of an embodiment of a printed circuit board 100 of the present application.
  • the printed circuit board 100 includes a substrate 110 , a dielectric layer 120 , and a metal layer 130 .
  • the dielectric layer 120 is located between the substrate 110 and the metal layer 130 .
  • the metal layer 130 is made of conductive material, which is used to form the above-mentioned pads 102 and transmission lines 103 on the assembly surface 101 .
  • the metal layer 130 can be made of copper foil.
  • the substrate 110 is the base material of the printed circuit board 100 , which is used to provide overall structural support of the printed circuit board 100 .
  • the dielectric layer 120 can be realized by using a semi-cured material, such as a prepreg, a prepreg (grease), etc., and the dielectric layer 120 is used to achieve bonding and fixing between the substrate 110 and the metal layer 130 .
  • the dielectric layer 120 (defined as the prepreg layer 150 in the following embodiments) can also be located between two adjacent substrates 110 to realize the The bonding between 110 is fixed.
  • the dielectric layer 120 further includes a first dielectric region 121 and a second dielectric region 122 .
  • the material of the first medium area 121 is the first medium
  • the material of the second medium area 122 is the second medium.
  • the position of the first dielectric region 121 is set at least corresponding to the position of the pad 102 , that is, the vertical projection of the pad 102 on the dielectric layer 120 is located within the first dielectric region 121 .
  • the vertical direction in the embodiment of the present application refers to the thickness direction of the substrate 110 or the printed circuit board 100 .
  • the Young's modulus of the first medium is smaller than the Young's modulus of the second medium. That is, the Young's modulus of the material in the first dielectric region 121 is smaller than the Young's modulus of the material in the second dielectric region 122 .
  • the coefficient of thermal expansion of the first medium is smaller than the coefficient of thermal expansion of the second medium.
  • the Young's modulus of the first medium is smaller than the Young's modulus of the second medium, and at the same time, the thermal expansion coefficient of the first medium is also smaller than that of the second medium.
  • FIG. 7 is an appearance structure diagram of the board-level architecture 400
  • FIG. 8 is a cross-sectional view of the board-level architecture 400 .
  • the signal legs 201 of the device 200 correspond to the pads 102 of the printed circuit board 100 one by one, and the signal legs 201 are fixed and connected to the pads 102 by soldering. Therefore, in the schematic diagram of FIG. 8 , a solder joint 203 is formed between the signal pin 201 and the bonding pad 102 .
  • each solder joint 203 formed by soldering the mounted device 200 can be located within the first dielectric region 121 of the dielectric layer 120 .
  • CTE coefficient of thermal expansion
  • the test medium materials of this application shown in Table 1 can be understood as different types of the above-mentioned first medium.
  • CTE is the coefficient of thermal expansion of the material in ppm/°C
  • E is the Young's modulus of the material in GPa
  • H is the thickness of the material in um.
  • the stress at corners A ⁇ B ⁇ C ⁇ D is the stress value at the four corners of the device 200 shown in FIG. 7 , and the unit is MPa.
  • the thermal fatigue stress effect at the four corners is the largest, and the cracking of the solder joint 203 usually occurs first at the four corners.
  • the signal pin stress is a stress test for a single signal pin 201 . Although the stress of the signal pin 201 is the same as that of the corners A ⁇ B ⁇ C ⁇ D, the thermal fatigue stress effect thereof is generally smaller than that of the four corners.
  • the existing dielectric material can be understood as the second medium involved in this application, whose Young's modulus is usually greater than 15GPa, and its thermal expansion coefficient is usually greater than 100ppm/°C. It can be seen that when the Young's modulus of the first medium is smaller than the Young's modulus of the second medium, and the adjustment of the coefficient of thermal expansion, thickness and other values are supplemented, the stress between the first medium and the device 200 is also Less stress than the second medium. Young's modulus can also be understood as the elastic modulus of the material in the tensile direction. When the Young's modulus of the material is higher, its thermal fatigue effect is usually more obvious. It can also be concluded from Table 1 that the benefit of thermal fatigue effect obtained by changing the Young's modulus of the material is greater than that obtained by changing the thermal expansion coefficient or thickness of the material. The benefits of changing the thermal expansion coefficient of the material are relatively large.
  • the solder joint 203 is made of metal, and its Young's modulus is lower than that of the semi-cured dielectric layer 120 . Therefore, through the setting of the first dielectric region 121 and the second dielectric region 122 in the printed circuit board 100 of the present application, the printed circuit board 100 adopts relatively low Young's modulus at the positions corresponding to each solder joint 203
  • the first medium cooperates with the solder joints 203, so that when each solder joint 203 is subjected to cyclic thermal fatigue stress, because the Young's modulus of the first medium is lower, it is not easy to cause cracks at the solder joints 203.
  • the thermal expansion coefficient of the first medium it can also be set to be smaller than that of the second medium, and an effect similar to changing Young's modulus can also be achieved.
  • setting the Young's modulus and thermal expansion coefficient of the first medium to be smaller than the Young's modulus and thermal expansion coefficient of the second medium can further ensure the reduction of thermal fatigue stress at the solder joint 203 .
  • the area overhead of the signal pin 201 of the device 200 on the mounting surface 101 of the printed circuit board 100 is also small.
  • the vertical projected area of the corresponding pad 102 on the dielectric layer 120 is also relatively small. Therefore, in the dielectric layer 120 , the area ratio of the first dielectric region 121 is relatively smaller than that of the second dielectric region 122 . That is, in the medium layer 120 , the content of the second medium is greater than that of the first medium. Therefore, in the dielectric layer 120 of the printed circuit board 100 of the present application, the first dielectric region 121 can be prepared by opening a small-area window on the second dielectric region 122 .
  • the second medium can be prepared by using a relatively conventional medium layer material
  • the first medium can be prepared by using a medium layer material with a relatively small Young's modulus and/or thermal expansion coefficient.
  • the material cost of the first medium is higher than that of the second medium.
  • the first dielectric region 121 is prepared by the above-mentioned small-area window opening, so that the dielectric layer 120 can retain the material properties of the second medium in a large area, and at the same time, use the first medium and each solder joint 203 Cooperate to prevent the solder joints 203 from cracking, thereby improving the connection reliability of the device 200 relative to the printed circuit board 100 and increasing the service life of the printed circuit board 100 carrying the device 200 .
  • the amount of the first medium used is relatively small, which can control the overall cost of the printed circuit board 100 . It can be understood that the cost of the board-level architecture 400 of the printed circuit board 100 of the present application and the electronic equipment equipped with the board-level architecture 400 are correspondingly controlled, and the reliability and service life are also correspondingly improved.
  • the Young's modulus of the defined first medium is less than or equal to 15 GPa.
  • the coefficient of thermal expansion of the first medium is less than or equal to 100 ppm/°C. It can be further defined that the coefficient of thermal expansion of the first medium is less than or equal to 35 ppm/°C.
  • the thermal curing temperature of the first medium is greater than or equal to 130°C.
  • the thermal curing temperature of the first medium may be close to the thermal curing temperature of the second medium, and the glass transition temperature after curing is greater than or equal to 130°C.
  • the above parameter definitions for the first medium can improve the stability of the first medium region 121 against the thermal fatigue effect of the solder joint 203 under the long-term periodic thermal fatigue stress, so as to avoid cracking of the solder joint 203 .
  • the above-mentioned first medium may be a single material, or the material used to form the first dielectric region 121 is described as a single material. At this time, it is only necessary to define the parameters of the single material to achieve the parameter definition of the first medium.
  • the first medium may be a composite material.
  • the composite material here can be understood as the first medium is a mixture of at least two materials, and it can also be understood that the materials used to form the first medium region 121 are at least two materials, and the at least two materials are formed by splicing to form the first medium.
  • a medium area 121 is a mixture of at least two materials, and it can also be understood that the materials used to form the first medium region 121 are at least two materials, and the at least two materials are formed by splicing to form the first medium.
  • the first medium is a composite material
  • the vertical projection of the device 200 on the dielectric layer 120 forms a first projection area 204 .
  • the body of the device 200 and each signal pin 201 are located within the first projection area 204 .
  • the first dielectric region 121 of the dielectric layer 120 completely accommodates the first projection region 204 . That is, within the range corresponding to the device 200 , the dielectric layer 120 is entirely configured as a first dielectric region 121 , and is soldered, fixed and adhered to the device 200 through the pad 102 on the first dielectric.
  • the device 200 itself generates heat during operation.
  • the bottom surface 202 of the device 200 is attached to the assembly surface 101 of the printed circuit board 100, because the material of the device 200 is different from the main material of the printed circuit board 100 (in this embodiment, the material of the dielectric layer 120), the device There will also be a difference in thermal expansion coefficient between the 200 and the dielectric layer 120 .
  • the first dielectric region 121 of the dielectric layer 120 is disposed corresponding to the device 200, so that the device 200 as a whole can cooperate with the first dielectric.
  • the Young's modulus of the first medium is smaller, or the thermal expansion coefficient difference between it and the body of the device 200 is smaller, the thermal fatigue stress difference between the device 200 and the dielectric layer 120 is further reduced, so that the device 200 and the dielectric layer The bonding state between the layers 120 is more stable, thereby ensuring reliable bonding between the two layers.
  • the overall area of the device 200 is larger than the area of its signal pin 201 , and the area of the first dielectric region 121 matching it is correspondingly larger.
  • the larger area of the first dielectric region 121 is also more conducive to processing and filling the first medium, and thus reduces the accuracy requirements for the first dielectric region 121, which is convenient Fabrication of the first dielectric zone 121 .
  • the edge of the first dielectric region 121 is also set to form a distance D from the edge of the first projected region 204, so as to ensure that the device 200 is attached to the dielectric layer 120 , it can be completely located within the first dielectric region 121 .
  • the minimum value of the distance D between the edge of the first projection area 204 and the edge of the first dielectric area 121 is set to be greater than or equal to 50 ⁇ m.
  • the first medium area 121 covers a larger area of the first projected area 204, and at the position corresponding to the pad 102 and its surrounding area, the material of the first medium is formed to cooperate with the solder joint 203, which can better ensure The coefficient of thermal expansion of the solder joint 203 and its surrounding area is smaller.
  • the numerical range of the separation distance D may also be set to satisfy: 5mil ⁇ D ⁇ 50mil.
  • the distance between the edge of the first dielectric region 121 is smaller than the edge of the first projected region 204, and the position accuracy of the first dielectric region 121 is also higher, so that it can be better positioned relative to the device 200, and at the same time
  • the area ratio of the second medium in the medium layer 120 is increased, ensuring the structural stability of the medium layer 120 .
  • the dielectric layer 120 of this application in some embodiments, its thickness is limited to be less than or equal to 75 ⁇ m. Since the first medium and the second medium in the medium layer 120 are mostly in a semi-cured state, when the overall thickness of the medium layer 120 is too thick, the overall structural stability of the printed circuit board 100 may be affected.
  • An intermediate dielectric layer 140 is further disposed between the dielectric layer 120 and the substrate 110 .
  • the intermediate dielectric layer 140 is also in a semi-cured state, and its function is similar to that of the dielectric layer 120 , and is used to achieve bonding and fixing between the substrate 110 and the metal layer 130 .
  • the material of the intermediate dielectric layer 140 and the second dielectric region 122 of the dielectric layer 120 may be the same, that is, the intermediate dielectric layer 140 may also be made of the second dielectric.
  • the function of the intermediate dielectric layer 140 is similar to that of the dielectric layer 120 , but it is necessary to ensure that the dielectric layer 120 is always on the side close to the metal layer 130 relative to the intermediate dielectric layer 140 to ensure the cooperation between the first dielectric region 121 and the pad 102 .
  • the sum of the thicknesses of the dielectric layer 120 and the intermediate dielectric layer 140 may also be set to be less than or equal to 75 ⁇ m.
  • the printed circuit board 100 in the board-level architecture 400 of the present application may also be configured as a printed circuit board with a composite layer structure.
  • a second metal layer 131 may also be provided between the substrate 110 and the dielectric layer 120 .
  • a plurality of transmission lines 103 may be formed in the second metal layer 131 by patterning, so that the second metal layer 131 has a transmission function in the layers of the printed circuit board 100 .
  • a plurality of via holes 104 can be opened in the dielectric layer 120, and the via holes 104 can be connected between the transmission line 103 on the assembly surface 101 and the transmission line 103 in the second metal layer 131, or the via holes 104 can be connected to the assembly surface 101. Between the pad 102 of the printed circuit board 100 and the transmission line 103 in the second metal layer 131, so as to realize the function of the printed circuit board 100 to transmit signals within the layer.
  • the number of substrates 110 is two (the number of substrates 110 in other embodiments may also be multiple layers).
  • Two substrates 110 are stacked, and a prepreg layer 150 is disposed between the two substrates 110 .
  • the prepreg layer 150 is used to connect and fix the two substrates 110 . Since the semi-cured layer 150 is also in a semi-cured state, and is also used to realize the connection function, in some embodiments, the material of the semi-cured layer 150 can also be realized by using a second medium.
  • a dielectric layer 120 and a metal layer 130 are disposed on opposite sides of the substrate 110 , and a dielectric layer 120 is disposed between each metal layer 130 and the substrate 110 .
  • Such a structure enables the front and back sides of the printed circuit board 100 to carry the device 200, that is, the printed circuit board 100 is formed as a double-sided printed circuit board in this embodiment.
  • the dielectric layer 120 on one side of the substrate 110 can correspond to the positions of the pads 102 in the metal layer 130 on the same side to set the positions of the first dielectric region 121 and the second dielectric region 122, or the dielectric
  • the positions of the first dielectric region 121 and the second dielectric region 122 are set corresponding to the positions of the devices 200 mounted on the same side of the layer 120; and the dielectric layer 120 on the other side of the substrate 110 is also based on the pads on the same side respectively. 102 or the position of the device 200 to set the positions of the first dielectric region 121 and the second dielectric region 122 .
  • the structure of the double-sided printed circuit board in the embodiment of FIG. 15 can also ensure the integrity of the devices 200 respectively mounted on the opposite sides of the dielectric layer 120 through the setting of the first dielectric region 121 and the second dielectric region 122. Connection reliability, avoiding cracking of solder joints 203.
  • the composite layer structure of the printed circuit board 100 can also be arranged in conjunction with each other.
  • the opposite sides of the printed circuit board 100 can carry the device 200, and the inside of the printed circuit board 100 is also provided with a second metal layer 131 for transmitting signals; or in some embodiments , the number of substrates 110 of the printed circuit board 100 is multiple, and the opposite sides of the printed circuit board 100 can also be equipped with devices 200, etc.; even in some embodiments, the printed circuit board 100 can also include the second metal layer 131 , and includes a plurality of substrates 110, and also has the function of a double-sided printed circuit board, and this specification will not repeat them here.
  • the printed circuit board manufacturing method provided in the second aspect of the present application can be understood as being used for manufacturing the above-mentioned printed circuit board 100 .
  • the printed circuit board manufacturing method may include the following steps:
  • the first dielectric region 121 is fabricated using the first medium
  • the second dielectric region 122 is fabricated using the second medium; wherein the Young's modulus of the first medium is smaller than the Young's modulus of the second medium modulus, and/or the coefficient of thermal expansion of the first medium is less than the coefficient of thermal expansion of the second medium;
  • the printed circuit board manufacturing method of the present application firstly provides a substrate 110 , and the substrate 110 has an outer surface 111 . Then, on the outer surface 111, a first dielectric region 121 (Fig. 16b) and a second dielectric region 122 (Fig. 16c) are produced respectively, wherein the first dielectric region 121 is prepared using the first medium, and the second dielectric region 122 is prepared using the second dielectric region 122. The medium is prepared, and the production sequence of the first dielectric region 121 and the second dielectric region 122 is not strictly defined in this embodiment.
  • the location area of the first dielectric region 121 can be set based on the location area of the device 200 to be mounted on the printed circuit board 100 , that is, based on the location area of the device 200 on the board-level structure 400 .
  • the dielectric layer 120 can be formed on the first outer surface 111 of the substrate 110 .
  • a metal layer 130 is fabricated and patterned to form a pad 102 (FIG. 16d).
  • the above-mentioned printed circuit board 100 can be formed.
  • the Young's modulus of the first medium is smaller than the Young's modulus of the second medium, and/or the thermal expansion coefficient of the first medium is smaller than the thermal expansion coefficient of the second medium, after it mounts the device 200, the solder joint 203 formed is thermally The fatigue effect is smaller, and the reliability and service life of the printed circuit board 100 can be improved.
  • step S100 that is, in the process of providing the substrate 110
  • the method of the present application may also include the following steps:
  • the printed circuit board 100 further includes the second metal layer 131 between the dielectric layer 120 and the substrate 110, it is also necessary to first form the second metal layer 131 on the outer surface 111 of the substrate 110 and then pattern it. , and then fabricate the first dielectric region 121 and the second dielectric region 122 respectively. That is, the method of the present application does not limit the dielectric layer 120 to be directly attached to the outer surface 111 of the substrate 110 . Therefore, after the above step S50 of "cutting the substrate 110", the following steps may also be included:
  • step S70 the circuit is etched on the substrate 110, that is, the second metal layer 131 is formed on the outer surface 111 of the substrate 110, and the transmission line 103 is formed after the second metal layer 131 is patterned.
  • steps such as browning the substrate 110 belong to the manufacturing process required in the process of providing the substrate 110 .
  • step S100 of "making the first dielectric region 121 with the first medium on the outer surface 111 of the substrate 110, and making the second dielectric region 122 with the second medium" the following sub-steps may be included:
  • the first dielectric region 121 is prepared on the substrate 110 , and then the second dielectric film layer 122 a is surface-attached to form the second dielectric region 122 .
  • the method first uses the first medium to make the first medium region 121 (see FIG. 17 a ) on the outer surface 111 of the substrate 110, and then makes a separate second medium at another place different from the outer surface 111.
  • Membrane layer 122a (see FIG. 17a).
  • the second dielectric film layer 122a is prepared by using the second medium, and the second dielectric film layer 122a needs to have transferable properties.
  • a hollow area 1221a (see Figure 17b) needs to be set up on the second dielectric film layer 122a.
  • the position and area size of the hollow area 1221a need to be opened with reference to the position and size of the first dielectric area 121 on the outer surface 111, so that the second When the dielectric film layer 122a is surface-attached on the outer surface 111, the first dielectric region 121 can be exposed through the hollow area 1221a, so that after the first dielectric region 121 and the second dielectric region 122 form a reliable pre-lamination, the subsequent lamination of the second When the first dielectric region 121 and the second dielectric region 122 are used, a relatively flat and continuous dielectric layer 120 can be formed (see FIG. 17c ).
  • the above step S110 of "making the first dielectric region 121 using the first dielectric on the outer surface 111 of the substrate 110" may include:
  • a film-like first dielectric is bonded on the outer surface 111 of the substrate 110 at low temperature to form a first dielectric region 121 .
  • FIG. 18 is a schematic flowchart of a method for manufacturing a printed circuit board of the present application corresponding to this embodiment.
  • the film-like (sheet) first medium can be fixed on the outer surface 111 by means of low temperature bonding, and then the second medium.
  • the method of opening the hollow area 1221a on the film layer 122a ensures that when the second dielectric film layer 122a is surface-attached to the outer surface 111, the hollow area 1221a is precisely aligned with the first dielectric area 121, and the dielectric layer 120 is formed.
  • the precision of the low-temperature dummy connection is relatively high, it is possible to produce the printed circuit board 100 corresponding to the above-mentioned embodiment of "the value of the separation distance D satisfies: 5mil ⁇ D ⁇ 50mil".
  • the step S110 of "using the first medium to form the first dielectric region 121 on the outer surface 111 of the substrate 110" may also include:
  • a paste-like first medium is printed on the outer surface 111 and then pre-cured to form the first medium area 121 .
  • the subsequent surface mount process of the second dielectric film layer 122a is similar to the process shown in FIG. 18 above. Specifically, the selection of the manufacturing method in FIG. 18 and FIG. 19 can be determined based on the characteristics of the first medium as film or paste.
  • the following sub-steps may also be included :
  • the second dielectric region 122 (see FIG. 20 a ) is formed on the outer surface 111 of the substrate 110 first, and then the first dielectric region 121 is formed by opening and filling.
  • the opening position of the hollow area 1221 needs to be set corresponding to the position of the device 200 to be carried on the printed circuit board 100 (see FIG. 20 b ).
  • the area size of the first medium needs to match the area size of the hollow area 1221 (see FIG. 20 c ).
  • This embodiment of the method is applicable to the production of the printed circuit board 100 in which the above-mentioned "minimum value of the separation distance D is greater than or equal to 50 ⁇ m". Compared with the embodiments shown in FIG. 18 and FIG. 19 , the method and process of this embodiment are simpler and the manufacturing cost is lower.
  • the printed circuit board 100 when the printed circuit board 100 is produced by the printed circuit board manufacturing method of the present application, if the printed circuit board 100 further includes the second metal layer 131, includes a plurality of substrates 110, and the opposite sides of the printed circuit board 100 Both sides need to carry the device 200 and other embodiments, all of which can be developed according to the steps of the above-mentioned method embodiments, and the reliability and usability of the printed circuit board 100 can be improved by setting the first dielectric region 121 at the position where the device 200 is mounted. life.
  • the printed circuit board 300 also includes a substrate 310 , a dielectric layer 320 , and a metal layer 330 .
  • the dielectric layer 320 is located between the substrate 310 and the metal layer 330 .
  • the metal layer 330 is made of conductive material, and is used to form pads and transmission lines of the printed circuit board 300 of this embodiment, wherein the pads are used to connect and fix the device 200 , and the transmission lines are used to transmit signals.
  • the substrate 310 is also used as the base material of the printed circuit board 300
  • the dielectric layer 320 is also made of semi-cured material, which is used to realize the bonding and fixing between the metal layer 330 and the substrate 310 .
  • the Young's modulus of the material for the dielectric layer 320 is less than or equal to 15 GPa, or the thermal expansion coefficient of the material for the dielectric layer 320 is less than or equal to 100 ppm/°C.
  • the Young's modulus of the material for making the dielectric layer 320 is less than or equal to 15 GPa, and its thermal expansion coefficient is less than or equal to 100 ppm/°C.
  • the material of the dielectric layer 320 can be prepared by using the above-mentioned first medium, and the Young's modulus of the first medium is less than or equal to 15 GPa.
  • the Young’s modulus of the first medium in this embodiment is less than or equal to 15GPa, and/or the thermal expansion coefficient of the material for making the dielectric layer 320 is less than or equal to 100ppm/°C , so the overall stress of the dielectric layer 320 of the printed circuit board 300 is relatively small.
  • the solder joints formed by the device 200 on the printed circuit board 300 are also not easy to crack because of the cooperation with the first medium, thereby improving the printed circuit board 300 provided by this embodiment. reliability and service life.
  • the printed circuit board 300 provided in this embodiment omits the application of the second medium, and it can also be understood that the dielectric layer 320 of the printed circuit board 300 is integrally set as The first dielectric region 121 of the above-mentioned printed circuit board 100 . Because the material used for the dielectric layer 320 has a small Young's modulus and/or thermal expansion coefficient, after the device 200 is mounted, similar beneficial effects can be obtained as with the above-mentioned printed circuit board 100 . At the same time, the printed circuit board 300 provided in this embodiment has a simpler structure than the printed circuit board 100 provided above, and there is no need to consider the alignment problem between the pad and the first medium, which also reduces the need for alignment. Positional accuracy requirements of the device 200 .
  • another printed circuit board 300 provided in the present application can also form some similar embodiments and achieve similar beneficial effects.
  • the Young’s modulus of the material for further setting the dielectric layer 320 is less than or equal to 3GPa; or the thermal expansion coefficient of the material for setting the dielectric layer 320 is less than or equal to 35ppm/°C; or the thermal curing temperature of the material for setting the dielectric layer 320 is the same as
  • the second medium is similar, and the glass transition temperature after curing is greater than or equal to 130°C.
  • another printed circuit board 300 provided by the present application may also include an intermediate dielectric layer, a second metal layer, a plurality of substrates 310, and two opposite sides of the printed circuit board 300 Embodiments such as the device 200 can all be carried, and will not be described here one by one.
  • the present application also provides a method for manufacturing the above-mentioned printed circuit board 300, including the following steps:
  • the dielectric layer 320 is made of the same material as a whole, steps such as window opening, alignment, and pre-stacking required when using two different materials are omitted.
  • the method for printing the circuit board 100 is simpler, and the manufacturing cost is also reduced.
  • the beneficial effect of the printed circuit board 300 manufactured based on this method is also similar to that of the above-mentioned printed circuit board 300 , and this description will not repeat them here.
  • the printed circuit board 300 shown in FIG. 22 and the printed circuit board 300 manufactured based on the steps shown in FIGS. Circuit board 100 has similar beneficial effects.
  • the board-level architecture 400 provided by this embodiment is assembled in an electronic device, it can also improve the reliability and service life of the electronic device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente demande concerne une carte de circuit imprimé et son procédé de fabrication, une architecture au niveau de la carte et un dispositif électronique équipé de l'architecture au niveau de la carte. La carte de circuit imprimé comprend un substrat et une couche diélectrique recouvrant une surface du substrat. Un plot est en outre disposé sur la surface de la couche diélectrique à l'opposé du substrat, et le plot est utilisé pour connecter un dispositif externe. La couche diélectrique comprend une première région diélectrique et une seconde région diélectrique, et la projection verticale du plot sur la couche diélectrique est située dans la première région diélectrique. Le matériau de la première région diélectrique est un premier diélectrique, le matériau de la seconde région diélectrique est un second diélectrique, le module de Young du premier diélectrique est inférieur à celui du second diélectrique, et/ou le coefficient de dilatation thermique du premier diélectrique est inférieur à celui du second diélectrique. Le premier diélectrique ayant un module de Young inférieur et/ou un coefficient de dilatation thermique inférieur est disposé en correspondance à l'emplacement du plot, de sorte que la contrainte de fatigue thermique à l'emplacement du plot peut être réduite et que la durée de vie de la carte de circuit imprimé est prolongée. Le dispositif électronique de la présente demande comprend la carte de circuit imprimé.
PCT/CN2022/133264 2021-11-27 2022-11-21 Carte de circuit imprimé et son procédé de fabrication, architecture au niveau de la carte et dispositif électronique WO2023093680A1 (fr)

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CN202111426426.XA CN114126206A (zh) 2021-11-27 2021-11-27 印制电路板及其制作方法、板级架构和电子设备
CN202111426426.X 2021-11-27

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1558710A (zh) * 2003-02-28 2004-12-29 ���ְ�˹��ʽ���� 具有阻止变形部件的电路板及电路板的形成方法
JP2007095727A (ja) * 2005-09-27 2007-04-12 Sanyo Electric Co Ltd セラミック基板およびこれを用いた電子デバイス
JP2012064868A (ja) * 2010-09-17 2012-03-29 Mitsubishi Electric Corp 電子部品
CN114126206A (zh) * 2021-11-27 2022-03-01 华为技术有限公司 印制电路板及其制作方法、板级架构和电子设备

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101055504B1 (ko) * 2009-07-30 2011-08-08 삼성전기주식회사 인쇄회로기판 및 그 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1558710A (zh) * 2003-02-28 2004-12-29 ���ְ�˹��ʽ���� 具有阻止变形部件的电路板及电路板的形成方法
JP2007095727A (ja) * 2005-09-27 2007-04-12 Sanyo Electric Co Ltd セラミック基板およびこれを用いた電子デバイス
JP2012064868A (ja) * 2010-09-17 2012-03-29 Mitsubishi Electric Corp 電子部品
CN114126206A (zh) * 2021-11-27 2022-03-01 华为技术有限公司 印制电路板及其制作方法、板级架构和电子设备

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