WO2023092506A1 - 像素阵列驱动方法、装置和显示面板 - Google Patents

像素阵列驱动方法、装置和显示面板 Download PDF

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Publication number
WO2023092506A1
WO2023092506A1 PCT/CN2021/133725 CN2021133725W WO2023092506A1 WO 2023092506 A1 WO2023092506 A1 WO 2023092506A1 CN 2021133725 W CN2021133725 W CN 2021133725W WO 2023092506 A1 WO2023092506 A1 WO 2023092506A1
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Prior art keywords
sub
pixels
row
pixel
signal
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PCT/CN2021/133725
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English (en)
French (fr)
Inventor
陈美珍
刁凯
侯清娜
陈信
谢洪洲
田影
余仁惠
刘晓阳
林疏链
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/922,021 priority Critical patent/US20240221695A1/en
Priority to CN202180003628.5A priority patent/CN116710995A/zh
Priority to PCT/CN2021/133725 priority patent/WO2023092506A1/zh
Publication of WO2023092506A1 publication Critical patent/WO2023092506A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance

Definitions

  • Embodiments of the present disclosure relate to a pixel array driving method, device and display panel.
  • a pixel array of a liquid crystal display panel usually includes multiple rows of gate lines and multiple columns of data lines intersecting with them.
  • the driving of the gate lines can be realized by an integrated driving circuit.
  • the gate driver circuit can also be directly integrated on the thin film transistor array substrate to prepare GOA (Gate driver On Array) as the gate driver circuit. Drive the gate lines.
  • GOA Gate driver On Array
  • the GOA technology helps to achieve a narrow frame design of the display panel, and can reduce the production cost of the display panel.
  • At least one embodiment of the present disclosure provides a method for driving a pixel array.
  • the pixel array includes multiple rows and multiple columns of sub-pixels, multiple gate lines and multiple data lines intersect to define multiple rows and multiple columns of sub-pixels, and the data lines electrically connected to the sub-pixels pass through switches.
  • the module is electrically connected to the data signal end, and the switch module receives a selection control signal to switch the connection state between the data line and the data signal end.
  • the multiple rows of sub-pixels include adjacent first row of sub-pixels and second row of sub-pixels.
  • the method includes: Gate signals are applied to gate lines corresponding to the subpixels in the first row and the subpixels in the second row, and the gate signals include an on state and an off state; during the period when the gate signal is applied to the subpixels in the second row to control the subpixels in the second row, After the gate signal applied to the sub-pixels in the first row is switched from the on state to the off state for a first length of time, the selection control signal corresponding to the sub-pixels in the second row controls the switch module to switch the connection state, the first The length of time is greater than 0.
  • each row of sub-pixels is divided into multiple sub-pixel groups, and multiple data lines electrically connected to multiple sub-pixels in each sub-pixel group are respectively connected to a data line through a switch module.
  • the signal terminals are electrically connected
  • the switch module corresponding to each sub-pixel includes a plurality of switch elements
  • the selection control signal includes a plurality of selection control signals
  • the plurality of switch elements respectively receive a plurality of selection control signals, so as to switch the switching elements correspondingly connected to the plurality of switch elements.
  • each sub-pixel group includes a first sub-pixel and a second sub-pixel, the data line connected to the first sub-pixel is connected to the data signal terminal through the first switching element, and the second The data line connected to the sub-pixel is connected to the data signal terminal through the second switch element, and the multiple selection control signals include the first selection control signal and the second selection control signal;
  • the first selection control signal and the second selection control signal are respectively applied to the first switching element and the second switching element corresponding to each sub-pixel group in the second row of sub-pixels, so that the first switching element and the second switching element The elements are turned on sequentially.
  • the second time length is greater than 0.
  • two sub-pixels separated by one column in each row of sub-pixels are respectively used as a first sub-pixel and a second sub-pixel to form a sub-pixel group.
  • the value range of the ratio of the first time length to the second time length is [0.8, 3.0].
  • the second time length is the time length required for the data signal end to switch from the first data signal to the second data signal, the first switch element is switched from on to off
  • the length of time required to be turned on and the length of time required for the second switching element to be switched from being off to being on are determined.
  • each sub-pixel group includes N sub-pixels, N is an integer greater than or equal to 2, and the gate signal is a periodic signal.
  • the value range of the ratio between the third time length T3 and the first time length T1 is [1.0, 5.0].
  • the value range of the ratio between the second time length T2 and the pulse width is [0.3, 2].
  • the value range of the ratio between the first time length T1 and the pulse width is [0.7, 3.0].
  • the first time length is positively related to the length of the connection line of the first row of sub-pixels, and the connection line is used to connect the signal source of the gate signal to the corresponding gate of each row of sub-pixels. the receiving end of the line.
  • the method further includes determining a first time length corresponding to the longest connection line among the plurality of connection lines of the sub-pixels in the first row;
  • the first time length is to determine the first time length corresponding to other connection lines except the longest connection line among the plurality of connection lines.
  • the method further includes dividing the pixel array into a plurality of regions, each region including multiple consecutive rows of sub-pixels;
  • the first time length corresponding to the longest connecting line in the line including: determining the far-end region farthest from the signal source of the gate signal from multiple regions; Connecting line, determine the first time length corresponding to the longest connecting line; determine the first time length corresponding to other connecting lines in multiple connecting lines except the longest connecting line according to the first time length corresponding to the longest connecting line , including: determining a first time length for multiple rows of sub-pixels in each region according to the first time length corresponding to the longest connection line.
  • At least one embodiment of the present disclosure provides a display panel.
  • the display panel includes a pixel array formed by multiple rows and columns of sub-pixels. Multiple gate lines and multiple data lines intersect to define multiple rows and multiple columns of sub-pixels.
  • the data lines electrically connected to the sub-pixels pass through
  • the switch module is electrically connected to the data signal end, and the switch module receives a selection control signal to switch the connection state between the data line and the data signal end.
  • the multiple rows of sub-pixels include the adjacent first row of sub-pixels and the second row of sub-pixels.
  • the pixel and the second row of sub-pixels respectively receive the gate signal of the corresponding gate line, and the gate signal includes an on state and an off state; during applying the gate signal to the second row of sub-pixels to control the second row of sub-pixels, and during After the gates of the first row of sub-pixels are successively switched from the on state to the off state for a first length of time, the switch module of the second row of sub-pixels receives a selection control signal to control the switch module of the second row of sub-pixels to switch the connection state .
  • each row of sub-pixels is divided into multiple sub-pixel groups, and multiple data lines electrically connected to multiple sub-pixels in each sub-pixel group are respectively connected to a data line through a switch module.
  • the signal terminals are electrically connected
  • the switch module corresponding to each sub-pixel includes a plurality of switch elements
  • the selection control signal includes a plurality of selection control signals
  • the plurality of switch elements respectively receive a plurality of selection control signals, so as to switch the switching elements correspondingly connected to the plurality of switch elements.
  • each sub-pixel group includes a first sub-pixel and a second sub-pixel
  • the data line connected to the first sub-pixel is connected to the data signal terminal through the first switch element
  • the second The data line connected to the sub-pixel is connected to the data signal terminal through the second switch element
  • the multiple selection control signals include the first selection control signal and the second selection control signal
  • the second time length between the switching of the first switch element from on to off and the conduction of the second switch element, and the second time length is greater than zero.
  • the display panel includes a non-display area and a display area, the pixel array is located in the display area, and the non-display area includes a signal source of a gate signal.
  • At least one embodiment of the present disclosure provides a driving device for a pixel array.
  • the pixel array includes multiple rows and multiple columns of sub-pixels. Multiple gate lines and multiple data lines intersect to define multiple rows and multiple columns of sub-pixels.
  • the data lines electrically connected to the sub-pixels pass through switches.
  • the module is electrically connected to the data signal end, and the switch module receives the selection control signal to switch the connection state between the data line and the data signal end.
  • the multiple rows of sub-pixels include the adjacent first row of sub-pixels and the second row of sub-pixels.
  • the driving device includes: The electrode driving circuit is configured to apply gate signals to the gate lines corresponding to the sub-pixels in the first row and the second sub-pixels respectively, and the gate signal includes an on state and an off state; a control circuit is configured to apply a gate signal to the sub-pixels in the second row applying a selection control signal, wherein, during the period of applying the gate signal to the sub-pixels of the second row to control the sub-pixels of the second row, at the first time when the gate signal applied to the sub-pixels of the first row is switched from an on state to an off state After the length, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state, the data driving circuit includes a data signal terminal, configured to provide a data signal to a data line connected to the data signal terminal, the first The length of time is greater than 0.
  • FIG. 1A shows a schematic diagram of a display panel
  • FIG. 1B shows a schematic diagram of the timing relationship of a cycle group
  • FIG. 1C and FIG. 1D show schematic diagrams of pixel misfilling in a display screen provided by at least one embodiment of the present disclosure
  • FIG. 2A shows a flowchart of a method for driving a pixel array provided by at least one embodiment of the present disclosure
  • FIG. 2B shows a timing diagram of a driving method of a pixel array provided by at least one embodiment of the present disclosure
  • FIG. 2C shows a schematic diagram of connection between sub-pixels and data signal terminals provided by at least one embodiment of the present disclosure
  • FIG. 2D shows a schematic diagram of a timing sequence of a sub-pixel group including 3 sub-pixels provided by at least one embodiment of the present disclosure
  • Fig. 3 shows a display panel provided by at least one embodiment of the present disclosure
  • FIG. 4 shows a timing diagram of gate signals received by each row of sub-pixels in the display panel shown in FIG. 3 provided by at least one embodiment of the present disclosure
  • Fig. 5 shows a flowchart of another driving method provided by at least one embodiment of the present disclosure.
  • FIG. 6 shows a block diagram of a driving device according to at least one embodiment of the present disclosure.
  • GOA can be used to provide gate signals (scanning signals) for multiple rows of gate lines in the pixel array, thereby controlling multiple rows of sub-pixels to be turned on sequentially, and at the same time, the data lines provide data signals to sub-pixels of corresponding rows in the pixel array, A frame of image is displayed by forming the grayscale voltage required for displaying an image in each sub-pixel. More and more current display panels use GOA technology to prepare gate drive circuits, so as to drive the gate lines.
  • FIG. 1A shows a schematic diagram of a display panel 100 .
  • the display panel 100 includes multiple rows and multiple columns of sub-pixels 101 arranged in an array.
  • each row of sub-pixels is connected to the same gate line 102 to receive gate signals
  • each column of sub-pixels is connected to the same data line 103 , so multiple gate lines and multiple data lines intersect to define multiple rows and multiple columns of sub-pixels.
  • the sub-pixels connected to the same gate line are regarded as the same row of sub-pixels, and the same row of sub-pixels may or may not be arranged in the same row.
  • the sub-pixels connected to the same data line As the same column, the same column of sub-pixels may or may not be arranged in the same column.
  • the present invention is also applicable to a double-gate structure, that is, two adjacent rows of sub-pixels include two gate lines, and one row of sub-pixels consists of two
  • the grid line control is not limited here.
  • the display panel 100 may be, for example, a liquid crystal display panel or an OLED display panel.
  • the display panel is a liquid crystal display panel, and the display panel includes an array substrate and an opposite substrate, and a liquid crystal layer is interposed between the array substrate and the opposite substrate.
  • Gate lines, data lines, sub-pixels, etc. are formed on the array substrate.
  • a sub-pixel includes a pixel electrode, a switching element, etc., and the switching element of the pixel unit is coupled to a corresponding gate line and a data line, so as to receive a gate signal and a data signal provided by the gate line and the data line.
  • the data lines electrically connected to the sub-pixels are electrically connected to a plurality of data signal terminals ( S1 , . . . , Sn) through a plurality of switch modules.
  • Multiple switch modules may correspond to multiple data signal terminals one by one, or k (integer greater than 0) switch modules may correspond to one data signal terminal.
  • Each switch module receives a selection control signal to switch the connection state of the data line and the data signal end.
  • each column of sub-pixels is connected to the same switch module, and the same switch module controls the connection state of the column of sub-pixels to the data signal terminal.
  • the switch module controls the data line to be connected to the data signal terminal, and when the selection control signal is at a low level, the switch module controls the data line to be disconnected from the data signal terminal.
  • the gate signal includes an on state and an off state.
  • the switch module of the row of sub-pixels controls the data lines connected to the multiple sub-pixels to conduct with the data signal terminal, the data signal terminal Charge the multiple sub-pixels to write the data signal at the data signal end to the multiple sub-pixels.
  • the pixel array includes N rows, N is an integer greater than 1, the subpixels in the PI ⁇ 1> row receive the gate signal CK1, the subpixels in the PI ⁇ 2> row receive the gate signal CK2, ... . . . the sub-pixels in the PI ⁇ N> row receive the gate signal CKN. It should be noted that the number of rows of sub-pixels included in the display panel can be set as required.
  • 8 gate signals are formed into a cycle group, and the gate signals are respectively applied to each row of sub-pixels of the pixel array. It should be understood that although the embodiment of the present disclosure uses 8 gate signals as a cyclic group for illustration, the present disclosure does not limit the number of gate signals in a cyclic group, for example, 6 or 12 gate signals may also be used. Signals are a cyclic group.
  • FIG. 1B shows a schematic diagram of the timing relationship of a cyclic group.
  • the eight gate signals are respectively CK1 , CK2 , CK3 , CK4 , CK5 , CLK6 , CK7 and CK8 , corresponding to different clock signals applied to the gate drive circuit.
  • the duty cycles of the gate signals CK1 to CK8 are all 25% and the periods are equal.
  • each of CK1 to CK8 has a high level time of 2H and a low level time of 6H.
  • H is the length of time required to charge a row of sub-pixels.
  • the duration of the high level of the gate signal is 2H
  • the sub-pixels in the row corresponding to the gate signal are precharged.
  • the overlapping part between the time when the gate signal of the first row of subpixels is turned on and the time when the second row of subpixel gate signals is turned on is the second row
  • the non-overlapping part between the time when the gate signal of the first row of sub-pixels is turned on and the time when the second row of sub-pixel gate signals is turned on is the actual charging time of the second row of sub-pixels.
  • the data signal terminal charges the sub-pixels of the row corresponding to the gate signal to write the data signal into the sub-pixels of the corresponding row.
  • the selection control signal MUX1 controls the data lines and data signal terminals of the first part of the subpixels in a row of subpixels to be turned on, so that the data signal terminals give the first part of subpixels Charge.
  • MUX2 controls the data lines and data signal terminals of the second part of the subpixels in a row of subpixels to be turned on, so that the data signal terminals charge the second part of the subpixels,
  • the selection control signal MUX1 corresponding to the gate signal CK2 of the next row is also immediately turned on and switched to high level to transfer to the second row of sub-pixels.
  • the first part of the sub-pixels in the charge is kept for a time of H/2.
  • the selection control signal MUX1 is switched to a low level
  • the selection control signal MUX2 is also switched to a high level synchronously, and the maintenance time is H/2, so as to transfer to the second row of sub-pixels
  • the second part of the subpixels in the pixel charges before switching low.
  • the delay of resistance and capacitance is relatively large.
  • the gate of the first row of sub-pixels is turned on.
  • the gate signal of the first row of sub-pixels is switched from high level to low level, for example, due to the influence of resistance and capacitance impedance, the gate signal is delayed, and immediate switching cannot be realized.
  • FIG. 1C and FIG. 1D are schematic diagrams of pixel misfilling in a display screen provided by at least one embodiment of the present disclosure.
  • FIG. 1C shows the display picture of the next frame (that is, the display picture of the second frame) among the two adjacent frames of display pictures sequentially displayed by the pixel array.
  • FIG. 1D shows an actual view of the eyepiece of the second frame of the display screen shown in FIG. 1C .
  • pixel 1 is black
  • pixel 2 is white
  • pixel 3 is white
  • pixel 4 is black
  • pixel 1 is white
  • pixel 2 is black
  • pixel 3 is black
  • pixel 4 is white.
  • the sub-pixels 110 in the mth row of the second frame display picture have pixel misfilling and appear jagged.
  • the area surrounded by the dotted oval circle in FIG. 1C and FIG. 1D is the area where the sub-pixels 110 in the mth row are located.
  • the pixel of the second frame display screen is wrongly filled because when at least part of the sub-pixels in the mth row are not turned off, the data signal terminal has already written data to the m+1th row, so that the data signal of the m+1th row is also blocked.
  • Write line m Since some sub-pixels in the m-th row have been turned off, while other sub-pixels are not turned off, the pixels in the m-th row in the second frame of the display screen are displayed as jagged.
  • At least one embodiment of the present disclosure provides a driving method of a pixel array, the driving method includes applying a gate signal to gate lines respectively corresponding to the first row of sub-pixels and the second sub-pixel, the gate signal includes turning on state and off state, the first row of sub-pixels and the second row of sub-pixels are two adjacent rows of sub-pixels; during the period of applying gate signals to the second row of sub-pixels to control the second row After the gate signal applied to the sub-pixels is switched from the on state to the off state for a first time period, a selection control signal corresponding to the sub-pixels of the second row is applied, and the first time period is greater than 0.
  • This method can alleviate problems such as wrong charging of pixels and abnormal display of the picture caused by the sub-pixels in the first row not being completely closed.
  • FIG. 2A shows a flowchart of a method for driving a pixel array provided by at least one embodiment of the present disclosure.
  • the method may include steps S10-S20.
  • Step S10 applying a gate signal to gate lines respectively corresponding to the first row of sub-pixels and the second sub-pixel, the gate signal includes an on state and an off state.
  • Step S20 during the period of applying the gate signal to the sub-pixels in the second row to control the sub-pixels in the second row, after the first time period in which the gate signal applied to the sub-pixels in the first row is switched from the on state to the off state, corresponding The selection control signal of the sub-pixels in the second row controls the switch module to switch the connection state.
  • the driving method provided by at least one embodiment of the present disclosure can be applied to the pixel array as shown in FIG. 1A .
  • the pixel array includes multiple rows and multiple columns of sub-pixels, multiple gate lines and multiple data lines intersect to define multiple rows and multiple columns of sub-pixels, the data lines electrically connected to the sub-pixels are electrically connected to the data signal terminal through the switch module, and the switch module receives the selection control signal To switch the connection state of the data line and the data signal terminal.
  • the switch module receives the selection control signal To switch the connection state of the data line and the data signal terminal.
  • the multiple rows of sub-pixels include adjacent first row of sub-pixels and second row of sub-pixels, that is, the first row of sub-pixels and the second row of sub-pixels may be any two rows of adjacent sub-pixels.
  • two adjacent rows of sub-pixels do not refer to two adjacent rows of sub-pixels in the arrangement of the pixel array, but refer to the timing of the gate signal two adjacent rows of sub-pixels.
  • two rows of sub-pixels adjacent in time sequence refer to two rows of sub-pixels with a difference of 1 time unit between gate signals, and 1 time unit may be the length of time for charging one row of sub-pixels.
  • PI ⁇ 1> is the first row of sub-pixels
  • PI ⁇ 2> is the same as PI ⁇ 1>
  • PI ⁇ 3> is the first row of sub-pixels
  • PI ⁇ 4> is the second row of sub-pixels adjacent to PI ⁇ 3>.
  • PI ⁇ 8> and PI ⁇ 11> can be two adjacent rows of sub-pixels, the first One row of sub-pixels is PI ⁇ 11>, and the second row of sub-pixels is PI ⁇ 8>.
  • the subpixels of other rows can be the first row of subpixels, and except for the first row of subpixels in the pixel array, the subpixels of other rows Each pixel may be a second row of sub-pixels.
  • step S10 gate signals are sequentially applied to the gate lines corresponding to the subpixels in the first row and the subpixels in the second row respectively, and the gate signals of the subpixels in the second row are delayed by 1H from the gate signals of the subpixels in the first row.
  • multiple gate signals are sequentially applied to multiple gate lines corresponding to multiple rows of sub-pixels in the pixel array.
  • FIG. 2B shows a timing diagram of a driving method of a pixel array provided by at least one embodiment of the present disclosure.
  • the sub-pixels in the first row and the sub-pixels in the second row are two adjacent rows of sub-pixels.
  • the gate signals of the subpixels in the second row are adjacent to the gate signals of the subpixels in the first row in timing, and the gate signals of the subpixels in the second row are delayed by 1H from the gate signals of the subpixels in the first row.
  • step S20 during the period of applying a gate signal to each row of subpixels in the plurality of rows of subpixels to control each row of subpixels, a selection control signal corresponding to each row of subpixels is applied.
  • the selection control signal corresponding to the sub-pixels in the second row controls the switch module to switch the connection state after a first period of time when the gate signal applied to the sub-pixels in the first row is switched from the on state to the off state.
  • the selection control signal of the sub-pixels in the second row controls the switch module to turn on the data lines and data signal lines corresponding to the first part of the sub-pixels in the second row of sub-pixels.
  • the on state of the gate signal is high level
  • the off state of the gate signal is low level
  • the selection control signal is high level
  • the switch module conducts the data line and the data signal terminal.
  • the gate signal of the second subpixel is at high level
  • the gate signal applied to the first row of subpixels is switched from high level to low level at time t1, and at time t2, the selected The control signal MUX1 is switched from low level to high level to control the switch module to turn on the data lines and data signal terminals corresponding to the first part of sub-pixels in the second row of sub-pixels.
  • Time t2 is later than time t1 for the duration of T1, and T1 is greater than 0.
  • the level reaches 90% of the highest level it is regarded as the level reaches the high level
  • the level reaches 10% of the lowest level it is regarded as the level reaches the low level.
  • the first time length T1 makes the gate signal applied to the sub-pixels in the first row be in an off state when the selection control signal is applied to the sub-pixels in the second row.
  • the selection control signal of the second row of subpixels controls the corresponding second row of subpixels again.
  • the switching module of the pixel is switched from off to on, so that the first row of subpixels is fully turned off before charging the second row of subpixels to write data signals, thereby alleviating the The resulting pixels are wrongly charged, and the display screen is displayed abnormally.
  • FIG. 2C shows a schematic diagram of connections between sub-pixels and data signal terminals provided by at least one embodiment of the present disclosure.
  • each row of sub-pixels is divided into multiple sub-pixel groups, and multiple data lines electrically connected to the multiple sub-pixels in each sub-pixel group are respectively electrically connected to a data signal terminal through the switch module.
  • each sub-pixel group includes a first sub-pixel and a second sub-pixel
  • the data line connected to the first sub-pixel is connected to the data signal terminal through the first switch element
  • the data line connected to the second sub-pixel is connected to the data signal terminal through the second switch element.
  • Data signal terminal connection
  • the same row of sub-pixels includes sub-pixels 201 to 208, etc., wherein, sub-pixel 201 and sub-pixel 203 are a sub-pixel group, sub-pixel 202 and sub-pixel 204 are a sub-pixel group, and the sub-pixel 205 and sub-pixel 207 are a sub-pixel group, and sub-pixel 206 and sub-pixel 208 are a sub-pixel group.
  • This embodiment does not limit the specific position of the row of sub-pixels.
  • sub-pixel 201 and sub-pixel 203 constitute a sub-pixel group
  • sub-pixel 202 and sub-pixel 204 constitute a sub-pixel group
  • sub-pixel 205 and sub-pixel 207 constitute a sub-pixel group
  • sub-pixel 206 and sub-pixel 208 constitute a sub-pixel group.
  • the switch module corresponding to the sub-pixel group composed of the sub-pixel 201 and the sub-pixel 203 includes a switch element 211 and a switch element 213, and the data lines electrically connected to the sub-pixel 201 and the sub-pixel 203 pass through the switch element 211 and the switch element 213 respectively. It is electrically connected with the data signal terminal S1.
  • the switch module corresponding to the sub-pixel group composed of the sub-pixel 202 and the sub-pixel 204 includes a switch element 212 and a switch element 214, and the data lines electrically connected to the sub-pixel 202 and the sub-pixel 204 are electrically connected to the data signal terminal S2 through the switch element 212 and the switch element 214 respectively. connect.
  • the switch module corresponding to the sub-pixel group composed of the sub-pixel 205 and the sub-pixel 207 includes a switch element 215 and a switch element 217, and the data line electrically connected to the sub-pixel 205 and the sub-pixel 207 is electrically connected to the data signal terminal S3 through the switch element 215 and the switch element 217 respectively. connect.
  • the switch module corresponding to the sub-pixel group composed of the sub-pixel 206 and the sub-pixel 208 includes a switch element 216 and a switch element 218, and the data line electrically connected to the sub-pixel 206 and the sub-pixel 208 is electrically connected to the data signal terminal S4 through the switch element 216 and the switch element 218 respectively. connect.
  • the switching element may be, for example, a thin film transistor.
  • the selection control signal includes a plurality of selection control signals.
  • the multiple selection control signals are respectively applied to different sub-pixels in a sub-pixel group.
  • the plurality of selection control signals include a first selection control signal and a second selection control signal; during applying a gate signal to the second row of subpixels to control the second row of subpixels, each subpixel in the second row of subpixels A first selection control signal and a second selection control signal are respectively applied to the first switch element and the second switch element corresponding to the group, so that the first switch element and the second switch element are sequentially turned on.
  • the selection control signal of each row of sub-pixels includes a selection control signal MUX1 and a selection control signal MUX2 .
  • selection control signals may be applied to a plurality of sub-pixels through a plurality of signal lines, respectively.
  • the selection control signal MUX1 includes MUX1_1 , MUX1_2 , MUX1_3 and MUX1_4
  • the selection control signal MUX2 includes MUX2_1 , MUX2_2 , MUX2_3 and MUX2_4 .
  • MUX1_1 , MUX1_2 , MUX1_3 , and MUX1_4 are signals with the same timing, and MUX2_1 , MUX2_2 , MUX2_3 , and MUX2_4 are signals with the same timing.
  • MUX1_1 , MUX1_2 , MUX1_3 , and MUX1_4 come from 4 signal lines respectively, and MUX2_1 , MUX2_2 , MUX2_3 , and MUX2_4 come from 4 signal lines respectively, which can improve the driving capability of the selection control signal.
  • a selection control signal is applied to a plurality of sub-pixels through one signal line.
  • MUX1 comes from one signal line
  • the selection control signal MUX1 is provided to sub-pixel 201 , sub-pixel 202 , sub-pixel 205 and sub-pixel 206 through one signal line.
  • MUX2 comes from another signal line through which the selection control signal MUX2 is supplied to the sub-pixel 203 , the sub-pixel 204 , the sub-pixel 207 and the sub-pixel 208 .
  • the switch element 211 and the switch element 213 receive the selection control signal MUX1 and the selection control signal MUX2 respectively, so as to switch the connection status of the plurality of data lines connected to the switch element 211 and the switch element 213 respectively and the data signal terminal S1 .
  • the selection control signal MUX1 and the selection control signal MUX2 are respectively applied to the first switching element and the second switching element.
  • the first switching element and the second switching element are sequentially turned on by the selection control signal MUX1 and the selection control signal MUX2 .
  • the switch element 211 turns on the data line corresponding to the sub-pixel 201 and the data signal terminal S1 to charge the sub-pixel 201, and the switch element 213 is turned off.
  • the sub-pixel groups composed of other sub-pixel groups and the sub-pixel 201 and the sub-pixel 203 will not be repeated here.
  • the data lines corresponding to the sub-pixel 201, the sub-pixel 202, the sub-pixel 205, and the sub-pixel 206 are connected to the data signal terminal S1, the data signal terminal S2, and the data signal terminal respectively.
  • S3 and the data signal terminal S4 are turned on to charge the sub-pixel 201 , the sub-pixel 202 , the sub-pixel 205 and the sub-pixel 206 respectively through the data signal terminal S1 , the data signal terminal S2 , the data signal terminal S3 and the data signal terminal S4 .
  • the data lines corresponding to the sub-pixel 203, the sub-pixel 204, the sub-pixel 207 and the sub-pixel 208 are respectively connected to the data signal terminal S1, the data signal terminal S2, the data signal terminal S3 and the data signal terminal S1.
  • the signal terminal S4 is turned on to charge the sub-pixel 203 , the sub-pixel 204 , the sub-pixel 207 and the sub-pixel 208 respectively through the data signal terminal S1 , the data signal terminal S2 , the data signal terminal S3 and the data signal terminal S4 .
  • sub-pixel 201, sub-pixel 202 and sub-pixel 203 are red light sub-pixel, green light sub-pixel and blue light sub-pixel respectively
  • sub-pixel 204, sub-pixel 205 and sub-pixel 206 are red light sub-pixel, green light sub-pixel and blue light sub-pixel respectively.
  • each sub-pixel group includes at least two sub-pixels.
  • the length of time, the second length of time is greater than 0.
  • the selection control signal MUX1 is switched from high level to low level at time t3, so that the data lines and The data signal terminal is switched from on to off, and after the second time length T2 at time t3, the selection control signal MUX2 is switched from low level to high level, so as to control the switch module to turn on the second part of the second row of sub-pixels
  • the second time length T2 is greater than 0.
  • the data lines corresponding to the second part of the subpixels in the second row of subpixels are turned on with the data signal end, thereby The display quality is further improved, and it is more in line with the characteristics of the display panel.
  • the second time length is based on the time length required for the data signal end to switch from the first data to the second data, the time length required for the first switch element to switch from on to off, and The second switch is determined by the length of time required to switch from off to on.
  • the second time length T2 is the time length required for the data signal end to switch from the first data to the second data, the time length required for the first switch element to be switched from on to off, and the time required for the second switch to be switched from off to off.
  • the time length required for the first switch element to be switched from on to off is the time length T22 required for the selection control signal MUX1 corresponding to the first switch element to be switched from high level to low level.
  • the time length required for the second switch to switch from off to on is the time length T23 required for the selection control signal MUX2 corresponding to the second switch element to switch from low level to high level.
  • each sub-pixel group includes N sub-pixels, N is an integer greater than or equal to 2, the gate signal is a periodic signal, and the third time length during which the gate signal is in the on state in each cycle
  • the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state, and the calculation formula of the pulse width of the selection control signal is:
  • W represents the pulse width
  • T3 represents the third time length
  • T1 represents the first time length
  • T2 represents the second time length.
  • the third time length T3 is the time period during which the gate signal of the second row of subpixels in two adjacent rows of subpixels is in the on state and the gate signal of the first row of subpixels is in the off state, that is, the gate lines of two adjacent rows are turned on The time period for locations where the times do not overlap. As shown in FIG. 2B, within one cycle of the gate signal, the time period during which the gate signal of the second row of subpixels is in the on state and the time period for which the gate signal of the first row of subpixels is in the off state is 1H, so in this example The third time length T3 is 1H.
  • the calculation formula for selecting the pulse width of the control signal is:
  • T4 is the time length between the moment when the gate signal of the second row of sub-pixels is switched from the on state to the off state and the last selection control signal in one sub-pixel group is switched from high level to low level. As shown in FIG. 2B , T4 is the time length between the moment t4 when the gate signal of the second row of sub-pixels is switched from the on state to the off state and the time t5 when the MUX2 is switched from the high level to the low level. This can ensure that the gate signal is always on during charging the sub-pixels in the second row, thereby ensuring sufficient charging of the sub-pixels in the second row.
  • the time length of T4 may be set by those skilled in the art based on experience or actual needs, for example, T4 may also be 50 ns, 100 ns, and so on.
  • FIG. 2D shows a schematic diagram of a timing sequence of a sub-pixel group including 3 sub-pixels provided by at least one embodiment of the present disclosure.
  • the three sub-pixels in the same sub-pixel group are respectively applied with the selection control signal MUX1 , the selection control signal MUX2 and the selection control signal MUX3 .
  • the value range of the ratio of the first time length T1 to the second time length T2 may be [0.8, 3.0].
  • the ratio of the first time length T1 to the second time length T2 may be a value between 1.5 and 2.0.
  • the value range of the ratio between the third time length T3 and the first time length T1 may be [1.0, 5.0].
  • the ratio between the third time length T3 and the first time length T1 is a value between 2.0 and 3.5.
  • the value range of the ratio between the second time length T2 and the pulse width may be [0.3, 2.0].
  • the ratio between the time length T2 and the pulse width is a value between 0.8 and 1.2.
  • the second time length T2 is equal to the pulse width.
  • the value range of the ratio between the first time length T1 and the pulse width may be [0.7, 3.0].
  • the ratio between the first time length T1 and the pulse width is a value between 1.5 and 2.0.
  • the first time length T1 needs to be an appropriate value, so that when the selection control signal is applied to the sub-pixels in the second row, the gate signal applied to the sub-pixels in the first row is in an off state.
  • a plurality of different values may be respectively assigned to the first time length T1, and then a display test is performed for each value to determine an appropriate T1 value from the plurality of different T1 values, so as to alleviate pixel misfilling.
  • the picture used for the display test may be a black and white checkerboard pattern.
  • the gate signal and the selection control signal of the two adjacent rows of sub-pixels are applied to the pixel array according to the timing sequence.
  • Gate signal and selection control signal the pixel array sequentially displays two frames of different black and white checkerboard images. Black pixels in the first black and white checkerboard frame become white pixels in the second black and white checkerboard frame, and white pixels in the first black and white checkerboard frame become black in the second black and white checkerboard frame pixels. Detect whether there is pixel misfill at the black-and-white junction in the second frame. If, when the first time length is the first value, the black and white grid images displayed on the display panel are correct, then the first value meets the display requirements, and the first value can be used as the first time length.
  • multiple values of the first time length T1 may be set sequentially from small to large, and then the above-mentioned display test is performed for each value, so as to determine the minimum value that meets the display requirements from the multiple values, This minimum value is taken as the first time length T1.
  • set the first time length T1 to be 800ns, 900ns, 1000ns, 1100ns, 1200ns, 1300ns, 1400ns, 1500ns respectively, and perform the display test in order of time length from small to large, if the first time length T1 is 800ns, At 900ns, 1000ns, 1100ns, and 1200ns, pixel error charging occurs on the display screen.
  • the first time length T1 is 1300ns, there is no pixel error charging on the display screen, and the minimum value of the first time length T1 is 1300ns.
  • the optimal first time length T1 may be determined from 1200 ns and 1300 ns by using a dichotomy method.
  • the first time length is positively related to the length of the connection line of the first row of sub-pixels, and the connection line is used to connect the signal source of the gate signal and the receiving end of the gate line corresponding to each row of sub-pixels. This embodiment will be described below in conjunction with FIG. 3 .
  • FIG. 3 shows a display panel 200 provided by at least one embodiment of the present disclosure.
  • the display panel 200 includes a display area DR and a non-display area PR other than the display area DR, for example, the non-display area PR surrounds the display area DR.
  • FIG. 3 is only a schematic diagram.
  • the non-display area PR is enlarged. Therefore, the difference between the display area DR and the non-display area PR shown in FIG.
  • the area size relationship between them is not a real size relationship.
  • the area of the display area is generally larger than the area of the non-display area.
  • the display region DR includes a pixel array, and the pixel array includes multiple rows and multiple columns of sub-pixels.
  • the pixel array can be similar to the pixel array in the display panel 100 shown in FIG. 1A, and 1, 2, 3, 4, 5, 6, 7, and 8 in FIG. PI ⁇ 1> row sub-pixels, ..., PI ⁇ 8> row sub-pixels) of the pixel array are connected to gate lines.
  • the non-display region PR includes the gate driving circuit 10 and the gate driving circuit 30 .
  • Each of the gate driving circuit 10 and the gate driving circuit 30 includes a plurality of cascaded shift register units.
  • the multiple cascaded shift register units are, for example, the first-stage shift register unit GOA1 , the second-stage shift register unit GOA2 , . . . the eighth-stage shift register unit GOA8 , and the like. It should be understood that although 8 shift register units are shown in the figure, the present disclosure does not limit the number of shift register units, and the number of shift register units may be determined according to actual needs.
  • the gate lines of multiple sub-pixels in the same row are connected to a shift register unit in the gate driving circuit 10 and the gate driving circuit 30 to receive gate signals output by the shift register unit.
  • a plurality of sub-pixels in a row of sub-pixels close to the gate driving circuit 10 are provided with gate signals by the gate driving circuit 10
  • a plurality of sub-pixels close to the gate driving circuit 30 are provided with gate signals by the gate driving circuit 30 .
  • the display panel may only include one gate drive circuit, and the gate lines of the same row of sub-pixels are connected to a shift register unit of the gate drive circuit, and the shift register unit sends A row of sub-pixels provides gate signals.
  • Each shift register unit has a first voltage terminal VDD1, a second Second voltage terminal VDD2, clock signal terminal CLKi (i is 1, 2, ..., N (N is an integer greater than 1)), third voltage terminal LVGL, fourth voltage terminal VGL, reset signal terminal Total reset, input terminal IN, the first output terminal GOUT and the second output terminal GOUT_C.
  • the input terminal IN of the shift register unit of the k+4th stage and the input terminal IN of the shift register unit of the kth stage An output terminal GOUT_C is connected, and k is an integer greater than or equal to 1.
  • the respective input terminals IN of the first-stage shift register unit to the fourth-stage shift register unit are respectively connected to the signal line STV1, the signal line STV2, the signal line STV3 and the signal line STV4, so as to obtain signals from the signal line STV1, the signal line STV2, the signal line The line STV3 and the signal line STV4 are connected to receive the frame start signal, and optionally, STV1-STV4 are the same frame start signal.
  • the first output terminal GOUT is configured to output the gate signal to the gate line.
  • the shift register units of each stage receive voltage signals from the signal line VDD1, the signal line VDD2, the signal line LVGL, and the signal line VGL, respectively.
  • the voltage signal VDD1 on the signal line VDD1 and the voltage signal VDD2 on the signal line VDD2 are mutually high and low, which can be used in the noise reduction circuit in the shift register unit.
  • the voltage signal VGL on the signal line VGL is used to lower the level of the display area, and the voltage signal LVGL on the signal line LVGL is used to lower the level of the noise reduction circuit.
  • the gate drive circuit 10 and the gate drive circuit 30 each further include a sub-clock signal line CLK1 for transmitting the first sub-clock signal, a sub-clock signal line CLK2 for transmitting the second sub-clock signal, and a sub-clock signal line CLK2 for transmitting the third sub-clock signal.
  • the sub-clock signal line CLK7 for the seventh sub-clock signal, and the sub-clock signal line CLK8 for transmitting the eighth sub-clock signal.
  • the number N of the shift register units included in the gate drive circuit 10 and the gate drive circuit 30 is an integer multiple of 8, and every 8 shift register units are used as a cycle group to respectively receive the sub-clock signal lines CLK1-CLK8 clock signal, and in response to the clock signal, a plurality of first output terminals GOUT output gate signals to a plurality of rows of sub-pixels.
  • the clock signal terminal CLK1 of the first-stage shift register unit is connected to the sub-clock signal line CLK1; the clock signal terminal CLK2 of the second-stage shift register unit is connected to the sub-clock signal line CLK2;
  • the clock signal end CLK3 of the bit register unit is connected to the sub-clock signal line CLK3;
  • the clock signal end CLK4 of the shift register unit of the fourth stage is connected to the sub-clock signal line CLK4;
  • the clock signal end CLK5 of the shift register unit of the fifth stage is connected to the sub-clock signal line CLK5 is connected;
  • the clock signal terminal CLK6 of the sixth-level shift register unit is connected to the sub-clock signal line CLK6;
  • the clock signal terminal CLK7 of the seventh-level shift register unit is connected to the sub-clock signal line CLK2;
  • the clock of the eighth-level shift register unit The signal terminal CLK8 is connected to the sub-clock signal line CLK2; the clock signal terminal CLK9 of the ninth shift register unit is connected to
  • FIG. 3 shows a double-sided drive, that is, the pixels in the same row are driven by the gate drive circuits at the left and right ends.
  • unilateral drive is also possible, for example, only non-display
  • the gate driving circuit on one side of the region may also be driven by bilateral parity, for example, the gate driving circuit on one side drives pixels in odd rows, and the gate driving circuit on the other side drives pixels in even rows, which is not limited here.
  • the gate driving circuit 10 and the gate driving circuit 30 may further include a signal source 11 and a signal source 31 respectively.
  • the signal source 11 is configured, for example, to provide the above-mentioned various signals to the various levels of shift register units of the gate driving circuit 10
  • the signal source 31 is configured, for example, to provide the above-mentioned various signals to the various levels of shift register units of the gate driving circuit 30 .
  • the phase relationship between the multiple clock signals provided by the signal source 11 and the signal source 31 may be determined according to actual requirements. In different examples, more clock signals may also be provided according to different configurations. Since the gate driving circuit 10 is similar to the gate driving circuit 30 , the following uses the gate driving circuit 10 and the signal source 11 as examples to describe embodiments of the present disclosure.
  • the signal source 11 provides a clock signal to each shift register unit through sub-clock signal lines CLK1 to CLK8 respectively, so that each shift register unit outputs a gate signal.
  • each shift register unit outputs the gate signals CK1 - CK8 illustrated in FIG. 1A .
  • the clock signals provided by the sub-clock signal lines CLK1 - CLK8 are the same as the gate signals CK1 - CK8 .
  • the timing of the gate signals output by the eight shift register units shown in FIG. 3 is adjacent to each other in the following order: 1st
  • the gate signal output by the first output terminal GOUT of the stage shift register unit -> the gate signal output by the first output terminal GOUT of the seventh stage shift register unit -> the first output terminal of the eighth stage shift register unit The gate signal output by GOUT.
  • Figure 3 shows that the gate drive circuit includes two output terminals.
  • the GOUT output terminal is used to output the gate drive signal to the corresponding row of pixels
  • GOUT_C is the output terminal used to transmit the cascaded signal.
  • the GOUT_C of the first-stage shift register unit provides input signals for the fifth-stage shift register unit, and the gate drive circuit can also only set the GOUT output terminal, that is, GOUT is used as the output signal of this row, and also as the cascade connection of other rows
  • the input signal is not limited here.
  • connection line is used to connect the signal source of the gate signal and the receiving end of the gate line corresponding to each row of sub-pixels. As shown in FIG. 3 , the connection line refers to the wiring between the signal source 11 and the receiving end of the gate line corresponding to each row of sub-pixels.
  • the signal source may refer to a timing controller IC.
  • the timing controller IC is connected to the CLK line of the display panel through the flexible circuit board after passing through the level-shifter.
  • the display panel is bound by COF (chip on film), that is, the source IC is bound Fixed to the FPC flexible circuit board, one end of the flexible circuit board is bound to the non-display area of the display panel, the other end of the flexible circuit board is bound to the PCB circuit board, and the timing controller IC (TCON- IC), the clock signal output by the timing controller IC is transmitted to the CLK signal line of the display panel through the signal line on the flexible circuit board after passing through the level conversion unit.
  • COF chip on film
  • the signal line of the flexible circuit board and the display can be electrically connected through their respective binding terminals, that is, the pads of the display panel and the gold fingers of the flexible circuit board.
  • the present invention also includes the COG (chip on glass) method, that is, the source IC is directly bound It is set in the non-display area of the display panel, which is not limited here.
  • the wiring includes the sub-clock signal line between the signal source 11 and the shift register units of each level and the wiring between the shift register units of each level and the receiving end of the correspondingly connected gate line.
  • the lengths of the plurality of wires between the receiving ends of the correspondingly connected gate lines are not much different, so the difference in the distance between the receiving end of the gate signal of each row of sub-pixels and the signal source 11 is mainly reflected in the multiple sub-clock signal lines ( That is, the lengths of sub-clock signal lines CLK1 to sub-clock signal lines CLK8) are different.
  • the different lengths here refer to the different distances of electrical transmission signals.
  • Figure 3 shows that the physical lengths of CLK1-CLK8 clock signal lines are different.
  • the physical length of the CLK1-CLK8 clock signal line can also be designed the same, but at this time, the electrical path taken by the signal source to transmit the CLK1 signal corresponding to the first row of pixels is to the position of the black node in the drawing.
  • the electrical transmission path of the CLK8 signal corresponding to the 8 rows of pixels is to the position of the black node in the figure. It can be seen that the electrical transmission path of the CLK signal transmission of the first row of pixels is longer than that of the 8th row of pixels CLK signal transmission .
  • the signal source 11 is located at the lower left corner of the display panel 200, and the sub-clock signal lines CLK1 to CLK8 corresponding to the sub-pixels in the row PI ⁇ 1> to the sub-pixels in the row PI ⁇ 8> are getting shorter and shorter, that is, The connection lines between the sub-pixels in the row PI ⁇ 1> to the sub-pixels in the row PI ⁇ 8> and the signal source 11 are getting shorter and shorter.
  • the sub-clock signal line CLK7 required by the sub-pixels in the seventh row is longer than the sub-clock signal line CLK8 required by the sub-pixels in the eighth row.
  • the gate signals received by each row of sub-pixels have different delays on the sub-clock signal lines.
  • FIG. 4 shows a timing diagram of gate signals received by each row of sub-pixels in the display panel shown in FIG. 3 provided by at least one embodiment of the present disclosure.
  • the sub-pixels in the PI ⁇ 1> row to the PI ⁇ Nth row are getting shorter and shorter, the sub-pixels in the PI ⁇ 1> row to the PI ⁇ Nth row
  • the delay of the gate signal of > is getting shorter and shorter (that is, the time required for the rising edge and the falling edge is getting shorter and shorter)
  • the respective gates of the sub-pixels in the PI ⁇ 1> row to the sub-pixels in the PI ⁇ N> row The time required for the signal to be switched from the on state to the off state is getting shorter and shorter, therefore, the first time length of each row of sub-pixels for switching is also getting shorter and shorter.
  • connection line corresponding to the PI ⁇ 1> line sub-image is longer than the connection line corresponding to the PI ⁇ 2> line sub-image, so the first time length of the PI ⁇ 1> line sub-image for switching is longer than that of the PI ⁇ 2> line sub-image Like the first length of time for switching is long.
  • an appropriate first time length can be set for each row of sub-pixels, which improves display efficiency while alleviating pixel mischarging.
  • Fig. 5 shows a flowchart of another driving method provided by at least one embodiment of the present disclosure.
  • the driving method may further include steps S30 and S40 in addition to steps S10 and S20 .
  • Step S30 and step S40 may, for example, be performed before steps S10 and S20.
  • Step S30 Determine a first time length corresponding to the longest connection line among the plurality of connection lines of the plurality of sub-pixels in the first row.
  • Step S40 According to the first time length corresponding to the longest connection line, determine the first time length corresponding to other connection lines except the longest connection line among the plurality of connection lines.
  • the method can reduce the time for determining the first time length corresponding to each row of sub-pixels, and improve the efficiency of determining the first time length.
  • the first time length corresponding to the longest connection line may be the first time length corresponding to the row of sub-pixels farthest from the signal source.
  • the sub-pixels in the PI ⁇ 1> row are the sub-pixels in the row farthest from the signal source, then in step S30 , the first time length corresponding to the sub-pixels in the PI ⁇ 1> row may be determined.
  • the first time length corresponding to the longest connection line is determined according to the method for performing a display test using a black and white checkerboard picture described above.
  • step S40 for example, according to the first time length corresponding to the sub-pixels in the PI ⁇ 1> row, determine the respective first time lengths of the sub-pixels in the PI ⁇ 2> row, . . . , the sub-pixels in the PI ⁇ N> row.
  • those skilled in the art can determine the difference of the first time length between two adjacent rows based on experience, and then the first time length corresponding to each row of sub-pixels decreases the difference in turn.
  • the first time length corresponding to the shortest connecting line may also be determined, and two adjacent rows may be determined according to the first time length corresponding to the shortest connecting line and the first time length corresponding to the longest connecting line The difference between the first length of time.
  • the driving method may further include step S50 in addition to steps S10 - S40 .
  • Step S50 may, for example, be performed before step S3.
  • Step S50 Divide the pixel array into multiple regions, each region includes multiple rows of continuous sub-pixels.
  • step S30 includes determining the farthest region from the plurality of regions that is farthest from the signal source of the gate signal, and determining the most The first time length corresponding to the long connection line.
  • step S40 includes determining a first time length for multiple rows of sub-pixels in each region according to the first time length corresponding to the longest connection line.
  • the first time lengths corresponding to multiple rows of sub-pixels in each region may be the same.
  • the pixel array is divided into multiple regions, and the first time length is respectively determined for each region, thereby improving calculation efficiency.
  • the number of rows of sub-pixels in each region may be the same or different.
  • the multiple regions of the pixel array can be divided by those skilled in the art according to the circuit routing in the display panel. For example, multiple rows of sub-pixels with similar gate signal delays are divided into one region.
  • the pixel array includes PI ⁇ 1> row of sub-pixels, PI ⁇ 2> row of sub-pixels, ..., PI ⁇ N> row of sub-pixels in total N (N>50) rows of sub-pixels, and PI ⁇ 1> row of sub-pixels Pixels, PI ⁇ 2> rows of sub-pixels, ..., PI ⁇ N> row of sub-pixels, the receiving end of the gate line is getting closer and closer to the signal source, and every 50 rows of sub-pixels are regarded as a region, and the distance from the signal source of the gate signal
  • the farthest remote area of the source is the area where PI ⁇ 1>, PI ⁇ 2>, ..., PI ⁇ 50> are located.
  • determining the first time length corresponding to the longest connection line based on the connection lines corresponding to the plurality of sub-pixels in the first row in the distal region described in step S30 above includes: The first time length corresponding to the first row of sub-pixels farthest from the signal source in the remote region is used as the first time length corresponding to the longest connection line.
  • the first time length corresponding to the sub-pixels in row PI ⁇ 1> is taken as the first time length corresponding to the longest connection line.
  • determining the first time length corresponding to the longest connection line based on the connection lines corresponding to the plurality of sub-pixels in the first row in the far-end region includes: calculating the number of sub-pixels in the far-end region The average value of the first time length corresponding to each of the sub-pixels in the first row is used as the first time length corresponding to the longest connection line.
  • the first time length corresponding to the longest connection line is (T PI ⁇ 1> +T PI ⁇ 2> +...+T PI ⁇ 50> )/50
  • T PI ⁇ 1> , T PI ⁇ 2> , . . . , T PI ⁇ 50> represent the first time lengths corresponding to PI ⁇ 1>, PI ⁇ 2>, . . . , PI ⁇ 50> respectively.
  • determining a first time length for multiple rows of sub-pixels in each region according to the first time length corresponding to the longest connection line described in step S40 above includes: determining an adjacent region The difference between the first time lengths in the first time length is determined according to the difference to determine a first time length for multiple rows of sub-pixels in each region.
  • those skilled in the art can determine the difference of the first time length between two adjacent areas based on experience, and determine the first time length corresponding to each area according to the difference and the first time length corresponding to the longest connecting line. length of time.
  • the multiple rows of sub-pixels in each region correspond to the same first time length.
  • the first time length corresponding to the area closest to the signal source may also be determined, and according to the first time length corresponding to the area closest to the signal source and the first time corresponding to the longest connection line The length determines the difference of the first time length between two adjacent regions.
  • the display panel includes a pixel array formed by multiple rows and columns of sub-pixels, multiple gate lines and multiple data lines cross to define multiple rows and multiple columns of sub-pixels, and the data lines electrically connected to the sub-pixels
  • the switch module is electrically connected to the data signal end, and the switch module receives a selection control signal to switch the connection state between the data line and the data signal end.
  • the multiple rows of sub-pixels include the adjacent first row of sub-pixels and the second row of sub-pixels, the first row of sub-pixels and the second row of sub-pixels respectively receive the gate signal of the corresponding gate line, and the gate signal includes open state and closed state. state.
  • the second row The switch module of the sub-pixel receives the selection control signal to control the switch module of the second row of sub-pixels to switch the connection state.
  • the display panel may be, for example, the example shown in FIG. 1A or FIG. 3 .
  • the display panel please refer to the above description about FIG. 1A or FIG. 3 .
  • each row of sub-pixels is divided into multiple sub-pixel groups, and multiple data lines electrically connected to the multiple sub-pixels in each sub-pixel group are respectively electrically connected to a data signal terminal through a switch module
  • the switch module corresponding to each sub-pixel includes a plurality of switch elements
  • the selection control signal includes a plurality of selection control signals
  • the plurality of switch elements respectively receive a plurality of selection control signals to switch between a plurality of data lines connected to the plurality of switch elements and The connection status of the data signal terminal.
  • each sub-pixel group includes a first sub-pixel and a second sub-pixel, the data line connected to the first sub-pixel is connected to the data signal terminal through the first switching element, and the data line connected to the second sub-pixel is The line is connected to the data signal terminal through the second switch element, and the plurality of selection control signals include the first selection control signal and the second selection control signal; during the second row of sub-pixels receiving gate signals, each sub-pixel in the second row of sub-pixels The first switch element and the second switch element corresponding to the pixel group are respectively turned on in response to the first selection control signal and the second selection control signal.
  • the display panel includes a non-display area and a display area
  • the pixel array is located in the display area
  • the non-display area includes a signal source of a gate signal.
  • the display panel 200 includes a non-display area PR and a display area DR.
  • the pixel array is located in the display area DR, and the non-display area PR includes the signal source 11 and the signal source 31 of the gate signal.
  • the pixel array includes multiple rows and multiple columns of sub-pixels, and multiple gate lines and multiple data lines cross to define multiple rows and multiple columns of sub-pixels.
  • the data line electrically connected to the sub-pixel is electrically connected to the data signal terminal through the switch module, and the switch module receives the selection control signal to switch the connection state between the data line and the data signal terminal.
  • the multiple rows of sub-pixels include the adjacent first row of sub-pixels. pixel and the second row of sub-pixels.
  • FIG. 6 shows a block diagram of a driving device 600 according to at least one embodiment of the present disclosure.
  • the driving device 600 may include a gate driving circuit 601 , a control circuit 602 and a data driving circuit 603 .
  • the driving device 600 may be connected to a pixel array 610 , and the pixel array 610 may be, for example, the pixel array shown in FIG. 1A .
  • the gate driving circuit 601 is configured to apply a gate signal to gate lines respectively corresponding to the sub-pixels in the first row and the second sub-pixel, and the gate signal includes an on state and an off state.
  • the gate driving circuit may be the gate driving circuit 10 and the gate driving circuit 30 in FIG. 3 .
  • the gate driving circuit please refer to the relevant description of the gate driving circuit 10 and the gate driving circuit 30 .
  • the control circuit 602 is configured to apply a selection control signal to the subpixels of the second row, during which the gate signal is applied to the subpixels of the second row to control the subpixels of the second row, and the gate signal applied to the subpixels of the first row is turned on from After the first period of time during which the state is switched to the off state, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state.
  • the first time length is greater than 0.
  • the data driving circuit 603 includes a data signal terminal configured to provide a data signal to a data line connected to the data signal terminal. It should be understood that the number of connection lines in FIG. 6 does not represent the actual number. FIG. 6 only schematically shows the connection relationship between the driving device 600 and the pixel array 610 , which does not limit the present disclosure.

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Abstract

一种像素阵列的驱动方法、装置和显示面板。像素阵列包括多行多列子像素（101），多条栅线（102）和多条数据线（103）交叉限定多行多列子像素（101），子像素（101）电连接的数据线通过开关模块与数据信号端电连接，开关模块接收选择控制信号以切换数据线与数据信号端的连接状态，多行子像素包括相邻的第一行子像素和第二行子像素，驱动方法包括：向第一行子像素和第二子像素分别对应的栅线施加栅极信号(S10)；在对第二行子像素施加栅极信号以控制第二行子像素期间，在向第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，对应于第二行子像素的选择控制信号控制开关模块切换连接状态(S20)。

Description

像素阵列驱动方法、装置和显示面板 技术领域
本公开的实施例涉及一种像素阵列驱动方法、装置和显示面板。
背景技术
在显示技术领域，例如液晶显示面板的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上制备GOA(Gate driver On Array)作为栅极驱动电路来对栅线进行驱动。GOA技术有助于实现显示面板的窄边框设计，并且可以降低显示面板的生产成本。
发明内容
本公开至少一个实施例提供一种像素阵列的驱动方法，像素阵列包括多行多列子像素，多条栅线和多条数据线交叉限定多行多列子像素，子像素电连接的数据线通过开关模块与数据信号端电连接，开关模块接收选择控制信号以切换数据线与数据信号端的连接状态，多行子像素包括相邻的第一行子像素和第二行子像素，该方法包括：向第一行子像素和第二子像素分别对应的栅线施加栅极信号，栅极信号包括开启状态和关闭状态；在对第二行子像素施加栅极信号以控制第二行子像素期间，在向第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，对应于第二行子像素的选择控制信号控制所述开关模块切换所述连接状态，第一时间长度大于0。
例如，在本公开一实施例提供的驱动方法中，每行子像素被划分为多个子像素组，与每个子像素组中的多个子像素电连接的多条数据线分别通过开关模块与一个数据信号端电连接，每个子像素对应的开关模块包括多个开关元件，选择控制信号包括多个选择控制信号，多个开关元件分别接收多个选择控制信号，以切换与多个开关元件对应连接的多条数据线与数据信号端的连接状态。
例如，在本公开一实施例提供的驱动方法中，每个子像素组包括第一子像素和第二子像素，第一子像素连接的数据线通过第一开关元件与数据信号端连接，第二子像素连接的数据线通过第二开关元件与数据信号端连接，多个选择控制信号包括第一选择控制信号和第二选择控制信号；在对第二行子像素施加栅极信号以控制第二行子像素期间， 向第二行子像素中每个子像素组对应的第一开关元件和第二开关元件分别施加第一选择控制信号和第二选择控制信号，使第一开关元件和第二开关元件依次导通。
例如，在本公开一实施例提供的驱动方法中，第一选择控制信号控制第一开关元件由导通向断开切换与第二选择控制信号控制第二开关元件导通之间具有第二时间长度，第二时间长度大于0。
例如，在本公开一实施例提供的驱动方法中，每行子像素中相隔一列的两个子像素分别作为第一子像素和第二子像素，以作为一个子像素组。
例如，在本公开一实施例提供的驱动方法中，第一时间长度与第二时间长度的比值的取值范围为[0.8,3.0]。
例如，在本公开一实施例提供的驱动方法中，第二时间长度是根据数据信号端从第一数据信号切换为第二数据信号所需要的时间长度、第一开关元件由导通切换为断开所需要的时间长度和第二开关元件由断开切换为导通所需要的时间长度确定。
例如，在本公开一实施例提供的驱动方法中，每个子像素组包括N个子像素，N为大于等于2的整数，栅极信号为周期信号，在每个周期内栅极信号处于开启状态期间的第三时间长度内，对应于所述第二行子像素的选择控制信号控制所述开关模块切换所述连接状态，选择控制信号的脉宽的计算公式为：W＝(T3-T1-(N-1)×T2)/N，W表示脉宽，T3表示第三时间长度，T1表示第一时间长度，T2表示第二时间长度。
例如，在本公开一实施例提供的驱动方法中，第三时间长度T3和第一时间长度T1之间的比值的取值范围为[1.0,5.0]。
例如，在本公开一实施例提供的驱动方法中，第二时间长度T2与脉宽之间的比值的取值范围为[0.3,2]。
例如，在本公开一实施例提供的驱动方法中，第一时间长度T1与脉宽之间的比值的取值范围为[0.7,3.0]。
例如，在本公开一实施例提供的驱动方法中，第一时间长度与第一行子像素的连接线长度正相关，连接线用于连接栅极信号的信号源与每行子像素对应的栅线的接收端。
例如，在本公开一实施例提供的驱动方法中，该方法还包括确定多个第一行子像素的多个连接线中最长连接线对应的第一时间长度；根据最长连接线对应的第一时间长度，确定多条连接线中除最长连接线之外的其他连接线对应的第一时间长度。
例如，在本公开一实施例提供的驱动方法中，该方法还包括将像素阵列划分为多个区域，每个区域包括连续的多行子像素；确定多个第一行子像素的多个连接线中最长连接线对应的第一时间长度，包括：从多个区域中确定距离栅极信号的信号源最远的远端 区域；基于远端区域中的多个第一行子像素对应的连接线，确定最长连接线对应的第一时间长度；根据最长连接线对应的第一时间长度，确定多条连接线中除最长连接线之外的其他连接线对应的第一时间长度，包括：根据最长连接线对应的第一时间长度，为每个区域中的多行子像素确定一个第一时间长度。
本公开至少一个实施例提供一种显示面板，显示面板包括多行多列子像素形成的像素阵列，多条栅线和多条数据线交叉限定多行多列子像素，子像素电连接的数据线通过开关模块与数据信号端电连接，开关模块接收选择控制信号以切换数据线与数据信号端的连接状态，多行子像素包括相邻的第一行子像素和第二行子像素，第一行子像素和第二行子像素分别接收对应的栅线的栅极信号，栅极信号包括开启状态和关闭状态；在对第二行子像素施加栅极信号以控制第二行子像素期间，以及在第一行子像素接收到的栅极先后从开启状态向关闭状态切换的第一时间长度之后，第二行子像素的开关模块接收选择控制信号以控制第二行子像素的开关模块切换连接状态。
例如，在本公开一实施例提供的显示面板中，每行子像素被划分为多个子像素组，与每个子像素组中的多个子像素电连接的多条数据线分别通过开关模块与一个数据信号端电连接，每个子像素对应的开关模块包括多个开关元件，选择控制信号包括多个选择控制信号，多个开关元件分别接收多个选择控制信号，以切换与多个开关元件对应连接的多条数据线与数据信号端的连接状态。
例如，在本公开一实施例提供的显示面板中，每个子像素组包括第一子像素和第二子像素，第一子像素连接的数据线通过第一开关元件与数据信号端连接，第二子像素连接的数据线通过第二开关元件与数据信号端连接，多个选择控制信号包括第一选择控制信号和第二选择控制信号；在第二行子像素接收栅极信号期间，第二行子像素中每个子像素组对应的第一开关元件和第二开关元件分别响应第一选择控制信号和第二选择控制信号而依次导通。
例如，在本公开一实施例提供的显示面板中，第一开关元件由导通向断开切换与第二开关元件导通之间具有第二时间长度，第二时间长度大于0。
例如，在本公开一实施例提供的显示面板中，显示面板包括非显示区和显示区，像素阵列位于显示区，非显示区包括栅极信号的信号源。
本公开至少一个实施例提供一种像素阵列的驱动装置，像素阵列包括多行多列子像素，多条栅线和多条数据线交叉限定多行多列子像素，子像素电连接的数据线通过开关模块与数据信号端电连接，开关模块接收选择控制信号以切换数据线与数据信号端的连接状态，多行子像素包括相邻的第一行子像素和第二行子像素，驱动装置包括：栅极驱 动电路，配置为向第一行子像素和第二子像素分别对应的栅线施加栅极信号，栅极信号包括开启状态和关闭状态；控制电路，配置为向所述第二行子像素施加选择控制信号，其中，在对第二行子像素施加栅极信号以控制第二行子像素期间，在向第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，对应于第二行子像素的选择控制信号控制所述开关模块切换所述连接状态，数据驱动电路包括数据信号端，配置为向与数据信号端连接的数据线提供数据信号，第一时间长度大于0。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A示出了一种显示面板的示意图；
图1B示出了一个循环组的时序关系示意图；
图1C和图1D示出了本公开至少一个实施例提供的在显示画面中出现像素错充的示意图；
图2A示出了本公开至少一实施例提供的一种像素阵列的驱动方法的流程图；
图2B示出了本公开至少一个实施例提供的像素阵列的驱动方法的时序示意图；
图2C示出本公开至少一个实施例提供的子像素与数据信号端的连接示意图；
图2D示出了本公开至少一个实施例提供的一种子像素组包括3个子像素的时序示意图；
图3示出了本公开至少一个实施例提供的一种显示面板；
图4示出了本公开至少一个实施例提供的图3所示的显示面板中每行子像素接收到的栅极信号的时序图；
图5示出了本公开至少一个实施例提供的另一种驱动方法的流程图；以及
图6示出了根据本公开至少一个实施例的驱动装置的框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
例如，可以采用GOA为像素阵列的多行栅线提供栅极信号(扫描信号)，从而控制多行子像素依序开启，并且同时由数据线向像素阵列中对应行的子像素提供数据信号，以在各子像素形成显示图像所需要的灰度电压，进而显示一帧图像。目前的显示面板越来越多地采用GOA技术来制备栅极驱动电路，从而对栅线进行驱动。
图1A示出了一种显示面板100的示意图。
如图1A所示，显示面板100包括呈阵列排布的多行多列的子像素101。例如，每行子像素与同一条栅线102连接以接收栅极信号，每列子像素与同一条数据线103连接，这样多条栅线和多条数据线交叉限定了多行多列子像素。在本公开中，与同一条栅线连接的子像素视为同一行子像素，同一行子像素可以排列为同一行也可以不是排列为同一行，类似的，与同一条数据线连接的子像素视为同一列，同一列子像素可以排列为同一列，也可以不是排列为同一列，本发明也适用于双栅结构，即相邻两行子像素中间包括两条栅线，一行子像素由两条栅线控制，在此不做限定。
显示面板100例如可以是液晶显示面板或者是OLED显示面板。例如，该显示面板为液晶显示面板，显示面板包括阵列基板和对置基板，阵列基板和对置基板之间夹置有液晶层。栅线、数据线、子像素等形成在阵列基板上。子像素包括像素电极、开关元件等，像素单元的开关元件与对应的栅线和数据线耦接，以接收栅线和数据线提供的栅极信号和数据信号。
如图1A所示，子像素电连接的数据线通过多个开关模块与多个数据信号端(S1，……，Sn)电连接。多个开关模块与多个数据信号端可以一一对应，或者也可以是k(大于0的整数)个开关模块与一个数据信号端对应。每个开关模块接收一个选择控制信号以切换数据线与数据信号端的连接状态。例如，每列子像素与同一个开关模块连接，由同一个开关模块控制该列子像素与数据信号端的连接状态。
例如，当选择控制信号为高电平时，开关模块控制数据线与数据信号端导通，当选择控制信号为低电平时，开关模块控制数据线与数据信号端断开。
栅极信号包括开启状态和关闭状态，当一行子像素的栅极信号处于开启状态并且该行子像素的开关模块控制与多个子像素分别连接的数据线与数据信号端导通时，数据信号端向该多个子像素充电，以向该多个子像素写入数据信号端的数据信号。
例如，如图1A所示，像素阵列包括N行，N为大于1的整数，PI<1>行的子像素接收栅极信号CK1、PI<2>行的子像素接收栅极信号CK2、……、PI<N>行的子像素接收栅极信号CKN。需要说明的是，显示面板包括的子像素的行数可以根据需要进行设置。
在本公开的一些实施例中，例如将8个栅极信号组成一个循环组，分别向像素阵列的每行子像素施加栅极信号。需要理解的是，虽然本公开的实施例以8个栅极信号为一个循环组进行说明，但是本公开不限定一个循环组中栅极信号的数量，例如也可以是6个、12个栅极信号为一个循环组。
图1B示出了一个循环组的时序关系示意图。
如图1B所示，8个栅极信号分别为CK1、CK2、CK3、CK4、CK5、CLK6、CK7和CK8，对应于施加给栅极驱动电路不同的时钟信号。
例如，栅极信号CK1至栅极信号CK8的占空比(即高电平持续的时间与周期的比值)均为25％且周期相等。例如，CK1至CK8中每个的高电平时间为2H，低电平时间为6H。H为对一行子像素进行充电所需要的时间长度。
如图1B所示，例如，对于一个时间周期，栅极信号的高电平持续时间为2H，在前1H的时间段内，对栅极信号对应行的子像素进行预充电。在后1H的时间段内，即相邻两行子像素中，第一行子像素栅极信号开启的时间和第二行子像素栅极信号开启的时间之间交叠的部分是第二行子像素进行预充电的过程，第一行子像素栅极信号开启的时间和第二行子像素栅极信号开启的时间之间不交叠的部分为第二行子像素实际充电时间，此时数据信号端向栅极信号对应行的子像素充电以向对应行的子像素写入数据信号。在后1H的时间段内的前1/2H的时间段内，选择控制信号MUX1控制一行子像素中的第一部分子像素的数据线和数据信号端导通，使得数据信号端给第一部分子像素充电。在后1H的时间段内的后1/2H的时间段内，MUX2控制一行子像素中第二部分子像素的数据线和数据信号端导通，使得数据信号端给第二部分子像素充电，如此设计，实现对于一行像素分至少两部分充电，对于大尺寸产品，可以保证像素充电率。
如图1B所示，例如栅极信号CK1从高电平到低电平转换时，此时下一行栅极信号CK2对应的选择控制信号MUX1也立即开启切换到高电平以向第二行子像素中的第一部 分子像素充电，保持时间H/2，当选择控制信号MUX1切换到低电平时，选择控制信号MUX2也同步切换到高电平，保持时间为H/2，以向第二行子像素中的第二部分子像素充电，然后再切换到低电平。
然而，由于大尺寸显示面板的GOA特性和布线的局限性，电阻电容的延迟较大，对于相邻进行充电的第一行子像素和第二行子像素，第一行子像素的栅极开启后，当第一行子像素的栅极信号由高电平切换到低电平的时候，例如由于电阻电容阻抗影响，导致栅极信号关闭延迟，无法实现立即切换，当对第二行子像素进行充电时候，由于第一行子像素并未完全关闭，第二行子像素的数据信号对第一行子像素进行充电，从而出现像素错充等问题，例如造成黑白格画面、类似锯齿不良等画面显示异常。
图1C和图1D示出了本公开至少一个实施例提供的在显示画面中出现像素错充的示意图。
图1C示出的是在像素阵列依次展示的相邻两帧显示画面中的后一帧显示画面(即，第二帧显示画面)。图1D示出的是图1C所示的第二帧显示画面的目镜实物图。
如图1C所示，在第二帧显示画面中，像素1为黑色，像素2为白色，像素3为白色，像素4为黑色。在第二帧显示画面的前一帧显示画面(即，第一帧显示画面)中，像素1为白色，像素2为黑色，像素3为黑色，像素4为白色。
当像素阵列显示的显示画面由第一帧显示画面切换为第二帧显示画面后，在如图1D所示，第二帧显示画面的第m行子像素110出现像素错充，呈现锯齿状。图1C和图1D中椭圆形虚线圈出的区域为第m行子像素110所在的区域。第二帧显示画面的像素错充是因为在第m行的至少部分子像素未关闭时，数据信号端已经向第m+1行写入数据，而导致第m+1行的数据信号也被写入第m行。由于第m行的部分子像素已经关闭，而另外部分子像素未关闭，因此在第二帧显示画面中第m行的像素显示为锯齿状。
为此，本公开的至少一实施例提供了一种像素阵列的驱动方法，该驱动方法包括向第一行子像素和第二子像素分别对应的栅线施加栅极信号，栅极信号包括开启状态和关闭状态，第一行子像素和第二行子像素为相邻的两行子像素；在对第二行子像素施加栅极信号以控制第二行子像素期间，在向第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，施加对应于第二行子像素的选择控制信号，第一时间长度大于0。该方法能够缓解由于第一行子像素未完全关闭导致的像素错充，画面显示异常等问题。
图2A示出了本公开的至少一实施例提供的一种像素阵列的驱动方法的流程图。
如图2A所示，该方法可以包括步骤S10～S20。
步骤S10：向第一行子像素和第二子像素分别对应的栅线施加栅极信号，栅极信号包括开启状态和关闭状态。
步骤S20：在对第二行子像素施加栅极信号以控制第二行子像素期间，在向第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，对应于第二行子像素的选择控制信号控制开关模块切换连接状态。
本公开的至少一实施例提供的驱动方法可以应用于如图1A所示的像素阵列。该像素阵列包括多行多列子像素，多条栅线和多条数据线交叉限定多行多列子像素，子像素电连接的数据线通过开关模块与数据信号端电连接，开关模块接收选择控制信号以切换数据线与数据信号端的连接状态。该像素阵列的实施例请参考上文图1A的描述。
这里，多行子像素包括相邻的第一行子像素和第二行子像素，即第一行子像素和第二行子像素可以是任意两行相邻的子像素。需要理解的是，在本公开的至少一实施例中，两行相邻的子像素并不是指在像素阵列的排布上是相邻的两行子像素，而是指栅极信号在时序上相邻的两行子像素。例如，在时序上相邻的两行子像素是指栅极信号之间相差1个时间单元的两行子像素，1个时间单元可以是1行子像素充电的时间长度。例如，在图1A和图1B所示的情景中，PI<1>与PI<2>的栅极信号相差1H，则PI<1>为第一行子像素，PI<2>为与PI<1>相邻的第二行子像素。类似地，PI<3>为第一行子像素，PI<4>为与PI<3>相邻的第二行子像素。类似地，若在一个情景中，PI<11>的栅极信号比PI<8>的栅极信号延迟1H，则PI<8>和PI<11>可以为相邻的两行子像素，第一行子像素为PI<11>，第二行子像素为PI<8>。
需要说明的是，在本公开中除像素阵列中最后一行子像素之外，其他行的子像素均可以是第一行子像素，除像素阵列中第一行子像素之外，其他行的子像素均可以是第二行子像素。
对于步骤S10，例如依次向第一行子像素和第二行子像素分别对应的栅线施加栅极信号，第二行子像素的栅极信号比第一行子像素的栅极信号延迟1H。
例如，对于图1A所示的像素阵列，向像素阵列中的多行子像素对应的多条栅线依次施加多个栅极信号。
图2B示出了本公开至少一个实施例提供的像素阵列的驱动方法的时序示意图。
如图2B所示，第一行子像素和第二行子像素为相邻的两行子像素。第二行子像素的栅极信号与第一行子像素的栅极信号在时序上相邻，并且第二行子像素的栅极信号比第一行子像素的栅极信号延迟1H。
对于步骤S20，在对多行子像素中的每行子像素施加栅极信号以控制每行子像素期 间，施加对应于每行子像素的选择控制信号。
例如，在向第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，对应于第二行子像素的选择控制信号控制开关模块切换连接状态。例如，第二行子像素的选择控制信号控制开关模块导通第二行子像素中第一部分子像素对应的数据线与数据信号线。
例如，栅极信号的开启状态为高电平，栅极信号的关闭状态为低电平，选择控制信号为高电平时，开关模块导通数据线和数据信号端。如图2B所示，在第二子像素的栅极信号处于高电平期间，向第一行子像素施加的栅极信号在t1时刻从高电平向低电平切换，在t2时刻，选择控制信号MUX1由低电平切换至高电平，以控制开关模块导通第二行子像素中第一部分子像素对应的数据线与数据信号端。t2时刻晚于t1时刻T1时间长度，T1大于0。
在本公开的至少一实施例中，电平达到最高电平的90％视为电平达到高电平，电平达到最低电平的10％视为电平达到低电平。
在本公开的至少一实施例中，第一时间长度T1使得在向第二行子像素施加选择控制信号时，向第一行子像素施加的栅极信号为关闭状态。
本公开的至少一实施例在向第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，第二行子像素的选择控制信号再控制对应于第二行子像素的开关模块由断开切换至导通，使得第一行子像素在充分得到关闭后，才向第二行子像素充电以写入数据信号，从而缓解了由于第一行子像素未完全关闭导致的像素错充，显示画面显示异常等问题。
图2C示出本公开至少一个实施例提供的子像素与数据信号端的连接示意图。
在本公开的一些实施例中，每行子像素被划分为多个子像素组，与每个子像素组中的多个子像素电连接的多条数据线分别通过开关模块与一个数据信号端电连接。
例如，每个子像素组包括第一子像素和第二子像素，第一子像素连接的数据线通过第一开关元件与数据信号端连接，第二子像素连接的数据线通过第二开关元件与数据信号端连接。
例如，如图2C所示，同一行子像素包括子像素201至子像素208等，其中，子像素201和子像素203为一个子像素组，子像素202和子像素204为一个子像素组，子像素205和子像素207为一个子像素组，子像素206和子像素208为一个子像素组。该实施例对于该一行子像素的具体位置不作限制。
在图2C所示的示例中，每行子像素中相隔一列的两个子像素分别作为第一子像素和 第二子像素以作为一个子像素组。例如，子像素201和子像素203为一个子像素组，子像素202和子像素204为一个子像素组，子像素205和子像素207为一个子像素组，子像素206和子像素208为一个子像素组。
如图2C所示，子像素201和子像素203组成的子像素组对应的开关模块包括开关元件211和开关元件213，子像素201和子像素203电连接的数据线分别通过开关元件211和开关元件213与数据信号端S1电连接。子像素202和子像素204组成的子像素组对应的开关模块包括开关元件212和开关元件214，子像素202和子像素204电连接的数据线分别通过开关元件212和开关元件214与数据信号端S2电连接。子像素205和子像素207组成的子像素组对应的开关模块包括开关元件215和开关元件217，子像素205和子像素207电连接的数据线分别通过开关元件215和开关元件217与数据信号端S3电连接。子像素206和子像素208组成的子像素组对应的开关模块包括开关元件216和开关元件218，子像素206和子像素208电连接的数据线分别通过开关元件216和开关元件218与数据信号端S4电连接。开关元件例如可以是薄膜晶体管。
在该实施例中，选择控制信号包括多个选择控制信号。该多个选择控制信号分别施加至一个子像素组中不同的子像素。例如，多个选择控制信号包括第一选择控制信号和第二选择控制信号；在对第二行子像素施加栅极信号以控制第二行子像素期间，向第二行子像素中每个子像素组对应的第一开关元件和所述第二开关元件分别施加第一选择控制信号和第二选择控制信号，使第一开关元件和第二开关元件依次导通。
例如，如图2C所示，每行子像素的选择控制信号包括选择控制信号MUX1和选择控制信号MUX2。在本公开的一些实施例中，可以通过多个信号线分别向多个子像素施加选择控制信号。例如，选择控制信号MUX1包括MUX1_1、MUX1_2、MUX1_3以及MUX1_4，选择控制信号MUX2包括MUX2_1、MUX2_2、MUX2_3以及MUX2_4。MUX1_1、MUX1_2、MUX1_3以及MUX1_4是时序相同的信号，MUX2_1、MUX2_2、MUX2_3以及MUX2_4是时序相同的信号。MUX1_1、MUX1_2、MUX1_3以及MUX1_4分别来自4个信号线，MUX2_1、MUX2_2、MUX2_3以及MUX2_4分别来自4个信号线，这样能够提高选择控制信号的驱动能力。
在本公开的另一些实施例中，通过1个信号线向多个子像素施加选择控制信号。例如，MUX1来自一个信号线，通过一个信号线向子像素201、子像素202、子像素205和子像素206提供选择控制信号MUX1。例如，MUX2来自另一个信号线，通过另一个信号线向子像素203、子像素204、子像素207和子像素208提供选择控制信号MUX2。该实施例节省显示面板的布局空间，简化电路。
如图2C所示，开关元件211和开关元件213分别接收选择控制信号MUX1和选择控制信号MUX2，以切换开关元件211和开关元件213分别对应连接的多条数据线与数据信号端S1的连接状态。
例如，对于子像素201至子像素208所在的行，在该行子像素对应的栅极信号处于开启状态期间，向第一开关元件和第二开关元件分别施加选择控制信号MUX1和选择控制信号MUX2，通过选择控制信号MUX1和选择控制信号MUX2使得第一开关元件和第二开关元件依次导通。例如，若选择控制信号MUX1为高电平，选择控制信号MUX2为低电平，开关元件211导通子像素201对应的数据线与数据信号端S1以向子像素201充电，开关元件213断开子像素203与数据信号端S1。若选择控制信号MUX1为低电平，选择控制信号MUX2为高电平时，开关元件213导通子像素203对应的数据线与数据信号端S1以向子像素203充电，开关元件211断开子像素201与数据信号端S1。其他子像素组与子像素201和子像素203组成的子像素组，在此不再赘述。
如图2C所示，在选择控制信号MUX1处于高电平期间，子像素201、子像素202、子像素205和子像素206对应的数据线分别与数据信号端S1、数据信号端S2、数据信号端S3以及数据信号端S4导通，以通过数据信号端S1、数据信号端S2、数据信号端S3以及数据信号端S4分别向子像素201、子像素202、子像素205和子像素206充电。类似地，在选择控制信号MUX2处于高电平期间，子像素203、子像素204、子像素207和子像素208对应的数据线分别与数据信号端S1、数据信号端S2、数据信号端S3以及数据信号端S4导通，以通过数据信号端S1、数据信号端S2、数据信号端S3以及数据信号端S4分别向子像素203、子像素204、子像素207和子像素208充电。
例如，子像素201、子像素202和子像素203分别为红光子像素、绿光子像素和蓝光子像素，子像素204、子像素205和子像素206分别为红光子像素、绿光子像素和蓝光子像素。
可以理解的是，虽然在图2C的示例中，两个子像素作为一个子像素组，但是本公开不限于两个子像素作为一个子像素组。例如，还可以是三个子像素作为一个子像素组，四个子像素作为一个子像素组等等。也即，每个子像素组至少包括两个子像素。
在本公开的一些实施例中，第一选择控制信号控制所述第一开关元件由导通向断开切换与所述第二选择控制信号控制所述第二开关元件导通之间具有第二时间长度，第二时间长度大于0。
如图2B所示，在第二行子像素的栅极信号处于高电平期间，在t3时刻选择控制信号MUX1由高电平向低电平切换，以使第一部分子像素对于的数据线和数据信号端由导 通向断开切换，在t3时刻的第二时间长度T2之后，选择控制信号MUX2由低电平切换至高电平，以控制开关模块导通第二行子像素中第二部分子像素对应的数据线与数据信号端，第二时间长度T2大于0。
该驱动方法能够使得第二行子像素的第一部分子像素对应的开关元件被充分断开后，再将第二行子像素的第二部分子像素对应的数据线与数据信号端导通，从而进一步提高了显示质量，更加符合显示面板的特性。
在本公开的一些实施例中，第二时间长度是根据数据信号端从第一数据切换为第二数据所需要的时间长度、第一开关元件由导通切换为断开所需要的时间长度和第二开关由断开切换为导通所需要的时间长度确定。
例如，第二时间长度T2是数据信号端从第一数据切换为第二数据所需要的时间长度、第一开关元件由导通切换为断开所需要的时间长度和第二开关由断开切换为导通所需要的时间长度之和。例如，第一开关元件由导通切换为断开所需要的时间长度为第一开关元件对应的选择控制信号MUX1由高电平切换为低电平所需要的时间长度T22。第二开关由断开切换为导通所需要的时间长度为第二开关元件对应的选择控制信号MUX2由低电平切换为高电平所需要的时间长度T23。
如图2B所示，第二时间长度T2是数据信号端从第一数据切换为第二数据所需要的时间长度T21、选择控制信号MUX1由高电平切换为低电平所需要的时间长度T22和选择控制信号MUX2由低电平切换为高电平所需要的时间长度T23之和。也即，T2＝T21+T22+T23。
在本公开的一些实施例中，每个子像素组包括N个子像素，N为大于等于2的整数，栅极信号为周期信号，在每个周期内栅极信号处于开启状态期间的第三时间长度内，对应于第二行子像素的选择控制信号控制开关模块切换连接状态，选择控制信号的脉宽的计算公式为：
W＝(T3-T1-(N-1)×T2)/N。
W表示脉宽，T3表示第三时间长度，T1表示第一时间长度，T2表示第二时间长度。
第三时间长度T3为相邻两行子像素中第二行子像素的栅极信号处于开启状态并且第一行子像素的栅极信号处于关闭状态的时间段，即相邻两行栅线开启时间不交叠的位置对应的时间段。如图2B所示，在栅极信号的一个周期内，第二行子像素的栅极信号处于开启状态并且第一行子像素的栅极信号处于关闭状态的时间段为1H，因此在该示例中第三时间长度T3为1H。
例如，在图2B的示例中，N＝2，W＝(1H-T1-T2)/2。例如，T1＝1300ns，T2＝750ns， 1H＝3700ns，则W＝825ns。
在本公开的另一些实施例中，选择控制信号的脉宽的计算公式为：
W＝(T3-T1-(N-1)×T2-T4)/N。
T4为第二行子像素的栅极信号从开启状态向关闭状态切换的时刻与一个子像素组中最后一个选择控制信号由高电平向低电平切换之间的时间长度。如图2B所示，T4为第二行子像素的栅极信号从开启状态向关闭状态切换的时刻t4与MUX2由高电平向低电平切换的时刻t5之间的时间长度。这样可以保证在向第二行子像素充电期间，栅极信号处于一直处于开启状态，从而保证第二行子像素的充分充电。
例如，例如，在图2B的示例中，N＝2，W＝(1H-T1-T2-T4)/2。例如，T1＝1300ns，T2＝750ns，1H＝3700ns，T4＝150ns则W＝750ns。
T4的时间长度可以是本领域技术人员根据经验或者实际需求而设定的，例如T4也可以是50ns、100ns等。
图2D示出了本公开至少一个实施例提供的一种子像素组包括3个子像素的时序示意图。
如图2D所示，当N＝3时，同一个子像素组中的3个子像素分别施加选择控制信号MUX1、选择控制信号MUX2和选择控制信号MUX3。选择控制信号MUX1、选择控制信号MUX2和选择控制信号MUX3的脉宽均为W’，W’＝(1H-T1-2×T2)/3。
在本公开的一些实施例中，第一时间长度T1与第二时间长度T2的比值的取值范围可以是[0.8,3.0]。例如，第一时间长度T1与第二时间长度T2的比值可以在1.5到2.0之间的数值。例如，T1＝1300ns，T2＝750ns。
在本公开的一些实施例中，第三时间长度T3和第一时间长度T1之间的比值的取值范围可以是[1.0,5.0]。例如，第三时间长度T3和第一时间长度T1之间的比值为2.0到3.5之间的数值。例如，第三时间长度T3为1H，1H＝3700ns。
在本公开的一些实施例中，第二时间长度T2与脉宽之间的比值的取值范围可以是[0.3,2.0]。例如，二时间长度T2与脉宽之间的比值为0.8到1.2之间的数值。例如，第二时间长度T2和脉宽相等。
在本公开的一些实施例中，第一时间长度T1与所述脉宽之间的比值的取值范围可以是[0.7,3.0]。例如，第一时间长度T1与所述脉宽之间的比值为1.5到2.0之间的数值。
在本公开的实施例中，第一时间长度T1需要是一个合适的值，以满足在向第二行子像素施加选择控制信号时，向第一行子像素施加的栅极信号为关闭状态。
例如，可以对第一时间长度T1分别赋予多个不同的值，然后针对每个值进行显示测 试以从多个不同的T1值中确定出合适的T1值，以缓解像素错充。
在本公开的一些实施例中，例如用于显示测试的画面可以是黑白棋盘格，在进行显示测试时，按照上述相邻两行子像素的栅极信号和选择控制信号的时序向像素阵列施加栅极信号和选择控制信号，像素阵列依次显示两帧不同的黑白棋盘格画面。在第一帧黑白棋盘格画面中的黑色像素在第二帧黑白棋盘格画面中变为白色像素，在第一帧黑白棋盘格画面中的白色像素在第二帧黑白棋盘格画面中变为黑色像素。检测在第二帧画面中的黑白交界处是否存在像素错充。若在第一时间长度为第一值时，显示面板显示的黑白格画面均无错充，则第一值符合显示要求，第一值可以作为第一时间长度。
在本公开的一些实施例中，例如可以从小到大依次设置多个第一时间长度T1的值，然后针对每个值进行上述显示测试，以从多个值中确定符合显示要求的最小值，将该最小值作为第一时间长度T1。
例如，设置第一时间长度T1分别为800ns、900ns、1000ns、1100ns、1200ns、1300ns、1400ns、1500ns，按照时间长度从小到大的顺序依次进行显示测试，若当第一时间长度T1分别为800ns、900ns、1000ns、1100ns、1200ns时，显示画面均出现像素错充，当第一时间长度T1为1300ns时，显示画面无像素错充，则第一时间长度T1的最小值为1300ns。
在本公开的一些实施例中，例如可以利用二分法从1200ns和1300ns中确定出最佳的第一时间长度T1。
在本公开的一些实施例中，第一时间长度与第一行子像素的连接线长度正相关，连接线用于连接栅极信号的信号源与每行子像素对应的栅线的接收端。下面结合图3来说明该实施例。
图3示出了本公开至少一个实施例提供的一种显示面板200。
如图3所示，该显示面板200包括显示区DR和除显示区DR之外的非显示区PR，例如，非显示区PR围绕显示区DR。
需要理解的是，图3仅为一种示意图，为了便于说明将显示区DR进行的缩小处理，将非显示区PR进行了扩大处理，因此图3示出的显示区DR和非显示区PR之间的面积大小关系并不是真实的大小关系。例如，显示区的面积通常大于非显示区的面积。
显示区DR包括像素阵列，像素阵列包括多行多列子像素。像素阵列例如可以类似于图1A所示的显示面板100中的像素阵列，图3中的1、2、3、4、5、6、7、8分别表示与每行子像素(例如图1A中像素阵列的PI<1>行子像素、……、PI<8>行子像素)连接的栅线。非显示区PR包括栅极驱动电路10和栅极驱动电路30。栅极驱动电路10和 栅极驱动电路30各自包括多个级联的移位寄存器单元。例如，多个级联的移位寄存器单元例如为第1级移位寄存器单元GOA1、第2级移位寄存器单元GOA2、……第8级移位寄存器单元GOA8等。需要理解的是，虽然图中示出了8个移位寄存器单元，但是本公开不限定移位寄存器单元的数量，移位寄存器单元的数量可以根据实际需求而定。
例如，同一行的多个子像素的栅线与栅极驱动电路10和栅极驱动电路30中的一个移位寄存器单元连接，以接收移位寄存器单元输出的栅极信号。例如，一行子像素中靠近栅极驱动电路10的多个子像素由栅极驱动电路10提供栅极信号，靠近栅极驱动电路30的多个子像素由栅极驱动电路30提供栅极信号。在本公开的另外一些实施例中，显示面板也可以只包括一个栅极驱动电路，同一行子像素的栅线与该栅极驱动电路的一个移位寄存器单元连接，由该移位寄存器单元向一行子像素提供栅极信号。
如图3所示，以栅极驱动电路包括CLK1-CLK8，8个时钟信号为例，也可以是6CLK或12CLK等，在此不限定，每个移位寄存器单元具有第一电压端VDD1、第二电压端VDD2、时钟信号端CLKi(i为1、2、……、N(N为大于1的整数))、第三电压端LVGL、第四电压端VGL、复位信号端Total reset、输入端IN、第一输出端GOUT和第二输出端GOUT_C。如图3所示，除第一级移位寄存器单元至第四级移位寄存器单元之外，第k+4级的移位寄存器单元的输入端IN和第k级的移位寄存器单元的第一输出端GOUT_C连接，k为大于等于1的整数。第一级移位寄存器单元至第四级移位寄存器单元各自的输入端IN分别与信号线STV1、信号线STV2、信号线STV3和信号线STV4连接，以从信号线STV1、信号线STV2、信号线STV3和信号线STV4连接接收帧起始信号，可选的，STV1-STV4是相同的帧起始信号。第一输出端GOUT配置为向栅线输出栅极信号。每一级的移位寄存器单元分别从信号线VDD1、信号线VDD2、信号线LVGL和信号线VGL接收电压信号。例如，信号线VDD1上的电压信号VDD1和信号线VDD2上的电压信号VDD2互为高低电平，可以用于移位寄存器单元中降噪电路。信号线VGL上的电压信号VGL用来拉低显示区的电平，信号线LVGL上的电压信号LVGL用来拉低降噪电路的电平。
如图3所示，该栅极驱动电路10和栅极驱动电路30各自还包括传输第一子时钟信号的子时钟信号线CLK1、传输第二子时钟信号的子时钟信号线CLK2、传输第三子时钟信号的子时钟信号线CLK3、传输第四子时钟信号的子时钟信号线CLK4、传输第五子时钟信号的子时钟信号线CLK5、传输第六子时钟信号的子时钟信号线CLK6、传输第七子时钟信号的子时钟信号线CLK7、传输第八子时钟信号的子时钟信号线CLK8。
例如，栅极驱动电路10和栅极驱动电路30包括的移位寄存器单元的个数N为8的 整数倍，每8个移位寄存器单元作为一个循环组，分别接收子时钟信号线CLK1～CLK8的时钟信号，并且响应于时钟信号由多个第一输出端GOUT向多行子像素输出栅极信号。例如，如图3所示，第1级移位寄存器单元的时钟信号端CLK1和子时钟信号线CLK1连接；第2级移位寄存器单元的时钟信号端CLK2和子时钟信号线CLK2连接；第3级移位寄存器单元的时钟信号端CLK3和子时钟信号线CLK3连接；第4级移位寄存器单元的时钟信号端CLK4和子时钟信号线CLK4连接；第5级移位寄存器单元的时钟信号端CLK5和子时钟信号线CLK5连接；第6级移位寄存器单元的时钟信号端CLK6和子时钟信号线CLK6连接；第7级移位寄存器单元的时钟信号端CLK7和子时钟信号线CLK2连接；第8级移位寄存器单元的时钟信号端CLK8和子时钟信号线CLK2连接；第9级移位寄存器单元的时钟信号端CLK9和子时钟信号线CLK1连接。本公开的实施例对于移位寄存器单元的具体结构不作限制，图3示意了双边驱动，即同一行像素由左右两端的栅极驱动电路驱动，当然也可以是单边驱动，例如仅仅保留非显示区一侧的栅极驱动电路，也可以是双边奇偶驱动，例如其中一侧的栅极驱动电路驱动奇数行像素，另外一侧的栅极驱动电路驱动偶数行像素，在此不做限定。
如图3所示，栅极驱动电路10和栅极驱动电路30还可以分别包括信号源11和信号源31。信号源11例如配置为向栅极驱动电路10的各级移位寄存器单元提供上述各个信号，信号源31例如配置为向栅极驱动电路30的各级移位寄存器单元提供上述各个信号。需要说明的是，信号源11和信号源31提供的多个时钟信号彼此之间的相位关系可以根据实际需求而定。在不同的示例中，根据不同的配置，还可以提供更多的时钟信号。由于栅极驱动电路10和栅极驱动电路30类似，下面以栅极驱动电路10和信号源11为例来说明本公开的实施例。
例如，信号源11分别通过子时钟信号线CLK1至CLK8向各个移位寄存器单元提供时钟信号，使得每个移位寄存器单元输出栅极信号。例如，每个移位寄存器单元输出图1A中示例的栅极信号CK1～CK8，实际上，子时钟信号线CLK1至CLK8提供的时钟信号是与栅极信号CK1～CK8相同的信号。
当第k级移位寄存器单元的时钟信号端CLKi接收的子时钟信号(CLK1～CLK8中的1个)为高电平时，第k级移位寄存器单元的第一输出端GOUT输出的栅极信号为开启状态。
由于上述子时钟信号CLK1至子时钟信号CLK8在时序上是相邻的，所以图3中所示的8个移位寄存器单元输出的栅极信号的时序是按照以下顺序彼此相邻的：第1级移位寄存器单元的第一输出端GOUT输出的栅极信号—>第2级移位寄存器单元的第一输 出端GOUT输出的栅极信号—>第3级移位寄存器单元的第一输出端GOUT输出的栅极信号—>第4级移位寄存器单元的第一输出端GOUT输出的栅极信号—>第5级移位寄存器单元的第一输出端GOUT输出的栅极信号—>第6级移位寄存器单元的第一输出端GOUT输出的栅极信号—>第7级移位寄存器单元的第一输出端GOUT输出的栅极信号—>第8级移位寄存器单元的第一输出端GOUT输出的栅极信号，图3中示意了栅极驱动电路包括两个输出端，GOUT输出端是用于输出栅极驱动信号给对应行像素，GOUT_C是用于传输级联信号的输出端，例如第一级移位寄存器单元的GOUT_C为第五级移位寄存器单元提供输入信号，栅极驱动电路也可以仅仅设置GOUT输出端，即GOUT即作为本行的输出信号，也作为其他行级联的输入信号，在此不做限定。
由于多个子像素从远到近排列为多行，每行子像素的栅极信号的接收端到信号源11的距离不同，因此每行子像素所需要的连接线长度不同，这里连接线长度不同指的是距离信号源端传输每行像素显示的CLK信号所走的电路传输路径不同。连接线用于连接栅极信号的信号源与每行子像素对应的栅线的接收端。如图3所示，连接线是指信号源11与每行子像素对应的栅线的接收端之间的走线。信号源可以指的是时序控制器IC。例如，时序控制器IC经过电平转换单元(level-shifter)后经过柔性电路板连接到显示面板的CLK线上，例如显示面板是通过COF(chip on film)的方式绑定，即将source IC绑定到FPC柔性电路板上，柔性电路板的一端绑定到显示面板的非显示区，柔性电路板的另外一端绑定到PCB电路板上，PCB电路板上设置有时序控制器IC(TCON-IC)，时序控制器IC输出的时钟信号，经过电平转换单元后，经过柔性电路板上的信号线，传输到显示面板的CLK信号线上，可选的，柔性电路板的信号线和显示面板的CLK信号线连接可以通过各自的绑定端子实现电连接，即显示面板的焊盘，柔性电路板的金手指，当然本发明也包括COG(chip on glass)的方式，即source IC直接绑定在显示面板的非显示区，在此不做限定。走线包括信号源11到各级移位寄存器单元之间的子时钟信号线和各级移位寄存器单元到对应连接的栅线的接收端之间的走线，由于各级移位寄存器单元到对应连接的栅线的接收端之间的多个走线的长度相差不大，因此每行子像素的栅极信号的接收端到信号源11的距离的差异主要体现在多个子时钟信号线(即子时钟信号线CLK1～子时钟信号线CLK8)的长度不同，需要说明的是，这里的长度不同指的是电学上传输信号的距离不同，图3示意出CLK1-CLK8时钟信号线物理长度不同，当然，CLK1-CLK8时钟信号线物理长度也可以相同设计，但此时从信号源传输到第一行像素对应的CLK1信号所走的电学路径是到附图中黑色结点的位置，对于第8行像素对应的CLK8信号所走的电学传输路径是到附图中黑色结点的位置，可见第一行像素CLK信号传输的电学传 输路径较第8行像素CLK信号传输的电学传输路径更长。
例如，信号源11位于显示面板200的左下角，PI<1>行子像素至PI<8>行子像素各自对应的子时钟信号线CLK1至子时钟信号线CLK8越来越短，也即，PI<1>行子像素至PI<8>行子像素各自与信号源11之间的连接线越来越短。例如，第七行子像素所需要的子时钟信号线CLK7大于第八行子像素所需要的子时钟信号线CLK8的长度。
由于每行子像素所需要的子时钟信号线的长度不同，因此，每行子像素接收到的栅极信号在子时钟信号线的延迟不同。
图4示出了本公开至少一个实施例提供的图3所示的显示面板中每行子像素接收到的栅极信号的时序图。
如图4所示，由于从第一行子像素对应的子时钟信号线CLK1到第八行子像素对应的子时钟信号线CLK8越来越短，因此，第一行子像素接收到的栅极信号CK1到第八行子像素接收到的栅极信号CK8的延迟越来越小，因此CK1至CK8的上升沿的时长越来越短，也即第一行子像素至第八行子像素接收到的栅极信号的上升沿的时长越来越短。
在本公开的一些实施例中，例如，由于PI<1>行子像素至第PI<N>行子像素的连接线越来越短，因此，PI<1>行子像素至第PI<N>的栅极信号的延迟越来越短(即，上升沿和下降沿所需要的时长越来越短)，因此PI<1>行子像素至第PI<N>行子像素各自的栅极信号由开启状态切换为关闭状态所需要的时间越来越短，因此，每行子像素用于切换的的第一时间长度也越来越短。
例如，PI<1>行子像对应的连接线比PI<2>行子像对应的连接线长，因此PI<1>行子像用于切换的第一时间长度比PI<2>行子像用于切换的第一时间长度长。
这样可以针对每一行子像素设置合适的第一时间长度，在缓解像素错充的同时，提高了显示效率。
图5示出了本公开至少一个实施例提供的另一种驱动方法的流程图。
如图5所示，该驱动方法除包括步骤S10和S20之外，还可以包括步骤S30和步骤S40。步骤S30和步骤S40例如可以在步骤S10和S20之前执行。
步骤S30：确定多个第一行子像素的多个连接线中最长连接线对应的第一时间长度。
步骤S40：根据最长连接线对应的第一时间长度，确定多条连接线中除最长连接线之外的其他连接线对应的第一时间长度。
该方法能够减少确定每行子像素对应的第一时间长度的时间，提高确定第一时间长度的效率。
对于步骤S30，最长连接线对应的第一时间长度可以是距离信号源最远的一行子像 素对应的第一时间长度。例如，在图1A所示的示例中，PI<1>行子像素是距离信号源最远的一行子像素，那么在步骤S30可以是确定PI<1>行子像素对应的第一时间长度。
例如，根据上文描述的利用黑白棋盘格画面进行显示测试的方法来确定最长连接线对应的第一时间长度。
对于步骤S40，例如，根据PI<1>行子像素对应的第一时间长度，确定PI<2>行子像素、……、PI<N>行子像素各自的第一时间长度。
在本公开的一些实施例中，例如本领域技术人员可以根据经验确定相邻两行之间的第一时间长度的差值，然后每行子像素对应的第一时间长度依次减少该差值。
在本公开的另一些实施例中，还可以确定最短连接线对应的第一时间长度，并且根据最短连接线对应的第一时间长度和最长连接线对应的第一时间长度确定相邻两行之间的第一时间长度的差值。
如图5所示，该驱动方法除包括步骤S10～S40之外，还可以包括步骤S50。步骤S50例如可以在步骤S3之前执行。
步骤S50：将像素阵列划分为多个区域，每个区域包括连续的多行子像素。
在该实施例中，步骤S30包括从多个区域中确定距离栅极信号的信号源最远的远端区域，以及基于远端区域中的多个第一行子像素对应的连接线，确定最长连接线对应的所述第一时间长度。
在该实施例中，步骤S40包括根据最长连接线对应的第一时间长度，为每个区域中的多行子像素确定一个第一时间长度。
在该实施例中，每个区域中的多行子像素对应的第一时间长度可以是相同的。
该实施例将像素阵列划分为多个区域，分别为每个区域确定第一时间长度，从而提高了计算效率。
在本公开的一些实施例中，每个区域中的子像素的行数可以相同也可以不相同。
像素阵列的多个区域可以是本领域技术人员根据显示面板中的电路走线划分的。例如，将栅极信号的延迟相差不大的多行子像素划分为一个区域。
例如，像素阵列包括PI<1>行子像素、PI<2>行子像素、……、PI<N>行子像素共N(N>50)行行子像素，并且PI<1>行子像素、PI<2>行子像素、……、PI<N>行子像素的栅线的接收端距离信号源越来越近，每50行子像素作为一个区域，则距离栅极信号的信号源最远的远端区域为PI<1>、PI<2>、……、PI<50>所在的区域。
在本公开的一些实施例中，上文步骤S30描述的基于远端区域中的多个第一行子像素对应的连接线，确定最长连接线对应的所述第一时间长度，包括：将远端区域中距离 信号源最远的第一行子像素对应的第一时间长度作为最长连接线对应的所述第一时间长度。
例如，PI<1>行子像素距离信号源最远，则将PI<1>行子像素对应的第一时间长度作为最长连接线对应的所述第一时间长度。
在本公开的一些实施例中，基于远端区域中的多个第一行子像素对应的连接线，确定最长连接线对应的所述第一时间长度，包括：计算远端区域中的多个第一行子像素各自对应的第一时间长度的平均值，将该平均值作为最长连接线对应的所述第一时间长度。例如，最长连接线对应的第一时间长度为(T PI<1>+T PI<2>+……+T PI<50>)/50，T PI<1>、T PI<2>、……、T PI<50>分别表示PI<1>、PI<2>、……、PI<50>各自对应的第一时间长度。
在本公开的一些实施例中，上文步骤S40描述的根据最长连接线对应的第一时间长度，为每个区域中的多行子像素确定一个第一时间长度，包括：确定相邻区域中第一时间长度之间的差值，根据差值确定为每个区域中的多行子像素确定一个第一时间长度。
例如，例如本领域技术人员可以根据经验确定相邻两区域之间的第一时间长度的差值，根据该差值和最长连接线对应的第一时间长度，确定每个区域对应的第一时间长度。每个区域中的多行子像素对应的第一时间长度相同。
在本公开的另一些实施例中，还可以确定距离信号源最近的区域对应的第一时间长度，并且根据距离信号源最近的区域对应的第一时间长度和最长连接线对应的第一时间长度确定相邻两区域之间的第一时间长度的差值。
本公开的另一方面提供了一种显示面板，显示面板包括多行多列子像素形成的像素阵列，多条栅线和多条数据线交叉限定多行多列子像素，子像素电连接的数据线通过开关模块与数据信号端电连接，开关模块接收选择控制信号以切换数据线与数据信号端的连接状态。多行子像素包括相邻的第一行子像素和第二行子像素，第一行子像素和第二行子像素分别接收对应的栅线的栅极信号，栅极信号包括开启状态和关闭状态。在对第二行子像素施加栅极信号以控制第二行子像素期间，以及在第一行子像素接收到的栅极先后从开启状态向关闭状态切换的第一时间长度之后，第二行子像素的开关模块接收选择控制信号以控制第二行子像素的开关模块切换连接状态。
显示面板例如可以是图1A或者图3所示的示例，显示面板的相关描述请参考上文关于图1A或者图3的描述。
在本公开的一些实施例中，每行子像素被划分为多个子像素组，与每个子像素组中的多个子像素电连接的多条数据线分别通过开关模块与一个数据信号端电连接，每个子像素对应的开关模块包括多个开关元件，选择控制信号包括多个选择控制信号，多个开 关元件分别接收多个选择控制信号，以切换与多个开关元件对应连接的多条数据线与数据信号端的连接状态。
在本公开的一些实施例中，每个子像素组包括第一子像素和第二子像素，第一子像素连接的数据线通过第一开关元件与数据信号端连接，第二子像素连接的数据线通过第二开关元件与数据信号端连接，多个选择控制信号包括第一选择控制信号和第二选择控制信号；在第二行子像素接收栅极信号期间，第二行子像素中每个子像素组对应的第一开关元件和第二开关元件分别响应第一选择控制信号和第二选择控制信号而依次导通。
在本公开的一些实施例中，第一开关元件由导通向断开切换与第二开关元件导通之间具有第二时间长度，第二时间长度大于0。
在本公开的一些实施例中，显示面板包括非显示区和显示区，像素阵列位于显示区，非显示区包括栅极信号的信号源。
如图3所示，显示面板200包括非显示区PR和显示区DR。像素阵列位于显示区DR，非显示区PR包括栅极信号的信号源11和信号源31。
本公开的另一方面提供了一种像素阵列的驱动装置，像素阵列包括多行多列子像素，多条栅线和多条数据线交叉限定多行多列子像素。子像素电连接的数据线通过开关模块与数据信号端电连接，开关模块接收选择控制信号以切换所述数据线与所述数据信号端的连接状态，多行子像素包括相邻的第一行子像素和第二行子像素。像素阵列可以参考图1A所示的显示面板100中的像素阵列。
图6示出了根据本公开至少一个实施例的驱动装置600的框图。
如图6所示，驱动装置600可以包括栅极驱动电路601、控制电路602和数据驱动电路603。
如图6所示，驱动装置600可以与像素阵列610连接，像素阵列610例如可以是图1A所示的像素阵列。
栅极驱动电路601配置为向第一行子像素和所述第二子像素分别对应的栅线施加栅极信号，栅极信号包括开启状态和关闭状态。例如，栅极驱动电路可以是图3中的栅极驱动电路10和栅极驱动电路30，关于栅极驱动电路的描述请参考栅极驱动电路10和栅极驱动电路30的相关描述。
控制电路602配置为向第二行子像素施加选择控制信号，在对第二行子像素施加栅极信号以控制第二行子像素期间，在向第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，对应于第二行子像素的选择控制信号控制开关模块切换连接状态。第一时间长度大于0。
数据驱动电路603包括数据信号端，配置为向与数据信号端连接的数据线提供数据信号。需要理解的是，图6中的连接线的数量并不代表真实的数量，图6只是示意性表示驱动装置600和像素阵列610之间的连接关系，对本公开不具有限定作用。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种像素阵列的驱动方法，其中，所述像素阵列包括多行多列子像素，多条栅线和多条数据线交叉限定多行多列所述子像素，
    所述子像素电连接的数据线通过开关模块与数据信号端电连接，所述开关模块接收选择控制信号以切换所述数据线与所述数据信号端的连接状态，
    所述多行子像素包括相邻的第一行子像素和第二行子像素，
    所述方法包括：
    向所述第一行子像素和所述第二子像素分别对应的栅线施加栅极信号，所述栅极信号包括开启状态和关闭状态；
    在对所述第二行子像素施加所述栅极信号以控制所述第二行子像素期间，在向所述第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，对应于所述第二行子像素的选择控制信号控制所述开关模块切换所述连接状态，
    其中，所述第一时间长度大于0。
  2. 根据权利要求1所述的方法，其中，每行子像素被划分为多个子像素组，与每个子像素组中的多个子像素电连接的多条数据线分别通过开关模块与一个数据信号端电连接，每个子像素对应的开关模块包括多个开关元件，
    所述选择控制信号包括多个选择控制信号，
    所述多个开关元件分别接收所述多个选择控制信号，以切换与所述多个开关元件对应连接的所述多条数据线与所述数据信号端的连接状态。
  3. 根据权利要求2所述的方法，其中，每个子像素组包括第一子像素和第二子像素，所述第一子像素连接的数据线通过第一开关元件与所述数据信号端连接，所述第二子像素连接的数据线通过第二开关元件与所述数据信号端连接，
    所述多个选择控制信号包括第一选择控制信号和第二选择控制信号；
    在对所述第二行子像素施加所述栅极信号以控制所述第二行子像素期间，向所述第二行子像素中每个子像素组对应的所述第一开关元件和所述第二开关元件分别施加所述第一选择控制信号和所述第二选择控制信号，使所述第一开关元件和所述第二开关元件导通。
  4. 根据权利要求3所述的方法，其中，所述第一选择控制信号控制所述第一开关元件由导通向断开切换与所述第二选择控制信号控制所述第二开关元件导通之间具有第二 时间长度，第二时间长度大于0。
  5. 根据权利要求3或4所述的方法，其中，每行子像素中相隔一列的两个子像素分别作为所述第一子像素和所述第二子像素，以作为一个子像素组。
  6. 根据权利要求4所述的方法，其中，所述第一时间长度与所述第二时间长度的比值的取值范围为[0.8,3.0]。
  7. 根据权利要求4-6任一项所述的方法，其中，所述第二时间长度是根据所述数据信号端从第一数据信号切换为第二数据信号所需要的时间长度、所述第一开关元件由导通切换为断开所需要的时间长度和所述第二开关元件由断开切换为导通所需要的时间长度确定。
  8. 根据权利要求4-7任一项所述的方法，其中，每个子像素组包括N个子像素，N为大于等于2的整数，
    所述栅极信号为周期信号，在每个周期内所述栅极信号处于所述开启状态期间的第三时间长度内，对应于所述第二行子像素的选择控制信号控制所述开关模块切换所述连接状态，
    所述选择控制信号的脉宽的计算公式为：
    W＝(T3-T1-(N-1)×T2)/N
    其中，W表示脉宽，T3表示所述第三时间长度，T1表示所述第一时间长度，T2表示所述第二时间长度。
  9. 根据权利要求8所述的方法，其中，所述第三时间长度T3和所述第一时间长度T1之间的比值的取值范围为[1.0,5.0]。
  10. 根据权利要求8所述的方法，其中，所述第二时间长度T2与所述脉宽之间的比值的取值范围为[0.3,2.0]。
  11. 根据权利要求8所述的方法，其中，所述第一时间长度T1与所述脉宽之间的比值的取值范围为[0.7,3.0]。
  12. 根据权利要求1-11任一项所述的方法，其中，所述第一时间长度与所述第一行子像素的连接线长度正相关，所述连接线用于连接所述栅极信号的信号源与每行子像素对应的所述栅线的接收端。
  13. 根据权利要求12所述的方法，还包括：
    确定多个所述第一行子像素的多个连接线中最长连接线对应的所述第一时间长度；
    根据所述最长连接线对应的所述第一时间长度，确定所述多条连接线中除所述最长连接线之外的其他连接线对应的第一时间长度。
  14. 根据权利要求13所述方法，还包括：
    将所述像素阵列划分为多个区域，每个区域包括连续的多行子像素；
    确定多个所述第一行子像素的多个连接线中最长连接线对应的所述第一时间长度，包括：
    从所述多个区域中确定距离所述栅极信号的信号源最远的远端区域；
    基于所述远端区域中的多个所述第一行子像素对应的连接线，确定所述最长连接线对应的所述第一时间长度；
    根据所述最长连接线对应的所述第一时间长度，确定所述多条连接线中除所述最长连接线之外的其他连接线对应的第一时间长度，包括：
    根据所述最长连接线对应的所述第一时间长度，为每个区域中的多行子像素确定一个第一时间长度。
  15. 一种显示面板，其中，所述显示面板包括多行多列子像素形成的像素阵列，多条栅线和多条数据线交叉限定多行多列所述子像素，所述子像素电连接的数据线通过开关模块与数据信号端电连接，所述开关模块接收选择控制信号以切换所述数据线与所述数据信号端的连接状态，
    所述多行子像素包括相邻的第一行子像素和第二行子像素，
    所述第一行子像素和所述第二行子像素分别接收对应的栅线的栅极信号，所述栅极信号包括开启状态和关闭状态；
    在对所述第二行子像素施加栅极信号以控制第二行子像素期间，以及在所述第一行子像素接收到的所述栅极先后从开启状态向关闭状态切换的第一时间长度之后，所述第二行子像素的开关模块接收选择控制信号以控制所述第二行子像素的开关模块切换所述连接状态。
  16. 根据权利要求15所述的显示面板，其中，每行子像素被划分为多个子像素组，与每个子像素组中的多个子像素电连接的多条数据线分别通过开关模块与一个数据信号端电连接，每个子像素对应的开关模块包括多个开关元件，
    所述选择控制信号包括多个选择控制信号，
    所述多个开关元件分别接收所述多个选择控制信号，以切换与所述多个开关元件对应连接的所述多条数据线与所述数据信号端的连接状态。
  17. 根据权利要求16所述的显示面板，其中，每个子像素组包括第一子像素和第二子像素，所述第一子像素连接的数据线通过第一开关元件与所述数据信号端连接，所述第二子像素连接的数据线通过第二开关元件与所述数据信号端连接，
    所述多个选择控制信号包括第一选择控制信号和第二选择控制信号；
    在所述第二行子像素接收所述栅极信号期间，所述第二行子像素中每个子像素组对应的所述第一开关元件和所述第二开关元件分别响应所述第一选择控制信号和所述第二选择控制信号而导通。
  18. 根据权利要求17所述的显示面板，其中，所述第一开关元件由导通向断开切换与所述第二开关元件导通之间具有第二时间长度，第二时间长度大于0。
  19. 根据权利要求15-18任一项所述的显示面板，其中，所述显示面板包括非显示区和显示区，所述像素阵列位于所述显示区，所述非显示区包括栅极信号的信号源。
  20. 一种像素阵列的驱动装置，其中，所述像素阵列包括多行多列子像素，多条栅线和多条数据线交叉限定多行多列所述子像素，
    所述子像素电连接的数据线通过开关模块与数据信号端电连接，所述开关模块接收选择控制信号以切换所述数据线与所述数据信号端的连接状态，
    所述多行子像素包括相邻的第一行子像素和第二行子像素，
    所述驱动装置包括：
    栅极驱动电路，配置为向所述第一行子像素和所述第二子像素分别对应的栅线施加栅极信号，所述栅极信号包括开启状态和关闭状态；
    控制电路，配置为向所述第二行子像素施加选择控制信号，其中，在对所述第二行子像素施加所述栅极信号以控制所述第二行子像素期间，在向所述第一行子像素施加的栅极信号从开启状态向关闭状态切换的第一时间长度之后，对应于所述第二行子像素的选择控制信号控制所述开关模块切换所述连接状态，
    数据驱动电路，包括所述数据信号端，配置为通过向与所述数据信号端连接的数据线提供数据信号；
    其中，所述第一时间长度大于0。
PCT/CN2021/133725 2021-11-26 2021-11-26 像素阵列驱动方法、装置和显示面板 WO2023092506A1 (zh)

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