WO2023077542A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023077542A1
WO2023077542A1 PCT/CN2021/130095 CN2021130095W WO2023077542A1 WO 2023077542 A1 WO2023077542 A1 WO 2023077542A1 CN 2021130095 W CN2021130095 W CN 2021130095W WO 2023077542 A1 WO2023077542 A1 WO 2023077542A1
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WIPO (PCT)
Prior art keywords
binding
layer
via hole
binding terminal
display
Prior art date
Application number
PCT/CN2021/130095
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English (en)
French (fr)
Inventor
黄灿
鲜于文旭
张春鹏
马蹄遥
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/765,831 priority Critical patent/US20240047471A1/en
Publication of WO2023077542A1 publication Critical patent/WO2023077542A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/90—Assemblies of multiple devices comprising at least one organic light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • Ultra-large display screens can meet people's needs for long-distance viewing and large-scale information display. Due to cost considerations, current super-sized display screens are usually implemented using a splicing technology, that is, multiple sub-display screens are spliced together to form a super-sized display screen. However, when multiple display screens are spliced together, large black splicing gaps will appear at the splicing area, which seriously affects the display quality of super-sized display screens.
  • the present application provides a display panel and a display device, so as to alleviate the technical problem of large splicing gaps at the splicing places of the existing super-large display screens.
  • An embodiment of the present application provides a display panel, which includes:
  • each of the display components further includes a plurality of signal lines disposed on a side of the plurality of first binding terminals away from the driving backplane, and each of the signal lines is respectively connected to the corresponding first binding terminal.
  • the fixed terminals are electrically connected, and are used to make the driving backplane provide signals to the corresponding signal lines through the first binding terminals.
  • the display component further includes a base substrate and a driving circuit layer disposed on the side of the base substrate away from the driving backplane, and the base substrate includes a plurality of The first binding terminal, the driving circuit layer includes a plurality of the signal lines.
  • the base substrate further includes a first barrier layer and a first substrate stacked on the first binding terminal, wherein the first substrate faces the In the driving circuit layer, the first barrier layer covers the first binding terminal, and the lower surface of the first binding terminal is exposed.
  • the base substrate further includes a second substrate disposed on the side of the first barrier layer away from the first substrate, and the second substrate The area of the first binding terminal is provided with an opening.
  • the driving circuit layer includes:
  • a gate insulating layer covering the semiconductor layer and the base substrate
  • a gate layer disposed on the gate insulating layer, including a gate and a gate scanning line;
  • a source-drain layer disposed on the interlayer insulating layer, including a source, a drain, and a data line;
  • the plurality of signal lines include the gate scanning lines and the data lines, and the gate scanning lines and the data lines are electrically connected to the corresponding first binding terminals.
  • the interlayer insulating layer is patterned to form a first via hole, and the first via hole penetrates to the first bonding terminal to expose the first bonding terminal. part of the upper surface of the fixing terminal, and the data line is electrically connected to the first binding terminal through the first via hole.
  • the interlayer insulating layer is patterned to form a second via hole and a third via hole, and the second via hole penetrates to the first binding terminal to expose Part of the upper surface of the first binding terminal, the third via hole penetrates to the gate scanning line to expose part of the gate scanning line, and the source-drain layer further includes a signal transfer line, The signal transfer line is electrically connected to the first binding terminal and the gate scanning line through the second via hole and the third via hole respectively.
  • the gate insulating layer is patterned to form a fourth via hole, and the fourth via hole penetrates to the first bonding terminal to expose the first bonding terminal.
  • the gate scanning line is electrically connected to the first binding terminal through the fourth via hole.
  • the driving backplane is provided with a second binding terminal corresponding to the first binding terminal of each of the display components, and the second binding terminal and the The first binding terminal is electrically connected.
  • An embodiment of the present application further provides a display device, which includes a casing and the display panel of one of the foregoing embodiments, the casing is formed with an accommodating cavity, and the display panel is disposed in the accommodating cavity.
  • a plurality of display components are arranged in an array on the driving backplane, and each of the display components includes a plurality of first binding terminals arranged on one side facing the driving backplane , each of the display components is electrically connected to the driving backplane through a plurality of the first binding terminals, and is electrically connected to the driving backplane by setting the first binding terminals on one side of the display component, so that the driving backplane Signals can be provided to the corresponding signal lines in the display component through the first binding terminal, so that there is no need to arrange lines such as driving circuits on the frame of the display component, so as to reduce or eliminate the frame of the display component, so that the display panel formed after splicing is basically There is no seam, which solves the problem that there is a large seam at the seam of the existing super-large display screen.
  • FIG. 1 is a schematic top view structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a partial cross-sectional structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a first partial cross-sectional structure of a display component provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a second partial cross-sectional structure of a display component provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a third partial cross-sectional structure of a display component provided by an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structure diagram of a display device provided by an embodiment of the present application.
  • the inventors of the present application found in research that the splicing gaps are mainly caused by the borders of the sub-display screens that participate in splicing to form super-sized display screens.
  • the frame of the sub-display is usually used to place various bonding wires and driving circuits (such as source driver chips) connected to the bonding wires, and the driving circuit provides driving signals to the sub-display,
  • the border area cannot be displayed, so that the adjacent sub-displays are spliced together to form a large splicing gap.
  • the splicing gap is displayed as a black line, which seriously affects the super-large size.
  • Figure 1 is a schematic top view of the display panel provided by the embodiment of the present application.
  • the example provided shows the first partial cross-sectional structural schematic diagram of the assembly.
  • the display panel 100 includes a driving backplane 1 and a plurality of display components 2 arrayed on the driving backplane 1 .
  • Each of the display components 2 includes a plurality of first binding terminals 11 disposed on one side facing the drive backplane 1, and each of the display components 2 is connected to the The drive backplane 1 is electrically connected.
  • Each of the display components 2 also includes a plurality of signal lines (such as the data line 253 shown in FIG. 2 and the data line 253 shown in FIG. gate scanning line 232 ), each of the signal lines is electrically connected to the corresponding first binding terminal 11, so that the driving backplane 1 can be connected to the corresponding first binding terminal 11
  • the signal lines provide signals.
  • each of the display components 2 further includes a base substrate 10 and a driving circuit layer 20 disposed on the side of the base substrate 10 away from the driving backplane 1, and the base substrate 10 includes a plurality of the The first binding terminal 11, the driving circuit layer 20 includes a plurality of the signal lines.
  • the base substrate 10 further includes a first barrier layer 12 and a first substrate 13 stacked on the first binding terminal 11, wherein the first substrate 13 faces the driving circuit layer 20,
  • the first barrier layer 12 covers the first binding terminal 11 , and the lower surface of the first binding terminal 11 is exposed.
  • the lower surface of the first binding terminal 11 refers to the side of the first binding terminal 11 away from the first barrier layer 12 , and the lower surface is exposed for electrical connection with the driving backplane 1 .
  • the first binding terminal 11 can be made of a metal or alloy with strong oxidation resistance and low resistivity, such as MO, AL alloy, etc., to ensure the stability of the first binding terminal 11 and the connection with the driving back Reliability of board 1 connection.
  • the base substrate 10 further includes a second barrier layer 14 disposed on the side of the first substrate 13 away from the first barrier layer 12 and disposed on the side of the second barrier layer 14 away from the The buffer layer 15 on the side of the first substrate 13 .
  • the first barrier layer 12, the second barrier layer 14, and the buffer layer 15 can be formed of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., to prevent Undesirable impurities or pollutants (such as moisture, oxygen, etc.) diffuse from the first substrate 13 into devices that may be damaged by these impurities or pollutants.
  • the substrate substrate of the present application 10 is not limited thereto, and the base substrate 10 of the present application may include more or less inorganic film layers.
  • the material of the first substrate 13 includes polyimide (Polyimide, PI) and other flexible film materials.
  • the buffer layer 15 can also provide a flat top surface to facilitate the preparation of the driving circuit layer 20 on the base substrate 10 .
  • the driving circuit layer 20 includes a semiconductor layer 21, a gate insulating layer 22, a gate layer 23, an interlayer insulating layer 24, and a source-drain layer 25, and the semiconductor layer 21 is disposed on the base substrate 10, more specifically, the semiconductor layer 21 is disposed on the buffer layer 15, the semiconductor layer 21 includes a channel region 211 and a source region 212 and a drain located on opposite sides of the channel region 211 District 213.
  • the gate insulating layer 22 covers the semiconductor layer 21 and the base substrate 10 .
  • the gate layer 23 is disposed on the gate insulating layer 22, and the gate layer 23 is patterned to form gates 231 and other signal lines such as gate scanning lines 232.
  • the gates 231 and the semiconductor layer The channel region 211 of 21 is provided correspondingly, and the gate scanning line 232 is electrically connected to the corresponding first binding terminal 11 .
  • the interlayer insulating layer 24 covers the gate layer 23 and the gate insulating layer 22 .
  • the source-drain layer 25 is disposed on the interlayer insulating layer 24, and the source-drain layer 25 is patterned to form other signal lines such as a source electrode 251, a drain electrode 252, and a data line 253.
  • the source electrode 251 The drain electrode 252 is electrically connected to the corresponding source region 212 and the drain region 213 of the semiconductor layer 21 , and the data line 253 is electrically connected to the corresponding first binding terminal 11 .
  • the multiple signal lines of the driving circuit layer 20 include the gate scanning lines 232 and the data lines 253 , and different signal lines are electrically connected to different first binding terminals 11 .
  • the interlayer insulating layer 24 is patterned to form a first via hole 241, and the first via hole 241 penetrates through the interlayer insulating layer 24, the gate insulating layer 22, the buffer layer 15, The second barrier layer 14, the first substrate 13, and the first barrier layer 12 reach the first binding terminal 11, so as to expose part of the upper surface of the first binding terminal 11, so
  • the upper surface of the first binding terminal 11 refers to a surface parallel to and opposite to the lower surface of the first binding terminal 11 .
  • the data line 253 is electrically connected to the first binding terminal 11 through the first via hole 241, and at the same time, the data line 253 is also electrically connected to the source 251 or the drain 252.
  • the data line 253 is electrically connected to the source electrode 251 as an example for illustration.
  • the second via hole 242 and the third via hole 243 are also formed by patterning the interlayer insulating layer 24, and the second via hole 242 has the same structure as the first via hole 241, that is, the second via hole 242 has the same structure as the first via hole 241.
  • the via hole 242 also penetrates through the interlayer insulating layer 24 , the gate insulating layer 22 , the buffer layer 15 , the second barrier layer 14 , the first substrate 13 and the first barrier layer 12 up to the first binding terminal 11 to expose part of the upper surface of the first binding terminal 11 .
  • the third via hole 243 penetrates through the interlayer insulating layer 24 to the gate scan line 232 to expose a part of the gate scan line 232 .
  • the source-drain layer 25 also includes a signal transfer line 254 arranged on the same layer as the data line 253, and the signal transfer line 254 passes through the second via hole 242 and the third via hole 243 to communicate with the data line 253 respectively.
  • the first binding terminal 11 is electrically connected to the gate scanning line 232 , so that the gate scanning line 232 is electrically connected to the first binding terminal 11 .
  • the interlayer insulating layer 24 is patterned to form a plurality of fifth via holes 244, and the plurality of fifth via holes 244 all penetrate the interlayer insulating layer 24 and the gate insulating layer 22, to expose the source region 212 and the drain region 213 respectively.
  • the source 251 is electrically connected to the source region 212 through one of the fifth via holes 244
  • the drain 252 is electrically connected to the drain region 213 through the other fifth via hole 244 .
  • the "same layer setting" in this application means that in the preparation process, the film layer formed by the same material is patterned to obtain at least two different features, and the at least two different features are the same layer settings.
  • the signal transfer line 254 and the data line 253 in this embodiment are obtained by patterning the same conductive film layer, then the signal transfer line 254 and the data line 253 are arranged on the same layer.
  • the plurality of signal lines of the driving circuit layer 20 in the present application are not limited to the data lines 253 and the gate scanning lines 232, and the plurality of signal lines may also include VSS, VDD power lines and other Various signal lines are used for display or non-display, and different signal lines are electrically connected to different first binding terminals 11 to obtain different signals.
  • the data line 253 is electrically connected to the corresponding first binding terminal 11 to obtain a source driving signal and provide it to the source 251;
  • the gate scan line 232 is connected to the corresponding first binding terminal 11.
  • the binding terminal 11 is electrically connected to obtain a gate scan signal and provide it to the gate 231 .
  • the driving circuit layer 20 further includes a planarization layer 26 covering the source-drain layer 25 and the interlayer insulating layer 24 .
  • the structure of the driving circuit layer 20 in the present application is not limited to that shown in this embodiment, the driving circuit layer 20 of the present application may also include more or fewer film layers, and the positional relationship of each film layer is not limited to this embodiment.
  • the gate layer 23 of the present application can also adopt a double gate structure, and the gate layer 23 can also be located under the semiconductor layer 21 to form a bottom gate structure.
  • FIG. 4 is a schematic diagram of a second partial cross-sectional structure of a display component provided by an embodiment of the present application.
  • the display component 2 further includes a light-emitting functional layer 30 disposed on the driving circuit layer 20, and the driving circuit layer 20 is used to provide driving for the light-emitting functional layer 30. voltage to make the light-emitting functional layer 30 emit light.
  • the display component 2 further includes an encapsulation layer 40 .
  • the light emitting functional layer 30 includes a pixel electrode 31 , a pixel definition layer 32 , a light emitting unit 33 and a cathode 34 .
  • the pixel electrode 31 is disposed on the planarization layer 26, and is electrically connected to the source electrode 251 or the drain electrode 252 through the via hole of the planarization layer 26.
  • the electrical connection between the data line 253 and the source electrode 251 is described as an example, and correspondingly, this embodiment is described by taking the electrical connection between the pixel electrode 31 and the drain electrode 252 as an example.
  • the pixel definition layer 32 is disposed on the pixel electrode 31 and the planarization layer 26, and the pixel definition layer 32 is patterned to form a pixel opening, and the pixel opening exposes part of the pixel electrode 31, so as to The installation area of the light emitting unit 33 is defined.
  • the light emitting unit 33 is formed by the light emitting material printed in the pixel opening of the pixel definition layer 32 , and the light emitting material of different colors forms the light emitting unit 33 of different colors.
  • the light-emitting unit 33 may include a red light-emitting unit formed by a red light-emitting material, a green light-emitting unit formed by a green light-emitting material, and a blue light-emitting unit formed by a blue light-emitting material.
  • the red light-emitting unit emits red light
  • the green light-emitting unit emits green light.
  • light, the blue light-emitting unit emits blue light.
  • the cathode 34 covers the light emitting unit 33 and the pixel definition layer 32 .
  • the light emitting unit 33 emits light under the joint action of the pixel electrode 31 and the cathode 34 , and the light emitting unit 33 of different colors emits light of different colors, thereby realizing the pixel display of the display component 2 .
  • the pixel electrode 31 may be a transparent electrode or a reflective electrode. If the pixel electrode 31 is a transparent electrode, the pixel electrode 31 may be made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), Formation of ZnO or In2O3. If the pixel electrode 31 is a reflective electrode, the pixel electrode 31 may include, for example, a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a combination thereof and a reflective layer made of ITO , IZO, ZnO or In2O3 layer. However, the pixel electrode 31 is not limited thereto, and the pixel electrode 31 may be formed of various materials, and may also be formed in a single-layer or multi-layer structure.
  • the pixel electrode 31 is a transparent electrode or a reflective electrode depends on the light emitting direction of the display panel 100.
  • the pixel electrode 31 can be a transparent electrode or a reflective electrode.
  • the electrodes of course, when reflective electrodes are used, the utilization rate of light emitted by the light emitting unit 33 can be improved; when the display panel 100 adopts bottom emission, the pixel electrodes 31 use transparent electrodes to increase the transmittance of light.
  • the display panel 100 adopts top emission as an example for illustration.
  • the cathode 34 needs to be formed of a transparent conductive material.
  • the cathode 34 may be formed of transparent conductive oxide (Transparent Conductive Oxide, TCO) such as ITO, IZO, ZnO or In2O3.
  • TCO Transparent Conductive Oxide
  • the light emitting functional layer 30 may also include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the light emitting unit 33 and the pixel electrode 31; An electron injection layer (EIL) and an electron transport layer (ETL) between the light emitting unit 33 and the cathode 34 .
  • HIL hole injection layer
  • HTL hole transport layer
  • EIL electron injection layer
  • ETL electron transport layer
  • the hole injection layer receives the holes transmitted by the pixel electrode 31, and the holes are transmitted to the light emitting unit 33 through the hole transport layer, and the electron injection layer receives the electrons transmitted by the cathode 34, and the electrons are transmitted to the light emitting unit 33 through the electron transport layer, and the holes and The electrons combine at the position of the light emitting unit 33 to generate excitons, and the excitons transition from the excited state to the ground state to release energy and emit light.
  • the encapsulation layer 40 covers the light-emitting functional layer 30 and is used to protect the light-emitting unit 33 of the light-emitting functional layer 30 and prevent the light-emitting unit 33 from failing due to intrusion of water and oxygen.
  • the encapsulation layer 40 can be encapsulated with a thin film, for example, the encapsulation layer 40 can be a laminated structure formed by sequentially laminating three layers of thin films of a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer or more Multilayer laminated structure.
  • the display panel 100 includes a driving backplane 1 and a plurality of display components 2 arranged in an array on the driving backplane 1, that is, a plurality of the display components 2 are spliced and bound to each other. on the drive backplane 1.
  • a plurality of signal lines of each of the display components 2 are electrically connected to the driving backplane 1 through different first binding terminals 11, specifically, the driving backplane 1 corresponds to each of the display
  • the first binding terminal 11 of the component 2 is provided with a second binding terminal 50, and the second binding terminal 50 is electrically connected to the first binding terminal 11, so that the display component 2 and the The drive backplane 1 is electrically connected.
  • the driving backplane 1 is also provided with a driving chip (not shown in the figure), and the second binding terminal 50 is also electrically connected to the driving chip, so as to transmit the driving signal of the driving chip to the corresponding 2 of the display components.
  • each display component 2 does not need to reserve a frame area to set a driver chip and various binding wirings, so that after a plurality of display components 2 are spliced, there will be no gaps between adjacent display components 2.
  • the large splicing gap solves the problem that there is a large splicing gap at the splicing part of the existing super-large display screen.
  • FIG. 5 is a schematic diagram of a third partial cross-sectional structure of a display component provided by an embodiment of the present application.
  • the base substrate 10 further includes a second substrate 16 disposed on the side of the first barrier layer 12 away from the first substrate 13, and the second substrate 16 The material may be the same as that of the first substrate 13 .
  • the second substrate 16 is provided with an opening 161 in a region corresponding to the first binding terminal 11, and the opening 161 exposes the first binding terminal 11, so that the display component 2 and the drive The backplane 1 achieves good electrical contact.
  • the gate scan line 232 is directly electrically connected to the corresponding first binding terminal 11 , so that no signal transfer line 254 is provided on the source-drain layer 25 .
  • the gate insulating layer 22 is patterned to form a fourth via hole 221, and the fourth via hole 221 penetrates through the gate insulating layer 22, the buffer layer 15, the second barrier layer 14, the The first substrate 13 and the first barrier layer 12 until the first binding terminal 11, so as to expose part of the upper surface of the first binding terminal 11, the gate scanning line 232 passes through the The fourth via hole 221 is electrically connected to the first binding terminal 11 .
  • the above-mentioned embodiments which will not be repeated here.
  • FIG. 6 is a schematic cross-sectional structure diagram of a display device provided by an embodiment of the present application.
  • the display device 1000 includes a casing 200 and a display panel 100 according to one of the above-mentioned embodiments, the casing 200 is formed with an accommodating cavity 201 , and the display panel 100 is disposed in the accommodating cavity 201 .
  • the present application provides a display panel and a display device.
  • the display panel includes a driving backplane and a plurality of display components arrayed on the driving backplane.
  • Each display component includes a plurality of first Binding terminals and a plurality of signal lines arranged on the side away from the driving backplane of the plurality of first binding terminals, each display component is electrically connected to the driving backplane through a plurality of first binding terminals, and each signal line is connected to the driving backplane respectively.
  • the corresponding first binding terminals are electrically connected, and are used to make the driving backplane provide signals to the corresponding signal lines through the first binding terminals, so that there is no need to arrange lines such as driving circuits on the frame of the display component, so as to reduce or eliminate the display components. frame, so that the display panels formed after splicing basically have no splicing seams, so as to alleviate the problem of large splicing gaps at the splicing places of existing super-large display screens.

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Abstract

一种显示面板（100）和显示装置（1000）；该显示面板（100）包括驱动背板（1）以及阵列排布在驱动背板（1）上的多个显示组件（2），每个显示组件（2）包括多个第一绑定端子（11）以及多个信号线，每个显示组件（2）通过多个第一绑定端子（11）与驱动背板（1）电连接，每个信号线分别与对应的第一绑定端子（11）电连接，以缓解现有超大尺寸显示屏的拼接处存在较大拼接缝隙的问题。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
 背景技术
随着显示技术的不断发展，超大尺寸显示屏的应用越来越广泛，超大尺寸显示屏能够满足人们远距离观看、较大信息量显示等需求。出于成本的考虑，目前的超大尺寸显示屏通常采用拼接技术实现，即把多个子显示屏相互拼接形成超大尺寸显示屏。然而当多个显示屏拼接起来时，会在拼接处出现较大的黑色拼接缝隙，严重影响超大尺寸显示屏的显示品味。
因此，现有超大尺寸显示屏的拼接处存在较大拼接缝隙的问题需要解决。
 技术问题
本申请提供一种显示面板和显示装置，以缓解现有超大尺寸显示屏的拼接处存在较大拼接缝隙的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，其包括：
驱动背板；以及
多个显示组件，阵列排布在所述驱动背板上，且每个所述显示组件包括面向所述驱动背板的一侧设置的多个第一绑定端子，每个所述显示组件通过多个所述第一绑定端子与所述驱动背板电连接；
其中，每个所述显示组件还包括设置于多个所述第一绑定端子远离所述驱动背板一侧的多个信号线，每个所述信号线分别与对应的所述第一绑定端子电连接，用于使所述驱动背板通过所述第一绑定端子给对应的所述信号线提供信号。
在本申请实施例提供的显示面板中，所述显示组件还包括衬底基板以及设置于所述衬底基板远离所述驱动背板一侧的驱动电路层，所述衬底基板包括多个所述第一绑定端子，所述驱动电路层包括多个所述信号线。
在本申请实施例提供的显示面板中，所述衬底基板还包括层叠设置在所述第一绑定端子上的第一阻隔层、第一衬底，其中，所述第一衬底面向所述驱动电路层，第一阻隔层覆盖所述第一绑定端子，且所述第一绑定端子的下表面裸露。
在本申请实施例提供的显示面板中，所述衬底基板还包括设置于所述第一阻隔层远离所述第一衬底一侧的第二衬底，所述第二衬底在对应所述第一绑定端子的区域设置有开口。
在本申请实施例提供的显示面板中，所述驱动电路层包括：
半导体层，设置于所述衬底基板上；
栅极绝缘层，覆于所述半导体层及所述衬底基板上；
栅极层，设置于所述栅极绝缘层上，包括栅极和栅极扫描线；
层间绝缘层，覆于所述栅极层及所述栅极绝缘层上；
源漏极层，设置于所述层间绝缘层上，包括源极、漏极以及数据线；
其中，多个所述信号线包括所述栅极扫描线和所述数据线，所述栅极扫描线和所述数据线与对应的所述第一绑定端子电连接。
在本申请实施例提供的显示面板中，所述层间绝缘层图案化形成有第一过孔，所述第一过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述数据线通过所述第一过孔与所述第一绑定端子电连接。
在本申请实施例提供的显示面板中，所述层间绝缘层图案化形成有第二过孔和第三过孔，所述第二过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述第三过孔贯穿至所述栅极扫描线，以裸露出部分所述栅极扫描线，所述源漏极层还包括信号转接线，所述信号转接线分别通过所述第二过孔和所述第三过孔与所述第一绑定端子和所述栅极扫描线电连接。
在本申请实施例提供的显示面板中，所述栅极绝缘层图案化形成第四过孔，所述第四过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述栅极扫描线通过所述第四过孔与所述第一绑定端子电连接。
在本申请实施例提供的显示面板中，所述驱动背板在对应每个所述显示组件的所述第一绑定端子处设置有第二绑定端子，所述第二绑定端子和所述第一绑定端子电连接。
本申请实施例还提供一种显示装置，其包括壳体和前述实施例其中之一的显示面板，所述壳体形成有容纳腔，所述显示面板设置在所述容纳腔内。
 有益效果
本申请提供的显示面板和显示装置中多个显示组件阵列排布在所述驱动背板上，每个所述显示组件包括面向所述驱动背板的一侧设置的多个第一绑定端子，每个所述显示组件通过多个所述第一绑定端子与所述驱动背板电连接，通过在显示组件的一侧设置第一绑定端子与驱动背板电连接，使得驱动背板能够通过第一绑定端子给显示组件内对应的信号线提供信号，从而无需在显示组件的边框设置驱动电路等线路，以减小或消除显示组件的边框，进而使拼接后形成的显示面板基本无拼接缝，解决了现有超大尺寸显示屏的拼接处存在较大拼接缝隙的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的一种俯视结构示意图。
图2为本申请实施例提供的显示面板的部分剖面结构示意图。
图3为本申请实施例提供的显示组件的第一种部分剖面结构示意图。
图4为本申请实施例提供的显示组件的第二种部分剖面结构示意图。
图5为本申请实施例提供的显示组件的第三种部分剖面结构示意图。
图6为本申请实施例提供的显示装置的剖面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
针对现有超大尺寸显示屏的拼接处存在较大拼接缝隙的问题，本申请的发明人在研究中发现，该拼接缝隙主要是由参与拼接形成超大尺寸显示屏的子显示屏的边框导致的，所述子显示屏的边框通常用于放置各种绑定走线以及与绑定走线连接的驱动电路（如源极驱动芯片）等，所述驱动电路给所述子显示屏提供驱动信号，而边框区域是不能显示的，使得相邻的所述子显示屏拼接在一块后形成较大的拼接缝隙，在所述大尺寸显示屏显示时，拼接缝隙处显示为黑线，严重影响超大尺寸显示屏的显示品味。
为此本申请的发明人提出了一种显示面板和显示装置已解决上述问题：
请结合参照图1至图3，图1为本申请实施例提供的显示面板的一种俯视结构示意图，图2为本申请实施例提供的显示面板的部分剖面结构示意图，图3为本申请实施例提供的显示组件的第一种部分剖面结构示意图。所述显示面板100包括驱动背板1以及阵列排布在所述驱动背板1上的多个显示组件2。每个所述显示组件2包括面向所述驱动背板1的一侧设置的多个第一绑定端子11，每个所述显示组件2通过多个所述第一绑定端子11与所述驱动背板1电连接。每个所述显示组件2还包括设置于多个所述第一绑定端子11远离所述驱动背板1一侧的多个信号线（如图2示出的数据线253和图3示出的栅极扫描线232），每个所述信号线分别与对应的所述第一绑定端子11电连接，用于使所述驱动背板1通过所述第一绑定端子11给对应的所述信号线提供信号。
具体地，每个所述显示组件2还包括衬底基板10以及设置于所述衬底基板10远离所述驱动背板1一侧的驱动电路层20，所述衬底基板10包括多个所述第一绑定端子11，所述驱动电路层20包括多个所述信号线。
所述衬底基板10还包括层叠设置在所述第一绑定端子11上的第一阻隔层12、第一衬底13，其中，所述第一衬底13面向所述驱动电路层20，第一阻隔层12覆盖所述第一绑定端子11，且所述第一绑定端子11的下表面裸露。所述第一绑定端子11的下表面是指所述第一绑定端子11远离所述第一阻隔层12的一面，该下表面裸露用于与所述驱动背板1电连接。所述第一绑定端子11可使用抗氧化性强且电阻率低的金属或合金制备，如MO、AL合金等，以保证所述第一绑定端子11的稳定性以及与所述驱动背板1连接的可靠性。
可选地，所述衬底基板10还包括设置于所述第一衬底13远离所述第一阻隔层12一侧的第二阻隔层14以及设置于所述第二阻隔层14远离所述第一衬底13一侧的缓冲层15。其中所述第一阻隔层12、所述第二阻隔层14以及所述缓冲层15均可由氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料形成，以防止不期望的杂质或污染物（例如湿气、氧气等）从所述第一衬底13扩散至可能因这些杂质或污染物而受损的器件中，当然地，本申请的所述衬底基板10不限于此，本申请的衬底基板10可包括更多或更少的无机膜层。而所述第一衬底13的材料包括聚酰亚胺（Polyimide，PI）等柔性薄膜材料。同时所述缓冲层15还可以提供平坦的顶表面，以利于在所述衬底基板10上制备所述驱动电路层20。
可选地，所述驱动电路层20包括半导体层21、栅极绝缘层22、栅极层23、层间绝缘层24以及源漏极层25，所述半导体层21设置于所述衬底基板10上，更具体地，所述半导体层21设置于所述缓冲层15上，所述半导体层21包括沟道区211以及位于所述沟道区211相对两侧的源极区212和漏极区213。所述栅极绝缘层22覆于所述半导体层21及所述衬底基板10上。所述栅极层23设置于所述栅极绝缘层22上，图案化所述栅极层23形成栅极231以及栅极扫描线232等其他信号线，所述栅极231与所述半导体层21的沟道区211对应设置，所述栅极扫描线232与对应的所述第一绑定端子11电连接。所述层间绝缘层24覆于所述栅极层23及所述栅极绝缘层22上。所述源漏极层25设置于所述层间绝缘层24上，图案化所述源漏极层25形成有源极251、漏极252以及数据线253等其他信号线，所述源极251和所述漏极252分别与对应的所述半导体层21的源极区212和漏极区213电连接，所述数据线253与对应的所述第一绑定端子11电连接。其中，所述驱动电路层20的多个所述信号线包括所述栅极扫描线232和所述数据线253，不同的所述信号线与不同的所述第一绑定端子11电连接。
具体地，所述层间绝缘层24图案化形成有第一过孔241，所述第一过孔241贯穿所述层间绝缘层24、所述栅极绝缘层22、所述缓冲层15、所述第二阻隔层14、所述第一衬底13以及所述第一阻隔层12直至所述第一绑定端子11，以裸露出所述第一绑定端子11的部分上表面，所述第一绑定端子11的上表面是指与所述第一绑定端子11的所述下表面平行相对的一面。所述数据线253通过所述第一过孔241与所述第一绑定端子11电连接，同时所述数据线253还与所述源极251或所述漏极252电连接，本申请以所述数据线253与所述源极251电连接为例说明。
进一步地，所述层间绝缘层24图案化还形成有第二过孔242和第三过孔243，所述第二过孔242和所述第一过孔241结构相同，即所述第二过孔242也贯穿所述层间绝缘层24、所述栅极绝缘层22、所述缓冲层15、所述第二阻隔层14、所述第一衬底13以及所述第一阻隔层12直至所述第一绑定端子11，以裸露出所述第一绑定端子11的部分上表面。所述第三过孔243贯穿所述层间绝缘层24至所述栅极扫描线232，以裸露出部分所述栅极扫描线232。所述源漏极层25还包括与所述数据线253同层设置的信号转接线254，所述信号转接线254分别通过所述第二过孔242和所述第三过孔243与所述第一绑定端子11和所述栅极扫描线232电连接，以使所述栅极扫描线232与所述第一绑定端子11电连接。
进一步地，所述层间绝缘层24图案化还形成有多个第五过孔244，多个所述第五过孔244均贯穿所述层间绝缘层24以及所述栅极绝缘层22，以分别裸露出所述源极区212和所述漏极区213。所述源极251通过其中一个所述第五过孔244与所述源极区212电连接，所述漏极252通过另一个所述第五过孔244与所述漏极区213电连接。
需要说明的是，本申请中的“同层设置”是指在制备工艺中，将相同材料形成的膜层进行图案化处理得到至少两个不同的特征，则所述至少两个不同的特征同层设置。比如，本实施例的所述信号转接线254与所述数据线253由同一导电膜层进行图案化处理后得到，则所述信号转接线254与所述数据线253同层设置。
另外，本申请中所述驱动电路层20的多个所述信号线不限于所述数据线253和所述栅极扫描线232，多个所述信号线还可包括VSS、VDD电源线以及其他用于显示或非显示的各种信号线，且不同的所述信号线与不同的所述第一绑定端子11电连接，以获取不同的信号。比如，所述数据线253与对应的所述第一绑定端子11电连接，以获取源极驱动信号并提供给所述源极251；所述栅极扫描线232与对应的所述第一绑定端子11电连接，以获取栅极扫描信号并提供给所述栅极231。
同时为了给所述驱动电路层20提供平坦的表面，所述驱动电路层20还包括覆于所述源漏极层25以及所述层间绝缘层24上的平坦化层26。当然地，本申请中驱动电路层20的结构不限于本实施例示意的，本申请的驱动电路层20还可包括更多或更少的膜层，且各膜层的位置关系也不限于本实施例示意的，比如本申请的所述栅极层23还可采用双栅结构，且所述栅极层23还可位于所述半导体层21的下方，形成底栅结构。
可以理解的是，请结合参照图1至图4，图4为本申请实施例提供的显示组件的第二种部分剖面结构示意图。为了实现所述显示组件2的显示功能，所述显示组件2还包括设置在所述驱动电路层20上的发光功能层30，所述驱动电路层20用于给所述发光功能层30提供驱动电压，以使所述发光功能层30发光。而为了保护所述发光功能层30的可靠性，避免水氧入侵导致发光功能层30失效，所述显示组件2还包括封装层40。
具体地，所述发光功能层30包括像素电极31、像素定义层32、发光单元33以及阴极34。所述像素电极31设置在所述平坦化层26上，并通过所述平坦化层26的过孔与所述源极251或所述漏极252电连接，当然地，由于本实施例以所述数据线253与所述源极251电连接为例说明，则相对应地，本实施例以所述像素电极31与所述漏极252电连接为例说明。所述像素定义层32设置于所述像素电极31以及所述平坦化层26上，且所述像素定义层32图案化形成有像素开口，所述像素开口裸露出部分所述像素电极31，以定义出发光单元33的设置区域。
所述发光单元33是由打印在所述像素定义层32的像素开口内的发光材料形成，不同颜色的发光材料形成不同颜色的发光单元33。比如发光单元33可以包括由红色发光材料形成的红色发光单元，由绿色发光材料形成的绿色发光单元，由蓝色发光材料形成的蓝色发光单元，红色发光单元发出红光，绿色发光单元发出绿光，蓝色发光单元发出蓝光。
所述阴极34覆盖所述发光单元33以及所述像素定义层32。所述发光单元33在所述像素电极31和所述阴极34的共同作用下发光，不同颜色的发光单元33发射不同颜色的光，进而实现所述显示组件2的像素显示。
可选地，所述像素电极31可以是透明电极或反射电极，如果所述像素电极31是透明电极，则所述像素电极31可以由例如氧化铟锡(ITO)、氧化铟锌(IZO)、ZnO或In2O3 形成。如果所述像素电极31是反射电极，则所述像素电极31例如可以包括由Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr或它们的组合形成的反射层以及由 ITO、IZO、ZnO或In2O3形成的层。然而，像素电极31不限于此，像素电极31可以由各种材料形成，并且也可以形成为单层或多层结构。
需要说明的是，所述像素电极31具体是采用透明电极还是反射电极需取决于所述显示面板100的出光方向，当显示面板100采用顶发光时，所述像素电极31可以是透明电极或反射电极，当然地，采用反射电极时能够提高发光单元33发出光线的利用率；当显示面板100采用底发光时，所述像素电极31采用透明电极，以提高光线的透过率。本实施例以所述显示面板100采用顶发光为例说明，如此，为了提高光线的透过率，所述阴极34需采用透明导电材料形成。例如所述阴极34可由ITO、IZO、ZnO或In2O3等透明导电氧化物（Transparent Conductive Oxide，TCO）形成。
可选地，所述发光功能层30还可包括设置于所述发光单元33与所述像素电极31之间的空穴注入层(HIL)、空穴传输层(HTL)；以及设置于所述发光单元33与所述阴极34之间的电子注入层(EIL)、电子传输层(ETL)。空穴注入层接收像素电极31传输的空穴，空穴经由空穴传输层传输至发光单元33，电子注入层接收阴极34传输的电子，电子经由电子传输层传输至发光单元33，空穴和电子在发光单元33位置结合后产生激子，激子由激发态跃迁至基态释放能量并发光。
所述封装层40覆盖所述发光功能层30，用于保护所述发光功能层30的发光单元33，避免水氧入侵导致发光单元33失效。可选地，所述封装层40可采用薄膜封装，比如所述封装层40可以为由第一无机封装层、有机封装层、第二无机封装层三层薄膜依次层叠形成的叠层结构或更多层的叠层结构。
在本实施例，所述显示面板100包括驱动背板1以及阵列排布在所述驱动背板1上的多个显示组件2，也即多个所述显示组件2相互拼接并绑定在所述驱动背板1上。每个所述显示组件2的多个信号线分别通过不同的所述第一绑定端子11与所述驱动背板1电连接，具体地，所述驱动背板1在对应每个所述显示组件2的所述第一绑定端子11处设置有第二绑定端子50，所述第二绑定端子50和所述第一绑定端子11电连接，进而使得所述显示组件2与所述驱动背板1电连接。同时，所述驱动背板1上还设置有驱动芯片（图未示）等，所述第二绑定端子50还与所述驱动芯片电连接，以把所述驱动芯片的驱动信号传输给对应的所述显示组件2。
如此，通过把驱动芯片等外围电路设置在所述驱动背板1上，并在每个所述显示组件2上设置深孔和第一绑定端子11，使得所述显示组件2内的各所述信号线通过深孔与所述第一绑定端子11电连接，并通过对应的所述第二绑定端子50连接到所述驱动芯片，实现信号的传递。从而每个所述显示组件2无需预留边框区域来设置驱动芯片以及各种绑定走线，使得多个所述显示组件2拼接后，相邻的所述显示组件2之间不会存在较大的拼接缝隙，解决了现有超大尺寸显示屏的拼接处存在较大拼接缝隙的问题。
在一种实施例中，请结合参照图1至图5，图5为本申请实施例提供的显示组件的第三种部分剖面结构示意图。与上述实施例不同的是，所述衬底基板10还包括设置于所述第一阻隔层12远离所述第一衬底13一侧的第二衬底16，所述第二衬底16的材料可与所述第一衬底13的材料相同。所述第二衬底16在对应所述第一绑定端子11的区域设置有开口161，所述开口161以裸露出所述第一绑定端子11，使所述显示组件2与所述驱动背板1实现良好的电接触。
同时，所述栅极扫描线232与对应的所述第一绑定端子11直接电连接，从而无需在所述源漏极层25设置信号转接线254。具体地，所述栅极绝缘层22图案化形成第四过孔221，所述第四过孔221贯穿所述栅极绝缘层22、所述缓冲层15、所述第二阻隔层14、所述第一衬底13以及所述第一阻隔层12直至所述第一绑定端子11，以裸露出所述第一绑定端子11的部分上表面，所述栅极扫描线232通过所述第四过孔221与所述第一绑定端子11电连接。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图6，图6为本申请实施例提供的显示装置的剖面结构示意图。所述显示装置1000包括壳体200和上述实施例其中之一的显示面板100，所述壳体200形成有容纳腔201，所述显示面板100设置在所述容纳腔201内。
根据上述实施例可知：
本申请提供一种显示面板和显示装置，显示面板包括驱动背板以及阵列排布在驱动背板上的多个显示组件，每个显示组件包括面向驱动背板的一侧设置的多个第一绑定端子以及设置于多个第一绑定端子远离驱动背板一侧的多个信号线，每个显示组件通过多个第一绑定端子与驱动背板电连接，每个信号线分别与对应的第一绑定端子电连接，用于使驱动背板通过第一绑定端子给对应的信号线提供信号，从而无需在显示组件的边框设置驱动电路等线路，以减小或消除显示组件的边框，进而使拼接后形成的显示面板基本无拼接缝，以缓解现有超大尺寸显示屏的拼接处存在较大拼接缝隙的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括：
    驱动背板；以及
    多个显示组件，阵列排布在所述驱动背板上，且每个所述显示组件包括面向所述驱动背板的一侧设置的多个第一绑定端子，每个所述显示组件通过多个所述第一绑定端子与所述驱动背板电连接；
    其中，每个所述显示组件还包括设置于多个所述第一绑定端子远离所述驱动背板一侧的多个信号线，每个所述信号线分别与对应的所述第一绑定端子电连接，用于使所述驱动背板通过所述第一绑定端子给对应的所述信号线提供信号。
  2. 根据权利要求1所述的显示面板，其中，所述显示组件还包括衬底基板以及设置于所述衬底基板远离所述驱动背板一侧的驱动电路层，所述衬底基板包括多个所述第一绑定端子，所述驱动电路层包括多个所述信号线。
  3. 根据权利要求2所述的显示面板，其中，所述衬底基板还包括层叠设置在所述第一绑定端子上的第一阻隔层、第一衬底，其中，所述第一衬底面向所述驱动电路层，第一阻隔层覆盖所述第一绑定端子，且所述第一绑定端子的下表面裸露。
  4. 根据权利要求3所述的显示面板，其中，所述衬底基板还包括设置于所述第一阻隔层远离所述第一衬底一侧的第二衬底，所述第二衬底在对应所述第一绑定端子的区域设置有开口。
  5. 根据权利要求4所述的显示面板，其中，所述驱动电路层包括：
    半导体层，设置于所述衬底基板上；
    栅极绝缘层，覆于所述半导体层及所述衬底基板上；
    栅极层，设置于所述栅极绝缘层上，包括栅极和栅极扫描线；
    层间绝缘层，覆于所述栅极层及所述栅极绝缘层上；
    源漏极层，设置于所述层间绝缘层上，包括源极、漏极以及数据线；
    其中，多个所述信号线包括所述栅极扫描线和所述数据线，所述栅极扫描线和所述数据线与对应的所述第一绑定端子电连接。
  6. 根据权利要求5所述的显示面板，其中，所述层间绝缘层图案化形成有第一过孔，所述第一过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述数据线通过所述第一过孔与所述第一绑定端子电连接。
  7. 根据权利要求5所述的显示面板，其中，所述层间绝缘层图案化形成有第二过孔和第三过孔，所述第二过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述第三过孔贯穿至所述栅极扫描线，以裸露出部分所述栅极扫描线，所述源漏极层还包括信号转接线，所述信号转接线分别通过所述第二过孔和所述第三过孔与所述第一绑定端子和所述栅极扫描线电连接。
  8. 根据权利要求5所述的显示面板，其中，所述栅极绝缘层图案化形成第四过孔，所述第四过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述栅极扫描线通过所述第四过孔与所述第一绑定端子电连接。
  9. 根据权利要求4所述的显示面板，其中，所述第二衬底的材料和所述第一衬底的材料相同。
  10. 根据权利要求1所述的显示面板，其中，所述驱动背板在对应每个所述显示组件的所述第一绑定端子处设置有第二绑定端子，所述第二绑定端子和所述第一绑定端子电连接。
  11. 一种显示装置，其包括：
    壳体，形成有容纳腔；
    显示面板，设置在所述容纳腔内，所述显示面板包括：
    驱动背板；以及
    多个显示组件，阵列排布在所述驱动背板上，且每个所述显示组件包括面向所述驱动背板的一侧设置的多个第一绑定端子，每个所述显示组件通过多个所述第一绑定端子与所述驱动背板电连接；
    其中，每个所述显示组件还包括设置于多个所述第一绑定端子远离所述驱动背板一侧的多个信号线，每个所述信号线分别与对应的所述第一绑定端子电连接，用于使所述驱动背板通过所述第一绑定端子给对应的所述信号线提供信号。
  12. 根据权利要求11所述的显示装置，其中，所述显示组件还包括衬底基板以及设置于所述衬底基板远离所述驱动背板一侧的驱动电路层，所述衬底基板包括多个所述第一绑定端子，所述驱动电路层包括多个所述信号线。
  13. 根据权利要求12所述的显示装置，其中，所述衬底基板还包括层叠设置在所述第一绑定端子上的第一阻隔层、第一衬底，其中，所述第一衬底面向所述驱动电路层，第一阻隔层覆盖所述第一绑定端子，且所述第一绑定端子的下表面裸露。
  14. 根据权利要求13所述的显示装置，其中，所述衬底基板还包括设置于所述第一阻隔层远离所述第一衬底一侧的第二衬底，所述第二衬底在对应所述第一绑定端子的区域设置有开口。
  15. 根据权利要求14所述的显示装置，其中，所述驱动电路层包括：
    半导体层，设置于所述衬底基板上；
    栅极绝缘层，覆于所述半导体层及所述衬底基板上；
    栅极层，设置于所述栅极绝缘层上，包括栅极和栅极扫描线；
    层间绝缘层，覆于所述栅极层及所述栅极绝缘层上；
    源漏极层，设置于所述层间绝缘层上，包括源极、漏极以及数据线；
    其中，多个所述信号线包括所述栅极扫描线和所述数据线，所述栅极扫描线和所述数据线与对应的所述第一绑定端子电连接。
  16. 根据权利要求15所述的显示装置，其中，所述层间绝缘层图案化形成有第一过孔，所述第一过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述数据线通过所述第一过孔与所述第一绑定端子电连接。
  17. 根据权利要求15所述的显示装置，其中，所述层间绝缘层图案化形成有第二过孔和第三过孔，所述第二过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述第三过孔贯穿至所述栅极扫描线，以裸露出部分所述栅极扫描线，所述源漏极层还包括信号转接线，所述信号转接线分别通过所述第二过孔和所述第三过孔与所述第一绑定端子和所述栅极扫描线电连接。
  18. 根据权利要求15所述的显示装置，其中，所述栅极绝缘层图案化形成第四过孔，所述第四过孔贯穿至所述第一绑定端子，以裸露出所述第一绑定端子的部分上表面，所述栅极扫描线通过所述第四过孔与所述第一绑定端子电连接。
  19. 根据权利要求14所述的显示装置，其中，所述第二衬底的材料和所述第一衬底的材料相同。
  20. 根据权利要求11所述的显示装置，其中，所述驱动背板在对应每个所述显示组件的所述第一绑定端子处设置有第二绑定端子，所述第二绑定端子和所述第一绑定端子电连接。
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