WO2023075093A1 - Transistor et son procédé de fabrication - Google Patents

Transistor et son procédé de fabrication Download PDF

Info

Publication number
WO2023075093A1
WO2023075093A1 PCT/KR2022/010761 KR2022010761W WO2023075093A1 WO 2023075093 A1 WO2023075093 A1 WO 2023075093A1 KR 2022010761 W KR2022010761 W KR 2022010761W WO 2023075093 A1 WO2023075093 A1 WO 2023075093A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
plug
transistor
substrate
via hole
Prior art date
Application number
PCT/KR2022/010761
Other languages
English (en)
Korean (ko)
Inventor
이상민
Original Assignee
주식회사 웨이비스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 웨이비스 filed Critical 주식회사 웨이비스
Priority to CN202280040187.0A priority Critical patent/CN117441233A/zh
Publication of WO2023075093A1 publication Critical patent/WO2023075093A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present invention relates to a transistor and a method for manufacturing the same, and more particularly, to a transistor having a reduced size and a method for manufacturing the same.
  • gallium nitride (GaN)-based transistor is capable of high-speed switching operation compared to conventional silicon (Si)-based transistors and is suitable for ultra-high-speed signal processing, as well as high voltage through the high withstand voltage characteristics of the material itself. It is attracting great attention because it can be applied stably to the environment.
  • a High Electron Mobility Transistor (HEMT) using gallium nitride (GaN) uses a 2-Dimensional Electron Gas (2DEG) generated at the interface between dissimilar materials, thereby increasing the mobility of electrons ( mobility), which is suitable for high-speed signal transmission.
  • 2DEG 2-Dimensional Electron Gas
  • These high electron mobility transistors are made on a substrate on which via-hole etching is very difficult, such as a silicon carbide (SiC) substrate.
  • a substrate on which via-hole etching is very difficult such as a silicon carbide (SiC) substrate.
  • SiC silicon carbide
  • the substrate is processed into a thickness of 100 ⁇ m or less through a back-grinding process, and then a mask pattern is formed on the rear surface of the substrate to perform plasma etching.
  • etching should be stopped when structures on the surface are revealed.
  • a substrate and an epitaxial layer are etched in a state in which a Ni layer is disposed as an etch stop layer capable of stopping etching on an upper portion of the epitaxial layer.
  • the present invention provides a method for electrically connecting a plug to a source electrode and a metal layer formed in a via hole by forming a plug on the front surface of a transistor and etching the via hole only until the surface of the plug is exposed on the rear surface of the substrate, and fabricated through the method Its purpose is to provide a transistor.
  • a method of manufacturing a transistor according to an embodiment of the present invention includes disposing a substrate having an epitaxial layer formed thereon, forming an insulating layer such that a partial region of the epitaxial layer is exposed, and a partial region exposed from the insulating layer in the epitaxial layer. Forming a plug passing through the plug, forming a conductive layer on top of the plug and the exposed epitaxial layer, forming a via hole in the substrate so that the lower surface of the plug is exposed, and forming a metal layer covering the lower portion of the substrate.
  • the forming of the plug may include forming a trench structure by etching the epitaxial layer and forming a plug in the trench structure.
  • the trench structure is characterized in that it is formed to pass through the epitaxial layer to a part of the substrate.
  • the step of processing the lower surface of the substrate to reduce the thickness of the substrate is characterized in that it further comprises.
  • the plug and the via hole are characterized in that the width of the via hole is greater than that of the plug in the lateral direction.
  • the via hole is characterized in that the width of the upper part of the via hole that contacts the lower surface of the plug is smaller than or equal to the width of the lower part of the via hole that does not contact the lower surface of the plug.
  • the forming of the via hole is characterized in that a lower region of the plug is exposed by forming the via hole by etching a portion of the epitaxial layer through the substrate.
  • the method may further include forming an ion implantation layer by implanting an n-type dopant into at least a portion of the epitaxial layer after the step of disposing the substrate.
  • the epitaxial layer is characterized by including a buffer layer and a barrier layer sequentially disposed on the substrate.
  • GaN gallium nitride
  • the forming of the metal layer is characterized by filling the inside of the via hole.
  • a transistor according to an embodiment of the present invention includes a substrate having an epitaxial layer formed thereon, an insulating layer disposed on an upper portion of the epitaxial layer, and a partial region of the epitaxial layer exposed, and a plug penetrating a partial region of the epitaxial layer exposed from the insulating layer. and a conductive layer disposed above the plug and the exposed epitaxial layer and in contact with the plug, and a metal layer disposed below the substrate, in contact with the plug exposed from the substrate, and electrically connected to the conductive layer through the plug.
  • the substrate includes a via hole formed at a position where a plug is disposed.
  • the via hole is characterized in that the upper width of the via hole is smaller than or equal to the width of the lower part of the via hole that is in contact with the lower surface of the plug.
  • the epitaxial layer is characterized by including a buffer layer and a barrier layer sequentially disposed on the substrate.
  • GaN gallium nitride
  • the plug penetrates through the epitaxial layer to a portion of the substrate, and the metal layer surrounds a lower region of the plug exposed from the substrate.
  • it is characterized in that it further comprises an ion implantation layer disposed on the upper portion of the epitaxial layer located on the lower portion of the conductive layer.
  • the end of the ion implantation layer overlaps the non-exposed region of the insulating layer.
  • the metal layer is formed to fill the inside of the via hole.
  • the plug is characterized in that it is formed in a T-shape.
  • the plug is characterized in that different metals are formed in multiple layers on at least a portion thereof.
  • the plug is characterized in that the lower width of the plug is smaller than the upper width of the via hole that is not in contact with the plug, and the upper width overlapping the conductive layer is smaller than the upper width of the via hole. .
  • the plug is characterized in that it contacts the metal layer at its lower surface or in its lower region.
  • a transistor includes a source electrode, a drain electrode and a gate electrode.
  • the plug and the via hole are formed below the source electrode.
  • the via hole is etched only until the surface of the plug is exposed on the rear surface of the substrate, thereby saving etching time and simplifying the etching process.
  • the buffer layer serves as the etch stop layer
  • a separate etch stop layer may be omitted.
  • the present invention does not penetrate the buffer layer and has a relatively smaller width than the prior art, the minimum size of the source electrode is relatively smaller than that of the prior art, so that the transistor can be miniaturized by dramatically reducing the size.
  • the buffer layer of the present invention remains without penetrating through the via hole, mechanical stability is excellent compared to the prior art, and thus the occurrence of failure due to mechanical problems caused by temperature change of the transistor can be reduced.
  • the thermal conductivity of the present invention can be increased, thereby improving heat dissipation characteristics.
  • FIG. 1 is a cross-sectional view showing a transistor according to an exemplary embodiment of the present invention.
  • 2A to 2K are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.
  • FIG 3 is a cross-sectional view showing a transistor according to another embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a transistor according to an exemplary embodiment of the present invention.
  • the transistor 10 includes a substrate 110, an epitaxial layer 120, an ion implantation layer 130, an insulating layer 140, and a conductive layer 150. and a metal layer 160 .
  • the substrate 110 may have an epitaxial layer 120 formed thereon.
  • the substrate 110 may be a silicon carbide (SiC) substrate, a silicon (Si) substrate, or a sapphire substrate.
  • the substrate 110 is a high purity single crystal form (High Purity Semi-Insulating, HPSI) or vanadium doped high resistance (Vanadium doped) that can reduce the leakage current of the transistor 10 It may be made of a substrate 110 of -resistance.
  • the epitaxial layer 120 may include a buffer layer 121 and a barrier layer 123 sequentially disposed on the substrate 110 .
  • the epitaxial layer 120 is a nitride-based semiconductor layer
  • GaN gallium nitride
  • the buffer layer 121 of the epitaxial layer 120 is made of a gallium nitride (GaN) layer
  • the barrier layer 123 is a gallium nitride (GaN) layer and an aluminum gallium nitride (Al x Ga y N) layer.
  • the ion implantation layer 130 may be disposed on the lower epitaxial layer 120 of the conductive layer 150, specifically at a position corresponding to the source electrode 150 (SE) or drain electrode 150 (DE) region. can be placed.
  • the ion implantation layer 130 is formed using an n-type dopant, and may be formed and disposed up to the buffer layer 121 after passing through the barrier layer 123 .
  • the insulating layer 140 may be disposed on top of the epitaxial layer 120 .
  • the insulating layer 140 may be disposed such that a partial region of the ion implantation layer 130 is exposed without covering the entire surface of the ion implantation layer 130, and a conductive layer is formed on the exposed portion of the ion implantation layer 130. (150) can be contacted. Accordingly, an end of the ion implantation layer 130 may overlap the insulating layer 140 and the conductive layer 150 in a region that is not exposed due to the insulating layer 140 .
  • the insulating layer 140 may be formed of, for example, nitride or oxide such as SiN, SiO 2 , or AlN.
  • the insulating layer 140 may be made of various materials capable of reducing surface traps of the epitaxial layer 120 without exposing the epitaxial layer 120 .
  • the plug P may be disposed through a partial region of the ion implantation layer 130 exposed from the insulating layer 140 . Specifically, the plug P may be disposed penetrating the ion implantation layer 130 and the epitaxial layer 120 so that one end may be positioned at the interface between the substrate 110 and the epitaxial layer 120 .
  • the plug P may be made of a metal material having corrosion resistance, and may be formed in a T shape with respect to the ion implantation layer 130 .
  • the conductive layer 150 may be disposed on the plug P and the exposed ion implantation layer 130 and may contact the plug P.
  • the conductive layers 150 disposed apart from each other in FIG. 1 may correspond to the source electrode 150 (SE) and the drain electrode 150 (DE), respectively, and include nickel (Ni), copper (Cu), gold ( Au), aluminum (Al), silicon (Si), it may be made of a material such as titanium (Ti).
  • the metal layer 160 may be disposed under the substrate 110 .
  • the metal layer 160 may be formed of a material such as titanium (Ti), titanium nitride (TiN), nickel (Ni), tantalum (Ta), or tantalum nitride (TaN) to increase adhesion and prevent diffusion of the metal layer 160.
  • a material such as copper (Cu) or gold (Au) may be formed in multiple layers to increase electrical and thermal conductivity.
  • the metal layer 160 may contact the plug P exposed from the substrate 110 and be electrically connected to the conductive layer 150 through the plug P.
  • the metal layer 160 is electrically connected by contacting the lower surface of the plug P exposed from the substrate 110, or electrically connected by contacting the lower surface of the plug P exposed from the substrate 110. can be connected
  • the substrate 110 may include a via hole H at a position corresponding to the position where the plug P is disposed. .
  • the buffer layer 121 serves as a conventional etch stop layer, and the substrate 110 is etched to the buffer layer 121 to expose the lower surface of the plug P. can be formed
  • a lower width W3 of the plug P in contact with the via hole H may be smaller than an upper width W1 of the via hole H in contact with the plug P.
  • the upper width W4 of the plug P overlapping the source electrode 150 (SE) may be formed to be larger than the upper width W1 of the via hole H. That is, the upper width W4 of the plug P may determine the minimum size of the source electrode 150 (SE).
  • the plug P is disposed on the top of the substrate 110, and the metal layer 160 disposed on the bottom of the substrate 110 and the plug P are electrically connected through the via hole H formed in the substrate 110.
  • the plug P is disposed on the top of the substrate 110, and the metal layer 160 disposed on the bottom of the substrate 110 and the plug P are electrically connected through the via hole H formed in the substrate 110.
  • the etching width should increase as the etching depth of the via hole H increases.
  • the conventional via hole is formed with a width corresponding to the substrate and the epitaxial layer. That is, the width of the conventional via hole determines the minimum size of the source electrode and furthermore the minimum size of the transistor, but the via hole H in the present invention does not penetrate the buffer layer 121 and is etched to a smaller depth than in the prior art.
  • the minimum size of the source electrode 150 (SE) can also be relatively smaller than the conventional one, and accordingly the size of the transistor 10 can be miniaturized by drastically reducing
  • the etching width should increase as the etching depth of the via hole H increases.
  • the aspect ratio which is the ratio between the etching width and the etching depth of the via hole (H) may vary depending on the performance of the etching equipment and the material of the etching mask pattern, but in the case of a silicon carbide (SiC) substrate, it is about 3:1 to 4:1 It has a certain aspect ratio. Therefore, when the via hole is etched to a depth of 100 ⁇ m in the conventional manner, the etching width becomes about 30 ⁇ m or more. On the other hand, in the present invention, when the via hole H is etched to a depth of 5 ⁇ m exposing the lower surface of the plug, the etching width is about 2 ⁇ m or less.
  • the source electrode 150 (SE) of may be smaller than in the prior art.
  • the source electrode 150 (SE) may have a width of 10 ⁇ m or less. there is.
  • the minimum size of the source electrode 150 (SE) is relatively smaller than the prior art because the via hole H has a relatively smaller width than the conventional transistor ( 10) can be miniaturized by drastically reducing the size.
  • the metal layer 160 is the surface of the substrate 110 It can be arranged in the same form as That is, the metal layer 160 may be disposed to cover the inner surface of the via hole H without completely filling the via hole H.
  • the source electrode pad PSE, the drain electrode pad PDE, and the gate electrode GE may be disposed on the epitaxial layer 120 and the metal layer 160 .
  • the source electrode pad PSE and the drain electrode pad PDE may be disposed on the source electrode 150 (SE) and the drain electrode 150 (DE), respectively, and the gate electrode GE is an exposed epitaxial layer ( 120, that is, between the source electrode 150 (SE) and the drain electrode 150 (DE).
  • an additional insulating layer may be disposed on the gate electrode GE, and a source connection field plate (Source Connected Field Plate, SCFP; not shown) may be disposed.
  • SCFP Source Connected Field Plate
  • the transistor 10 passes through the metal layer 160 without a separate electrical connection such as wire bonding. An electrical connection may be made to the source electrode 150 (SE).
  • 2A to 2K are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.
  • a method of manufacturing a transistor 10 includes disposing a substrate 110 on which an epitaxial layer 120 is formed, an insulating layer such that a partial region of the epitaxial layer 120 is exposed ( 140), forming a plug P penetrating a partial region exposed from the insulating layer 140 in the epitaxial layer 120, conducting on the plug P and the exposed epitaxial layer 120 It may include forming a layer 150, forming a via hole H in the substrate 110 to expose the lower surface of the plug P, and forming a metal layer 160 covering the lower portion of the substrate. there is.
  • a substrate 110 having an epitaxial layer 120 formed thereon may be disposed.
  • the substrate 110 may be a silicon carbide (SiC) substrate, a silicon (Si) substrate, or a sapphire substrate.
  • the substrate 110 is a high-purity single-crystal form (High Purity Semi-Insulating, HPSI) or vanadium-doped high-resistance (Vanadium doped) that can reduce the leakage current of the transistor 10. resistance) of the substrate 110.
  • the epitaxial layer 120 is a nitride-based semiconductor layer that can be grown on the substrate 110 and may include a buffer layer 121 and a barrier layer 123 that are sequentially disposed.
  • the buffer layer 121 of the epitaxial layer 120 is made of a gallium nitride (GaN) layer
  • the barrier layer 123 is a gallium nitride (GaN) layer and an aluminum gallium nitride (Al x Ga y N) layer.
  • the epitaxial layer 120 may be grown on the substrate 110 using various known methods such as MOCVD, MBE, or HVPE, and the growth height of the epitaxial layer 120 may be about 0.5 to 5 ⁇ m.
  • an ion implantation layer 130 may be formed by implanting an n-type dopant into at least a portion of the epitaxial layer 120 .
  • an ion implantation mask pattern may be formed on the epitaxial layer 120 to expose a partial region of the epitaxial layer 120, and then Si+ ions may be implanted.
  • the ion implantation layer 130 may be formed in the regions of the barrier layer 123 and the buffer layer 121 .
  • an insulating layer 140 may be formed on the ion implantation layer 130 .
  • an insulating layer 140 made of a nitride or oxide such as SiN, SiO 2 , or AlN may be deposited on the entire upper surface of the ion implantation layer 130 .
  • the insulating layer 140 does not expose the epitaxial layer 120 on top of the ion implantation layer 130, reduces surface traps of the epitaxial layer 120 and the ion implantation layer 130, and It may be a variety of materials capable of reducing thermal shock.
  • the insulating layer 140 may be formed before the ion implantation layer 130 is formed or may be formed after the ion implantation layer 130 is formed.
  • a portion of the insulating layer 140 may be removed to expose a portion of the epitaxial layer 120 .
  • the region where the source electrode 150 (SE) and the drain electrode 150 (DE) are to be formed is removed from the insulating layer 140 deposited on the entire upper surface of the epitaxial layer 120 and the ion implantation layer 130
  • the epitaxial layer 120 not only the epitaxial layer 120 but also an upper portion of the ion implantation layer 130 may be exposed.
  • the ohmic contact resistance may be further reduced by removing the barrier layer 123 together.
  • a plug P penetrating a partial region exposed from the insulating layer 140 in the epitaxial layer 120 may be formed.
  • the upper portions of the epitaxial layer 120 and the ion implantation layer 130 where the source electrode 150 (SE) is to be formed may be etched until the upper surface of the substrate 110 is exposed to form a trench structure.
  • about 0.5 to 5 ⁇ m may be etched according to the thickness of the epitaxial layer 120 to form the plug P.
  • the size of the source electrode 150 (SE) can be determined by the size of the plug P, and thus the size of the source electrode 150 (SE) can be minimized. . A detailed description thereof will be described later.
  • the T-shaped plug P may be formed by filling the metal having corrosion resistance.
  • the plug P may be formed by filling the trench etched region with a material such as nickel (Ni), copper (Cu), or gold (Au).
  • a metal film such as titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or platinum (Pt) is formed between the plug P and the ion implantation layer 130
  • Ti titanium
  • Ta tantalum
  • TaN tantalum nitride
  • W tungsten
  • Pt platinum
  • a conductive layer 150 corresponding to the source electrode 150 (SE) and the drain electrode 150 (DE) on the plug P and the exposed epitaxial layer 120 can form
  • a material such as nickel (Ni), copper (Cu), gold (Au), aluminum (Al), silicon (Si), or titanium (Ti) is placed on the plug P and the exposed epitaxial layer 120. may be deposited to form the conductive layer 150 .
  • heat treatment such as a rapid thermal annealing process may be performed to reduce electrical contact resistance between the conductive layer 150 and the ion implantation layer 130 .
  • gate electrodes GE may be formed between the conductive layers 150 at both ends corresponding to the source electrode 150 (SE) and the drain electrode 150 (DE). there is. Specifically, a portion of the insulating layer 140 between the source electrode 150 (SE) and the drain electrode 150 (DE) is removed, and on top of the exposed epitaxial layer 120, for example, nickel (Ni), etc. A material may be deposited to form the gate electrode GE.
  • the lower surface of the substrate 110 may be processed to reduce the thickness of the substrate 110 .
  • the lower surface of the silicon carbide (SiC) substrate 110 may be polished so that the thickness D of the substrate 110 is about 85 ⁇ m, and a mechanical or chemical treatment method may be used as the polishing method.
  • a via hole H may be formed in the substrate 110 to expose a lower surface of the plug P.
  • a mask pattern may be grown on an area of the lower surface of the substrate 110 except for an area corresponding to the plug P, and after etching an area exposed from the mask pattern, the mask pattern may be removed.
  • the mask pattern may be made of nickel (Ni).
  • the via hole H may be formed by etching from the lower surface of the substrate 110 to a predetermined depth. It may be smaller than or equal to the width W2. If the upper width W1 of the via hole H is greater than the lower width W2, the metal layer 160 is not continuous but is formed in a broken form when forming the metal layer 160, or an empty space in the metal layer 160 A void is formed, which may cause deterioration in performance or reliability of the transistor 10 .
  • the metal layer 160 may be more easily formed inside the via hole H.
  • a portion of the epitaxial layer 120 may be etched through the substrate 110 .
  • the via hole H extends to a partial area of the epitaxial layer 120, the lower area of the plug P may be exposed. That is, in addition to the lower surface of the plug P, the lower region of the plug P including the lower surface of the plug P is exposed, and the metal layer 160 is the lower region of the plug P exposed from the substrate 110. can wrap Through this, as the contact surface between the metal layer 160 and the plug P increases, electrical connectivity between the metal layer 160 and the plug P can be further improved.
  • a metal layer 160 covering a lower portion of the substrate 110 may be formed.
  • the metal layer 160 is thinly formed along the inner surface of the via hole H to the same thickness as the thickness formed on the substrate 110, or as shown in FIG. 1, the inside of the via hole H is formed using a filling plating process. It can be formed into a flat shape by filling it with metal.
  • the metal layer 160 is formed of materials such as titanium (Ti), titanium nitride (TiN), nickel (Ni), tantalum (Ta), tantalum nitride (TaN), and electricity and heat to increase adhesion and prevent diffusion of the metal layer 160.
  • materials such as copper (Cu) and gold (Au) may be formed in multiple layers.
  • the metal layer 160 may contact the plug P exposed from the substrate 110 and be electrically connected to the source electrode 150 (SE) through the plug P.
  • the surface of the metal layer 160 may be polished mechanically or chemically.
  • a source electrode pad PSE and a drain electrode pad are formed in an upper region corresponding to the source electrode 150 (SE) and the drain electrode 150 (DE) of the conductive layer 150.
  • PDE can be formed.
  • the source electrode pad PSE and the drain electrode pad PDE may be formed of a material such as copper (Cu), gold (Au), or aluminum (Al).
  • the plug P is formed on the front surface of the substrate 110, and the via hole H is formed on the rear surface of the substrate 110 so as not to penetrate the buffer layer 121, so that a conventional etch stop layer is used.
  • a conventional etch stop layer is used.
  • the buffer layer 121 serves as an etch stop layer, a separate etch stop layer configuration can be omitted, the etching process of the via hole H can be simplified, and etching is stopped by the thick buffer layer 121 Because of this, the via hole can be etched without fear of being under- or over-etched.
  • the buffer layer 121 of the present invention since the buffer layer 121 of the present invention remains without penetrating the via hole H, it has excellent mechanical stability compared to the prior art, thereby reducing the occurrence of failure due to mechanical problems due to temperature change of the transistor 10 can
  • the thermal conductivity can be increased and the heat dissipation characteristics can be improved.
  • FIG 3 is a cross-sectional view showing a transistor according to another embodiment of the present invention.
  • the transistor 10 includes a substrate 110, an epitaxial layer 120, an ion implantation layer 130, an insulating layer 140, and a conductive layer 150. and a metal layer 160 .
  • the plug P in the other embodiment of FIG. 3 is the insulating layer 140 It may pass through the epitaxial layer 120 exposed from the substrate 110 and pass through.
  • the lower region of the plug P is exposed in addition to the lower surface of the plug P, and the metal layer 160 may cover the lower region of the plug P exposed from the substrate 110. .
  • the contact surface between the metal layer 160 and the plug P increases, electrical connectivity between the metal layer 160 and the plug P can be further improved.
  • the via hole is etched only until the surface of the plug is exposed on the rear surface of the substrate, thereby saving etching time. Therefore, it is possible to reduce the manufacturing time of the transistor, so there is industrial applicability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un transistor, et un procédé de fabrication d'un transistor comprenant les étapes consistant à : disposer un substrat ayant une couche épitaxiale sur celui-ci ; former une couche isolante de manière à exposer une partie de la couche épitaxiale ; former une fiche pénétrant dans une région partielle exposée à partir de la couche isolante dans la couche épitaxiale ; former une couche conductrice au-dessus de la fiche et de la couche épitaxiale exposée ; former un trou d'interconnexion dans le substrat de manière à exposer une surface inférieure de la fiche ; et former une couche métallique recouvrant une partie inférieure du substrat.
PCT/KR2022/010761 2021-10-28 2022-07-29 Transistor et son procédé de fabrication WO2023075093A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202280040187.0A CN117441233A (zh) 2021-10-28 2022-07-29 晶体管及其制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20210145640 2021-10-28
KR10-2021-0145640 2021-10-28

Publications (1)

Publication Number Publication Date
WO2023075093A1 true WO2023075093A1 (fr) 2023-05-04

Family

ID=86159468

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2022/010761 WO2023075093A1 (fr) 2021-10-28 2022-07-29 Transistor et son procédé de fabrication

Country Status (3)

Country Link
KR (1) KR20230061224A (fr)
CN (1) CN117441233A (fr)
WO (1) WO2023075093A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080073752A1 (en) * 2006-09-27 2008-03-27 Nec Electronics Corporation Semiconductor apparatus
US20090001478A1 (en) * 2007-06-29 2009-01-01 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20130146946A1 (en) * 2010-08-06 2013-06-13 Panasonic Corporation Semiconductor device and method for fabricating same
KR20170048125A (ko) * 2015-10-23 2017-05-08 주식회사 기가레인 고전자이동도 트랜지스터 및 그의 제조방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5298559B2 (ja) 2007-06-29 2013-09-25 富士通株式会社 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080073752A1 (en) * 2006-09-27 2008-03-27 Nec Electronics Corporation Semiconductor apparatus
US20090001478A1 (en) * 2007-06-29 2009-01-01 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20130146946A1 (en) * 2010-08-06 2013-06-13 Panasonic Corporation Semiconductor device and method for fabricating same
KR20170048125A (ko) * 2015-10-23 2017-05-08 주식회사 기가레인 고전자이동도 트랜지스터 및 그의 제조방법

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KWON HO-SANG, CHOI GIL-WONG, LEE SANG-MIN, KIM DONG-WOOK: "S-Band 300-W GaN HEMT Internally Matched Power Amplifier", THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE - JOURNAL OF KIEES, THE KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE, KOREA, vol. 31, no. 1, 1 January 2020 (2020-01-01), Korea , pages 43 - 50, XP093061020, ISSN: 1226-3133, DOI: 10.5515/KJKIEES.2020.31.1.43 *

Also Published As

Publication number Publication date
CN117441233A (zh) 2024-01-23
KR20230061224A (ko) 2023-05-08

Similar Documents

Publication Publication Date Title
US7217954B2 (en) Silicon carbide semiconductor device and method for fabricating the same
US7659574B2 (en) Manufacturing method of semiconductor device
CN111656498B (zh) 半导体装置及其制造方法
JP3086906B1 (ja) 電界効果トランジスタ及びその製造方法
US20020003290A1 (en) Semiconductor devices and methods for manufacturing the same
JPH0745815A (ja) 半導体装置およびその製造方法
WO2017069461A1 (fr) Transistor à haute mobilité électronique et son procédé de fabrication
JPH09260405A (ja) 半導体装置とその製造方法
JPH03262136A (ja) シリコン基板上に第３族−第５族材料で製造された高性能トランジスタの改良及びその製造方法
WO2023075093A1 (fr) Transistor et son procédé de fabrication
CN116013776B (zh) 屏蔽栅沟槽型晶体管的制备方法及屏蔽栅沟槽型晶体管
KR20060117179A (ko) 반도체 장치 및 반도체 장치의 제조 방법
KR0122736B1 (ko) 바이폴라트랜지스터 및 그 제조방법
JPH0766959B2 (ja) 集積回路の製造方法
CN115547830A (zh) 氮化镓功率器件的制作方法、器件以及集成电路
WO2017069464A1 (fr) Transistor à haute mobilité électronique et son procédé de fabrication
WO2018110833A1 (fr) Transistor à grande mobilité d'électrons et son procédé de fabrication
WO2017069462A1 (fr) Transistor à haute mobilité d'électrons et son procédé de fabrication
JP3298472B2 (ja) 絶縁ゲート型半導体装置の製造方法
WO2018110831A1 (fr) Dispositif électronique à base de nitrure et son procédé de fabrication
WO2017069460A2 (fr) Transistor à haute mobilité électronique et son procédé de fabrication
WO2017069463A1 (fr) Transistor à haute mobilité électronique et son procédé de fabrication
WO2016208864A1 (fr) Transistor à base de nitrure pour mise en œuvre de hors service normal
WO2010131849A2 (fr) Dispositif luminescent à semi-conducteurs
WO2024085528A1 (fr) Transistor à couches minces et son procédé de fabrication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22887299

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202280040187.0

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE