WO2017069460A2 - Transistor à haute mobilité électronique et son procédé de fabrication - Google Patents

Transistor à haute mobilité électronique et son procédé de fabrication Download PDF

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Publication number
WO2017069460A2
WO2017069460A2 PCT/KR2016/011534 KR2016011534W WO2017069460A2 WO 2017069460 A2 WO2017069460 A2 WO 2017069460A2 KR 2016011534 W KR2016011534 W KR 2016011534W WO 2017069460 A2 WO2017069460 A2 WO 2017069460A2
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Prior art keywords
source electrode
insulating layer
pad
electrode wiring
drain electrode
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PCT/KR2016/011534
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English (en)
Korean (ko)
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WO2017069460A3 (fr
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이상민
정연국
구황섭
김현제
정희석
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(주)기가레인
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Priority claimed from KR1020160047549A external-priority patent/KR101856687B1/ko
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Publication of WO2017069460A2 publication Critical patent/WO2017069460A2/fr
Publication of WO2017069460A3 publication Critical patent/WO2017069460A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present invention relates to a high electron mobility transistor and a method of manufacturing the same, and more particularly, to a high electron mobility transistor and a method of manufacturing the same to improve the yield of the device and the reliability of the device.
  • gallium nitride-based transistors Due to the development of information and communication technology, the demand for high withstand voltage transistors operating in a high speed switching environment or a high voltage environment is increasing. Recently, gallium nitride-based transistors have a high-speed switching operation compared to conventional silicon-based transistors, and are suitable for high-speed signal processing and can be applied to high-voltage environments through the high voltage resistance of the material itself. It is getting attention. Particularly in the case of High Electron Mobility Transistor (HEMT) using gallium nitride, electron mobility (2DEG; 2-Dimensional Electron Gas) generated at the interface between heterogeneous materials is used. Mobility can be increased, which is an advantage for high speed signal transmission.
  • HEMT High Electron Mobility Transistor
  • a source electrode wiring electrically connected to the source electrode is formed under the source electrode in order to minimize the size thereof. Etching to a depth to form a source electrode wiring via penetrating the lower portion of the source electrode, and to form a source electrode wiring by plating a thin metal film on the surface of the source electrode wiring via.
  • the source electrode wiring forming process performs the back-grinding process to etch to a predetermined depth from the rear surface of the thinned substrate, the etching rate is reduced and the etching uniformity is lowered than the case of etching the thick substrate before the back-grinding process.
  • cracks are generated in the substrate, thereby lowering the yield of the device and the reliability of the device.
  • the process of forming the source electrode wiring is one of materials in which a substrate made of the SiC wafer, etc., is difficult to form vias, and thus, the substrate is formed at a predetermined depth from a rear surface of the substrate. -As the grinding process does not use the low temperature binder and the high temperature binder is difficult to remove, the process is very difficult and the yield of the device is lowered.
  • the source electrode wiring forming process forms a source electrode wiring by plating a thin metal film on the surface of the source electrode wiring via, so that most of the source electrode wiring via is empty so that the thermal conductivity of the device is low due to low thermal conductivity. There is this.
  • the solder used for solder bonding for packaging the device may be located at the front of the substrate through the bottom of the via. There is a problem that the reliability of the device may be lowered and the life of the device may be shortened.
  • An object of the present invention is to simplify the process by forming a source electrode wiring electrically connected to the source electrode under the source electrode to minimize the size of the transistor, to form the source electrode wiring in the front and to fill the via for source electrode wiring with a conductor. To provide a high electron mobility transistor and a method of manufacturing the same that can improve the heat dissipation of the device.
  • a high electron mobility transistor according to an embodiment of the present invention
  • the stepped portion may be formed at both sides of the source electrode and the drain electrode to cover a portion of an upper surface of the first insulating layer.
  • a second insulating layer formed on the first insulating layer, wherein the second insulating layer covers a portion of an upper surface of each of the source electrode and the drain electrode, between the first insulating layer and the via pad for source electrode wiring.
  • the recess is formed on the upper portion of the source electrode at all times.
  • the source electrode pad and the drain electrode pad cover portions of upper surfaces of both sides of the electrode, and the source electrode and the exposed portion of the source electrode and the drain electrode are removed by removing a portion of the first insulating layer and the second insulating layer, respectively. It is formed on the drain electrode.
  • the diameter of the upper portion of the via pad for source electrode wiring is greater than that of the lower portion of the rear side.
  • the via pad for source electrode wiring may be any one of copper and gold.
  • the base layer includes a gallium nitride (GaN) layer.
  • forming a second insulating layer on an entire surface of the gate electrode After forming the gate electrode, forming a second insulating layer on an entire surface of the gate electrode; And removing a portion of the first insulating layer and the second insulating layer on the source electrode and the drain electrode to form a source electrode pad and a drain electrode pad on the exposed source electrode and the drain electrode, respectively.
  • a method of manufacturing a high electron mobility transistor includes forming a base layer on a substrate on which a source electrode wiring forming portion is defined; Forming a first insulating layer on the front surface; Forming vias for source electrode wiring by etching the first insulating layer, the base layer, and the substrate on the source electrode wiring forming portion to a predetermined depth from a front surface thereof; Filling the source electrode wiring via with a conductor to form a via pad for source electrode wiring; A source on the base layer exposed by removing a portion of the first insulating layer adjacent to the source electrode wiring via pad and a portion of the first insulating layer spaced apart from the source electrode via via pad Forming an electrode and a drain electrode; And removing a portion of the first insulating layer between the source electrode and the drain electrode to form a gate electrode on the exposed base layer.
  • the gate electrode After forming the gate electrode, forming a second insulating layer on an entire surface of the gate electrode; And removing a portion of the second insulating layer on the source electrode and the drain electrode to form a source electrode pad and a drain electrode pad on the exposed source electrode and the drain electrode, respectively.
  • a diameter of an upper portion in a front side direction is larger than a diameter of a lower portion in a rear side direction.
  • An upper surface area of the via pad for source electrode wiring occupies 50% or more of the bottom area of the source electrode.
  • At least one via pad for source electrode wiring is formed. It said base layer includes a gallium nitride (GaN) layer.
  • the high electron mobility transistor according to the present invention and a method of manufacturing the same have a method of forming a source electrode wiring electrically connected to the source electrode under the source electrode.
  • the back-grinding process is performed to increase the etching speed, improve the etching uniformity, and improve the cracking of the substrate, compared to the conventional technique of etching the back surface of the thinned substrate to a predetermined depth. By suppressing the effect of improving the yield of the device and the reliability of the device.
  • the present invention forms a via pad for the source electrode wiring and performs the back-grinding process, so that the back-grinding process is performed without the substrate etching process for forming the source electrode wiring via, so that the high temperature bonding agent in the back-grinding process is performed.
  • a low temperature binder which can be more easily removed can be used to facilitate the process, thereby improving the yield of the device.
  • the present invention forms a via pad for source electrode wiring by etching and filling to a predetermined depth from the entire surface of the substrate in a thick state, so that all the vias for the source electrode wiring are filled, so that the thermal conductivity of the prior art is higher than that of the via for the empty source electrode wiring. It has a high effect to improve the heat dissipation of the device to improve the performance of the device.
  • the present invention forms a via pad for source electrode wiring by etching and filling to a predetermined depth from the entire surface of the thick substrate, so that solder and flux used for solder bonding for packaging the device cannot flow into the substrate, thereby ensuring reliability of the device. It has the effect of improving the performance and preventing the shortening of the life of the device.
  • the present invention can be etched more stably by etching a thick substrate to a predetermined depth from the front surface, it is possible to form a wider width of the via pad for source electrode wiring than the etching of a thin substrate to a predetermined depth from the rear surface. There can improve the electrical conductivity and thermal conductivity.
  • FIG. 1 is a cross-sectional view showing a high electron mobility transistor according to a first embodiment.
  • FIG. 2 is a plan view illustrating a plurality of via pads for source electrode wiring formed in the source electrode of FIG. 1.
  • FIG. 3 is a plan view illustrating one via pad for source electrode wiring formed in the source electrode of FIG. 1.
  • 4A to 4H are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to an embodiment.
  • FIG. 5 is a cross-sectional view illustrating a high electron mobility transistor according to a second embodiment.
  • 6A to 6G are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a second embodiment.
  • barrier layer 19 metal mask
  • BSP Back layer VA: Via for source electrode wiring
  • VAP Via pad for source electrode wiring SE: Source electrode
  • drain electrode PDE drain electrode pad
  • PAS1 First Insulation Layer
  • PAS2 Second Insulation Layer
  • SD1 first seed layer SD2: second seed layer
  • SD3 third seed layer SD4: fourth seed layer
  • first, second, etc. are used herein to describe various members, regions, and / or portions, it is obvious that these members, components, regions, layers, and / or portions are not limited by these terms. Do. These terms do not imply any particular order, up or down, or superiority, and are only used to distinguish one member, region or region from another member, region or region. Accordingly, the first member, region, or region described below may refer to the second member, region, or region without departing from the teachings of the present invention.
  • the high electron mobility transistor according to the first embodiment includes a substrate 11 having a source electrode wiring forming portion, a base layer 10 formed on the substrate 11, and a source electrode wiring.
  • the drain electrode DE, the source electrode SE, and the drain electrode formed on the base layer 10 and spaced apart from the source electrode SE and the source electrode SE formed on the base layer 10 of the formation portion.
  • a source formed by etching the base layer 10 and the substrate 11 of the gate electrode GE and the source electrode wiring forming portion formed on the base layer 10 between DE to a predetermined depth from the front surface and filling the conductor.
  • a via pad for electrode wiring (VAP) is included.
  • the first insulating layer PAS1 formed on the base layer 10, the second insulating layer PAS2 formed on the first insulating layer PAS1, and the source electrode SE are electrically connected to each other.
  • the semiconductor device may further include a drain electrode pad PDE formed on the drain electrode DE and electrically connected to the source electrode pad PSE and the drain electrode DE formed on the SE.
  • the first insulating layer PAS1 is formed so that the first insulating layer PAS1 is the source electrode SE and the drain electrode DE. Cover part of the upper surface of both sides.
  • the source electrode pad PSE and the drain electrode pad PDE may be exposed by removing portions of the first insulating layer PAS1 and the second insulating layer PAS2 on the source electrode SE and the drain electrode DE, respectively. It is formed on the source electrode SE and the drain electrode DE.
  • the substrate 11 may include a source electrode wiring forming portion, and may be formed of sapphire (Al 2 O 3 ), gallium nitride (GaN), silicon (Si), silicon carbide (SiC), or the like.
  • the base layer 10 is formed on the substrate 11, the buffer layer 13 is formed on the nucleation layer 12, and the barrier layer 15 is formed on the buffer layer 13.
  • the nucleation layer 12, the buffer layer 13, and the barrier layer 15 may be made of aluminum nitride (AlN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN), respectively.
  • the source electrode SE is formed on the via pad VAP for source electrode wiring.
  • the drain electrode DE is formed on the base layer 10 spaced apart from the source electrode SE.
  • the gate electrode GE is formed on the base layer 10 between the source electrode SE and the drain electrode DE.
  • FIG. 2 is a plan view illustrating a plurality of source electrode wiring via pads formed in the source electrode of FIG. 1
  • FIG. 3 is a plan view illustrating one source electrode wiring via pad formed in the source electrode of FIG. 1.
  • the source electrode wiring via pad VAP is surrounded by the substrate 11 and the base layer 10, and is formed by etching and filling the source electrode wiring forming portion from a front surface to a predetermined depth.
  • the via pad for source electrode wiring is formed by etching and filling the base layer 10 and the substrate 11 to a predetermined depth from the front surface, so that the diameter of the upper portion of the front side is lower than that of the rear side. It may be formed larger than the diameter. In this case, it is formed to be opposite to the shape of the prior art and the source electrode wiring via pad (VAP) that is etched from the rear surface. However, it is also possible to etch the same diameter of the upper portion and the lower portion by the Bosch process.
  • the via pad VAP for source electrode wiring penetrates to the rear surface of the substrate 11 during the back-grinding process after forming the source electrode pad PSE and the drain electrode pad PDE to be described later.
  • the source electrode wiring via pads VAP penetrating the front and rear surfaces are formed in the same manner as the source electrode wiring via pads VAP are formed on the rear surface of the substrate 11 in the related art. Therefore, the source electrode wiring via pads (VAP) penetrating the front and rear surfaces are formed while solving the problems occurring when the source electrode wiring via pads (VAP) are formed on the rear surface.
  • the via pad for source electrode wiring is formed by filling the source electrode wiring forming portion with a conductor such as copper (Cu), gold (Au) to improve the electrical conductivity and the thermal conductivity of the transistor.
  • a conductor such as copper (Cu), gold (Au) to improve the electrical conductivity and the thermal conductivity of the transistor.
  • At least one via pad VAP for source electrode wiring is formed in the source electrode SE, as shown in FIG. 2, or as shown in FIG. 3, 50 of the bottom area of the source electrode SE. It can be formed accounting for more than%. In order to improve electrical conductivity and thermal conductivity through the via pad for source electrode wiring (VAP).
  • the via pad for source electrode wiring (VAP) is formed on the front surface
  • the number thereof may be at least one. That is, only one may be formed, or two or more may be formed in order to improve the heat dissipation efficiency of the transistor.
  • the via pad VAP for the source electrode wiring is formed with 50% or more of the bottom area of the source electrode SE, thereby providing electrical conductivity and heat. The conductivity can be improved.
  • the electrical conductivity and thermal conductivity may be improved by forming the size close to the size and shape of the source electrode SE.
  • the substrate 11 in a thick state is etched to a predetermined depth from the front side, so that the substrate 11 in a thin state can be etched more stably than the etching depth from the back side to a predetermined depth, so that a via pad for source electrode wiring (VAP) Since the width of the film can be widened, the via pad for source electrode wiring (VAP) can be formed as shown in FIGS. 2 and 3, thereby improving the electrical conductivity and the thermal conductivity.
  • VAP via pad for source electrode wiring
  • 4A to 4H are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a first embodiment.
  • a method of manufacturing a high electron mobility transistor includes forming a base layer 10 on a substrate 11 on which a source electrode wiring forming portion is defined, and a base layer 10 and a substrate 11 on the source electrode wiring forming portion.
  • a source electrode wiring via (VA) by etching the substrate to a predetermined depth from the front surface, and filling the source electrode wiring via (VA) with a conductor to form a source electrode wiring via pad (VAP), and a source electrode wiring via
  • VA source electrode wiring via
  • VAP source electrode wiring via pad
  • Forming a drain electrode DE Forming a drain electrode DE, forming a first insulating layer PAS1 on the entire surface of the source electrode SE, the drain electrode DE, and the base layer 10, and forming the source electrode SE and the drain electrode. A portion of the first insulating layer PAS1 between the layers DE is exposed on the exposed base layer 10. Forming a gate electrode GE in the portion.
  • the method may further include forming a source electrode pad PSE and a drain electrode pad PDE on the exposed source electrode SE and the drain electrode DE by removing a portion of the insulating layer PAS2.
  • the base layer 10 is deposited on the substrate 11 on which the source electrode wiring forming region is defined.
  • the base layer 10 may be formed by stacking the nucleation layer 12, the buffer layer 13, and the barrier layer 15.
  • the nucleation layer 12, the buffer layer 13, and the barrier layer 15 may be made of aluminum nitride (AlN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN), respectively.
  • a first seed layer SD1 is deposited on the base layer 10.
  • the first seed layer SD1 may be deposited using a deposition process such as sputtering, and may be formed of Ti / Cu, Ti / Al, Ti / W, Ti / Au, Ti / Ni / Cu, or the like. .
  • a photosensitive film (not shown) is coated on the first seed layer SD1 to perform a photolithography process. Thereafter, the photosensitive film is selectively exposed and developed such that the photosensitive film remains only on the source electrode wiring forming portion.
  • a metal mask 19 is grown on the first seed layer SD1 on both sides of the remaining photoresist. At this time, the metal mask 19 is grown to about 7 ⁇ 10 ⁇ m.
  • the metal mask 19 may be made of nickel (Ni), copper (Cu), gold (Au), or the like.
  • the remaining photoresist layer is removed to expose the first seed layer SD1 of the source electrode wiring forming region, and then the exposed first seed layer SD1 is exposed using the metal mask 19 as a mask. Etch it.
  • the base layer 10 and the substrate 11 of the source electrode wiring forming portion are etched to a predetermined depth from the entire surface to form a via for source electrode wiring ( VA).
  • a via pad VAP for source electrode wiring is formed by filling the source electrode wiring via VA with a conductor.
  • the metal mask 19 and the first seed layer SD1 are removed, and the second seed layer SD2 is deposited on the entire surface including the via VA for source electrode wiring.
  • the photolithography process is performed to expose only the second seed layer SD2 on the source electrode wiring via VA, and then grow a conductor on the exposed second seed layer SD2 to form a via pad for source electrode wiring ( VAP).
  • VAP via pad for source electrode wiring
  • the second seed layer SD2 on the base layer 10 on both sides of the via pad VAP for the source electrode wiring is removed.
  • FIG. 4D illustrates the removal of the second seed layer SD2 on the base layer 10 on both sides of the via pad VAP for the source electrode wiring.
  • the second seed layer SD2 may be made of Ti / Cu, Ti / Al, Ti / Ni / Cu, Ti / Au, or the like.
  • the conductor may be made of copper (Cu), gold (Au), or the like.
  • the source electrode SE is formed on the via pad VAP for source electrode wiring
  • the drain electrode DE is formed on the base layer 10 by being spaced apart from the source electrode SE. do.
  • the photolithography process is performed to form the via pad VAP for the source electrode wiring and the base layer 10 where the base layer 10 and the drain electrode DE are to be formed.
  • the source electrode SE and the drain electrode DE are formed by performing a lift-off process or the like.
  • the first conductive layer may be made of an ohmic contact metal such as Ti / Al / Ni / Au, Ti / Al / Ti / Ni / Au.
  • the first conductive layer is deposited and then heat treated to form an ohmic contact.
  • the first insulating layer PAS1 is deposited on the entire surface including the source electrode SE and the drain electrode DE. Then, the first insulating layer PAS1 is selectively etched by performing a photolithography process so that the base layer 10 on which the lower portion of the gate electrode GE to be formed in the later step is formed is exposed.
  • the first insulating layer PAS1 may be formed of silicon nitride or the like.
  • the photolithography process is performed to expose the first insulating layer PAS1 on which the upper portion of the gate electrode GE is to be seated. Let's do it.
  • the exposed first insulating layer PAS1 may be both sides of the first insulating layer PAS1 etched for the lower portion of the gate electrode GE.
  • a second conductive layer (not shown) is deposited on the entire surface of the portion where the gate electrode GE is to be exposed, and a lift off process is performed to form the gate electrode GE.
  • the second conductive layer may be made of Ni / Au, Ti / Al / Ni / Au, Ti / Al / Ti / Ni / Au, and the like.
  • the gate electrode GE is formed between the source electrode SE and the drain electrode DE.
  • a second insulating layer PAS2 is deposited on the gate electrode GE and on the first insulating layer PAS1.
  • the second insulating layer PAS2 may be formed of silicon nitride or the like.
  • the photolithography process is performed such that the source electrode SE is exposed to be connected to the lower portion of the source electrode pad PSE to be formed in a later process and the drain electrode DE to be connected to the lower portion of the drain electrode pad PDE is exposed.
  • the second insulating layer PAS2 and the first insulating layer PAS1 are selectively etched.
  • a third seed layer SD3 is deposited on the second insulating layer PAS2, on the exposed source electrode SE, and on the exposed drain electrode DE.
  • the third seed layer SD3 may be formed of Ti / Cu, Ti / Al, Ti / W, Ti / Au, Ti / Ni / Cu, and the like.
  • the photolithography process is performed to expose only the third seed layer SD3 on which the source electrode pad PSE and the drain electrode pad PDE are to be formed, and then, on the exposed third seed layer SD3. 3, a conductive layer (not shown) is grown to form a source electrode pad PSE above the source electrode SE, and a drain electrode pad PDE above the drain electrode DE.
  • each of the source electrode pad PSE and the drain electrode pad PDE is made of copper (Cu), gold (Au), or the like.
  • the back surface of the substrate 11 facing the front surface of the substrate 11 on which the source electrode pad PSE and the drain electrode pad PDE are formed is back-grinded.
  • a rear end of the via pad VAP for source electrode wiring is exposed by a back-grinding process under the substrate 11.
  • the height of the via pad VAP for source electrode wiring is about 50 ⁇ m to 100 ⁇ m.
  • the back-grinding process is not shown, a low temperature conjugate, a carrier wafer, and the like are used.
  • a low temperature binder may be used that is easier to remove than a high temperature binder.
  • the back-grinding process is performed using a low temperature wax (Wax) as a low temperature binder.
  • a fourth seed layer SD4 is deposited on the rear surface of the substrate 11 where the rear end of the via pad VAP for source electrode wiring is exposed, and then a fourth conductive layer (not shown) is formed from the fourth seed layer SD4.
  • the fourth seed layer SD4 may be formed of Ti / Cu, Ti / Al, Ti / W, Ti / Au, Ti / Ni / Cu, and the like.
  • the back layer BSP may be formed of a conductor such as copper (Cu), gold (Au), and the like to improve electrical conductivity and thermal conductivity.
  • the high electron mobility transistor according to the first embodiment and the method of manufacturing the same have a method of forming a source electrode wiring electrically connected to the source electrode SE under the source electrode, before the back-grinding process.
  • a via pad (VAP) for source electrode wiring is formed by etching and filling from a front surface of a thick substrate to a predetermined depth, thereby performing back-grinding process to etch to a predetermined depth from a rear surface of a thinned substrate.
  • VAP via pad
  • the high electron mobility transistor according to the first embodiment and the manufacturing method thereof form a via pad (VAP) for source electrode wiring and perform a back-grinding process, so that the back-grinding process is easier to remove than a high temperature binder.
  • VAP via pad
  • One low temperature binder can be used and the process is easy to improve the yield of the device.
  • the high electron mobility transistor according to the first embodiment and the method of manufacturing the same are etched and filled to a predetermined depth from the entire surface of the substrate in a thick state to form a via pad (VAP) for source electrode wiring. Since the whole is filled, most of the related arts have higher thermal conductivity than the vias for the empty source electrode wirings (VA), thereby improving heat dissipation of the device, thereby improving performance of the device.
  • VAP via pad
  • the high electron mobility transistor according to the first embodiment and the method of manufacturing the same are filled with all of the source electrode wiring vias as described above, the solder and the flux used for solder bonding for packaging the device are transferred to the substrate. It can not flow in, improving the reliability of the device and preventing the device from shortening its lifespan.
  • the present invention can be etched more stably than the etching of the thin substrate 11 to a predetermined depth from the rear surface of the via pad for source electrode wiring ( The width of the VAP) can be widened to improve the electrical conductivity and the thermal conductivity.
  • FIG. 5 is a cross-sectional view illustrating a high electron mobility transistor according to a second embodiment.
  • 6A to 6G are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a second embodiment.
  • the high electron mobility transistor according to the second embodiment of the present invention includes a substrate 11 having a source electrode wiring forming portion, a base layer 10 formed on the substrate 11, A source electrode SE formed on the base layer 10 of the source electrode wiring forming portion, a drain electrode DE formed on the base layer 10 and spaced apart from the source electrode SE, and a source electrode SE.
  • the base layer 10 and the substrate 11 of the gate electrode GE and the source electrode wiring forming portion formed on the base layer 10 between the drain electrodes DE are etched to a predetermined depth from the front surface and filled with a conductor. And a via pad (VAP) for forming a source electrode wiring.
  • VAP via pad
  • the via pad for source electrode wiring is formed after the first insulating layer PAS1 is first deposited on the base layer 10 deposited on the substrate 11, and thus the via pad for source electrode wiring is formed.
  • the VAP and the source electrode SE may be different from the configuration of the first embodiment.
  • the via pad VAP for source electrode wiring is surrounded by the substrate 11, the base layer 10, and the source electrode SE.
  • the source electrode SE and the drain electrode DE have a stepped portion S on which both sides of the source electrode SE and the drain electrode DE cover a portion of an upper surface of the first insulating layer PAS1.
  • a recess C is formed on the source electrode SE between the first insulating layer PAS1 and the via pad VAP for source electrode wiring.
  • the high electron mobility transistor according to the present invention further includes a first insulating layer PAS1 formed on the base layer 10, and includes a source electrode SE, a drain electrode DE, and a gate electrode.
  • the GE is formed on the base layer 10 by removing the first insulating layer PAS1 after the first insulating layer PAS1 is formed on the base layer 10, and forming the source electrode SE and the gate electrode GE.
  • both sides of the drain electrode DE cover a portion of the upper surface of the first insulating layer PAS1.
  • the second insulating layer PAS2 further includes a second insulating layer PAS2 formed on the first insulating layer PAS1, and the second insulating layer PAS2 covers a portion of an upper surface of each of the source electrode SE and the drain electrode DE.
  • the gate electrode GE is covered.
  • the semiconductor device may further include a source electrode pad PSE formed on the source electrode SE and a drain electrode pad PDE formed on the drain electrode DE, and further include a source electrode pad PSE and a drain electrode pad PDE. ) Is formed on the exposed source electrode SE and the drain electrode DE by removing a portion of the second insulating layer PAS2 formed on the source electrode SE and the drain electrode DE, respectively.
  • the method may include forming the base layer 10 on the substrate 11 on which the source electrode wiring forming region is defined, and forming a first layer on the top surface of the base layer 10. Forming the insulating layer PAS1, and etching the first insulating layer PAS1, the base layer 10, and the substrate 11 on the source electrode wiring forming region to a predetermined depth from the entire surface of the source electrode wiring via.
  • a portion of the first insulating layer PAS1 and a portion of the first insulating layer PAS1 spaced apart from the via pad VAP for source electrode wiring are removed to expose the source electrode SE and the drain on the exposed base layer 10.
  • Forming an electrode DE, the first insulating layer PAS1 between the source electrode SE and the drain electrode DE Removing a portion of the gate electrode to form a gate electrode GE on the exposed base layer 10.
  • the base layer 10 is deposited on the substrate 11 on which the source electrode wiring forming region is defined.
  • the base layer 10 may be formed by stacking the nucleation layer 12, the buffer layer 13, and the barrier layer 15.
  • a first insulating layer PAS1 is deposited on the base layer 10.
  • the first seed layer SD1 is deposited on the first insulating layer PAS1, the source electrode wiring forming portion is covered with a photoresist (not shown), and then the metal mask 19 is first coated. It is grown on the seed layer SD1. Then, the photoresist covered on the source electrode wiring forming region is removed, and the first insulating layer PAS1, the base layer 10 and the substrate 11 of the source electrode wiring forming region are etched to a predetermined depth from the entire surface for source electrode wiring. Form a via (VA).
  • VA via
  • the second seed layer SD2 is formed on the entire surface, and the via VA for source electrode wiring is formed.
  • a via pad for source electrode wiring (VAP) is formed by filling the source electrode wiring via (VA) with a conductor.
  • the first insulating layer PAS1 is etched along a predetermined outer circumference of the via pad VAP for defining the source electrode to define the source electrode forming region, and the source electrode forming region and the source electrode forming region.
  • the first insulating layer PAS1 of the spaced portion is etched to define the drain electrode forming region.
  • a source electrode SE is formed on an upper surface of the via pad VAP for source electrode wiring and the source electrode forming portion, and a drain electrode DE is formed on the drain electrode forming portion on the base layer 10.
  • a stepped portion S in which both sides of the source electrode SE and the drain electrode DE cover a part of the upper surface of the first insulating layer PAS1 is formed.
  • a recess C is formed on the source electrode SE between the first insulating layer PAS1 and the via pad VAP for source electrode wiring. The recess C is generated due to the space between the first insulating layer PAS1 and the via pad VAP for source electrode wiring.
  • the subsequent process of forming the third seed layer SD3 and back-grinding the back surface of the substrate and forming the fourth seed layer SD4 and the back layer BSP is substantially the same as the process of the first embodiment.
  • the present invention is capable of improving the reliability of a high electron mobility transistor by forming a source wiring via and preventing solder flux from flowing therein.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention concerne un transistor à haute mobilité électronique et son procédé de fabrication. Le transistor à haute mobilité électronique selon un mode de réalisation de la présente invention comprend : un substrat dans lequel est définie une partie de formation de câblage d'électrode de source ; une couche de base formée sur le substrat ; une électrode de source formée sur la couche de base de la partie de formation de câblage d'électrode de source ; une électrode de drain espacée de l'électrode de source et formée sur la couche de base ; une électrode de grille formée sur la couche de base entre l'électrode de source et l'électrode de drain ; et une pastille de trou d'interconnexion pour un câblage d'électrode de source, qui est formée par gravure de la couche de base de la partie de formation de câblage d'électrode de source et du substrat à une profondeur prédéfinie depuis la surface avant associée, puis par remplissage d'un conducteur en son sein.
PCT/KR2016/011534 2015-10-23 2016-10-14 Transistor à haute mobilité électronique et son procédé de fabrication WO2017069460A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2015-0147655 2015-10-23
KR20150147655 2015-10-23
KR1020160047549A KR101856687B1 (ko) 2015-10-23 2016-04-19 고전자이동도 트랜지스터 및 그의 제조방법
KR10-2016-0047549 2016-04-19

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JP3184493B2 (ja) * 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
JP2006086398A (ja) * 2004-09-17 2006-03-30 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007157829A (ja) * 2005-12-01 2007-06-21 Matsushita Electric Ind Co Ltd 半導体装置
KR101890749B1 (ko) * 2011-10-27 2018-08-23 삼성전자주식회사 전극구조체, 이를 포함하는 질화갈륨계 반도체소자 및 이들의 제조방법
KR101946008B1 (ko) * 2012-07-17 2019-02-08 삼성전자주식회사 고전자 이동도 트랜지스터 및 그 제조방법

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