WO2018110831A1 - Dispositif électronique à base de nitrure et son procédé de fabrication - Google Patents

Dispositif électronique à base de nitrure et son procédé de fabrication Download PDF

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WO2018110831A1
WO2018110831A1 PCT/KR2017/012441 KR2017012441W WO2018110831A1 WO 2018110831 A1 WO2018110831 A1 WO 2018110831A1 KR 2017012441 W KR2017012441 W KR 2017012441W WO 2018110831 A1 WO2018110831 A1 WO 2018110831A1
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layer
ohmic contact
nitride
protective layer
opening portion
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Korean (ko)
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이상민
구황섭
김현제
정희석
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주식회사 웨이비스
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Definitions

  • the present invention relates to a nitride-based electronic device and a method for manufacturing the same, and more particularly to a nitride-based electronic device and a method for manufacturing the same that can prevent the nitride layer is damaged during the heat treatment.
  • nitride electronic devices have a wider energy band gap than conventional semiconductor materials such as Si and GaAs, have high thermal and chemical stability, and have high electron saturation rates. Therefore, it is known to be suitable for high frequency and high power applications.
  • Nitride-based electronic devices provide a large band discontinuity at the bonding interface by stacking heterogeneous nitride layers, respectively, a channel layer and a barrier layer, and can improve electron mobility because high concentrations of electrons can be induced due to large band discontinuities. have.
  • Patent No. 10-1202497 June 12, 2012, a nitride-based transistor having a protective layer and a low damage recess and a method of manufacturing the same).
  • a gap is formed between the ohmic contact and the protective layer during the formation of the ohmic contact in contact with the source and the drain.
  • the gap is 0.1 to 0.5 mu m, through which part of the barrier layer is exposed.
  • a high temperature heat treatment is performed to reduce the contact resistance of the ohmic contact.
  • the high temperature heat treatment is usually performed at a temperature of 850 ° C. or higher, and an inert gas such as nitrogen in the gas phase is supplied during the heat treatment.
  • a gap exists between the ohmic contact and the protective layer, and a portion of the channel layer is exposed through the gap, and the exposed channel layer is damaged during the high temperature heat treatment.
  • the channel layer is nitride based and may have surface traps.
  • the trap may react with nitrogen or damage due to thermal shock. If the channel layer is damaged, there is a problem that the sheet resistance increases.
  • the protective layer is a passivation layer that neutralizes the surface trap of the channel layer, but can prevent the nitrogen reaction by the trap, the thermal shock generated during the heat treatment of 850 °C or more can not be completely blocked. Therefore, the channel layer having the protective layer formed thereon may be deformed due to thermal shock, and the sheet resistance may increase.
  • the above patent has a problem that the effect of the current injection can be reduced because the ohmic contact is located above the barrier layer.
  • the present invention has been made in view of the above problems, and provides a nitride-based electronic device capable of preventing exposure of a channel layer when performing an ohmic contact heat treatment, and a method of manufacturing the same.
  • another technical problem to be solved by the present invention is to provide a nitride-based electronic device that can reduce the possibility of deformation of the nitride-based semiconductor layer by thermal shock and a method of manufacturing the same.
  • another technical problem to be solved by the present invention is to provide a nitride-based electronic device and a method of manufacturing the same that can increase the current injection effect.
  • a nitride based electronic device includes a channel layer, a barrier layer, and a protective layer sequentially stacked on an upper portion of a substrate, and a protective layer exposed through an opening portion of the protective layer.
  • the ohmic contact can be configured to be located above the lower layer of the protective layer exposed to the opening portion and a portion of the protective layer around the opening portion.
  • the opening portion is a space defined by a portion of an upper surface of the barrier layer and both end surfaces of the protective layer, and a bottom surface of the ohmic contact is an upper surface of the barrier layer exposed by the opening portion. It can be contacted.
  • the opening portion is a space defined by a portion of the upper surface of the channel layer, and both end surfaces of the protective layer and the barrier layer, and a bottom surface of the ohmic contact is exposed by the opening portion. It can be in contact with the upper surface of the channel layer.
  • the present invention may further include an ion implantation layer formed on at least the lower layer of the protective layer exposed by the opening portion.
  • the ion implantation layer exposed by the opening portion may be located at a portion of the barrier layer.
  • the ion implantation layer exposed by the opening portion may be located at a portion of the channel layer.
  • the opening portion may selectively expose a central portion of the upper surface of the ion implantation layer.
  • the ion implantation layer may be obtained by implanting an n-type dopant into the barrier layer or the barrier layer and the channel layer.
  • the nitride-based electronic device manufacturing method a) a step of sequentially forming a channel layer and a barrier layer on the upper surface of the substrate, b) forming a protective layer on the upper surface of the barrier layer and c) removing at least a portion of the protective layer to form an opening portion, exposing a lower layer of the protective layer, which is a layer located below the protective layer, and d) a photoresist pattern on the resultant of step c). Exposing an opening portion and a portion of the protective layer around the opening portion, and e) depositing an ohmic contact forming material on top of the resultant of step d) and removing the photoresist pattern. And forming an ohmic contact located above the opening portion and above the protective layer around the opening portion.
  • the method may further include a step of lowering contact resistance of the ohmic contact by heat treatment at 850 ° C. or more.
  • step b) a part of the protective layer is removed to form an opening part exposing a part of the barrier layer, and in step e), the bottom surface of the ohmic contact is exposed. Contact with the barrier layer.
  • step b) a portion of the protective layer and a lower barrier layer are formed to form an opening part exposing a part of the channel layer, and in step e) the ohmic contact.
  • the bottom of the may contact the exposed channel layer.
  • the method may further include forming an ion implantation layer by injecting an n-type dopant into a portion of the lower layer of the protective layer.
  • step b) a part of the protective layer is removed to form an opening part when the ion implantation layer is exposed, and in step e), the ion where the bottom surface of the ohmic contact is exposed. Contact with the injection layer.
  • the ion implantation layer in contact with the bottom surface of the ohmic contact may be formed on the barrier layer or may be formed on the channel layer.
  • the opening portion may expose an upper portion of the ion implantation layer.
  • the method may further include lowering contact resistance of the ohmic contact by performing a heat treatment at 400 to 500 ° C.
  • the nitride-based electronic device of the present invention and a method for manufacturing the same prevent the gap between the ohmic contact and the protective layer and prevent the lower barrier layer from being exposed, thereby preventing sheet resistance of the barrier layer due to reaction or thermal shock during heat treatment. There is an effect that can prevent the increase.
  • the nitride-based electronic device of the present invention and a method for manufacturing the same by selectively forming an ion implantation layer on the lower portion of the ohmic contact, lowering the heat treatment temperature for reducing the contact resistance of the ohmic contact to reduce the sheet resistance of the barrier layer below the protective layer to There is an effect that can prevent the increase by.
  • the nitride-based electronic device of the present invention and the method for manufacturing the same have an effect of improving the current injection effect by directly contacting the ohmic contact with the surface of the channel layer.
  • the heat treatment can be performed without a separate protective layer, thereby reducing the process steps.
  • FIG. 1 is a partial cross-sectional view of a nitride-based electronic device according to a first embodiment of the present invention.
  • FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process of a nitride-based electronic device according to a first embodiment of the present invention.
  • FIG 3 is a partial cross-sectional view of a nitride-based electronic device according to a second embodiment of the present invention.
  • 4A to 4E are cross-sectional views illustrating a process of manufacturing a nitride-based electronic device according to a second embodiment of the present invention.
  • 5A and 5B are partial cross-sectional views of a nitride electronic device according to a third embodiment of the present invention.
  • 6A to 6D are cross-sectional views illustrating a manufacturing process of a nitride electronic device according to a third embodiment of the present invention.
  • 7A to 7E are cross-sectional views of subsequent process steps of the embodiments of the present invention.
  • first, second, etc. are used herein to describe various members, regions, and / or portions, it is obvious that these members, components, regions, layers, and / or portions should not be limited by these terms. Do. These terms do not imply any particular order, up or down, or superiority, and are only used to distinguish one member, region or region from another member, region or region. Accordingly, the first member, region, or region described below may refer to the second member, region, or region without departing from the teachings of the present invention.
  • FIG. 1 is a partial cross-sectional view of a nitride-based electronic device according to a first embodiment of the present invention.
  • the nitride electronic device includes a substrate 10, a channel layer 20 formed on the substrate 10, and an upper portion of the channel layer 20.
  • the substrate 10 may be a known material such as SiC, sapphire, etc.
  • the channel layer 20 is a nitride semiconductor layer such as GaN
  • the barrier layer 30 is a nitride semiconductor layer such as AlGaN.
  • the channel layer 20 and the barrier layer 30 may be different nitride-based semiconductor layers so that two-dimensional electron gas (2DEG / 2-Dimensional Electron Gas) may be generated at an interface between different materials.
  • the protective layer 40 positioned on the upper portion of the barrier layer 30 serves to neutralize the surface trap of the barrier layer 30, and may use a nitride-based semiconductor layer such as SiN. It is not necessary to use a nitride semiconductor layer as the protective layer 40. Any insulating layer that can be used for the purpose of preventing the exposure of the barrier layer 30, neutralizing the surface trap, and reducing the thermal shock can be used regardless of the type. Do. However, it is preferable to determine the components of the protective layer 40 in consideration of the lattice aberration with the barrier layer 30 which is a nitride-based semiconductor layer.
  • the passivation layer 40 is located only on a part of the barrier layer 30, and the barrier layer 30 where the passivation layer 40 is not located is an area where the ohmic contact 50 is in contact with a specific area of the nitride-based electronic device.
  • the nitride-based high electron mobility transistor (HEMT) may be a source or drain region.
  • the ohmic contact 50 is positioned on the barrier layer 30 exposed through the opening portion formed in a portion of the protective layer 40.
  • the ohmic contact 50 prevents the barrier layer 30 from being exposed.
  • the ohmic contact 50 may include a lower contact 51 filling the upper side of the barrier layer 30, on which the protective layer 40 is not formed, and the side surface of the protective layer 40, and the lower contact (
  • the upper contact 52 may be configured to be in contact with the upper portion of 51 and have a planar area larger than the planar area of the lower contact 51.
  • the lower contact 51 and the upper contact 52 are disposed so that their centers coincide with each other in the vertical direction, and both sides of the upper contact 52 may partially cover a portion of the protective layer 40 positioned on the side of the opening. It is configured to cover.
  • Such a structure of the ohmic contact 50 is thicker than the conventional ohmic contact described above, and covers a portion of the protective layer 40 to form a gap between the ohmic contact 50 and the protective layer 40. This is a big difference in that the barrier layer 30 can be completely blocked from being exposed.
  • the shape of the ohmic contact 50 may have more various embodiments, the lower contact 51 completely filling the opening portion of the protective layer 40 and the protective layer adjacent to the side of the opening portion on the lower contact 51. It may be divided into an upper contact 52 covering a portion of the 40, it may be applied regardless of the shape.
  • the present invention prevents a portion of the barrier layer 30 from being exposed between the ohmic contact 50 and the protective layer 40. Therefore, problems occurring when the barrier layer 30 is exposed may be solved.
  • the surface trap of the barrier layer 30 may prevent the reaction with inert gas such as nitrogen in the heat treatment furnace.
  • the thermal shock may be alleviated to prevent the barrier layer 30 from being damaged.
  • the substrate 10 having the channel layer 20 formed thereon and the barrier layer 30 formed on the channel layer 20 is prepared.
  • the channel layer 20 may be one of GaN, AlGaN, InGaN, and AlInGaN, and may be formed on the substrate 10 using known techniques related to the growth of nitride semiconductors.
  • Known nitride semiconductor growth methods include MOCVD, MBE or HVPE.
  • the barrier layer 30 is grown on the channel layer 20.
  • the barrier layer 30 may be AlxGa (1-x) N (where 0 ⁇ x ⁇ 1), or may be AlN, AlInN, AlGaN, or AlInGaN. Use to grow.
  • a protective layer 40 is deposited on the barrier layer 30, and then a part of the deposited protective layer 40 is removed to form an opening portion 41.
  • the opening portion 41 here is a space defined by the cross section of the removed portion of the protective layer 40 and the top surface of the barrier layer 30 exposed by the removal of the protective layer 40.
  • the region of the barrier layer 30 exposed through the opening portion 41 may be a region where a source or a drain is formed when the nitride-based electronic device is a nitride-based high mobility transistor (HEMT).
  • HEMT high mobility transistor
  • the protective layer 40 may be formed of nitride such as SiN or SiO 2. Oxides, and the like, and are formed by vapor deposition by a known deposition method. The terms deposition and growth are used interchangeably, but it can be understood that the two terms are equivalent at the level of ordinary skill in the art.
  • a photoresist PR is applied to the upper portion of the resultant of FIG. 2B, and a photoresist PR pattern is formed to expose the opening portion 41 through photosensitive development.
  • the portion exposed by the photoresist PR pattern includes an opening portion 41 and a portion of the protective layer 40 positioned around the opening portion 41.
  • the ohmic contact 50 is formed by a lift-off method of removing the photoresist (PR) pattern.
  • the ohmic contact 50 has a shape that completely fills the opening portion 41 and covers a portion of the upper portion of the protective layer 40 around the opening portion 41. That is, the shape coincides with the region opened by the photoresist PR pattern in FIG. 2C.
  • the barrier layer 30 Since the structure exposed to the upper surface of the electronic device in the process of performing a heat treatment to lower the resistance of the ohmic contact 50 is the protective layer 40 and the ohmic contact 50, the barrier layer 30 is not exposed to the outside . Therefore, damage to the barrier layer 30 can be prevented.
  • FIG 3 is a partial cross-sectional view of a nitride-based electronic device according to a second embodiment of the present invention.
  • the nitride-based electronic device may have the substrate 10, the channel layer 20, the barrier layer 30, and the protection as in the first embodiment described with reference to FIG. 1.
  • the ion implantation layer 60 formed in a portion of the barrier layer 30 on the lower side of the ohmic contact 50 is further configured.
  • the ion implantation layer 60 may be formed on the upper portion of the channel layer 20 as well as the barrier layer 30.
  • the ion implantation layer 60 is formed by implanting an n-type dopant, and specifically, may be implanted with Si. At this time, the implantation concentration of Si is preferably 1x10 19 or more.
  • the formation of the ion implantation layer 60 may reduce the contact resistance between the ohmic contact 50, which is a metal, and the barrier layer 30. Reducing the contact resistance of the ohmic contact 50 may lower the temperature in the heat treatment process.
  • the temperature of the heat treatment process is 850 ° C. or more.
  • the nitride-based electronic device of the present invention completely prevents the exposure of the barrier layer 30, the barrier layer 30 may be subjected to some degree of thermal shock.
  • the ion implantation layer 60 is formed to contact the ohmic contact 50.
  • the resistance is reduced and heat treatment is performed in the relatively low temperature range of 400 to 500 ° C.
  • the contact resistance of the ohmic contact 50 can be treated to be less than 1 ⁇ / mm.
  • the channel layer 20 is formed on the substrate 10, and the barrier layer 30 is formed on the channel layer 20.
  • the channel layer 20 may be one of GaN, AlGaN, InGaN, and AlInGaN, and may be formed on the substrate 10 using known techniques related to the growth of nitride semiconductors.
  • Known nitride semiconductor growth methods include MOCVD, MBE or HVPE.
  • the barrier layer 30 is grown on the channel layer 20.
  • the barrier layer 30 may be AlxGa (1-x) N (where 0 ⁇ x ⁇ 1), or may be AlN, AlInN, AlGaN, or AlInGaN. Use to grow.
  • an n-type dopant is implanted into the barrier layer 30 or a part of the barrier layer 30 and the channel layer 40 to form the ion implantation layer 60.
  • the location where the ion implantation layer 60 is formed may be a source or drain region when the nitride-based electronic device of the present invention is a nitride-based high mobility transistor (HEMT).
  • HEMT high mobility transistor
  • an ion implantation mask pattern or an ion implantation buffer pattern is formed on the barrier layer 30 to selectively select the barrier layer 30 at the position where the ion implantation layer 60 is formed.
  • the ion implantation process can be performed.
  • a heat treatment process for activating the ion implantation layer 60 may be performed. However, the heat treatment may be performed simultaneously with the heat treatment of the ohmic contact 50.
  • the protective layer 40 is deposited on the top surface of the barrier layer 30 and the ion implantation layer 60, and then a portion of the deposited protective layer 40 is removed.
  • the opening portion 41 is a space defined by the cross section of the removed portion of the protective layer 40 and the top surface of the ion implantation layer 60 exposed by the removal of the protective layer 40. It is preferable that the opening portion 41 selectively exposes only the central portion of the upper surface of the ion implantation layer 60, not exposing the upper front surface of the ion implantation layer 60.
  • the opening portion 41 exposes the entire surface of the ion implantation layer 60
  • a part of the barrier layer 30 at the side portion of the ion implantation layer 60 may be exposed depending on the process margin.
  • the effect of reducing ohmic contact 50 contact resistance due to the formation of the ion implantation layer 60 may not be fully achieved.
  • the protective layer 40 may be formed of nitride such as SiN or SiO 2. Oxides, and the like, and are formed by vapor deposition by a known deposition method.
  • a photoresist PR is applied on top of the resultant of FIG. 4C, and a protection positioned around the opening portion 41 and the opening portion 41 through post-photo development. A portion of layer 40 is exposed.
  • the ohmic contact 50 is formed by removing the photoresist (PR) pattern.
  • the ohmic contact 50 has a shape that completely fills the opening portion 41 and covers a portion of the upper portion of the protective layer 40 around the opening portion 41. Therefore, the bottom surface of the ohmic contact 50 contacts the top surface of the ion implantation layer 60.
  • the structures exposed on the upper surface of the electronic device during the heat treatment to lower the resistance of the ohmic contact 50 are the protective layer 40 and the ohmic contact 50, and the barrier layer 30 and the ion implantation layer 60 are formed. ) Is not exposed to the outside. Therefore, damage to the barrier layer 30 and the ion implantation layer 60 can be prevented.
  • the barrier layer 30 and the ion implantation layer 60 can be prevented from being thermally shocked, and the activation of the ion implantation layer 60 is simultaneously performed. Can be achieved.
  • the ohmic contact 50 covers a part of the protective layer 40 to expose the barrier layer 30 and the ion implantation layer 60. It can prevent the reaction with nitrogen in the heat treatment step.
  • the formation of the ion implantation layer 60 lowers the contact resistance of the ohmic contact 50 so that heat treatment can be performed at a relatively low temperature, and the barrier layer 30 and the ion implantation layer 60 are subjected to thermal shock. It can be prevented.
  • 5A and 5B are partial cross-sectional views of a nitride electronic device according to a third embodiment of the present invention.
  • the nitride electronic device has a structure in which a substrate 10, a channel layer 20, a barrier layer 30, and a protective layer 40 are formed.
  • 5A further includes an ohmic contact 50, wherein the bottom surface of the ohmic contact 50 is configured to directly contact the channel layer 20.
  • the bottom surface of the ohmic contact 50 may contact the ion implantation layer 60 formed in the channel layer 20.
  • the bottom of the ohmic contact 50 is in contact with the top of the barrier layer 30.
  • the bottom of the ohmic contact 50 is not the barrier layer 30, but the channel layer 20.
  • the layer in which the ohmic contact 50 is contacted may be clearly described as the barrier layer 30 or the channel layer 20, and the layer in which the bottom surface of the ohmic contact 50 is in contact.
  • the description may be referred to as a 'lower layer of the protective layer 40'.
  • the current injection effect may be improved, and the efficiency of the high electron mobility transistor or the light emitting device, which is an example of the nitride-based electronic device, may be improved.
  • the channel layer 20 is formed on the substrate 10, and the barrier layer 30 is formed on the channel layer 20, as shown in FIG. 2A. do.
  • the protective layer 40 is formed on the entire upper surface of the barrier layer 30.
  • a portion of the protective layer 40 is removed, and then a portion of the barrier layer 30 exposed by the removal of the protective layer 40 is removed to thereby remove the channel layer 20.
  • An opening portion 41 is formed that exposes an upper portion of the.
  • the opening portion 41 refers to the cross section of the removed portion of the protective layer 40 and the barrier layer 30 and the channel layer 20 exposed by the removal of the protective layer 40 and the barrier layer 30. It is the space defined by the upper surface.
  • the region of the channel layer 20 exposed through the opening portion 41 may be a source or drain region when the nitride-based electronic device is a nitride-based high mobility transistor (HEMT).
  • HEMT high mobility transistor
  • the ion implantation layer may be formed on a part of the barrier layer 30 and the channel layer 20 through ion implantation before the formation of the protective layer 40, and the protective layer 40 may be formed. Thereafter, the opening portion 41 may be formed to expose the ion implantation layer formed in the channel layer 20.
  • a photoresist PR is applied on the upper part of the resultant of FIG. 6B, and a protection positioned around the opening portion 41 and the opening portion 41 through post-photo development.
  • a photoresist (PR) pattern is formed that exposes a portion of layer 40.
  • the photoresist (PR) pattern is removed to completely fill the opening portion 41, and a protective layer around the opening portion 41. 40 forms an ohmic contact 50 covering a portion of the upper portion.
  • the bottom of the ohmic contact 50 directly contacts the channel layer 20 or the ion implantation region formed in the channel layer 20.
  • the structures exposed on the upper surface of the electronic device during the heat treatment to lower the resistance of the ohmic contact 50 are the protective layer 40 and the ohmic contact 50, and the barrier layer 30 and the channel layer 20. Is not exposed to the outside. Therefore, damage to the barrier layer 30 and the channel layer 20 can be prevented.
  • the heat treatment temperature of the ohmic contact 50 may be lowered.
  • the thermal treatment temperature of the ohmic contact 50 may be lowered to protect the barrier layer 30 and the channel layer 20 from thermal shock.
  • the nitride-based electronic device of the present invention and the manufacturing method thereof include the barrier layer 30, the channel layer 20, or the ohmic contact 50 so as to cover the protective layer 40 around the opening part 41.
  • a portion of the lower layer of the protective layer 40 which is the ion implantation layer 60 can be prevented from being exposed. Therefore, the reaction caused by the surface trap can be prevented and the thermal shock can be reduced.
  • the present invention can reduce the contact resistance of the ohmic contact 50 by forming the ion implantation layer 60, it is possible to protect each layer from thermal shock by lowering the heat treatment temperature to lower the contact resistance.
  • the ohmic contact 50 directly contacts the channel layer 20 or the ion implantation layer formed in the channel layer 20, thereby improving the current injection effect.
  • a passivation layer 70 is deposited on an upper front surface of the structure illustrated in FIG. 2D, and a portion of the passivation layer 70 is removed to expose a portion of the upper portion of the ohmic contact 50.
  • the passivation layer 70 may be a nitride-based or oxide-based semiconductor layer, and preferably may be formed by depositing SiN x .
  • a gate electrode (not shown) is formed first, followed by a passivation layer 70.
  • a field plate 80 is formed on a portion of the passivation layer 70 and connected to the ohmic contact 50 by using a metal pattern forming process such as a lift-off process.
  • the field plate 80 may also be positioned on the upper passivation layer 70 of the gate electrode.
  • the substrate 10 is made thinner by removing a predetermined thickness from the back surface of the substrate 10.
  • the method of removing the back surface of the substrate 10 may use mechanical polishing, chemical treatment, or the like.
  • vias 11 are formed from the rear surface of the substrate 10 to expose the bottom surface of the ohmic contact 50 as shown in FIG. 7D.
  • the via 11 is filled with a conductor, and a conductor layer 90 covering the back surface of the substrate 10 is formed.
  • the conductor layer 90 is in contact with the bottom surface of the ohmic contact 50 exposed by the via 11.
  • the formation region of the conductor layer 90 in contact with the ohmic contact 50 becomes a source region when the nitride-based electronic device of the present invention is a high electron mobility transistor.
  • the present invention provides a nitride-based electronic device and a method for manufacturing the same which can prevent the nitride layer from being damaged during the heat treatment.

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Abstract

본 발명은 질화물계 전자소자 및 그 제조방법에 관한 것으로, 기판의 상부에 순차적층되는 채널층, 장벽층 및 보호층과, 보호층의 개구 부분을 통해 노출되는 보호층의 하부층에 접촉되는 오믹 콘택을 포함하는 질화물계 전자소자에 있어서, 상기 오믹 콘택은 개구 부분으로 노출된 상기 보호층의 하부층의 상부 및 상기 개구 부분 주변의 상기 보호층의 일부 상부에 위치하도록 구성된다. La présente invention concerne un dispositif électronique à base de nitrure et son procédé de fabrication, le dispositif électronique à base de nitrure comprenant : une couche de canal, une couche barrière et une couche de protection empilées séquentiellement sur la partie supérieure d'un substrat ; et un contact ohmique établissant un contact avec une couche inférieure de la couche de protection, la couche inférieure étant exposée par l'intermédiaire d'une partie d'ouverture de la couche de protection, le contact ohmique étant positionné sur la partie supérieure de la couche inférieure de la couche de protection exposée par l'intermédiaire de la partie d'ouverture, et sur une partie de la partie supérieure de la couche de protection entourant la partie d'ouverture.
PCT/KR2017/012441 2016-12-13 2017-11-03 Dispositif électronique à base de nitrure et son procédé de fabrication WO2018110831A1 (fr)

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KR102396072B1 (ko) * 2020-11-13 2022-05-11 한국원자력연구원 GaN계 전자 소자의 오믹 접촉 형성 방법 및 이에 따라 제조된 GaN계 전자 소자의 오믹 접촉

Citations (5)

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JP2007329350A (ja) * 2006-06-08 2007-12-20 Matsushita Electric Ind Co Ltd 半導体装置
JP2011119607A (ja) * 2009-12-07 2011-06-16 Sharp Corp 窒化物系化合物半導体装置、及びその製造方法
JP2013021016A (ja) * 2011-07-07 2013-01-31 Sharp Corp ＧａＮ系半導体素子の製造方法
US20140124792A1 (en) * 2012-11-05 2014-05-08 Cree, Inc. Ni-rich schottky contact
KR20150013346A (ko) * 2012-09-14 2015-02-04 파워 인티그레이션즈, 인크. 다중 게이트 유전체 층을 갖는 헤테로구조 트랜지스터

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007329350A (ja) * 2006-06-08 2007-12-20 Matsushita Electric Ind Co Ltd 半導体装置
JP2011119607A (ja) * 2009-12-07 2011-06-16 Sharp Corp 窒化物系化合物半導体装置、及びその製造方法
JP2013021016A (ja) * 2011-07-07 2013-01-31 Sharp Corp ＧａＮ系半導体素子の製造方法
KR20150013346A (ko) * 2012-09-14 2015-02-04 파워 인티그레이션즈, 인크. 다중 게이트 유전체 층을 갖는 헤테로구조 트랜지스터
US20140124792A1 (en) * 2012-11-05 2014-05-08 Cree, Inc. Ni-rich schottky contact

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