WO2023071028A1 - Dispositif d'alimentation normalement fermé p-gan ayant une structure de grille périodique - Google Patents

Dispositif d'alimentation normalement fermé p-gan ayant une structure de grille périodique Download PDF

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Publication number
WO2023071028A1
WO2023071028A1 PCT/CN2022/081268 CN2022081268W WO2023071028A1 WO 2023071028 A1 WO2023071028 A1 WO 2023071028A1 CN 2022081268 W CN2022081268 W CN 2022081268W WO 2023071028 A1 WO2023071028 A1 WO 2023071028A1
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Prior art keywords
layer
gan
periodic
layers
power device
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PCT/CN2022/081268
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English (en)
Chinese (zh)
Inventor
王洪
高升
谢子敬
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华南理工大学
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Publication of WO2023071028A1 publication Critical patent/WO2023071028A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to the field of semiconductors, in particular to a p-GaN normally-off power device with a periodic gate structure.
  • GaN HEMTs high electron mobility transistors
  • the existing mainstream solution is to use a p-GaN layer device to deplete the two-dimensional electron gas under the gate by growing a p-GaN layer.
  • a p-GaN layer device to deplete the two-dimensional electron gas under the gate by growing a p-GaN layer.
  • Mg ionization efficiency of Mg in p-GaN
  • a larger doping concentration is required to effectively deplete the two-dimensional electrons under the gate. gas.
  • This will make it easy for Mg to diffuse into the barrier layer and channel layer, resulting in degradation of device reliability (NE Posthuma, et al, 2016 28 th ISPSD conference). Therefore, on the one hand, it is necessary to improve the ionization efficiency of Mg; on the other hand, it is necessary to reduce the concentration of doped holes or introduce a barrier layer to limit the downward diffusion of Mg.
  • the present invention proposes a p-GaN normally-off power device with a periodic gate structure.
  • the step-type polarization electric field between the p-GaN/InGaN layers with variable indium composition effectively improves the ionization efficiency of Mg, and the periodic InGaN layers also prevent Mg from diffusing into the barrier layer and channel layer. effect.
  • the object of the present invention is achieved at least by one of the prior art solutions.
  • a p-GaN normally-off power device with a periodic gate structure including a substrate, a nucleation layer, a buffer layer, a channel layer, an insertion layer, and a barrier layer from bottom to top;
  • a source and a drain are arranged above the barrier layer, a periodic p-GaN/InGaN layer formed on the barrier layer is arranged between the source and the drain, and a gate is arranged on the periodic p-GaN/InGaN layer .
  • the periodic p-GaN/InGaN layer is periodically distributed with multiple layers of In b Ga 1-b N layers with low indium composition and In a Ga 1-a N layers with high indium composition from bottom to top, and A p-GaN layer is arranged between adjacent In b Ga 1-b N layers with low indium composition and In a Ga 1-a N layers with high indium composition.
  • the p-GaN of the p-GaN layer is doped with Mg, and the hole concentration is 2E17-2E18 cm ⁇ 3 .
  • the total thickness of the periodic p-GaN/InGaN layer is 80-120nm, wherein, the total thickness of all p-GaN layers is 60-90nm, each layer of In b Ga 1-b N layer with low indium composition
  • the thickness of each layer of In a Ga 1-a N layer with high indium composition is 0.5-5 nm.
  • the number of layers of In a Ga 1-a N layer with high indium composition is not less than 2; the low indium composition In the In b Ga 1-b N layer of the composition, 0.05 ⁇ b ⁇ 0.3, the number of layers of the In b Ga 1-b N layer of the low indium composition is not less than 2; the In a Ga 1-a of the high indium composition
  • the number of N layers is the same as that of the low indium composition InbGa1 -bN layer.
  • the substrate is silicon; the nucleation layer is AlN; the buffer layer is AlGaN; the channel layer is GaN; the insertion layer is AlN; and the barrier layer is AlGaN.
  • the present invention has the following beneficial effects and advantages:
  • Using periodic p-GaN/InGaN layers instead of p-GaN layers can effectively improve the ionization efficiency of Mg through the step-type polarization electric field between p-GaN/InGaN layers with variable indium composition.
  • it can be used in On the basis of satisfying the two-dimensional electron gas under the depletion gate, the doping concentration of Mg in p-GaN can be reduced to a certain extent, and the diffusion of Mg to the barrier layer and channel layer can be reduced, thereby reducing the leakage channel.
  • the band gap of In b Ga 1-b N with low indium composition is smaller. Compared with In a Ga 1- a N, In b Ga 1- b N has a lower threshold voltage under the same thickness. less impact.
  • the p-GaN layer and the InGaN layer are periodically arranged at intervals, it is equivalent to introducing a barrier layer under each layer of p-GaN with a small thickness, which can further effectively reduce the Mg barrier layer and channel Layer diffusion, thereby improving the reliability of the device.
  • FIG. 1 is a schematic structural diagram of a p-GaN normally-off power device de with a periodic gate structure in an embodiment of the present invention.
  • Example 2 is a simulated transfer curve of a p-GaN normally-off power device with a periodic gate structure corresponding to the control group, Example 1 and Example 2.
  • a p-GaN normally-off power device with a periodic gate structure as shown in FIG. Layer 106;
  • a source and a drain are arranged above the barrier layer 106, a periodic p-GaN/InGaN layer 107 formed on the barrier layer is arranged between the source and the drain, and the gate is arranged on the periodic p-GaN/InGaN layer 107. layer.
  • the substrate is silicon; the nucleation layer is AlN; the buffer layer is AlGaN; the channel layer is GaN; the insertion layer is AlN; the barrier layer is AlGaN;
  • the periodic p-GaN/InGaN layer 107 has multiple layers of In b Ga 1-b N layers with low indium composition and In a Ga 1-a N layers with high indium composition distributed periodically from bottom to top, and adjacent A p-GaN layer is arranged between the In b Ga 1-b N layer with low indium composition and the In a Ga 1-a N layer with high indium composition.
  • the In b Ga 1-b N layer with low indium composition b is 0.06, the thickness is 10nm, and the number of layers is 2;
  • the In a Ga 1-a N layer with high indium composition a is 0.6, the thickness is 4nm, and the number of layers is 2;
  • the total thickness of all p-GaN layers is 72 nm
  • the number of p-GaN layers is 4, and the p-GaN of the p-GaN layer is all doped with Mg, and the hole concentration is 2E18 cm -3 .
  • a p-GaN normally-off power device with a periodic gate structure as shown in FIG. Layer 106;
  • a source and a drain are arranged above the barrier layer 106, a periodic p-GaN/InGaN layer 107 formed on the barrier layer is arranged between the source and the drain, and the gate is arranged on the periodic p-GaN/InGaN layer 107. layer.
  • the substrate is silicon; the nucleation layer is AlN; the buffer layer is AlGaN; the channel layer is GaN; the insertion layer is AlN; the barrier layer is AlGaN;
  • the periodic p-GaN/InGaN layer 107 has multiple layers of In b Ga 1-b N layers with low indium composition and In a Ga 1-a N layers with high indium composition distributed periodically from bottom to top, and adjacent A p-GaN layer is arranged between the In b Ga 1-b N layer of low indium composition and the In a Ga 1-a N layer of high indium composition;
  • the In b Ga 1-b N layer with low indium composition b is 0.06, the thickness is 5nm, and the number of layers is 4;
  • the In a Ga 1-a N layer with high indium composition a is 0.6, the thickness is 2nm, and the number of layers is 4;
  • the total thickness of all p-GaN layers is 72 nm, the number of p-GaN layers is 8, and the p-GaN of the p-GaN layer is all doped with Mg, and the hole concentration is 2E18 cm -3 ;
  • Fig. 2 is the simulated transfer curve corresponding to control group, embodiment 1 and embodiment 2, wherein in the control group, there is no InGaN layer, the total thickness of all p-GaN layers is the same as that of all p-GaN layers in embodiment 1 and embodiment 2 The total thickness remains the same, and the concentration of doped Mg in p-GaN is also the same; the composition of InGaN in Example 1 and Example 2 is also the same, but the thickness and period are different; it can be seen from Figure 2 that compared with the control group , the threshold voltages of Example 1 and Example 2 are positively shifted, and compared with Example 1, the threshold voltage of Example 2 is larger.
  • step-type polarization electric field between the p-GaN/InGaN layers 107 with variable indium composition can effectively improve the ionization efficiency of Mg, thereby increasing the threshold voltage. And with the increase of the number of cycles, the interaction of the polarization electric field is stronger, and the threshold voltage is further increased.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention divulgue un dispositif d'alimentation normalement fermé p-GaN ayant une structure de grille périodique. Le dispositif comprend un substrat, une couche de nucléation, une couche tampon, une couche de canal, une couche d'insertion et une couche barrière de bas en haut, une électrode de source et une électrode de drain étant situées sur la couche barrière ; une couche p-GaN/InGaN périodique qui est formée sur la couche barrière étant située entre l'électrode de source et l'électrode de drain ; une électrode de grille étant située sur la couche périodique de p-GaN/InGaN ; une pluralité de couches de InbGa1-bN présentant des composants à faible teneur en indium et une pluralité de couches de InaGa1-aN présentant des composants à haute teneur en indium étant périodiquement distribuées sur la couche périodique de p-p-GaN/InGaN de bas en haut ; et une couche P-GaN étant située entre chaque couche de InbGa1-bN présentant des composants à faible teneur en indium et une couche de InaGa1-aN présentant des composants à haute teneur en indium qui sont adjacentes. Au moyen de la présente invention, l'efficacité d'ionisation de Mg dans le p-GaN peut être efficacement améliorée, et par conséquent la concentration de dopage de Mg peut être réduite sur la base de la garantie qu'un gaz d'électrons bidimensionnel sous une grille est évacué.
PCT/CN2022/081268 2021-10-28 2022-03-16 Dispositif d'alimentation normalement fermé p-gan ayant une structure de grille périodique WO2023071028A1 (fr)

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CN202111264534.1 2021-10-28
CN202111264534.1A CN114122107B (zh) 2021-10-28 2021-10-28 一种周期栅结构的p-GaN常闭型功率器件

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118099207A (zh) * 2024-04-26 2024-05-28 山东大学 基于In组分调控InGaN的增强型GaN功率器件

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114122107B (zh) * 2021-10-28 2023-07-18 华南理工大学 一种周期栅结构的p-GaN常闭型功率器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916633A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置
CN104979387A (zh) * 2014-04-10 2015-10-14 丰田自动车株式会社 开关元件
CN107393956A (zh) * 2017-07-06 2017-11-24 中国科学院半导体研究所 包含p型超晶格的增强型高电子迁移率晶体管及制备方法
WO2020062221A1 (fr) * 2018-09-30 2020-04-02 苏州晶湛半导体有限公司 Structure semi-conductrice et son procédé de fabrication
CN114122107A (zh) * 2021-10-28 2022-03-01 华南理工大学 一种周期栅结构的p-GaN常闭型功率器件

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112510087B (zh) * 2020-12-01 2023-07-11 晶能光电股份有限公司 p型栅增强型GaN基HEMT器件及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916633A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置
CN104979387A (zh) * 2014-04-10 2015-10-14 丰田自动车株式会社 开关元件
CN107393956A (zh) * 2017-07-06 2017-11-24 中国科学院半导体研究所 包含p型超晶格的增强型高电子迁移率晶体管及制备方法
WO2020062221A1 (fr) * 2018-09-30 2020-04-02 苏州晶湛半导体有限公司 Structure semi-conductrice et son procédé de fabrication
CN114122107A (zh) * 2021-10-28 2022-03-01 华南理工大学 一种周期栅结构的p-GaN常闭型功率器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118099207A (zh) * 2024-04-26 2024-05-28 山东大学 基于In组分调控InGaN的增强型GaN功率器件

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