WO2023070777A1

WO2023070777A1 - Electronic device testing method and testing apparatus

Info

Publication number: WO2023070777A1
Application number: PCT/CN2021/131551
Authority: WO
Inventors: 程振; 李志雄
Original assignee: 深圳市江波龙电子股份有限公司
Priority date: 2021-10-28
Filing date: 2021-11-18
Publication date: 2023-05-04
Also published as: CN116047246A

Abstract

An electronic device testing method and testing apparatus, the testing method comprising: providing a test circuit board (200), wherein a first contact point is provided on the test circuit board (200); arranging a flexible conductive layer between the test circuit board (200) and an electronic device under test, wherein a second contact point is provided on the electronic device under test; and pressing the test circuit board (200) and the electronic device under test, such that the first contact point and the second contact point, which correspond to each other, are electrically connected by means of the flexible conductive layer, so as to use the test circuit board (200) to test the electronic device under test. By means of the testing method, cost increases are reduced while increasing the testing frequency.

Description

Electronic device testing method and testing device

This application claims the priority of Chinese Patent Application No. 2021112662633, the contents of which are incorporated in this application by reference.

【Technical field】

The present application relates to the field of testing, in particular to a testing method and testing device for electronic devices.

【Background technique】

With the development of science and technology, technologies and products related to the semiconductor industry have penetrated into all aspects of our lives and become an indispensable part of our lives. In industrial production, semiconductor testing is an essential part. Semiconductor testing records chips that do not meet the requirements and removes them before entering the subsequent process. The testing process generally includes wafer testing, packaging testing and system-level testing. Wafer testing, also known as CP (Chip Probe), is the first important step. However, the cost of several wafer testing methods in the prior art is directly proportional to the testing frequency, and the higher the testing frequency, the higher the cost.

【Content of invention】

The main purpose of the present application is to provide a testing method and testing device for electronic devices, so as to solve the problem in the prior art that the cost is too high when the test frequency is increased when testing related electronic devices.

In order to solve the above technical problems, the first technical solution adopted by the present application is to provide a testing method for electronic devices. The method includes: providing a test circuit board, the test circuit board is provided with a first contact point; a flexible conductive layer is provided between the test circuit board and the electronic device under test; wherein, the electronic device under test is provided with a second contact point ; Pressing the test circuit board and the electronic device under test, so that the corresponding first contact point and the second contact point are electrically connected through the flexible conductive layer, so as to use the test circuit board to test the electronic device under test.

In order to solve the above technical problems, the second technical solution adopted by the present application is to provide a testing device. The device includes: a test circuit board, one side of the test circuit board is provided with a first contact point; a test chip, the test chip is arranged on the other side of the test circuit board, and is electrically connected to the test circuit board; When the electronic device under test is tested, a flexible conductive layer is set between the electronic device under test and the test circuit board, and the test circuit board and the electronic device under test are pressed together so that the second contact point on the electronic device under test is aligned with the corresponding The first contact point is electrically connected through the flexible conductive layer, so as to use the test chip to test the electronic device under test.

The beneficial effect of the present application is: by making the first contact point of the test circuit board protrude, the flexible conductive layer is used for electrical connection, the use of the probe is canceled, and the signal attenuation caused by the probe being too long is avoided when the probe is used Or the cost of opening the card increases when the test frequency is increased, and the length of the conduction is reduced, thereby further reducing signal attenuation and increasing the testable frequency.

【Description of drawings】

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic diagram of an implementation scenario of a conventional wafer test;

FIG. 2 is a schematic diagram of a conventional wafer test cantilever needle test-implementation scene;

FIG. 3 is a schematic diagram of a conventional wafer test vertical needle test-implementation scenario;

FIG. 4 is a schematic diagram of a conventional wafer test MEMS needle test-implementation scene;

5 is a schematic flow diagram of the first embodiment of the electronic device testing method of the present application;

6 is a schematic flow diagram of the second embodiment of the electronic device testing method of the present application;

7 is a schematic flow chart of the third embodiment of the electronic device testing method of the present application;

Fig. 8 is a schematic flow chart of the fourth embodiment of the electronic device testing method of the present application

Fig. 9 is a schematic flow chart of the fifth embodiment of the electronic device testing method of the present application

Fig. 10 is a schematic structural view of the first embodiment of the testing device of the present application

Fig. 11 is a schematic diagram of the testing device of the present application being tested.

【Detailed ways】

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The terms "first", "second", etc. in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

The basic principle of wafer test, as shown in Figure 1, is similar to its test structure. The wafer to be tested is placed on a support with a probe card fixed on it, usually a PCB board with probes. During the test, all the tests are transmitted to the wafer through the pin card to judge whether the chip on the wafer is normal. After testing a chip, the bracket will move to continue testing other chips. There are usually a lot of circuits and copper wires on the needle card, and the test machine applies the test voltage to the probes on the needle card through these circuits. The needle card then pricks these probes to the test points of the chip for voltage delivery, thereby performing a test.

There are three conventional wafer test methods: cantilever needle test, vertical needle test and MEMS needle test.

As shown in Figure 2, the cantilever needle test is to connect the test point on the needle card PCB to the probe, and then extend the probe non-vertically. Probes are usually fixed with epoxy.

As shown in Figure 3, the vertical pin test is to connect the test points on the pin card PCB to the vertical probes set on the connector.

As shown in Figure 4, the MEMS pin test is to connect the test points on the pin card PCB to the MEMS probes set on the substrate. MEMS (Micro-Electro-Mechanical System) wafer-level testing is proposed by Janet Cassard of the National Institute of Standards and Technology to provide a five-in-one reference material (RM) solution. This standard substance is a chip with a test structure independently, and the test structure obtains material and space characteristics through five standard test methods.

The MEMS five-in-one chip is a NIST standard substance used to measure space and material properties, divided into RM8096 and RM8097. The RM8096 is fabricated using a 1.5μm compound semiconductor (CMOS) process line and micromachining etch. It is reported that each layer of this standard substance is a compound oxide layer. RM8097 is made by the backside etching technology of multi-layer surface micromachining MEMS polysilicon, and the characteristics of the polysilicon material of the first and second layers are publicly reported.

Five standard test methods are used to test the characteristics of MEMS five-in-one chips, namely: Young's modulus, step height, residual strain, strain gradient and plane length. Among them, the test methods of Young's modulus and step height have been reported in "Semiconductor Instruments and Materials International (SEMI)", and the measurement methods of residual strain, strain gradient, and plane length are provided by "American International Association for Measurement & Materials (ASTM)" publicly reported that each of the above measurement methods has a series of accuracy and correction data.

Among the above three methods, the cantilever needle is easy to manufacture and its cost is the lowest. However, due to the structure of the cantilever needle, the probe length of the cantilever needle is the longest. That is to say, the signal attenuation and the crosstalk caused by long signals during the test are The maximum frequency of the signal that can be tested by the cantilever needle test is generally not greater than 100MHz.

Among the three test methods, the MEMS probe has the shortest signal line and the highest test frequency, but the cost of opening the card is too expensive. The test frequency, card opening cost and design difficulty of the vertical needle test method are all between the above two test methods.

In order to make wafer testing take into account both testing frequency and cost consumption, the present application proposes the following electronic device testing method and testing device.

As shown in FIG. 5 , FIG. 5 is a schematic flowchart of the first embodiment of the electronic device testing method of the present application. This test method includes the following steps:

S11: Provide a test circuit board.

Wherein, the test circuit board is provided with a first contact point. The first contact point on the test circuit board protrudes from the surface of the test circuit board facing the electronic device under test. Specifically, the first contact point may be formed by bonding pads to test points on the test circuit board. The pads are connected and bound to the test points on the test circuit board by soldering and other operations, and the pads protrude from the surface of the test circuit board facing the electronic device under test, thereby forming a contact point that can be electrically connected to the second contact point first point of contact. This pad is made of a sandable, conductive material.

In one embodiment, the electronic device under test is a wafer, and the test circuit board is a pin card, that is, a PCB substrate provided with protruding first contact points.

S12: Arranging a flexible conductive layer between the test circuit board and the electronic device under test.

Wherein, the electronic device under test is provided with a second contact point. The second contact point on the electronic device under test and the first contact point on the test circuit board can be electrically connected to test the electronic device under test. The second contact point on the electronic device under test may protrude from the surface of the electronic device under test, or may be flush with the surface of the electronic device under test.

When testing the electronic device under test, a flexible conductive layer is added between the electronic device under test and the test circuit board. The flexible conductive layer can change its conductivity according to the pressure it receives. The flexible conductive layer includes anisotropic conductive silicone ACR (Anisotropic Conductive Rubber).

S13: Pressing the test circuit board and the electronic device under test.

Press the test circuit board and the electronic device under test, so that the flexible conductive layer between the second contact point of the electronic device under test and the first contact point of the test circuit board is under greater pressure, so that the flexible conductive layer here The conductivity of the layer is enhanced to conduct the electronic device under test to the test circuit board.

In this embodiment, by making the first contact point of the test circuit board protrude, the flexible conductive layer is used for electrical connection, the use of the probe is eliminated, and the signal attenuation or the signal caused by the excessive length of the probe is avoided when the probe is used. When the test frequency is increased, the cost of opening the card increases, and the length of the conduction is reduced, thereby further reducing signal attenuation and increasing the testable frequency.

As shown in FIG. 6 , FIG. 6 is a schematic flowchart of a second embodiment of the electronic device testing method of the present application. This embodiment is a further extension of step S11. This test method includes the following steps:

S21: Provide a circuit board.

A test circuit board is provided, and the circuit board has a plurality of test points for electrically connecting with the electronic device under test.

S22: Soldering is performed on at least part of the plurality of test points.

Solder the part that needs to be tested among the multiple test points on the test circuit board to form a solder joint that protrudes from the surface of the test circuit board facing the electronic device under test as the first contact point for electrical connection . Specifically, the first contact point may be formed by bonding pads to test points on the test circuit board. The pads are connected and bound to the test points on the test circuit board by soldering and other operations, and the pads protrude from the surface of the test circuit board facing the electronic device under test, thereby forming a contact point that can be electrically connected to the second contact point first point of contact. This pad is made of a sandable, conductive material.

As shown in FIG. 7 , FIG. 7 is a schematic flowchart of a third embodiment of the electronic device testing method of the present application. This embodiment is a further extension of step S11. This test method includes the following steps:

S31: Provide a circuit board.

S32: Soldering is performed on at least part of the plurality of test points.

S33: Perform grinding treatment on at least part of at least one solder joint.

The first contact points after soldering are usually uneven. For the stability and consistency of the test, all the solder points are ground to protrude from the test circuit board to the edge of the electronic device under test. The surface on one side has a preset height so that all solder joints are flush. Or select a solder joint, grind other solder joints to the same height as the solder joint, so that all solder joints are flush.

As shown in FIG. 8 , FIG. 8 is a schematic flowchart of a fourth embodiment of the electronic device testing method of the present application. This test method includes the following steps:

S41: Provide a test circuit board.

Wherein, the test circuit board is provided with a first contact point. The second contact point on the test circuit board protrudes from the surface of the test circuit board facing the electronic device under test. Specifically, the first contact point may be formed by bonding pads to test points on the test circuit board. The pads are connected and bound to the test points on the test circuit board by soldering and other operations, and the pads protrude from the surface of the test circuit board facing the electronic device under test, thereby forming a contact point that can be electrically connected to the second contact point first point of contact. This pad is made of a sandable, conductive material.

S42: Disposing a flexible conductive layer on the side of the electronic device under test where the second contact point is provided.

The electronic device under test is provided with a second contact point. The second contact point on the electronic device under test and the first contact point on the test circuit board can be electrically connected to test the electronic device under test. The second contact point on the electronic device under test may protrude from the surface of the electronic device under test, or may be flush with the surface of the electronic device under test.

A flexible conductive layer is added to the side of the electronic device under test where the second contact point is provided, that is, the side where electrical connection can be made for testing. The flexible conductive layer can change its conductivity according to the pressure it receives. The flexible conductive layer includes anisotropic conductive silicone ACR (Anisotropic Conductive Rubber).

S43: Place the side of the test circuit board provided with the first contact point facing the flexible conductive layer and place it on the flexible conductive layer.

Place the test circuit board on the flexible conductive layer with the side provided with the first contact point facing the flexible conductive layer. The position of the first contact point on the test circuit board is aligned with the position of the node on the electronic device under test, so that the flexible conductive layer between the two positions can be pressed during pressing, which enhances the conductivity of this part, thereby conducting Corresponding first contact point and second contact point.

S44: Press the test circuit board toward one side of the electronic device under test.

In an embodiment, the test circuit board may be stationary while testing is being performed. Press the electronic device under test toward the test circuit board to increase the pressure on the flexible conductive layer and increase the conductivity of the flexible conductive layer.

As shown in FIG. 9 , FIG. 9 is a schematic flowchart of a fifth embodiment of the electronic device testing method of the present application. This test method includes the following steps:

S51: Provide a test circuit board.

S52: Laying a flexible conductive layer on the side of the electronic device under test provided with the second contact point.

On the side where the electronic device under test is provided with the second contact point, that is, the side that can be electrically connected for testing, a flexible conductive layer is pasted. The flexible conductive layer can change its conductivity according to the pressure it receives. The flexible conductive layer includes anisotropic conductive silicone ACR (Anisotropic Conductive Rubber).

S53: Place the side of the test circuit board provided with the first contact point facing the flexible conductive layer and place it on the flexible conductive layer.

S54: Press the test circuit board toward one side of the electronic device under test.

S55: removing the flexible conductive layer pasted on the electronic device under test.

After the test is completed, the attached flexible conductive layer can be removed to use the device under test for subsequent testing or packaging processes.

As shown in FIG. 10 , FIG. 10 is a schematic structural diagram of the first embodiment of the testing device of the present application. The test device includes a test chip 100 and a test circuit board 200 .

Wherein, one side of the test circuit board 200 is provided with a first contact point, and the second contact point on the electronic device under test and the first contact point on the test circuit board 200 can be electrically connected so as to conduct the electronic device under test. test. The first contact point includes a solder joint formed by a soldering process. The test chip 100 is disposed on the other side of the test circuit board 200 and is electrically connected to the test circuit board.

When the test device is testing the electronic device under test, a flexible conductive layer is provided between the electronic device under test and the test circuit board 200, and the test circuit board 200 and the electronic device under test are pressed together so that the electronic device under test The second contact point is electrically connected to the corresponding first contact point through the flexible conductive layer, so as to use the test chip 100 to test the electronic device under test, as shown in FIG. 11 .

In summary, through the methods or devices described in the above several embodiments, by making the first contact point of the test circuit board protrude, and using a flexible conductive layer for electrical connection, the use of probes is eliminated, and the use of When the probe is too long, the signal attenuation caused by the probe or the cost of opening the card increases when the test frequency is increased, and the length of the conduction is reduced, thereby further reducing the signal attenuation and increasing the testable frequency.

In the several implementation manners provided in this application, it should be understood that the disclosed methods and devices may be implemented in other ways. For example, the device implementation described above is only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated units in the above other embodiments are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc., which can store program codes. .

The above is only an embodiment of the application, and does not limit the patent scope of the application. Any equivalent structure or equivalent process conversion made by using the specification and drawings of the application, or directly or indirectly used in other related technologies fields, are all included in the scope of patent protection of this application in the same way.

Claims

A method for testing an electronic device, comprising:

providing a test circuit board, the test circuit board is provided with a first contact point;

A flexible conductive layer is provided between the test circuit board and the electronic device under test; wherein, a second contact point is provided on the electronic device under test;

Pressing the test circuit board and the electronic device under test, so that the corresponding first contact point and the second contact point are electrically connected through the flexible conductive layer, so that the test circuit board can be used to The electronic device under test is tested.
The method according to claim 1, characterized in that,

The first contact point protrudes from a side of the test circuit board facing the electronic device under test.
The method according to claim 1, characterized in that,

A test circuit board is provided, comprising:

A circuit board is provided; wherein, the circuit board is provided with a plurality of test points;

Soldering is performed on at least part of the plurality of test points to form at least one solder point as the first contact point.
The method according to claim 3, characterized in that,

After performing the soldering operation on at least part of the plurality of test points, it also includes:

Grinding at least a portion of the at least one solder joint to make the at least one solder joint flush.
The method according to claim 1, characterized in that,

The arranging a flexible conductive layer between the test circuit board and the electronic device under test includes:

The flexible conductive layer is provided on the side of the electronic device under test provided with the second contact point;

placing the side of the test circuit board with the first contact point facing the flexible conductive layer and placing it on the flexible conductive layer;

The press-fitting of the test circuit board and the electronic device under test includes:

The test circuit board is pressed toward one side of the electronic device under test.
The method according to claim 5, characterized in that,

The arranging the flexible conductive layer on the side where the second contact point is provided on the electronic device under test includes:

affixing the flexible conductive layer on the side of the electronic device under test provided with the second contact point;

After using the test circuit board to test the electronic device under test, it also includes:

removing the flexible conductive layer pasted on the electronic device under test.
The method according to any one of claims 1-6, characterized in that,

The flexible conductive layer is anisotropic conductive adhesive.
The method according to any one of claims 1-6, characterized in that,

The electronic device is a wafer.
A test device, characterized in that the test device comprises:

A test circuit board, one side of the test circuit board is provided with a first contact point;

A test chip, the test chip is arranged on the other side of the test circuit board and is electrically connected to the test circuit board;

Wherein, when the test device is testing the electronic device under test, a flexible conductive layer is arranged between the electronic device under test and the test circuit board, and the test circuit board and the electronic device under test are tested. Pressing, so that the second contact point on the electronic device under test is electrically connected to the corresponding first contact point through the flexible conductive layer, so as to use the test chip to test the electronic device under test.
The testing device according to claim 9, characterized in that,

The first contact point is a solder joint formed by a soldering process.