WO2023070777A1 - Procédé de test et appareil de test de dispositif électronique - Google Patents

Procédé de test et appareil de test de dispositif électronique Download PDF

Info

Publication number
WO2023070777A1
WO2023070777A1 PCT/CN2021/131551 CN2021131551W WO2023070777A1 WO 2023070777 A1 WO2023070777 A1 WO 2023070777A1 CN 2021131551 W CN2021131551 W CN 2021131551W WO 2023070777 A1 WO2023070777 A1 WO 2023070777A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
electronic device
circuit board
device under
contact point
Prior art date
Application number
PCT/CN2021/131551
Other languages
English (en)
Chinese (zh)
Inventor
程振
李志雄
Original Assignee
深圳市江波龙电子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市江波龙电子股份有限公司 filed Critical 深圳市江波龙电子股份有限公司
Publication of WO2023070777A1 publication Critical patent/WO2023070777A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices

Definitions

  • the present application relates to the field of testing, in particular to a testing method and testing device for electronic devices.
  • Wafer testing also known as CP (Chip Probe)
  • CP Chip Probe
  • the main purpose of the present application is to provide a testing method and testing device for electronic devices, so as to solve the problem in the prior art that the cost is too high when the test frequency is increased when testing related electronic devices.
  • the first technical solution adopted by the present application is to provide a testing method for electronic devices.
  • the method includes: providing a test circuit board, the test circuit board is provided with a first contact point; a flexible conductive layer is provided between the test circuit board and the electronic device under test; wherein, the electronic device under test is provided with a second contact point ; Pressing the test circuit board and the electronic device under test, so that the corresponding first contact point and the second contact point are electrically connected through the flexible conductive layer, so as to use the test circuit board to test the electronic device under test.
  • the second technical solution adopted by the present application is to provide a testing device.
  • the device includes: a test circuit board, one side of the test circuit board is provided with a first contact point; a test chip, the test chip is arranged on the other side of the test circuit board, and is electrically connected to the test circuit board;
  • a flexible conductive layer is set between the electronic device under test and the test circuit board, and the test circuit board and the electronic device under test are pressed together so that the second contact point on the electronic device under test is aligned with the corresponding
  • the first contact point is electrically connected through the flexible conductive layer, so as to use the test chip to test the electronic device under test.
  • the beneficial effect of the present application is: by making the first contact point of the test circuit board protrude, the flexible conductive layer is used for electrical connection, the use of the probe is canceled, and the signal attenuation caused by the probe being too long is avoided when the probe is used Or the cost of opening the card increases when the test frequency is increased, and the length of the conduction is reduced, thereby further reducing signal attenuation and increasing the testable frequency.
  • FIG. 1 is a schematic diagram of an implementation scenario of a conventional wafer test
  • FIG. 2 is a schematic diagram of a conventional wafer test cantilever needle test-implementation scene
  • FIG. 3 is a schematic diagram of a conventional wafer test vertical needle test-implementation scenario
  • FIG. 4 is a schematic diagram of a conventional wafer test MEMS needle test-implementation scene
  • FIG. 5 is a schematic flow diagram of the first embodiment of the electronic device testing method of the present application.
  • FIG. 6 is a schematic flow diagram of the second embodiment of the electronic device testing method of the present application.
  • FIG. 7 is a schematic flow chart of the third embodiment of the electronic device testing method of the present application.
  • Fig. 8 is a schematic flow chart of the fourth embodiment of the electronic device testing method of the present application.
  • Fig. 9 is a schematic flow chart of the fifth embodiment of the electronic device testing method of the present application.
  • Fig. 10 is a schematic structural view of the first embodiment of the testing device of the present application
  • Fig. 11 is a schematic diagram of the testing device of the present application being tested.
  • the basic principle of wafer test is similar to its test structure.
  • the wafer to be tested is placed on a support with a probe card fixed on it, usually a PCB board with probes.
  • a probe card fixed on it, usually a PCB board with probes.
  • all the tests are transmitted to the wafer through the pin card to judge whether the chip on the wafer is normal.
  • the bracket will move to continue testing other chips.
  • the needle card then pricks these probes to the test points of the chip for voltage delivery, thereby performing a test.
  • the cantilever needle test is to connect the test point on the needle card PCB to the probe, and then extend the probe non-vertically. Probes are usually fixed with epoxy.
  • the vertical pin test is to connect the test points on the pin card PCB to the vertical probes set on the connector.
  • the MEMS pin test is to connect the test points on the pin card PCB to the MEMS probes set on the substrate.
  • MEMS Micro-Electro-Mechanical System
  • wafer-level testing is proposed by Janet Cassard of the National Institute of Standards and Technology to provide a five-in-one reference material (RM) solution.
  • RM five-in-one reference material
  • the MEMS five-in-one chip is a NIST standard substance used to measure space and material properties, divided into RM8096 and RM8097.
  • the RM8096 is fabricated using a 1.5 ⁇ m compound semiconductor (CMOS) process line and micromachining etch. It is reported that each layer of this standard substance is a compound oxide layer.
  • CMOS compound semiconductor
  • RM8097 is made by the backside etching technology of multi-layer surface micromachining MEMS polysilicon, and the characteristics of the polysilicon material of the first and second layers are publicly reported.
  • the cantilever needle is easy to manufacture and its cost is the lowest.
  • the probe length of the cantilever needle is the longest. That is to say, the signal attenuation and the crosstalk caused by long signals during the test are
  • the maximum frequency of the signal that can be tested by the cantilever needle test is generally not greater than 100MHz.
  • the MEMS probe has the shortest signal line and the highest test frequency, but the cost of opening the card is too expensive.
  • the test frequency, card opening cost and design difficulty of the vertical needle test method are all between the above two test methods.
  • the present application proposes the following electronic device testing method and testing device.
  • FIG. 5 is a schematic flowchart of the first embodiment of the electronic device testing method of the present application. This test method includes the following steps:
  • the test circuit board is provided with a first contact point.
  • the first contact point on the test circuit board protrudes from the surface of the test circuit board facing the electronic device under test.
  • the first contact point may be formed by bonding pads to test points on the test circuit board.
  • the pads are connected and bound to the test points on the test circuit board by soldering and other operations, and the pads protrude from the surface of the test circuit board facing the electronic device under test, thereby forming a contact point that can be electrically connected to the second contact point first point of contact.
  • This pad is made of a sandable, conductive material.
  • the electronic device under test is a wafer
  • the test circuit board is a pin card, that is, a PCB substrate provided with protruding first contact points.
  • S12 Arranging a flexible conductive layer between the test circuit board and the electronic device under test.
  • the electronic device under test is provided with a second contact point.
  • the second contact point on the electronic device under test and the first contact point on the test circuit board can be electrically connected to test the electronic device under test.
  • the second contact point on the electronic device under test may protrude from the surface of the electronic device under test, or may be flush with the surface of the electronic device under test.
  • a flexible conductive layer is added between the electronic device under test and the test circuit board.
  • the flexible conductive layer can change its conductivity according to the pressure it receives.
  • the flexible conductive layer includes anisotropic conductive silicone ACR (Anisotropic Conductive Rubber).
  • the flexible conductive layer is used for electrical connection, the use of the probe is eliminated, and the signal attenuation or the signal caused by the excessive length of the probe is avoided when the probe is used.
  • the test frequency is increased, the cost of opening the card increases, and the length of the conduction is reduced, thereby further reducing signal attenuation and increasing the testable frequency.
  • FIG. 6 is a schematic flowchart of a second embodiment of the electronic device testing method of the present application. This embodiment is a further extension of step S11.
  • This test method includes the following steps:
  • a test circuit board is provided, and the circuit board has a plurality of test points for electrically connecting with the electronic device under test.
  • the first contact point may be formed by bonding pads to test points on the test circuit board.
  • the pads are connected and bound to the test points on the test circuit board by soldering and other operations, and the pads protrude from the surface of the test circuit board facing the electronic device under test, thereby forming a contact point that can be electrically connected to the second contact point first point of contact.
  • This pad is made of a sandable, conductive material.
  • FIG. 7 is a schematic flowchart of a third embodiment of the electronic device testing method of the present application. This embodiment is a further extension of step S11.
  • This test method includes the following steps:
  • a test circuit board is provided, and the circuit board has a plurality of test points for electrically connecting with the electronic device under test.
  • S32 Soldering is performed on at least part of the plurality of test points.
  • the first contact point may be formed by bonding pads to test points on the test circuit board.
  • the pads are connected and bound to the test points on the test circuit board by soldering and other operations, and the pads protrude from the surface of the test circuit board facing the electronic device under test, thereby forming a contact point that can be electrically connected to the second contact point first point of contact.
  • This pad is made of a sandable, conductive material.
  • S33 Perform grinding treatment on at least part of at least one solder joint.
  • the first contact points after soldering are usually uneven.
  • all the solder points are ground to protrude from the test circuit board to the edge of the electronic device under test.
  • the surface on one side has a preset height so that all solder joints are flush. Or select a solder joint, grind other solder joints to the same height as the solder joint, so that all solder joints are flush.
  • FIG. 8 is a schematic flowchart of a fourth embodiment of the electronic device testing method of the present application. This test method includes the following steps:
  • the test circuit board is provided with a first contact point.
  • the second contact point on the test circuit board protrudes from the surface of the test circuit board facing the electronic device under test.
  • the first contact point may be formed by bonding pads to test points on the test circuit board.
  • the pads are connected and bound to the test points on the test circuit board by soldering and other operations, and the pads protrude from the surface of the test circuit board facing the electronic device under test, thereby forming a contact point that can be electrically connected to the second contact point first point of contact.
  • This pad is made of a sandable, conductive material.
  • S42 Disposing a flexible conductive layer on the side of the electronic device under test where the second contact point is provided.
  • the electronic device under test is provided with a second contact point.
  • the second contact point on the electronic device under test and the first contact point on the test circuit board can be electrically connected to test the electronic device under test.
  • the second contact point on the electronic device under test may protrude from the surface of the electronic device under test, or may be flush with the surface of the electronic device under test.
  • a flexible conductive layer is added to the side of the electronic device under test where the second contact point is provided, that is, the side where electrical connection can be made for testing.
  • the flexible conductive layer can change its conductivity according to the pressure it receives.
  • the flexible conductive layer includes anisotropic conductive silicone ACR (Anisotropic Conductive Rubber).
  • test circuit board Place the test circuit board on the flexible conductive layer with the side provided with the first contact point facing the flexible conductive layer.
  • the position of the first contact point on the test circuit board is aligned with the position of the node on the electronic device under test, so that the flexible conductive layer between the two positions can be pressed during pressing, which enhances the conductivity of this part, thereby conducting Corresponding first contact point and second contact point.
  • the test circuit board may be stationary while testing is being performed. Press the electronic device under test toward the test circuit board to increase the pressure on the flexible conductive layer and increase the conductivity of the flexible conductive layer.
  • FIG. 9 is a schematic flowchart of a fifth embodiment of the electronic device testing method of the present application. This test method includes the following steps:
  • the test circuit board is provided with a first contact point.
  • the first contact point on the test circuit board protrudes from the surface of the test circuit board facing the electronic device under test.
  • the first contact point may be formed by bonding pads to test points on the test circuit board.
  • the pads are connected and bound to the test points on the test circuit board by soldering and other operations, and the pads protrude from the surface of the test circuit board facing the electronic device under test, thereby forming a contact point that can be electrically connected to the second contact point first point of contact.
  • This pad is made of a sandable, conductive material.
  • the electronic device under test is provided with a second contact point.
  • the second contact point on the electronic device under test and the first contact point on the test circuit board can be electrically connected to test the electronic device under test.
  • the second contact point on the electronic device under test may protrude from the surface of the electronic device under test, or may be flush with the surface of the electronic device under test.
  • a flexible conductive layer is pasted.
  • the flexible conductive layer can change its conductivity according to the pressure it receives.
  • the flexible conductive layer includes anisotropic conductive silicone ACR (Anisotropic Conductive Rubber).
  • S53 Place the side of the test circuit board provided with the first contact point facing the flexible conductive layer and place it on the flexible conductive layer.
  • test circuit board Place the test circuit board on the flexible conductive layer with the side provided with the first contact point facing the flexible conductive layer.
  • the position of the first contact point on the test circuit board is aligned with the position of the node on the electronic device under test, so that the flexible conductive layer between the two positions can be pressed during pressing, which enhances the conductivity of this part, thereby conducting Corresponding first contact point and second contact point.
  • the test circuit board may be stationary while testing is being performed. Press the electronic device under test toward the test circuit board to increase the pressure on the flexible conductive layer and increase the conductivity of the flexible conductive layer.
  • the attached flexible conductive layer can be removed to use the device under test for subsequent testing or packaging processes.
  • FIG. 10 is a schematic structural diagram of the first embodiment of the testing device of the present application.
  • the test device includes a test chip 100 and a test circuit board 200 .
  • one side of the test circuit board 200 is provided with a first contact point, and the second contact point on the electronic device under test and the first contact point on the test circuit board 200 can be electrically connected so as to conduct the electronic device under test. test.
  • the first contact point includes a solder joint formed by a soldering process.
  • the test chip 100 is disposed on the other side of the test circuit board 200 and is electrically connected to the test circuit board.
  • a flexible conductive layer is provided between the electronic device under test and the test circuit board 200, and the test circuit board 200 and the electronic device under test are pressed together so that the electronic device under test
  • the second contact point is electrically connected to the corresponding first contact point through the flexible conductive layer, so as to use the test chip 100 to test the electronic device under test, as shown in FIG. 11 .
  • the use of probes is eliminated, and the use of When the probe is too long, the signal attenuation caused by the probe or the cost of opening the card increases when the test frequency is increased, and the length of the conduction is reduced, thereby further reducing the signal attenuation and increasing the testable frequency.
  • the disclosed methods and devices may be implemented in other ways.
  • the device implementation described above is only illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated units in the above other embodiments are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) execute all or part of the steps of the methods described in various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc., which can store program codes. .

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

Procédé de test et un appareil de test de dispositif électronique, le procédé de test consistant : à fournir une carte de circuit imprimé de test (200), un premier point de contact étant disposé sur la carte de circuit imprimé de test (200) ; à agencer une couche conductrice souple entre la carte de circuit imprimé de test (200) et un dispositif électronique testé, un second point de contact étant disposé sur le dispositif électronique testé ; et à presser la carte de circuit imprimé de test (200) et le dispositif électronique testé, de telle sorte que le premier point de contact et le second point de contact, qui correspondent l'un à l'autre, soient connectés électriquement au moyen de la couche conductrice souple, de manière à utiliser la carte de circuit imprimé de test (200) pour tester le dispositif électronique testé. Grâce au procédé de test, les augmentations de coût sont réduites tout en augmentant la fréquence de test.
PCT/CN2021/131551 2021-10-28 2021-11-18 Procédé de test et appareil de test de dispositif électronique WO2023070777A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111266263.3 2021-10-28
CN202111266263.3A CN116047246A (zh) 2021-10-28 2021-10-28 电子器件的测试方法及测试装置

Publications (1)

Publication Number Publication Date
WO2023070777A1 true WO2023070777A1 (fr) 2023-05-04

Family

ID=86120519

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/131551 WO2023070777A1 (fr) 2021-10-28 2021-11-18 Procédé de test et appareil de test de dispositif électronique

Country Status (2)

Country Link
CN (1) CN116047246A (fr)
WO (1) WO2023070777A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200502556A (en) * 2003-07-10 2005-01-16 Siliconware Precision Industries Co Ltd Wafer test method
CN101183119A (zh) * 2006-11-13 2008-05-21 采钰科技股份有限公司 晶片级测试电路板的制造方法及其结构
US20090289253A1 (en) * 2008-05-21 2009-11-26 Stats Chippac, Ltd. Semiconductor Wafer and Method of Forming Sacrificial Bump Pad for Wafer Probing During Wafer Sort Test
TWM460390U (zh) * 2012-12-04 2013-08-21 Standard Technology Service Inc 晶圓測試載板及晶圓測試機台
TWM461871U (zh) * 2012-12-04 2013-09-11 Standard Technology Service Inc 晶圓測試載板及晶圓測試機台
CN111308306A (zh) * 2020-03-12 2020-06-19 深圳市江波龙电子股份有限公司 一种晶圆测试装置和晶圆测试方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200502556A (en) * 2003-07-10 2005-01-16 Siliconware Precision Industries Co Ltd Wafer test method
CN101183119A (zh) * 2006-11-13 2008-05-21 采钰科技股份有限公司 晶片级测试电路板的制造方法及其结构
US20090289253A1 (en) * 2008-05-21 2009-11-26 Stats Chippac, Ltd. Semiconductor Wafer and Method of Forming Sacrificial Bump Pad for Wafer Probing During Wafer Sort Test
TWM460390U (zh) * 2012-12-04 2013-08-21 Standard Technology Service Inc 晶圓測試載板及晶圓測試機台
TWM461871U (zh) * 2012-12-04 2013-09-11 Standard Technology Service Inc 晶圓測試載板及晶圓測試機台
CN111308306A (zh) * 2020-03-12 2020-06-19 深圳市江波龙电子股份有限公司 一种晶圆测试装置和晶圆测试方法

Also Published As

Publication number Publication date
CN116047246A (zh) 2023-05-02

Similar Documents

Publication Publication Date Title
JP3486841B2 (ja) 垂直型プローブカード
KR20040077971A (ko) 실리콘 핑거 접촉기를 갖는 접촉 구조체
JPH07109840B2 (ja) 半導体ｉｃの試験装置及び試験方法
TW510010B (en) Semiconductor integrated circuit testing system and method
US7262617B2 (en) Method for testing integrated circuit, and wafer
TW200816339A (en) Bump test units and apparatus, and methods for testing bumps
JPH11101820A (ja) プローブカードおよびそれを用いたウエハテスト方法
US6433360B1 (en) Structure and method of testing failed or returned die to determine failure location and type
US7523369B2 (en) Substrate and testing method thereof
WO2023070777A1 (fr) Procédé de test et appareil de test de dispositif électronique
TW201118381A (en) Test device for high-frequency vertical probe card
US7723980B2 (en) Fully tested wafers having bond pads undamaged by probing and applications thereof
TW584727B (en) Wafer level probe card
JP2004053409A (ja) プローブカード
TWI713274B (zh) 電氣特性之檢查方法、及半導體裝置之製造方法
TWI281035B (en) Test board for high-frequency system level test
JP3535728B2 (ja) 半導体集積回路の検査装置
TWI455222B (zh) 半導體元件堆疊結構測試方法
TWI326770B (fr)
TW201321758A (zh) 探針卡
JP2002185103A (ja) 実装用基板の実装面における電極パッドの平坦性評価方法
US7408189B2 (en) Method of testing FPC bonding yield and FPC having testing pads thereon
TWI754335B (zh) 檢測裝置
US9485671B2 (en) Inter-stage test structure for wireless communication apparatus
TWI260416B (en) Coplanar test board

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21962121

Country of ref document: EP

Kind code of ref document: A1