WO2023067926A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2023067926A1
WO2023067926A1 PCT/JP2022/033369 JP2022033369W WO2023067926A1 WO 2023067926 A1 WO2023067926 A1 WO 2023067926A1 JP 2022033369 W JP2022033369 W JP 2022033369W WO 2023067926 A1 WO2023067926 A1 WO 2023067926A1
Authority
WO
WIPO (PCT)
Prior art keywords
passivation layer
layer
opening
electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/033369
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
正貴 木島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2023555000A priority Critical patent/JPWO2023067926A1/ja
Priority to US18/293,919 priority patent/US20240347408A1/en
Priority to CN202280057520.9A priority patent/CN117836906A/zh
Priority to DE112022005058.6T priority patent/DE112022005058T5/de
Publication of WO2023067926A1 publication Critical patent/WO2023067926A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Definitions

  • the present disclosure relates to semiconductor devices.
  • a semiconductor device using a silicon nitride layer and a polyimide layer for a passivation layer formed on an electrode is disclosed.
  • a semiconductor device includes a substrate having a first main surface, an electrode provided above the first main surface, a first passivation layer covering the electrode and containing an inorganic material, and the first passivation layer. a second passivation layer formed on the second passivation layer and comprising an organic material, wherein a first opening is formed in the first passivation layer to expose a portion of the electrode; A second opening is formed contiguous with the first opening, and the second side wall surface of the second opening is inside the first side wall surface of the first opening.
  • FIG. 1 is a top view showing the semiconductor device according to the embodiment.
  • FIG. 2 is a cross-sectional view showing the semiconductor device according to the embodiment.
  • FIG. 3 is a cross-sectional view (part 1) showing the method of manufacturing the semiconductor device according to the embodiment.
  • FIG. 4 is a cross-sectional view (Part 2) showing the method for manufacturing the semiconductor device according to the embodiment.
  • FIG. 5 is a cross-sectional view (Part 3) showing the method for manufacturing the semiconductor device according to the embodiment.
  • FIG. 6 is a cross-sectional view (part 4) showing the method for manufacturing the semiconductor device according to the embodiment.
  • a plated layer is formed on the surface of the electrode, the plated layer may come off when a wire is bonded to the plated layer.
  • An object of the present disclosure is to provide a semiconductor device capable of suppressing peeling of a plating layer formed on the surface of an electrode.
  • a semiconductor device includes a substrate having a first main surface, an electrode provided above the first main surface, and a first passivation layer covering the electrode and containing an inorganic material. and a second passivation layer formed on the first passivation layer and containing an organic material, wherein a first opening exposing a portion of the electrode is formed in the first passivation layer, the A second opening connected to the first opening is formed in the second passivation layer, and the second sidewall surface of the second opening is inside the first sidewall surface of the first opening.
  • the second side wall surface of the second opening is inside the first side wall surface of the first opening, when the plating layer is formed on the surface of the electrode, part of the plating layer forms the electrode and the second passivation layer. will be located between Therefore, when a wire is bonded to the plating layer, even if an external force acts on the plating layer in a direction away from the first main surface, a force directed toward the first main surface acts on the plating layer from the second passivation layer. do. Therefore, peeling of the plating layer can be suppressed.
  • [2] In [1], in a cross section perpendicular to the first main surface and the first side wall surface, in a direction parallel to the first main surface between the first side wall surface and the second side wall surface may be 1 ⁇ m or more and 5 ⁇ m or less. If the maximum value of this distance is less than 1 ⁇ m, the portion of the plated layer of the second passivation layer that acts on the force directed toward the first main surface becomes too small, which may make it difficult to suppress peeling of the plated layer. On the other hand, if the maximum value of this distance exceeds 5 ⁇ m, it becomes difficult to form a plated layer between the second passivation layer and the electrode, and there is a possibility that voids may occur.
  • part of the lower surface of the first passivation layer may be in contact with the upper surface of the electrode. In this case, it is easy to suppress the penetration of the plating solution along the surface of the electrode.
  • the thickness of the first passivation layer may be 0.2 ⁇ m or more and 1.0 ⁇ m or less. If the thickness is less than 0.2 ⁇ m, the resistance to moisture may be lowered. On the other hand, if the thickness exceeds 1.0 ⁇ m, the first passivation layer may exert a large stress on the substrate.
  • the shape of the first opening when viewed from above in a direction perpendicular to the first main surface, has a minimum radius of curvature of 10 ⁇ m or more at each of the four corners. It may be a rectangle with rounded corners of 100 ⁇ m or less.
  • the first passivation layer may include a silicon nitride layer. In this case, excellent resistance to moisture is likely to be obtained.
  • the second passivation layer may include a polyimide layer. In this case, it is easy to obtain an appropriate degree of hardness on the surface.
  • the substrate may be a silicon carbide substrate. In this case, it is easy to obtain excellent withstand voltage.
  • FIG. 1 is a top view showing the semiconductor device according to the embodiment.
  • FIG. 2 is a cross-sectional view showing the semiconductor device according to the embodiment.
  • FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG.
  • the semiconductor device 100 mainly includes a substrate 10, an ohmic layer 20, an electrode 30, a plating layer 40, a first passivation layer 50, a second passivation layer 50, and a second passivation layer 50. layer 60;
  • the substrate 10 is, for example, a silicon carbide substrate.
  • Substrate 10 includes, for example, silicon carbide single crystal substrate 11 and silicon carbide epitaxial layer 12 on silicon carbide single crystal substrate 11 .
  • the substrate 10 has a first major surface 1 and a second major surface 2 opposite the first major surface 1 .
  • Silicon carbide epitaxial layer 12 forms first main surface 1
  • silicon carbide single-crystal substrate 11 forms second main surface 2 .
  • Silicon carbide single crystal substrate 11 and silicon carbide epitaxial layer 12 are made of hexagonal silicon carbide of polytype 4H, for example.
  • a plurality of semiconductor regions doped with impurities may be formed in silicon carbide epitaxial layer 12 .
  • a semiconductor element such as a field effect transistor is formed on the substrate 10 .
  • the first main surface 1 is a plane in which the ⁇ 0001 ⁇ plane or the ⁇ 0001 ⁇ plane is inclined in the off direction by an off angle of 8° or less.
  • the first main surface 1 is the (000-1) plane or a plane in which the (000-1) plane is inclined in the off direction by an off angle of 8° or less.
  • the off direction may be, for example, the ⁇ 11-20> direction or the ⁇ 1-100> direction.
  • the off angle may be, for example, 1° or more, or may be 2° or more.
  • the off angle may be 6° or less, or may be 4° or less.
  • Ohmic layer 20 is selectively formed on first main surface 1 and is in ohmic contact with part of silicon carbide epitaxial layer 12 .
  • the ohmic layer 20 is made of a material containing nickel silicide (NiSi), for example.
  • Ohmic layer 20 may be made of a material containing titanium (Ti), aluminum, and silicon.
  • Electrode 30 is formed on the ohmic layer 20. Electrode 30 is, for example, an aluminum electrode. Electrode 30 is electrically connected to substrate 10 via ohmic layer 20 .
  • the first passivation layer 50 contains an inorganic material.
  • First passivation layer 50 is formed on silicon carbide epitaxial layer 12 and partially covers electrode 30 .
  • a first opening 51 is formed in the first passivation layer 50 .
  • a first opening 51 is formed on the electrode 30 , and a portion of the electrode 30 is exposed through the first opening 51 .
  • the first passivation layer 50 includes, for example, a silicon nitride (SiN) layer.
  • the first passivation layer 50 may be a silicon nitride layer.
  • the first opening 51 has a first side wall surface 51S.
  • the first side wall surface 51S may be perpendicular to the first principal surface 1 or may be inclined from a plane perpendicular to the first principal surface 1 .
  • a portion of the bottom surface 52 of the first passivation layer 50 is in contact with the top surface 32 of the electrode 30 .
  • the second passivation layer 60 contains an organic material.
  • a second passivation layer 60 is formed over the first passivation layer 50 .
  • a second opening 61 that continues to the first opening 51 is formed in the second passivation layer 60 .
  • a second opening 61 is formed on the first passivation layer 50 , and a portion of the first passivation layer 50 and a portion of the electrode 30 are exposed through the second opening 61 .
  • the second opening 61 has a second side wall surface 61S. In plan view from a direction perpendicular to the first main surface 1, the second side wall surface 61S is inside the first side wall surface 51S.
  • the second side wall surface 61S may be perpendicular to the first principal surface 1 or may be inclined from a plane perpendicular to the first principal surface 1 .
  • the second passivation layer 60 includes, for example, a polyimide layer.
  • the second passivation layer 60 may be a polyimide layer.
  • the plating layer 40 has a nickel (Ni) plating layer 41 , a palladium (Pd) plating layer 42 and a gold (Au) plating layer 43 .
  • a portion of the plating layer 40 is between the electrode 30 and the second passivation layer 60 in the direction perpendicular to the first main surface 1 .
  • the Ni plating layer 41 is formed on the electrode 30 inside the first opening 51 and the second opening 61 .
  • a portion of the Ni plating layer 41 is between the electrode 30 and the second passivation layer 60 in the direction perpendicular to the first main surface 1 .
  • the Ni plating layer 41 may contain phosphorus (P).
  • the Pd plating layer 42 is formed on the Ni plating layer 41 inside the second opening 61 .
  • the Au plating layer 43 is formed on the Pd plating layer 42 inside the second opening 61 .
  • the thickness of the Ni plating layer 41 is preferably 3.0 ⁇ m or more and 7.0 ⁇ m or less, more preferably 4.0 ⁇ m or more and 6.0 ⁇ m or less.
  • the thickness of the Pd plating layer 42 is preferably 20 nm or more and 40 nm or less, more preferably 25 nm or more and 35 nm or less.
  • the thickness of the Au plating layer 43 is preferably 30 nm or more and 70 nm or less, more preferably 40 nm or more and 60 nm or less.
  • 3 to 6 are cross-sectional views showing the method of manufacturing the semiconductor device 100 according to the embodiment.
  • a substrate 10 is prepared.
  • silicon carbide epitaxial layer 12 is formed on silicon carbide single crystal substrate 11 .
  • various semiconductor regions are formed in the silicon carbide epitaxial layer 12 by ion implantation or the like.
  • an ohmic layer 20 is formed on the first main surface 1 and an electrode 30 is formed on the ohmic layer 20 .
  • a first passivation layer 50 is formed on the first main surface 1 so as to cover the ohmic layer 20 and the electrode 30 .
  • the first passivation layer 50 for example, a silicon nitride layer is formed.
  • a second passivation layer 60 is then formed on the first passivation layer 50 .
  • a polyimide layer is formed.
  • a second opening 61 is formed in the second passivation layer 60 .
  • the second opening 61 has a second side wall surface 61S.
  • the second passivation layer 60 is a photosensitive polyimide layer, exposing and developing the second passivation layer 60 can form the second openings 61 .
  • the first passivation layer 50 is etched to form a first opening 51 in the first passivation layer 50 .
  • this etching for example, dry etching using a mixed gas of carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) is performed without applying a bias voltage.
  • This etching is, for example, isotropic etching.
  • the first opening 51 has, for example, a first side wall surface 51S located outside the second side wall surface 61S in plan view from a direction perpendicular to the first main surface 1, and a lower surface 52 of the first passivation layer 50. A portion is formed so as to contact the upper surface 32 of the electrode 30 .
  • a plating layer 40 is formed.
  • a plating solution is used to form a Ni plating layer 41, a Pd plating layer 42 and an Au plating layer 43 in this order.
  • the Ni plating layer 41 is formed such that a portion of the Ni plating layer 41 extends between the electrode 30 and the second passivation layer 60 in the direction perpendicular to the first main surface 1 .
  • the semiconductor device 100 according to the embodiment can be manufactured.
  • the second side wall surface 61S of the second opening 61 is inside the first side wall surface 51S of the first opening 51 . Therefore, when the plating layer 40 is formed on the surface of the electrode 30 , part of the plating layer 40 , for example, part of the Ni plating layer 41 , is perpendicular to the first main surface 1 , so that the electrode 30 and the second It comes to be positioned between the passivation layer 60 . Therefore, when a wire is bonded to the plating layer 40 , even if an external force is applied to the plating layer 40 in a direction away from the first main surface 1 , the plating layer 40 does not move from the second passivation layer 60 to the first main surface 1 . A force acts in a direction. Therefore, peeling of the plating layer 40 can be suppressed.
  • the silicon nitride layer in the first passivation layer 50 By including the silicon nitride layer in the first passivation layer 50, excellent resistance to moisture can be obtained.
  • the second passivation layer 60 includes a polyimide layer, the surface can be provided with appropriate hardness. Further, since the substrate 10 is a silicon carbide substrate, excellent breakdown voltage can be obtained.
  • the maximum value of the distance L1 between the first side wall surface 51S and the second side wall surface 61S in the direction parallel to the first main surface 1 is , preferably 1 ⁇ m or more and 5 ⁇ m or less. If the maximum value of the distance L1 is less than 1 ⁇ m, the portion of the second passivation layer 60 that applies the force toward the first main surface 1 to the plated layer 40 becomes too small, making it difficult to suppress the peeling of the plated layer 40 .
  • the maximum value of the distance L1 exceeds 5 ⁇ m, it becomes difficult to form the plated layer 40 between the second passivation layer 60 and the electrode 30, and there is a possibility that a gap may occur.
  • the maximum value of the distance L1 is more preferably 2 ⁇ m or more and 4 ⁇ m or less.
  • the thickness t1 of the first passivation layer is preferably 0.2 ⁇ m or more and 1.0 ⁇ m or less. If the thickness t1 is less than 0.2 ⁇ m, the resistance to moisture may deteriorate. If the thickness t1 exceeds 1.0 ⁇ m, a large stress may act on the substrate 10 from the first passivation layer 50 . On the other hand, the thickness t1 is more preferably 0.3 ⁇ m or more and 0.9 ⁇ m or less, and still more preferably 0.4 ⁇ m or more and 0.8 ⁇ m or less.
  • the shape of the first opening 51 and the second opening 61 in plan view from the direction perpendicular to the first main surface 1 may be a rectangle with rounded corners.
  • the minimum radius of curvature of each of the four corners of the first opening 51 is preferably 10 ⁇ m or more and 100 ⁇ m or less. If the minimum radius of curvature is less than 10 ⁇ m, stress tends to concentrate on corners, and cracks may occur in the first passivation layer 50 . On the other hand, if the minimum radius of curvature exceeds 100 ⁇ m, the portion of the electrode 30 covered with the first passivation layer 50 may become excessive.
  • This minimum radius of curvature is more preferably 20 ⁇ m or more and 90 ⁇ m or less, and still more preferably 30 ⁇ m or more and 80 ⁇ m or less.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
PCT/JP2022/033369 2021-10-21 2022-09-06 半導体装置 Ceased WO2023067926A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2023555000A JPWO2023067926A1 (https=) 2021-10-21 2022-09-06
US18/293,919 US20240347408A1 (en) 2021-10-21 2022-09-06 Semiconductor device
CN202280057520.9A CN117836906A (zh) 2021-10-21 2022-09-06 半导体器件
DE112022005058.6T DE112022005058T5 (de) 2021-10-21 2022-09-06 Halbleitervorrichtung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-172674 2021-10-21
JP2021172674 2021-10-21

Publications (1)

Publication Number Publication Date
WO2023067926A1 true WO2023067926A1 (ja) 2023-04-27

Family

ID=86058991

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/033369 Ceased WO2023067926A1 (ja) 2021-10-21 2022-09-06 半導体装置

Country Status (5)

Country Link
US (1) US20240347408A1 (https=)
JP (1) JPWO2023067926A1 (https=)
CN (1) CN117836906A (https=)
DE (1) DE112022005058T5 (https=)
WO (1) WO2023067926A1 (https=)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016086069A (ja) * 2014-10-24 2016-05-19 三菱電機株式会社 半導体素子および半導体装置
JP2018137348A (ja) * 2017-02-22 2018-08-30 サンケン電気株式会社 半導体装置
JP2019201160A (ja) * 2018-05-18 2019-11-21 株式会社デンソー 半導体装置
WO2021065722A1 (ja) * 2019-09-30 2021-04-08 ローム株式会社 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619639U (https=) 1979-07-23 1981-02-20
JP2770390B2 (ja) 1989-03-24 1998-07-02 日本電気株式会社 半導体装置
JPH0396243A (ja) 1989-09-08 1991-04-22 Seiko Epson Corp 半導体集積回路装置
JP2021172674A (ja) 2020-04-17 2021-11-01 住友化学株式会社 ゴム組成物、ゴム組成物を製造する方法、及び防振材

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016086069A (ja) * 2014-10-24 2016-05-19 三菱電機株式会社 半導体素子および半導体装置
JP2018137348A (ja) * 2017-02-22 2018-08-30 サンケン電気株式会社 半導体装置
JP2019201160A (ja) * 2018-05-18 2019-11-21 株式会社デンソー 半導体装置
WO2021065722A1 (ja) * 2019-09-30 2021-04-08 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
CN117836906A (zh) 2024-04-05
DE112022005058T5 (de) 2024-08-01
JPWO2023067926A1 (https=) 2023-04-27
US20240347408A1 (en) 2024-10-17

Similar Documents

Publication Publication Date Title
CN102473599B (zh) 半导体芯片及其制造方法
US12471339B2 (en) SiC semiconductor device
CN110574154B (zh) 电容器及其制造方法
JP4435864B2 (ja) 半導体素子
US20120187544A1 (en) Semiconductor apparatus having penetration electrode and method for manufacturing the same
US20240274481A1 (en) Semiconductor device
CN111584364A (zh) 半导体装置的制造方法及半导体装置
WO2023067926A1 (ja) 半導体装置
US20240297088A1 (en) Semiconductor device
US20240290673A1 (en) Semiconductor device
WO2023067925A1 (ja) 半導体装置及び半導体装置の製造方法
EP4044254A2 (en) Semiconductor device and semiconductor package
JP2022186426A (ja) 半導体装置およびその製造方法
JP2023031665A (ja) 半導体装置及びウェハ
US20240290679A1 (en) Semiconductor device
US20240282657A1 (en) Semiconductor device
US20240282738A1 (en) Semiconductor device
JP2008204972A (ja) 半導体装置及びその製造方法
US20260013201A1 (en) Semiconductor device and semiconductor device production method
US20240282749A1 (en) Semiconductor device
JP3872031B2 (ja) 半導体装置の製造方法
US20240282836A1 (en) Semiconductor device
US20240282682A1 (en) Semiconductor package
JP5439727B2 (ja) 半導体装置
WO2023243470A1 (ja) ウエハ構造および半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22883237

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2023555000

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 202280057520.9

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 112022005058

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22883237

Country of ref document: EP

Kind code of ref document: A1