WO2023062883A1 - 炭化珪素半導体装置 - Google Patents

炭化珪素半導体装置 Download PDF

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Publication number
WO2023062883A1
WO2023062883A1 PCT/JP2022/025185 JP2022025185W WO2023062883A1 WO 2023062883 A1 WO2023062883 A1 WO 2023062883A1 JP 2022025185 W JP2022025185 W JP 2022025185W WO 2023062883 A1 WO2023062883 A1 WO 2023062883A1
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Prior art keywords
edge
region
silicon carbide
film
gate
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PCT/JP2022/025185
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English (en)
French (fr)
Japanese (ja)
Inventor
光亮 内田
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to US18/681,214 priority Critical patent/US20240313058A1/en
Priority to DE112022004888.3T priority patent/DE112022004888T5/de
Priority to CN202280058963.XA priority patent/CN117882200A/zh
Priority to JP2023554257A priority patent/JPWO2023062883A1/ja
Publication of WO2023062883A1 publication Critical patent/WO2023062883A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies

Definitions

  • the present disclosure relates to silicon carbide semiconductor devices.
  • a silicon carbide semiconductor device in which a metal plate is connected to a source pad of a semiconductor chip using solder has been proposed as a silicon carbide semiconductor device used in a power module.
  • a gate pad is provided in the vicinity of the source pad, a passivation film is provided to prevent solder provided on the source pad from reaching the gate pad when melted.
  • a silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface, a gate pad and a source pad formed on the first main surface, and formed on the gate pad and the source pad. and a second passivation film formed on the first passivation film, the first passivation film being a first insulation between the gate pad and the source pad.
  • first edge is outside said third edge and said second edge is outside said fourth edge.
  • FIG. 1 is a top view showing a silicon carbide semiconductor device according to an embodiment.
  • FIG. 2 is a cross-sectional view (Part 1) showing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 3 is a cross-sectional view (Part 2) showing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 4 is a cross-sectional view showing the configuration of a unit cell.
  • FIG. 5 is a top view showing a silicon carbide semiconductor device according to a modification of the embodiment.
  • FIG. 6 is a cross-sectional view showing a silicon carbide semiconductor device according to a modification of the embodiment.
  • An object of the present disclosure is to provide a silicon carbide semiconductor device capable of suppressing migration of a source pad due to heat generation.
  • a plane including the X1-X2 direction and the Y1-Y2 direction is referred to as the XY plane
  • a plane including the Y1-Y2 direction and the Z1-Z2 direction is referred to as the YZ plane
  • a plane including the Z1-Z2 direction and the X1-X2 direction. is described as the ZX plane.
  • the Z1-Z2 direction is the vertical direction
  • the Z1 side is the upper side
  • the Z2 side is the lower side.
  • the term "planar view” refers to viewing the object from the Z1 side
  • the term "planar shape” refers to the shape of the object viewed from the Z1 side.
  • a silicon carbide semiconductor device includes a silicon carbide substrate including a first main surface, a gate pad and a source pad formed on the first main surface, the gate pad and a first passivation film formed on the source pad; and a second passivation film formed on the first passivation film, wherein the first passivation film comprises the gate pad and the source pad. a first opening exposing the gate pad and having a first edge; and a second opening exposing the source pad and having a second edge. and a first plated film formed on the gate pad inside the first opening, and a second plated film formed on the source pad inside the second opening.
  • the second passivation film is also formed on the first plating film and the second plating film, and the second passivation film comprises a second insulation isolation portion covering the first insulation isolation portion; a third opening exposing the first plating film and having a third edge; and a fourth opening exposing the second plating film and having a fourth edge; The first edge is outside the third edge and the second edge is outside the fourth edge when viewed in plan from a vertical direction.
  • the first edge is outside the third edge and the second edge is outside the fourth edge when viewed in plan from the direction perpendicular to the first main surface. Therefore, even if the first plated film and the second plated film are formed widely in a plane parallel to the first main surface, when the metal plate is connected to the source pad using solder, the melted solder will not reach the gate. The pad 110 is difficult to reach. Therefore, conduction between the source pad and the gate pad through solder can be suppressed. Therefore, heat can be easily released from the silicon carbide substrate in the direction in which the first main surface is located through the first plating film and the second plating film, and migration of the source pad due to heat generation can be suppressed.
  • a first distance between the first end of the source pad closest to the gate pad and the second edge when viewed from above in a direction perpendicular to the first main surface may be 80% or less of the second distance between the first end and the fourth edge. In this case, it is easy to form the second plating film widely, and it is easy to suppress migration of the source pad due to heat generation.
  • the first distance may be 60% or less of the second distance. In this case, it is easier to suppress migration of the source pad due to heat generation.
  • the first distance may be 40% or less of the second distance. In this case, it is easier to suppress migration of the source pad due to heat generation.
  • the first end of the source pad closest to the gate pad and the second edge when viewed from above in a direction perpendicular to the first main surface may be 30 ⁇ m or less. In this case, it is easy to form the second plating film widely, and it is easy to suppress migration of the source pad due to heat generation.
  • the silicon carbide substrate has an active region including a plurality of unit cells, and a termination region provided around the active region;
  • the second edge may be separated from the plurality of unit cells when viewed in plan from a direction perpendicular to one main surface.
  • the heat generated in each unit cell is easily transferred to the source pad, the heat is less likely to remain inside the silicon carbide semiconductor device, and migration of the source pad due to heat generation is easily suppressed.
  • the silicon carbide substrate has an active region including a plurality of unit cells, and a termination region provided around the active region, and the termination A region may be covered by both the first passivation film and the second passivation film. In this case, excellent moisture resistance is obtained in the termination region and good reliability is obtained.
  • the first passivation film may be an inorganic film
  • the second passivation film may be an organic film. In this case, good moisture resistance due to the first passivation film and good flexibility due to the second passivation film are obtained.
  • FIG. 1 is a top view showing a silicon carbide semiconductor device according to an embodiment.
  • 2 and 3 are cross-sectional views showing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG.
  • FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG.
  • FIG. 4 is a cross-sectional view showing the configuration of a unit cell.
  • silicon carbide semiconductor device 100 includes silicon carbide substrate 10, gate insulating film 81, gate electrode 82, source electrode 60, drain electrode 70, It mainly has an interlayer insulating film 20 , a first passivation film 210 , a second passivation film 220 , a gate pad 110 , a first plating film 112 , a source pad 120 and a second plating film 122 . .
  • Silicon carbide substrate 10 includes silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 on silicon carbide single crystal substrate 50 .
  • Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 .
  • Silicon carbide epitaxial layer 40 forms first main surface 1
  • silicon carbide single-crystal substrate 50 forms second main surface 2 .
  • Silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 are made of hexagonal silicon carbide of polytype 4H, for example.
  • Silicon carbide single-crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type conductivity (first conductivity type).
  • a semiconductor element is formed on silicon carbide substrate 10 .
  • the first main surface 1 is a plane in which the ⁇ 0001 ⁇ plane or the ⁇ 0001 ⁇ plane is inclined in the off direction by an off angle of 8° or less.
  • the first main surface 1 is the (000-1) plane or a plane in which the (000-1) plane is inclined in the off direction by an off angle of 8° or less.
  • the off direction may be, for example, the ⁇ 11-20> direction or the ⁇ 1-100> direction.
  • the off angle may be, for example, 1° or more, or may be 2° or more.
  • the off angle may be 6° or less, or may be 4° or less.
  • Silicon carbide semiconductor device 100 has an active region 6 and a termination region 7 provided around active region 6 when viewed in plan from a direction perpendicular to first main surface 1 .
  • the active region 6 is a region in which a plurality of unit cells 8 are arranged.
  • the unit cells 8 are arranged in the Y1-Y2 direction with the X1-X2 direction as the longitudinal direction. The dimensions in the Y1-Y2 direction of each unit cell 8 are common.
  • Each unit cell 8 has a pair of gate trenches 5 and gate electrodes 82 .
  • the unit cells 8 are arranged at a constant pitch in the Y1-Y2 direction.
  • Silicon carbide epitaxial layer 40 includes drift region 11, body region 12, source region 13, first embedded region 15A, second embedded region 15B, first contact region 16A, and second contact region 16B. , a buried junction termination extension (JTE) region 17 and a surface JTE region 18 .
  • JTE buried junction termination extension
  • a body region 12 , a source region 13 , a first buried region 15A and a first contact region 16A are provided within the active region 6 .
  • a buried JTE region 17 and a surface JTE region 18 are provided within the termination region 7 .
  • Drift region 11 is provided over active region 6 and termination region 7 .
  • the second buried region 15B and the second contact region 16B are provided over a portion of the active region 6 and a portion of the termination region 7, respectively.
  • the drift region 11 contains n-type impurities such as nitrogen or phosphorus (P), and has n-type conductivity.
  • the doping of the n-type impurity to the drift region 11 is preferably performed by doping the impurity during the epitaxial growth of the drift region 11, not by ion implantation.
  • the body region 12 is provided on the drift region 11.
  • Body region 12 contains a p-type impurity such as aluminum (Al) and has p-type conductivity (second conductivity type).
  • the source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12 .
  • the source region 13 contains an n-type impurity such as nitrogen or phosphorus and has an n-type conductivity.
  • Source region 13 constitutes first main surface 1 .
  • the first contact region 16A contains p-type impurities such as aluminum and has p-type conductivity.
  • First contact region 16A constitutes first main surface 1 .
  • the first contact region 16A penetrates through the source region 13 and contacts the body region 12 .
  • a plurality of gate trenches 5 are provided in the first main surface 1 .
  • the gate trenches 5 extend in the X1-X2 direction, and a plurality of gate trenches 5 are arranged in the Y1-Y2 direction.
  • Gate trench 5 has a bottom surface 4 consisting of a drift region 11 .
  • Gate trench 5 has a side surface 3 extending through source region 13 and body region 12 to bottom surface 4 .
  • the bottom surface 4 is, for example, a plane parallel to the second main surface 2 .
  • the angle of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 50° or more and 65° or less. This angle may be, for example, 55° or more. This angle may be, for example, 60° or less.
  • Side 3 preferably has a ⁇ 0-33-8 ⁇ plane.
  • the ⁇ 0-33-8 ⁇ plane is a crystal plane that provides excellent mobility.
  • the angle of the side surface 3 with respect to the plane containing the bottom surface 4 may be 90°
  • the first buried region 15A contains p-type impurities such as aluminum and has p-type conductivity.
  • the first embedded region 15A is located closer to the second main surface 2 (Z2 side) than the first contact region 16A.
  • the first contact region 16A is located closer to the first main surface 1 (Z1 side) than the first buried region 15A.
  • the first embedded region 15A is in contact with the first contact region 16A.
  • the first buried region 15A is formed at a position deeper than the gate trench 5. As shown in FIG.
  • the upper end surface of the first embedded region 15A is located closer to the second main surface 2 than the bottom surface 4 of the gate trench 5 (Z2 side).
  • the second contact region 16B contains p-type impurities such as aluminum and has p-type. Second contact region 16B constitutes first main surface 1 .
  • the second contact region 16B is formed in an annular shape in plan view.
  • the second contact region 16B is formed from the edge of the active region 6 to the termination region 7. As shown in FIG.
  • the depth of the second contact region 16B may be equal to the depth of the first contact region 16A.
  • the second buried region 15B contains p-type impurities such as aluminum and has p-type conductivity.
  • the second embedded region 15B is formed in an annular shape in plan view.
  • the second buried region 15B is located closer to the second main surface 2 (Z2 side) than the second contact region 16B.
  • the second contact region 16B is located closer to the first main surface 1 (Z1 side) than the second embedded region 15B.
  • the second buried region 15B is in contact with the second contact region 16B.
  • the second buried region 15B is formed at a position deeper than the gate trench 5. As shown in FIG.
  • the upper end surface of the second embedded region 15B is located closer to the second main surface 2 than the bottom surface 4 of the gate trench 5 (Z2 side).
  • the depth of the second embedded region 15B may be equal to the depth of the first embedded region 15A.
  • the embedded JTE region 17 is in contact with the second embedded region 15B in a direction parallel to the first main surface 1.
  • Embedded JTE region 17 is formed in an annular shape in plan view.
  • Embedded JTE region 17 contains p-type impurities such as aluminum and has p-type conductivity.
  • the embedded JTE region 17 is separated from the first major surface 1 and the second major surface 2 . A portion of the upper end surface of embedded JTE region 17 is in contact with the lower end surface of second contact region 16B.
  • the surface JTE region 18 is in contact with the second contact region 16B in a direction parallel to the first main surface 1.
  • the surface JTE region 18 is formed in an annular shape in plan view.
  • the surface JTE region 18 contains p-type impurities such as aluminum and has p-type conductivity.
  • Surface JTE region 18 is provided above buried JTE region 17 .
  • Surface JTE region 18 is spaced from buried JTE region 17 .
  • Surface JTE region 18 is located closer to first main surface 1 than buried JTE region 17 (Z1 side).
  • Embedded JTE region 17 is located closer to second main surface 2 than surface JTE region 18 (Z2 side).
  • Surface JTE region 18 constitutes first main surface 1 .
  • a portion of drift region 11 is between surface JTE region 18 and buried JTE region 17 .
  • the concentration of p-type impurities in the surface JTE region 18 is lower than the concentration of p-type impurities in the second contact region 16B.
  • a gate insulating film 81 is provided in contact with the side surface 3 and the bottom surface 4 .
  • the gate insulating film 81 is, for example, an oxide film.
  • the gate insulating film 81 is made of a material containing silicon dioxide, for example.
  • Gate insulating film 81 is in contact with drift region 11 at bottom surface 4 .
  • Gate insulating film 81 is in contact with each of source region 13 , body region 12 and drift region 11 at side surface 3 .
  • Gate insulating film 81 may be in contact with source region 13 on first main surface 1 .
  • a gate electrode 82 is provided on the gate insulating film 81 .
  • the gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. Gate electrode 82 is arranged inside gate trench 5 .
  • a gate insulating film 81 is also provided on the second contact region 16B in a region within the active region 6 and outside the region in which the plurality of unit cells 8 are provided.
  • a gate contact portion 113 is provided on the gate insulating film 81 in this region. Gate contact portion 113 is a portion of gate electrode 82 .
  • An interlayer insulating film 20 is provided in contact with the gate electrode 82 and the gate insulating film 81 .
  • the interlayer insulating film 20 is made of a material containing silicon dioxide, for example.
  • a first contact hole 21 for a gate is formed in the interlayer insulating film 20 .
  • Gate contact portion 113 is exposed from interlayer insulating film 20 through first contact hole 21 .
  • Second contact holes 22 for the source are formed in the interlayer insulating film 20 and the gate insulating film 81 at regular intervals in the Y1-Y2 direction.
  • the second contact hole 22 is formed within a region in which the plurality of unit cells 8 are provided.
  • the second contact holes 22 are provided such that the gate trenches 5 are positioned between the second contact holes 22 adjacent in the Y1-Y2 direction.
  • the second contact hole 22 extends in the X1-X2 direction.
  • the source region 13 and the first contact region 16A are exposed from the interlayer insulating film 20 and the gate insulating film 81 through the second contact hole 22 .
  • the source electrode 60 is provided inside the second contact hole 22 and is in contact with the first main surface 1 .
  • the source electrode 60 is in contact with the source region 13 and the first contact region 16A on the first main surface 1 .
  • the source electrode 60 is made of a material containing nickel silicide (NiSi), for example.
  • Source electrode 60 may be made of a material containing titanium (Ti), aluminum, and silicon.
  • the source electrode 60 is in ohmic contact with the source region 13 and the first contact region 16A. That is, source electrode 60 is connected to silicon carbide substrate 10 through second contact hole 22 .
  • the gate pad 110 is provided on the interlayer insulating film 20 and is in contact with the gate contact portion 113 through the first contact hole 21 .
  • Gate pad 110 is made of a material including, for example, aluminum, an aluminum alloy, copper (Cu), or a copper alloy.
  • Gate pad 110 may be composed of materials including aluminum and copper.
  • a barrier metal film such as a titanium nitride (TiN) film may be provided between gate pad 110 and interlayer insulating film 20 .
  • Gate pad 110 is electrically connected to all gate electrodes 82 via gate contact portion 113 .
  • the source pad 120 is provided on the interlayer insulating film 20 and is in contact with the source region 13 and the first contact region 16A on the first main surface 1 through the second contact hole 22 .
  • Source pad 120 is made of a material including, for example, aluminum, an aluminum alloy, copper, or a copper alloy.
  • Source pad 120 is electrically insulated from gate electrode 82 by interlayer insulating film 20 .
  • Source pad 120 may be composed of materials including aluminum and copper.
  • a barrier metal film such as a titanium nitride (TiN) film may be provided between the source pad 120 and the interlayer insulating film 20 .
  • the surface of the source pad 120 may have unevenness reflecting the second contact hole 22 .
  • a first passivation film 210 is formed on the gate pad 110 and the source pad 120 .
  • the first passivation film 210 is, for example, an inorganic film such as a silicon nitride film.
  • the first passivation layer 210 has a first isolation portion 211 between the gate pad 110 and the source pad 120 .
  • the first passivation layer 210 has a first opening 212 exposing the gate pad 110 and a second opening 213 exposing the source pad 120 .
  • the first opening 212 has a first edge 214 and the second opening 213 has a second edge 215 .
  • the shape of the first opening 212 and the second opening 213 is rectangular when viewed from the direction perpendicular to the first main surface 1 .
  • the first plated film 112 is formed on the gate pad 110 inside the first opening 212 .
  • the first plated film 112 includes, for example, a nickel (Ni) plated film, a palladium (Pd) plated film, and a gold (Au) plated film.
  • a Ni plating film is formed on the gate pad 110 and contains phosphorus (P).
  • the Pd plating film is formed on the Ni plating film.
  • the Au plating film is formed on the Pd plating film.
  • the second plated film 122 is formed on the source pad 120 inside the second opening 213 .
  • the second plated film 122 has, for example, a nickel plated film, a palladium plated film, and a gold plated film.
  • a Ni plating film is formed on the source pad 120 and contains phosphorus.
  • the Pd plating film is formed on the Ni plating film.
  • the Au plating film is formed on the Pd plating film.
  • the second passivation film 220 is formed on the first passivation film 210 , the first plating film 112 and the second plating film 122 .
  • the second passivation film 220 is, for example, an organic film such as a polyimide film.
  • the second passivation film 220 has a second isolation portion 221 covering the first isolation portion 211 .
  • the second passivation film 220 has a third opening 222 exposing the first plating film 112 and a fourth opening 223 exposing the second plating film 122 .
  • the third opening 222 has a third edge 224 and the fourth opening 223 has a fourth edge 225 .
  • the shapes of the third opening 222 and the fourth opening 223 are rectangular when viewed from the direction perpendicular to the first main surface 1 .
  • the first edge 214 is outside the third edge 224 and the second edge 215 is outside the fourth edge 225 when viewed in plan from the direction perpendicular to the first main surface 1 .
  • the termination region 7 is covered with both the first passivation film 210 and the second passivation film 220 .
  • First passivation film 210 is formed to expose the peripheral edge of first main surface 1 .
  • the second passivation film 220 covers the first passivation film 210 from above and from the sides, and is in contact with the first main surface 1 outside the first passivation film 210 .
  • first edge 214 of first opening 212 extends outside third edge 224 of third opening 222 when viewed from above in a direction perpendicular to first main surface 1 .
  • the second edge 215 of the second opening 213 is outside the fourth edge 225 of the fourth opening 223 . Therefore, even if the first plated film 112 and the second plated film 122 are formed widely in a plane parallel to the first main surface 1 (in the XY plane), the metal plate is connected to the source pad 120 using solder. It is difficult for the molten solder to reach the gate pad 110 when the solder is applied. Therefore, conduction between the source pad 120 and the gate pad 110 via solder can be suppressed.
  • a bonding wire may be connected to the source pad 120 .
  • the termination region 7 since the termination region 7 is covered with both the first passivation film 210 and the second passivation film 220, the termination region 7 has excellent moisture resistance and good reliability.
  • the second passivation film 220 covers the first passivation film 210 from above and from the sides and is in contact with the first main surface 1 outside the first passivation film 210, it is possible to prevent moisture from entering from the sides. good resistance is obtained.
  • the first passivation film 210 is an inorganic film and the second passivation film 220 is an organic film, good moisture resistance due to the first passivation film 210 and good flexibility due to the second passivation film 220 can be obtained. be done.
  • the first distance L1 between the first end portion 121 of the source pad 120 closest to the gate pad 110 and the second edge 215 is the first distance L1. It is preferably 80% or less of the second distance L2 between the end 121 and the fourth edge 225. This is because the second plated film 122 is easily formed widely, and migration of the source pad 120 due to heat generation is easily suppressed.
  • the first distance L1 is more preferably 60% or less of the second distance L2, and even more preferably 40% or less of the second distance L2.
  • the side surface of the source pad 120 near the gate pad 110 , the inner wall surface of the second opening 213 and the inner wall surface of the fourth opening 223 may be perpendicular to the first main surface 1 or not perpendicular to the first main surface 1 .
  • the first end 121 in the plan view is the side surface of the source pad 120 close to the gate pad 110 .
  • the second edge 215 in plan view refers to the portion of the inner wall surface of the second opening 213 farthest from the gate pad 110.
  • the fourth edge 225 in plan view refers to the portion of the inner wall surface of the fourth opening 223 farthest from the gate pad 110. It is assumed that
  • the first distance L1 is preferably 30 ⁇ m or less. This is because the second plated film 122 is easily formed widely, and migration of the source pad 120 due to heat generation is easily suppressed.
  • the first distance L1 is more preferably 25 ⁇ m or less, and even more preferably 20 ⁇ m or less.
  • the second edge 215 is separated from all the unit cells 8 when viewed in plan from the direction perpendicular to the first main surface 1 .
  • the first passivation film 210 does not overlap the unit cell 8 when viewed from the direction perpendicular to the first main surface 1 . This is because the heat generated in each unit cell 8 is easily transferred to source pad 120 , heat is less likely to stay inside silicon carbide semiconductor device 100 , and migration of source pad 120 due to heat generation is easily suppressed.
  • FIG. 5 is a top view showing a silicon carbide semiconductor device according to a modification of the embodiment.
  • FIG. 6 is a cross-sectional view showing a silicon carbide semiconductor device according to a modification of the embodiment.
  • FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIG.
  • silicon carbide semiconductor device 100A has three gate runners 110A connected to gate pad 110 .
  • Gate runners 110A each have a portion extending in the Y1-Y2 direction.
  • a source pad 120 is provided between two gate runners 110A adjacent in the X1-X2 direction.
  • third contact holes 21A for the gate runners 110A are formed in the interlayer insulating film 20, in addition to the first contact holes 21, third contact holes 21A for the gate runners 110A are formed. Gate contact portion 113 is exposed from interlayer insulating film 20 through third contact hole 21A.
  • the first passivation film 210 has a third isolation portion 211A between the gate runner 110A and the source pad 120 in addition to the first isolation portion 211 .
  • the first passivation film 210 has, in addition to the first opening 212 and the second opening 213, a fifth opening 212A exposing the gate runner 110A.
  • Silicon carbide semiconductor device 100A has third plated film 112A formed on gate runner 110A inside fifth opening 212A.
  • the third plated film 112A includes, for example, a nickel plated film, a palladium plated film, and a gold plated film.
  • a Ni plating film is formed on the gate runners 110A and contains phosphorus.
  • the Pd plating film is formed on the Ni plating film.
  • the Au plating film is formed on the Pd plating film.
  • the third plated film 112A is covered with a second passivation film 220. As shown in FIG.
  • the silicon carbide semiconductor device 100A according to the modification also provides the same effects as the first embodiment. Further, since heat is transmitted through third plated film 112A, uniformity of temperature inside silicon carbide semiconductor device 100A can be improved.

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PCT/JP2022/025185 2021-10-13 2022-06-23 炭化珪素半導体装置 Ceased WO2023062883A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US18/681,214 US20240313058A1 (en) 2021-10-13 2022-06-23 Silicon carbide semiconductor device
DE112022004888.3T DE112022004888T5 (de) 2021-10-13 2022-06-23 Siliziumkarbid-Halbleitervorrichtung
CN202280058963.XA CN117882200A (zh) 2021-10-13 2022-06-23 碳化硅半导体器件
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