WO2023060496A1 - Puce et son procédé de fabrication et dispositif électronique - Google Patents

Puce et son procédé de fabrication et dispositif électronique Download PDF

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Publication number
WO2023060496A1
WO2023060496A1 PCT/CN2021/123690 CN2021123690W WO2023060496A1 WO 2023060496 A1 WO2023060496 A1 WO 2023060496A1 CN 2021123690 W CN2021123690 W CN 2021123690W WO 2023060496 A1 WO2023060496 A1 WO 2023060496A1
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WO
WIPO (PCT)
Prior art keywords
chip
layer
wafer
hole
rewiring layer
Prior art date
Application number
PCT/CN2021/123690
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English (en)
Chinese (zh)
Inventor
张童龙
郑见涛
陶军磊
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180099653.8A priority Critical patent/CN117529807A/zh
Priority to PCT/CN2021/123690 priority patent/WO2023060496A1/fr
Publication of WO2023060496A1 publication Critical patent/WO2023060496A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device

Definitions

  • the present application relates to the field of chip technology, in particular to a chip, a manufacturing method thereof, and electronic equipment.
  • a heat sink is provided on the upper surface of the chip (also called a chip) to help the chip dissipate heat.
  • a connector (such as a slot, i.e. socket) is provided on the lower surface of the chip to form an electrical path, so as to realize the electrical connection between the chip and the PCB (printed circuit board, printed circuit board).
  • the cooling plate, chip, connector, and PCB can be mechanically connected by bolts. The use of this mechanical connection method will generate a certain pressure on the chip. Since the wafer in the chip is prone to cracks and damage, it will cause problems such as high risk of chip installation and low reliability.
  • Embodiments of the present application provide a chip, a manufacturing method thereof, and an electronic device, which can improve the mechanical strength and wiring capability of the chip.
  • the present application provides a chip, which includes a rewiring layer, a chip, a plastic packaging material, and a first through hole.
  • the chip is arranged on the rewiring layer; the plastic encapsulation material wraps the side of the chip and the bottom of the rewiring layer; the first through hole penetrates the chip, the rewiring layer, and the plastic encapsulation material at the bottom of the rewiring layer, and the inner wall of the first through hole covers Insulation Materials.
  • the interior of the first through hole is insulated from the wafer and the signal lines in the redistribution layer, so as to avoid problems such as short circuit of the chip passing through the first through hole.
  • the chip provided in the embodiment of the present application, on the one hand, by providing a rewiring layer in the chip, the chip can be electrically connected to the PCB through the rewiring layer, thereby reducing the wiring density inside the chip, reducing interconnection resistance and delay, etc. , thereby improving the interconnection capability of the chip.
  • the overall mechanical strength of the chip is improved, thereby reducing the risk of damage due to pressure when the chip is assembled with the heat sink and PCB. probability.
  • the inner wall of the first through hole is covered with a waterproof layer, and the insulating material is covered on the waterproof layer.
  • the waterproof layer includes a silicon nitride layer.
  • the waterproof layer further includes at least one metal layer, and the at least one metal layer covers the silicon nitride layer.
  • the insulating material forms a hollow insulating layer in the first through hole.
  • connecting devices such as bolts
  • connecting devices can be used to assemble and connect the chip with the heat sink and PCB through the hollow position in the first through hole, which can reduce the pressure on the chip during assembly to a greater extent, and further Reduce the chance of chip damage.
  • the first through hole is filled with an insulating material.
  • the connecting device can be used to directly extend into the insulating material to assemble and connect the chip with the heat sink and PCB.
  • the wafer is a complete wafer, that is, the chip is a wafer-level chip. Based on the large size of the chip, a large number of transistors and computing cores can be integrated, so that it has ultra-high computing power, ultra-high advantages such as memory.
  • the rewiring layer is connected to the chip through a non-conductive adhesive layer.
  • a non-conductive adhesive layer can be formed on the lower surface of the wafer first, and then the rewiring layer prepared on other carrier sheets can be transferred to the chip through the bonding effect of the non-conductive adhesive layer.
  • the rewiring layer is disposed on the surface of the wafer.
  • the rewiring layer can be formed directly on the lower surface of the wafer.
  • the embodiment of the present application also provides an electronic device, including a bolt, a heat dissipation plate, a chip, and a printed circuit board.
  • the chip is arranged on the printed circuit board, and the heat dissipation plate is arranged on the top of the chip.
  • the chip includes a rewiring layer, a chip and a plastic packaging material, the chip is arranged on the rewiring layer, the plastic packaging material wraps the side of the chip and the bottom of the rewiring layer; the chip also includes a first through hole, the first through hole penetrates the wafer, and the rewiring layer , and the plastic sealing material at the bottom of the rewiring layer; one end of the bolt is fixed on the heat sink, the other end of the bolt passes through the first through hole and is fixed on the printed circuit board, and the space between the bolt and the inner wall of the first through hole is filled with Insulation Materials.
  • the embodiment of the present application also provides a method for manufacturing a chip, including: setting a chip, and opening a first through hole through the chip; using a plastic sealing material to plastic seal the side of the chip, and filling the plastic sealing material into the first through hole; A rewiring layer is arranged on the bottom surface of the chip; and the bottom of the rewiring layer is plastic-sealed with a plastic sealing material.
  • the chip manufacturing method further includes: opening a second through hole in the molding material filled in the first through hole, and the second through hole penetrates the wafer, the rewiring layer, and the bottom of the rewiring layer plastic packaging material.
  • arranging the rewiring layer on the bottom surface of the wafer includes: making a rewiring layer on the bottom surface of the wafer.
  • arranging the rewiring layer on the bottom surface of the wafer includes: making a rewiring layer on a carrier, coating a non-conductive adhesive layer on the bottom surface of the wafer, transferring the rewiring layer on the carrier to a non-conductive adhesive surface of the knot.
  • FIG. 1 is a schematic diagram of an assembly structure of a chip provided in the related art of the present application
  • FIG. 2 is a schematic diagram of an assembly structure of a chip provided in an embodiment of the present application.
  • FIG. 3a is a schematic plan view of a chip provided in an embodiment of the present application.
  • Fig. 3b is the schematic cross-sectional structure diagram of Fig. 3a along OO' position
  • Fig. 3c is a schematic diagram of a chip provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a chip provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a chip provided by an embodiment of the present application.
  • FIG. 6 is a flow chart of a chip manufacturing method provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a chip in the manufacturing process provided by the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a chip in the manufacturing process provided by the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a chip in the manufacturing process provided by the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a chip in the manufacturing process provided by the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a chip in the manufacturing process provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a chip in the manufacturing process provided by the embodiment of the present application.
  • At least one (item) means one or more, and “multiple” means two or more.
  • “And/or” is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, “A and/or B” can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an “or” relationship.
  • At least one of the following” or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • An embodiment of the present application provides an electronic device, and the present application does not limit the application field of the electronic device.
  • the electronic device can be applied to artificial intelligence (artificial intelligence) fields, deep computing fields, and the like.
  • the embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.
  • the above-mentioned electronic devices may be electronic products such as mobile phones, computers, tablet computers, notebooks, vehicle-mounted computers, smart watches, and smart bracelets.
  • the electronic device may include a chip 100 , a heat sink 200 and a printed circuit board (PCB) 300 .
  • PCB printed circuit board
  • the heat dissipation plate 200 is disposed on the upper surface of the chip 100 , and the heat dissipation plate 200 and the upper surface of the chip 100 may be bonded by thermal interface material (TIM glue for short).
  • thermal interface material TIM glue for short.
  • At least one wafer is disposed in the chip 100 , and the chip may be a large-size chip, that is, a large-size wafer is used in the chip, such as a wafer larger than 150 mm ⁇ 150 mm.
  • the lower surface S2 of the chip 100 is electrically connected to the PCB 300.
  • the above-mentioned chip may be a wafer-level chip, that is, the chip in the chip is a complete wafer. It can be understood here that the chip uses a complete wafer (that is, a large-sized wafer), which can integrate a large number of transistors (such as more than 1.2 trillion transistors) and computing cores (such as more than 400,000 computing cores), so that It has the advantages of ultra-high computing power and ultra-high memory.
  • through holes can be set at the positions facing the chip 100, the cooling plate 200, and the PCB 300; that is, the chip 100, the cooling plate 200, PCB 300 are respectively provided with through holes (V2, V3, V4) at corresponding positions.
  • the chip 100, the cooling plate 200, and the PCB 300 can be fixedly connected through the through holes by using connectors.
  • the connector may include a bolt, one end of the bolt may be fixed on the heat dissipation plate 200, and the other end of the bolt passes through the chip 100 and the heat dissipation plate 200.
  • Through holes (V2, V3, V4) are fixed on the PCB 300 to fix the three together; and an insulating material can be filled between the bolts and the inner walls of the through holes (V2, V3, V4) to prevent the bolts from contacting the chip. Contact can cause damage to the chip.
  • the chip 100 provided by the embodiment of the present application itself has high mechanical strength, which can reduce the probability of chip damage due to pressure and improve reliability.
  • the specific configuration of the chip 100 provided in the embodiment of the present application will be described below.
  • Fig. 3a is a schematic plan view of a chip 100 provided by an embodiment of the present application
  • Fig. 3b is a schematic cross-sectional view along OO' in Fig. 3a.
  • the chip 100 provided by the embodiment of the present application includes a redistribution layer 1 (redistribution layer, RDL) and at least one chip 2 disposed on the redistribution layer 1 .
  • RDL redistribution layer
  • FIG. 3 b only one wafer 2 is provided in the chip 100 for schematic illustration. In other possible implementation manners, two or more wafers 1 may be stacked in the chip 100 .
  • the number of wiring layers in the rewiring layer 1 can be multiple layers or single layer, which is not limited in the present application, and can be set according to actual needs. It should be understood that the wafer 2 may include a wafer at the bottom and devices fabricated on the surface of the wafer.
  • the wafer 2 may be a complete wafer, that is, the chip 100 is a wafer-level chip.
  • film layers may or may not be provided between the above-mentioned rewiring layer 2 and the wafer 1 (that is, direct contact), which is not limited in the present application, and may be provided according to actual needs.
  • a non-conductive adhesive layer 4 (non-conductive film, NCF) may be provided between the rewiring layer 1 and the wafer 2 .
  • the non-conductive adhesive layer 4 can be made on the lower surface of the wafer 1 first, and then the rewiring layer 1 made on other carrier sheets can be transferred to the chip through the bonding effect of the non-conductive adhesive layer 4;
  • the rewiring layer 1 may be disposed on the lower surface of the wafer 2 .
  • the rewiring layer 1 can be directly fabricated on the lower surface of the wafer 2; for details, reference can be made to subsequent fabrication method embodiments, which will not be repeated here.
  • the sides of the chip 2 and the bottom of the rewiring layer 1 are all wrapped by a plastic encapsulation material a.
  • the chip 100 is also provided with a first through hole V1, the first through hole V1 runs through the wafer 2, the rewiring layer 1, and the molding material a at the bottom of the rewiring layer 1, and the inner wall of the first through hole V1 is covered with the insulating material b In this way, when the chip 100 is applied to an electronic device, it can be assembled and connected to the cooling plate 200 and the PCB 300 through bolts at the position of the first through hole V1.
  • the inside of the first through hole V1 is insulated from the signal lines in the wafer 2 and the rewiring layer 1 to avoid problems such as short circuit of the chip passing through the first through hole V1 .
  • the chip 2 can be electrically connected to the PCB 300 through the rewiring layer, thereby reducing the wiring density inside the chip and reducing the wiring density. Small interconnect resistance and delay, etc., thereby improving the interconnection capability of the chip.
  • the overall mechanical strength of the chip is improved, thereby reducing the pressure caused by the chip when it is assembled with the heat sink and PCB. chance of damage.
  • the present application does not limit the specific composition of the molding material a wrapped on the side of the above-mentioned chip 1, the plastic molding material a wrapped on the bottom of the rewiring layer 2, and the insulating material b covered on the inner wall of the first through hole V1, and the three can be the same , can also be different, and may need to be set in practice.
  • epoxy resin, polyimide (polyimide, PI) and the like can be used for both the molding material a and the insulating material b.
  • the wall of the wafer 1 located in the first through hole V1 can be covered with a waterproof layer,
  • the insulating material b is covered on the waterproof layer. That is to say, the wall of the first through hole V1 located at the wafer 1 can be coated with a waterproof layer first, and then the first through hole V1 is filled with the insulating material b.
  • the application does not limit the waterproof material used in the waterproof layer, such as silicon oxide (SiO 2 ), silicon nitride (SiN), titanium (Ti), nickel (Ni), etc.; the waterproof layer can be a single-layer structure, or It can be a multi-layer composite structure; in practice, it can be set according to needs.
  • the waterproof material used in the waterproof layer such as silicon oxide (SiO 2 ), silicon nitride (SiN), titanium (Ti), nickel (Ni), etc.
  • the waterproof layer can be a single-layer structure, or It can be a multi-layer composite structure; in practice, it can be set according to needs.
  • a silicon nitride layer with a dense structure can be used in the waterproof layer, so as to have a good blocking effect on water vapor.
  • the waterproof layer may use a metal layer that has certain adhesion and is not easily oxidized, such as a titanium (Ti) layer, a nickel (Ni) layer, and the like.
  • the waterproof layer may use a composite film layer of a silicon nitride layer and a metal layer.
  • the waterproof layer may use a titanium layer as a bottom layer, and a silicon nitride layer is provided on the surface of the titanium layer.
  • the inside of the first through hole V1 can be set to be filled with insulating material b; in this way, the chip 100 can be directly connected to the heat sink by using a connecting device to extend into the insulating material b.
  • Board 200, PCB 300 are assembled and connected.
  • the insulating material b can form a hollow insulating layer on the inner wall of the first through hole V1, that is, a through hole is formed in the middle of the first through hole V1 (that is, the first through hole V1 two through holes), so that the connecting device (such as a bolt) can assemble and connect the chip 100 with the cooling plate 200 and the PCB 300 through the through holes.
  • the connecting device such as a bolt
  • the insulating material b can cover the entire inner wall of the first through hole V1; as shown in Figure 4 and Figure 5, the insulating material b can also cover the first through hole Part of the inner wall of V1 ; for example, the insulating material b covers the inner wall of the first through hole V1 at the position of the wafer 2 .
  • the upper surface is a passive surface, and the passive surface is connected to the heat dissipation plate 200 as a heat dissipation channel to realize heat dissipation of the chip 100 .
  • the lower surface of the chip 100 is an active surface, through which the electrical connection with the PCB is realized.
  • the lower surface (ie, the active surface) of the chip 100 may be provided with bumps P (bumps), so as to realize the electrical connection between the chip 100 and the PCB through the bumps P.
  • the arrangement form of the bumps P involved in this application is not limited, and the arrangement can be selected according to needs.
  • the embodiment of the present application also provides a manufacturing method of the aforementioned chip, but the aforementioned chip manufacturing method is not limited thereto.
  • the embodiment of the present application provides a chip manufacturing method that may include:
  • Step 01 referring to FIG. 7 , setting a wafer 2 and opening a first through hole V1 through the wafer 2 .
  • the aforementioned wafer 2 may be a complete wafer.
  • FIG. 7 and the following are schematic illustrations of setting one wafer 2 as an example. In some possible embodiments, multiple wafers 2 may be stacked.
  • step 01 dry etching, wet etching or laser (laser) etching can be used to open holes on the wafer 2 to form the first Via V1.
  • sputtering physical vapor deposition, PVD
  • chemical vapor deposition chemical vapor deposition, CVD
  • Ti, Ni At least one of materials such as SiN to form a barrier layer (not shown in FIG. 7 ) on the wall of the first through hole V1 to prevent water vapor or other gases from entering the chip through the wall of the first through hole V1, resulting in The chip is damaged.
  • Step 02 plastic-encapsulates the side of the chip 2 with the molding material a, and fills the molding material a into the first through hole V1.
  • the molding material a can be molded by compression molding (compression mold) to the side surface and the upper surface S1 of the wafer 2, and the molding material a can be filled to the first through hole V1.
  • the plastic encapsulation material a may be an insulating material, such as epoxy resin, polyimide, etc., but is not limited thereto.
  • the mechanical strength of the chip 100 can be improved by using the molding material a to plastic-encapsulate the side of the chip 2 .
  • Step 03 as shown in (c) of FIG. 9 , arrange a rewiring layer 1 on the bottom of the wafer 2 (ie, the lower surface S2 ).
  • the rewiring layer 1 may be formed on other carriers first and then transferred to the bottom surface of the wafer 2 .
  • the rewiring layer 1 can be fabricated on a carrier (carrier) 20 .
  • the carrier sheet 20 may be a glass substrate or a metal substrate, which is not limited in this application.
  • a non-conductive bonding layer 3 may be coated on the lower surface S2 of the wafer 2 .
  • the redistribution layer 1 on the carrier sheet 20 is transferred to the surface of the non-conductive adhesive layer 2 .
  • the non-conductive adhesive layer 3 has a certain bonding effect on the rewiring layer 1 to ensure the separation of the rewiring layer 1 from the carrier sheet 20 .
  • the non-conductive adhesive layer 3 can protect the lower surface S2 of the wafer 2 to a certain extent.
  • the lower surface S2 of the wafer 2 may be provided with bumps P (bump).
  • the pads on the surface of the rewiring layer 1 can be bonded to the bumps on the lower surface S2 of the wafer 2 .
  • the carrier 20 can be separated from the rewiring layer 1 by laser, thermal or mechanical methods, so that the carrier 20 can be removed.
  • the bump P can be made of Cu (copper) material, and has solder (such as tin-silver alloy) at the end, so that it can be melted at a lower temperature.
  • solder such as tin-silver alloy
  • the solder at the end of the bump on the lower surface S2 of the wafer 2 melts, and can form a metal compound with the pad on the surface of the rewiring layer 1 .
  • Step 04 referring to FIG. 10 , use plastic sealing material a to plastic seal the bottom of the rewiring layer 2 .
  • the bottom of the rewiring layer 2 is plastic-sealed with the molding material a, which can improve the mechanical strength of the chip 100 .
  • the molding material used in step 04 may be the same as or different from the molding material used in step 02, which is not limited in this application, and can be set according to actual needs.
  • a grinding process can be used to grind and thin the molding material a located on the upper surface S1 of the wafer 2 to expose the upper surface S1 of the wafer 2 to form a heat dissipation path.
  • bumps P can be formed on the surface of the rewiring layer 1 first, And the bump P is exposed after the bottom of the rewiring layer 1 is plastic-sealed with the plastic packaging material a, so as to realize the electrical connection between the chip 100 and the PCB 300.
  • the chip 100 in order to reduce the probability of damage to the chip, as shown in FIG.
  • the chip 100 can be directly assembled and connected to the heat dissipation plate 200 and the PCB 300 through the second through hole.
  • dry etching, wet etching or laser (laser) etching can be used in step 05 to form a second Two through holes V2.
  • the side wall of the second through hole V2 retains the plastic encapsulation material a so as to protect the chip 2 and reduce the impact of the chip when it is assembled with the heat sink 200 and PCB300 through the second through hole V2. The risk of damage to the chip due to backlog and so on.
  • the manufacturing method of the above-mentioned chip is only schematically explained by taking the manufacturing process of the chip in Fig. 4 as an example.
  • the manufacturing process of the chip shown in Fig. 5 is similar to the aforementioned manufacturing method, and its main difference is: with reference to Fig.
  • the rewiring layer 1 can be fabricated directly on the lower surface S2 of the wafer 2 through step 03; other relevant fabrication processes can be combined with FIG.
  • the size of the sequence numbers of the above-mentioned processes does not mean the order of execution, and the execution order of each production process should be determined by its function and position, and should not be used in the embodiments of the present application.
  • the implementation process constitutes any limitation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente demande a trait au domaine technique des puces et concerne une puce et son procédé de fabrication ainsi qu'un dispositif électronique. La présente demande peut améliorer la résistance mécanique et la capacité de câblage de la puce. La puce comprend une couche de recâblage, une tranche, un matériau d'encapsulation en plastique et un premier trou traversant. La tranche est disposée sur la couche de recâblage. Le matériau d'encapsulation en plastique enveloppe les surfaces latérales de la tranche et le fond de la couche de recâblage. Le premier trou traversant traverse la tranche, la couche de recâblage et le matériau d'encapsulation en plastique au fond de la couche de recâblage, et la paroi interne du premier trou traversant est recouverte d'un matériau isolant.
PCT/CN2021/123690 2021-10-14 2021-10-14 Puce et son procédé de fabrication et dispositif électronique WO2023060496A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180099653.8A CN117529807A (zh) 2021-10-14 2021-10-14 芯片及其制作方法、电子设备
PCT/CN2021/123690 WO2023060496A1 (fr) 2021-10-14 2021-10-14 Puce et son procédé de fabrication et dispositif électronique

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Application Number Priority Date Filing Date Title
PCT/CN2021/123690 WO2023060496A1 (fr) 2021-10-14 2021-10-14 Puce et son procédé de fabrication et dispositif électronique

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WO2023060496A1 true WO2023060496A1 (fr) 2023-04-20

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140191A (zh) * 2015-09-17 2015-12-09 中芯长电半导体（江阴）有限公司 一种封装结构及再分布引线层的制作方法
CN110571201A (zh) * 2019-09-29 2019-12-13 广东佛智芯微电子技术研究有限公司 一种高散热扇出型三维异构双面塑封结构及其制备方法
TW202036812A (zh) * 2019-03-26 2020-10-01 新加坡商Ｐｅｐ創新有限公司 半導體裝置封裝方法及半導體裝置
DE102020128171A1 (de) * 2020-03-27 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package und Verfahren zu dessen Herstellung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140191A (zh) * 2015-09-17 2015-12-09 中芯长电半导体（江阴）有限公司 一种封装结构及再分布引线层的制作方法
TW202036812A (zh) * 2019-03-26 2020-10-01 新加坡商Ｐｅｐ創新有限公司 半導體裝置封裝方法及半導體裝置
CN110571201A (zh) * 2019-09-29 2019-12-13 广东佛智芯微电子技术研究有限公司 一种高散热扇出型三维异构双面塑封结构及其制备方法
DE102020128171A1 (de) * 2020-03-27 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package und Verfahren zu dessen Herstellung

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