WO2023056798A1 - 一种背栅调制器件及其制备方法、存储器、逻辑器件 - Google Patents

一种背栅调制器件及其制备方法、存储器、逻辑器件 Download PDF

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WO2023056798A1
WO2023056798A1 PCT/CN2022/115094 CN2022115094W WO2023056798A1 WO 2023056798 A1 WO2023056798 A1 WO 2023056798A1 CN 2022115094 W CN2022115094 W CN 2022115094W WO 2023056798 A1 WO2023056798 A1 WO 2023056798A1
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layer
single crystal
silicon substrate
crystal silicon
sidewall
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PCT/CN2022/115094
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English (en)
French (fr)
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张骥
叶甜春
罗军
李彬鸿
苏炳熏
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广东省大湾区集成电路与系统应用研究院
锐立平芯微电子(广州)有限责任公司
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Publication of WO2023056798A1 publication Critical patent/WO2023056798A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Definitions

  • the present invention relates to the technical field of semiconductor devices, and more specifically, the present invention can provide a back gate modulation device, a manufacturing method thereof, a memory, and a logic device.
  • SONOS Silicon-Oxide-Nitride-Oxide-Silicon
  • Silicon-Oxide-Nitride-Oxide-Silicon have the advantages of simple process, good compatibility, low power consumption, and strong scalability.
  • FDSOI Fully Depleted Silicon-On-Insulator (Silicon-On-Insulator) technology is combined with SONOS technology to prepare semiconductor devices with low power consumption and high performance.
  • one or more embodiments of the present invention provide a back gate modulation device and its preparation method, memory, and logic device.
  • the present invention provides a back gate modulation device, which may include but not limited to a silicon substrate, an ONO layer, a single crystal silicon layer, a gate, a first side wall, a second side wall wall, the first source and drain, and the second source and drain.
  • the ONO layer is filled in the cavity formed on the silicon substrate.
  • a single crystal silicon layer is formed on the ONO layer.
  • the gate is formed on the single crystal silicon layer.
  • the first sidewall surrounds the sidewall of the gate and is disposed on the single crystal silicon layer.
  • the second sidewall surrounds the sidewall of the first sidewall and is disposed on the single crystal silicon layer.
  • the first source and drain are arranged on the silicon substrate and are located at one side of the single crystal silicon layer.
  • the second source and drain are arranged on the silicon substrate and on the other side of the single crystal silicon layer.
  • the back gate modulation device also includes a shallow trench isolation structure.
  • the shallow trench isolation structure is formed in the silicon substrate. Both the first source and drain and the second source and drain are disposed in the silicon substrate region surrounded by the shallow trench isolation structure.
  • the ONO layer includes a tunnel oxide layer, a nitride layer, and a blocking oxide layer arranged in sequence; wherein, the blocking oxide layer is arranged on the silicon substrate.
  • first sidewall is a silicon nitride layer
  • second sidewall is a silicon oxide layer
  • the gate is composed of a floating gate structure.
  • the gate is composed of polysilicon and silicon oxynitride.
  • the present invention also provides a memory, which may include but not limited to the back gate modulation device described in the embodiments of the present invention.
  • the present invention provides a logic device, which includes the back gate modulation device described in the embodiment of the present invention.
  • the present invention can also provide a method for manufacturing a back gate modulation device, which may include but not limited to one or more of the following steps.
  • a silicon substrate is provided.
  • a shallow trench isolation structure is formed in the silicon substrate.
  • a sacrificial layer is epitaxially grown on the surface of the silicon substrate surrounded by the shallow trench isolation structure, and a single crystal silicon layer is formed on the sacrificial layer.
  • a gate is formed on the single crystal silicon layer, a first sidewall is formed on a sidewall of the gate, and a second sidewall is formed on a sidewall of the first sidewall.
  • the sacrificial layer is exposed by sequentially vertically etching the single crystal silicon layer and the sacrificial layer.
  • a cavity is formed by etching away the sacrificial layer, and the silicon substrate and the single crystal silicon layer are exposed.
  • An ONO layer is formed in the cavity between the silicon substrate and the single crystal silicon layer.
  • a first source and drain and a second source and drain are formed in the silicon substrate region surrounded by the shallow trench isolation structure.
  • forming an ONO layer in the cavity between the silicon substrate and the single crystal silicon layer includes:
  • a nitride layer is filled between the tunnel oxide layer and the blocking oxide layer.
  • the beneficial effects of the present invention are: compared with the prior art, the present invention can flexibly control the thickness of the monocrystalline silicon layer (top layer silicon) and the ONO structure through the thickness of the sacrificial layer (epitaxial SiGe) and the substrate (Si) according to actual needs , the flexibility of the device structure is high, so as to maximize the performance of the back gate modulation device.
  • the storage device manufactured based on the invention can effectively increase the storage window, realize multi-bit storage, and has the advantages of high service life and the like.
  • the logic device manufactured based on the invention can realize the equivalent effect of different back gate voltages, and has the advantages of low energy consumption and the like.
  • manufacturing the SON structure based on the single crystal silicon wafer in the present invention can greatly reduce the cost, for example, the cost can be reduced by about 80% compared with the SOI wafer.
  • FIG. 1 shows a schematic cross-sectional structure of a silicon substrate provided in one or more embodiments of the present invention.
  • FIG. 2 shows a schematic diagram of a shallow trench isolation (STI) structure fabricated on a silicon substrate in one or more embodiments of the present invention.
  • STI shallow trench isolation
  • Fig. 3 shows a schematic diagram of the device structure after forming a sacrificial layer and a single crystal silicon layer in one or more embodiments of the present invention.
  • FIG. 4 shows a schematic diagram of a device structure after forming gates and double sidewalls in one or more embodiments of the present invention.
  • FIG. 5 shows a schematic diagram of the device structure after vertical etching of the monocrystalline silicon layer and the sacrificial layer in one or more embodiments of the present invention.
  • FIG. 6 shows a schematic diagram of the device structure after etching away the sacrificial layer and forming a cavity in one or more embodiments of the present invention.
  • Fig. 7 shows a schematic diagram of the device structure after forming an ONO layer at the cavity position in one or more embodiments of the present invention.
  • FIG. 8 shows a schematic diagram of the device structure after forming the first source and drain and the second source and drain in one or more embodiments of the present invention.
  • a silicon substrate 100. A silicon substrate.
  • the first side wall (the black filled part in the figure).
  • the first source and drain 901.
  • a second source and drain 901.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on” another layer/element in one orientation, the layer/element can be located “below” the other layer/element when the orientation is reversed.
  • one or more embodiments of the present invention can provide a method for manufacturing a back gate modulation device, so as to manufacture the back gate modulation device provided by the present invention, and solve one or more problems existing in the prior art A number of questions are detailed below.
  • a silicon substrate 100 is provided based on the cleaned silicon substrate.
  • the embodiment of the present invention can use a silicon substrate 100 formed of a single crystal silicon wafer (specifically, a bulk silicon wafer) to fabricate a back gate modulation device, which can effectively reduce costs, for example, by about 80% compared with SOI wafers.
  • a shallow trench isolation structure (STI, Shallow Trench Isolation) 200 may be formed in a silicon substrate 100 . It should be understood that the specific process of the shallow trench isolation process can be selected according to specific conditions, and will not be repeated in this embodiment of the present invention.
  • a sacrificial layer 300 can be grown epitaxially (Epi, Epitaxy) on the surface of the silicon substrate 100 surrounded by the shallow trench isolation structure 200, and a single crystal silicon layer 400 can be formed on the sacrificial layer 300.
  • the sacrificial layer 300 in this embodiment is specifically a SiGe (silicon germanium) layer, that is, a layer of SiGe is epitaxially formed on the Si surface in this step, and the thickness of SiGe can be deduced according to the thickness of the subsequently formed ONO layer.
  • the thickness is the same; then a layer of single crystal silicon can be added on the outside, and the thickness of single crystal silicon considers the loss of RTO (Rapid Thermal Oxidation, rapid thermal oxidation) or HTO (High Temperature Oxidation, high temperature oxidation) in the subsequent steps.
  • RTO Rapid Thermal Oxidation, rapid thermal oxidation
  • HTO High Temperature Oxidation, high temperature oxidation
  • a gate 500 and double sidewall structures are formed on the single crystal silicon layer 400 .
  • the first sidewall 600 is formed on the sidewall of the gate 500 and the second sidewall 700 is formed on the sidewall of the first sidewall 600.
  • the first sidewall 600 is a silicon nitride layer.
  • the two sidewalls 700 are silicon oxide layers.
  • the gate 500 is composed of a floating gate structure (FloatingGate).
  • the gate 500 may be composed of polysilicon (Poly) and silicon oxynitride (SiON).
  • the present invention sequentially performs high temperature oxidation (HTO), SiN deposition, high temperature oxidation (HTO) and rapid thermal annealing (RTP, Rapid Thermal Processing) treatment, and then performs LDD (Lightly doped drain, lightly doped drain) Injection) treatment, and finally make silicon nitride sidewalls and silicon oxide sidewalls.
  • HTO high temperature oxidation
  • HTO high temperature oxidation
  • RTP Rapid Thermal annealing
  • LDD Lightly doped drain, lightly doped drain
  • Injection LDD
  • the sacrificial layer 300 is exposed by sequentially vertically etching the single crystal silicon layer 400 and the sacrificial layer 300 .
  • the source and drain regions are vertically etched to form corresponding grooves and expose the side surfaces of the sacrificial layer 300 (SiGe).
  • the vertical etching may adopt a dry etching method.
  • a cavity is formed by etching away the sacrificial layer 300 , and the silicon substrate 100 and the single crystal silicon layer 400 are exposed.
  • the process of etching the sacrificial layer 300 in the present invention may specifically adopt a wet etching method, that is, etch away the SiGe layer.
  • an ONO layer is formed in the cavity between the silicon substrate 100 and the single crystal silicon layer 400 .
  • the present invention provides a SON (Silicon On None, cavity-on-silicon technology) back-gate modulation device based on bulk silicon wafers, specifically because there is a SON during the preparation process.
  • the ONO (Oxide-Nitride-Oxide, Oxide-Nitride-Oxide) layer specifically includes a tunnel oxide layer 800, a nitride layer 801, and a blocking oxide layer 802.
  • the silicon substrate and the single crystal silicon layer 400 Forming the ONO layer in the cavity between them may include: growing a tunnel oxide layer 800 on the exposed surface of the single crystal silicon layer 400 and growing a blocking oxide layer 802 on the exposed surface of the silicon substrate 100, specifically by rapid thermal oxidation (RTO) or high temperature oxidation (HTO) method to grow oxide (Oxide) on the lower surface of the single crystal silicon layer 400 at the cavity and the upper surface of the silicon substrate 100; and between the tunnel oxide layer 800 and the blocking oxide layer 802 Nitride layer 801 is filled in between.
  • SiN is specifically deposited and filled to form an ONO layer, thereby completing the processing of the SONOS structure.
  • the source and drain electrodes are epitaxially grown on the silicon substrate 100 with external leakage.
  • one or more embodiments of the present invention can also provide a back gate modulation device, and the back gate modulation device in the present invention may specifically include but not limited to a silicon substrate 100 , shallow trench isolation structure 200, ONO layer, single crystal silicon layer 400, gate 500, first spacer 600, second spacer 700, first source and drain 900, second source and drain 901, etc.
  • the shallow trench isolation structure 200 is formed in a silicon substrate 100 which is a substrate formed based on a single crystal silicon (Si) wafer.
  • the shallow trench isolation structure 200 is an STI (Shallow Trench Isolation) structure, which can be formed of insulating materials, such as silicon oxide.
  • the ONO layer is filled and formed on the silicon substrate 100.
  • the ONO layer in the embodiment of the present invention includes a tunnel oxide layer 800, a nitride layer 801, and a blocking oxide layer 802 arranged in sequence; wherein, the blocking oxide layer 802 in the embodiment of the present invention It is arranged on the silicon substrate 100, the nitride layer 801 is arranged on the oxide layer 802, and the tunnel oxide layer 800 is arranged on the nitride layer 801 to form oxide (Oxide)-nitride (Nitride)-oxide (Oxide) )layer.
  • the single crystal silicon layer 400 is formed on the ONO layer, specifically disposed on the tunnel oxide layer 800 .
  • the silicon substrate 100, the ONO layer and the single crystal silicon layer 400 together form a SONOS structure.
  • the gate 500 is formed on the single crystal silicon layer 400 .
  • the gate 500 in some embodiments of the present invention is composed of a floating gate structure for storage devices; in this case, the floating gate structure is used as a positive gate, and the positive gate is connected to the word line, and the data "01" is stored by writing the word line and "00", and the SONOS structure of the present invention is used as the back gate, which is connected to the bit line, and then the data "11" and "10” are stored by writing the bit line.
  • Vt Shift offset voltage
  • this patent proposes double-bit How storage is written compared to conventional technology.
  • the gate 500 in other embodiments of the present invention is composed of polysilicon and silicon oxynitride, and the back gate modulation device of this structure can be used for logic devices.
  • the SONOS structure can be used as the back gate in this case, and the back gate is connected to the bit line, so as to write "1" or "0" or not write through the bit line.
  • the quantum well structure of the SONOS structure energy band provided by the embodiment of the present invention has a good storage effect, different back gate information can be written in a pulsed manner to achieve the equivalent effect of different back gate voltages (body bias)
  • the back gate is in the 0V state most of the time, and there is no need for a higher voltage input of about 2V, so as to avoid the problem of leakage to the substrate in all directions and the parasitic coupling effect that may be caused by continuous application of the back gate voltage.
  • this patent proposes a way to replace the conventional SOI back bias.
  • the first sidewall 600 surrounds the sidewall of the gate 500 and is disposed on the single crystal silicon layer 400 .
  • the first sidewall 600 is a silicon nitride layer.
  • the second sidewall 700 surrounds the sidewall of the first sidewall 600 and is disposed on the monocrystalline silicon layer 400; the second sidewall 700 is a silicon oxide layer.
  • the first source and drain 900 and the second source and drain 901 can be respectively disposed on both sides of the single crystal silicon layer 400 .
  • the first source and drain electrodes 900 are disposed on the silicon substrate 100 and located on one side of the single crystal silicon layer 400 .
  • the second source and drain 901 are disposed on the silicon substrate 100 and on the other side of the single crystal silicon layer 400 . It should be understood that the second source and drain 901 is a drain when the first source and drain 900 is a source in the present invention, or the first source and drain 900 is a drain when the second source and drain 901 is a source in the present invention.
  • Both the first source and drain 900 and the second source and drain 901 in the embodiment of the present invention are disposed in the area of the silicon substrate 100 surrounded by the shallow trench isolation structure 200 .
  • the present invention can also provide a memory, and the memory may specifically include the back gate modulation device in the embodiment of the present invention.
  • Memory is a storage device.
  • a storage device is a device that can store a large amount of binary information. It is used to store a large amount of data during the working process of computers and other digital systems. It is an indispensable part of computers and digital systems.
  • the invention helps to significantly increase the access speed and storage capacity of the storage device, so as to meet the requirements of computers and other digital systems on the operation speed and massive data processing.
  • the memory device includes a plurality of memory cells (MemoryCell), and each memory cell includes the back gate modulation device provided by the embodiment of the present invention; the memory provided by the present invention can be Flash Memory (flash memory).
  • the present invention can also provide a logic device (Logic), which may include the back gate modulation device in the embodiment of the present invention.
  • Logic logic device
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise specifically defined.

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Abstract

本发明提供了一种背栅调制器件及其制备方法、存储器、逻辑器件，其中背栅调制器件可包括但不限于硅衬底、ONO层、单晶硅层、栅极、第一侧墙、第二侧墙、第一源漏极及第二源漏极。ONO层填充于硅衬底上形成的空腔内，单晶硅层形成于ONO层上，栅极形成于单晶硅层上，第一侧墙环绕在栅极的侧壁周围，设置于单晶硅层上，第二侧墙环绕在第一侧墙的侧壁周围，设置于单晶硅层上；第一源漏极设置于硅衬底上，处于单晶硅层的一旁侧；第二源漏极设置于硅衬底上，处于单晶硅层的另一旁侧。本发明能够根据实际需要通过牺牲层和衬底的厚度灵活地控制单晶硅层和ONO结构的厚度，从而最大程度地发挥出背栅调制器件的性能，并能够有效降低器件成本。

Description

一种背栅调制器件及其制备方法、存储器、逻辑器件 技术领域
本发明涉及半导体器件技术领域，更为具体地，本发明能够提供一种背栅调制器件及其制备方法、存储器、逻辑器件。
背景技术
随着集成电路技术的不断发展，出于器件集成度、性能、成本等因素的考虑，对半导体器件的结构设计要求越来越高。SONOS(Silicon-Oxide-Nitride-Oxide-Silicon，硅-氧化物-氮化物-氧化物-硅)器件具有工艺简单、兼容性较好、功耗低以及扩展性较强等优点，经常将FDSOI(FullyDepleted Silicon-On-Insulator，全耗尽绝缘体上硅)技术与SONOS技术相结合，以制备出功耗低、性能强的半导体器件。
但是，由于现有SONOS器件工艺以及结构上设计存在的局限，无法根据实际情况灵活调整SONOS关键器件层的厚度，影响了半导体器件的性能，而且器件加工成本较高。
发明内容
为解决现有技术无法灵活调整SONOS关键器件层的厚度、成本高等问题，本发明一个或多个实施例提供了一种背栅调制器件及其制备方法、存储器、逻辑器件。
为实现上述技术目的，本发明提供了一种背栅调制器件，该背栅调制器件可包括但不限于硅衬底、ONO层、单晶硅层、栅极、第一侧墙、第二侧墙、第一源漏极以及第二源漏极。
ONO层，填充于所述硅衬底上形成的空腔内。
单晶硅层，形成于所述ONO层上。
栅极，形成于所述单晶硅层上。
第一侧墙，环绕在所述栅极的侧壁周围，设置于所述单晶硅层上。
第二侧墙，环绕在所述第一侧墙的侧壁周围，设置于所述单晶硅层上。
第一源漏极，设置于所述硅衬底上，处于所述单晶硅层的一旁侧。
第二源漏极，设置于所述硅衬底上，处于所述单晶硅层的另一旁侧。
进一步地，该背栅调制器件还包括浅槽隔离结构。
浅槽隔离结构，形成于所述硅衬底中。所述第一源漏极和所述第二源漏极，均设置于所述浅槽隔离结构围成的硅衬底区域内。
进一步地，所述ONO层包括依次设置的隧穿氧化层、氮化层以及阻挡氧化层；其中，所述阻挡氧化层设置于所述硅衬底上。
进一步地，所述第一侧墙为氮化硅层，所述第二侧墙为氧化硅层。
进一步地，所述栅极由浮栅结构组成。
进一步地，所述栅极由多晶硅和氮氧化硅组成。
为实现上述的技术目的，本发明还提供了一种存储器，所述存储器可包括但不限于本发明实施例中所述的背栅调制器件。
为实现上述的技术目的，本发明提供了一种逻辑器件，所述逻辑器件包括本发明实施例中所述的背栅调制器件。
为实现上述的技术目的，本发明还能够提供一种背栅调制器件的制备方法，该制备方法可包括但不限于如下的一个或多个步骤。
提供硅衬底。
在所述硅衬底中形成浅槽隔离结构。
在由所述浅槽隔离结构包围的硅衬底的表面外延生长出一层牺牲层，以及在所述牺牲层上形成单晶硅层。
在所述单晶硅层上形成栅极，以及在所述栅极的侧壁上形成第一侧墙和在所述第一侧墙的侧壁上形成第二侧墙。
通过依次垂直刻蚀所述单晶硅层和所述牺牲层的方式露出所述牺牲层。
通过刻蚀掉所述牺牲层形成空腔，并露出所述硅衬底和所述单晶硅层。
在所述硅衬底与所述单晶硅层之间的所述空腔中形成ONO层。
在所述浅槽隔离结构围成的硅衬底区域内形成第一源漏极和第二源 漏极。
进一步地，本发明实施例中在所述硅衬底与所述单晶硅层之间的所述空腔中形成ONO层包括：
在露出的单晶硅层的表面生长隧穿氧化层和在露出的硅衬底的表面生长阻挡氧化层；
在所述隧穿氧化层和所述阻挡氧化层之间填充氮化层。
本发明的有益效果为：与现有技术相比，本发明可根据实际需要通过牺牲层(外延SiGe)和衬底(Si)的厚度灵活控制单晶硅层(顶层硅)和ONO结构的厚度，器件结构灵活性较高，从而最大程度地发挥出背栅调制器件的性能。基于本发明制作的存储器件能够有效提高存储窗口，实现多比特位存储，并具有使用寿命高等优点。基于本发明制作的逻辑器件可实现不同背栅压的等效效果，并具有能耗低等优点。另外，本发明基于单晶硅晶圆制作SON结构可极大地降低成本，例如相比SOI晶圆可降低80％左右的成本。
附图说明
图1示出了本发明一个或多个实施例中所提供的硅衬底的截面结构示意图。
图2示出了本发明一个或多个实施例中在硅衬底上制作有浅槽隔离(STI)结构后的示意图。
图3示出了本发明一个或多个实施例中形成牺牲层和单晶硅层后的器件结构示意图。
图4示出了本发明一个或多个实施例中形成栅极和双侧墙后的器件结构示意图。
图5示出了本发明一个或多个实施例中垂直刻蚀单晶硅层和牺牲层后的器件结构示意图。
图6示出了本发明一个或多个实施例中刻蚀掉牺牲层后形成空腔后的器件结构示意图。
图7示出了本发明一个或多个实施例中在空腔位置形成ONO层后的 器件结构示意图。
图8示出了本发明一个或多个实施例中形成第一源漏极和第二源漏极后的器件结构示意图。
图中，
100、硅衬底。
200、浅槽隔离结构。
300、牺牲层。
400、单晶硅层。
500、栅极。
600、第一侧墙(图中黑色填充部分)。
700、第二侧墙。
800、隧穿氧化层。801、氮化层。802、阻挡氧化层。
900、第一源漏极。901、第二源漏极。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
如图1至图8所示，本发明一个或多个实施例能够提供一种背栅调制器件的制备方法，以制造出本发明提供的背栅调制器件，并解决现有技术存在的一个或多个问题，具体说明如下。
如图1所示，基于清洗后的提供硅衬底100。本发明实施例能够使用单晶硅晶圆(具体为体硅晶圆)形成的硅衬底100制作背栅调制器件，该方式能够有效地降低成本，例如较SOI晶圆成本降低约80％。
如图2所示，本发明实施例具体可在硅衬底100中形成浅槽隔离结构(STI，Shallow Trench Isolation)200。应当理解的是，浅槽隔离工艺具体过程可根据具体情况进行选择，本发明实施例不再进行赘述。
如图3所示，本发明实施例可由浅槽隔离结构200包围的硅衬底100的表面外延(Epi，Epitaxy)生长出一层牺牲层300，以及在牺牲层300上形成单晶硅层400。本实施例中的牺牲层300具体为SiGe(硅锗)层，即本步骤在Si表面外延一层SiGe，SiGe的厚度可根据后续形成的ONO层厚度反推确定，例如ONO层厚度与SiGe的厚度相同；然后可再外沿一层单晶硅，单晶硅的厚度考虑后续步骤中的RTO(Rapid Thermal Oxidation，快速热氧化)或HTO(High Temperature Oxidation，高温氧化)的损失。
如图4所示，在单晶硅层400上形成栅极500和双侧墙结构。具体在栅极500的侧壁上形成第一侧墙600以及在第一侧墙600的侧壁上形成第二侧墙700，本发明实施例中第一侧墙600为氮化硅层，第二侧墙700为氧化硅层。本发明实施例中的背栅调制器件用于存储器时，该栅极500由浮栅结构(FloatingGate)组成。本发明实施例中的背栅调制器件用于逻辑器件时，该栅极500可由多晶硅(Poly)和氮氧化硅(SiON)组成。
以形成浮栅结构为例，本发明依次进行高温氧化(HTO)、SiN沉积、高温氧化(HTO)及快速热退火(RTP，Rapid Thermal Processing)处理，然后进行LDD(Lightly doped drain，轻掺杂注入)处理，最后制作氮化硅侧墙和氧化硅侧墙。应当理解的是，制作侧墙的工艺具体实现过程可根据需要进行选择，本发明实施例将不再进行赘述。
如图5所示，通过依次垂直刻蚀单晶硅层400以及牺牲层300的方式露出牺牲层300。本实施例具体垂直刻蚀源漏区域，形成相应的凹槽，并露出牺牲层300(SiGe)的侧面。其中，垂直刻蚀可采用干法刻蚀方式。
如图6所示，通过刻蚀掉牺牲层300形成空腔，并露出硅衬底100和单晶硅层400。本发明中实现刻蚀牺牲层300的过程具体可采用湿法刻蚀方式，即刻蚀掉SiGe层。应当理解的是，由于图6为器件结构截面图，本实施例空腔在图示中的虚线处示意出，而实际结构中在其他方向还存在对上部相关结构的支撑，而并非是悬空的结构。
如图7所示，在硅衬底100与单晶硅层400之间的空腔中形成ONO层。可见本发明提供一种基于体硅晶圆制作的SON(Silicon On Nothing，空腔上硅技术)背栅调制器件，具体为在制备过程中存在SON情况。
ONO(Oxide-Nitride-Oxide，氧化物-氮化物-氧化物)层具体包括隧穿氧化层800、氮化层801以及阻挡氧化层802，本发明实施例在硅衬底与单晶硅层400之间的空腔中形成ONO层可包括：在露出的单晶硅层400的表面生长隧穿氧化层800和在露出的硅衬底100的表面生长阻挡氧化层802，具体可通过快速热氧化(RTO)或高温氧化(HTO)方式在空腔处的单晶硅层400下表面以及硅衬底100的上表面生长氧化物(Oxide)；并在隧穿氧化层800和阻挡氧化层802之间填充氮化层801，本发明实施例具体沉积填充SiN，形成ONO层，从而完成了SONOS结构的加工。
如图8所示，在外漏的硅衬底100上外延出源漏电极，本发明实施例具体在浅槽隔离结构200围成的硅衬底100区域内形成第一源漏极900和第二源漏极901，从而实现基本的晶体管结构制作。
与本发明提供的器件制备方法基于同一发明构思，本发明一个或多个实施例中还能够提供一种背栅调制器件，本发明中的背栅调制器件具体可包括但不限于硅衬底100、浅槽隔离结构200、ONO层、单晶硅层400、栅极500、第一侧墙600、第二侧墙700、第一源漏极900以及第二源漏极901等。
浅槽隔离结构200形成于硅衬底100中，该硅衬底100为基于单晶硅(Si)晶圆形成的衬底。浅槽隔离结构200即STI(Shallow Trench Isolation)结构，可由绝缘材料形成，例如氧化硅等。
ONO层填充于硅衬底100上形成的，本发明实施例中的ONO层包括依次设置的隧穿氧化层800、氮化层801以及阻挡氧化层802；其中，本发明实施例阻挡氧化层802设置于硅衬底100上，氮化层801设置于氧化层802上，隧穿氧化层800设置于氮化层801上，以形成氧化物(Oxide)-氮化物(Nitride)-氧化物(Oxide)层。
单晶硅层400形成于ONO层上，具体设置于隧穿氧化层800上。本发明中的硅衬底100、ONO层及单晶硅层400共同形成SONOS结构。
栅极500形成于单晶硅层400上。本发明一些实施例中的栅极500由浮栅结构组成，以用于存储器件；在该情况下浮栅结构作为正栅，正栅与字线连接，通过字线写入方式存储数据“01”和“00”，而且本发明的SONOS结构作为背栅，背栅与位线连接，进而通过位线写入方式存储数据“11”和“10”。可见本发明能够有效拓宽偏移电压(Vt Shift)的变化范围和提高存储窗口，以获得更多的存储比特数，具体可实现双比特存储的数据写入目的，如下表中本专利提出双比特存储的写入方式与常规技术的比较。
Figure PCTCN2022115094-appb-000001
Figure PCTCN2022115094-appb-000002
本发明另一些实施例中的栅极500由多晶硅和氮氧化硅组成，该结构形式的背栅调制器件可用于逻辑器件。本实施例该情况下可利用SONOS结构作为背栅，背栅与位线连接，以通过位线写入“1”或“0”或不写入。具体地，由于本发明实施例提供的SONOS结构能带的量子阱结构，具有良好的存储效应，可通过脉冲方式写入不同背栅信息，以实现不同背栅压(body bias)的等效效果，除此之外的绝大部分时间背栅处于0V状态，无需2V左右的较高电压输入，避免持续施加背栅压可能造成向衬底各个方向漏电的问题和引发寄生的耦合效应的问题，并具有能耗低等优点，如下表中本专利提出实现替代常规SOI背偏压的方式。
Figure PCTCN2022115094-appb-000003
第一侧墙600环绕在栅极500的侧壁周围，设置于单晶硅层400上。本发明实施例中第一侧墙600为氮化硅层。
第二侧墙700环绕在第一侧墙600的侧壁周围，设置于单晶硅层400上；第二侧墙700为氧化硅层。
本发明实施例中的第一源漏极900和第二源漏极901可分别设置于单晶硅层400的两侧。具体地，第一源漏极900设置于硅衬底100上，并处于单晶硅层400的一旁侧。第二源漏极901设置于硅衬底100上，以及处于单晶硅层400的另一旁侧。应当理解的是，本发明第一源漏极900为源 极时第二源漏极901为漏极，或者本发明第二源漏极901为源极时第一源漏极900为漏极。
本发明实施例中的第一源漏极900和第二源漏极901均设置于浅槽隔离结构200围成的硅衬底100区域内。
本发明还能够提供一种存储器，该存储器具体可包括本发明实施例中的背栅调制器件。存储器即存储器件，存储器件是一种能够存储大量二值信息的器件，用于计算机和其他一些数字系统工作过程中对大量数据进行存储，属于计算机和数字系统不可缺少的组成部分。本发明有助于明显地提升存储器件的访问速度以及存储容量，以满足计算机和其他数字系统对运行速度和大量数据处理的要求。存储器件包括多个存储单元(MemoryCell)，每个存储单元均包括本发明实施例提供的背栅调制器件；本发明提供的存储器可为Flash Memory(闪存)。
本发明还能够提供一种逻辑器件(Logic)，该逻辑器件可包括本发明实施例中的背栅调制器件。
在本说明书的描述中，参考术语“本实施例”、“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (10)

  1. 一种背栅调制器件，其特征在于，包括：
    硅衬底；
    ONO层，填充于所述硅衬底上形成的空腔内；
    单晶硅层，形成于所述ONO层上；
    栅极，形成于所述单晶硅层上；
    第一侧墙，环绕在所述栅极的侧壁周围，设置于所述单晶硅层上；
    第二侧墙，环绕在所述第一侧墙的侧壁周围，设置于所述单晶硅层上；
    第一源漏极，设置于所述硅衬底上，处于所述单晶硅层的一旁侧；
    第二源漏极，设置于所述硅衬底上，处于所述单晶硅层的另一旁侧。
  2. 根据权利要求1所述的背栅调制器件，其特征在于，还包括：
    浅槽隔离结构，形成于所述硅衬底中；
    所述第一源漏极和所述第二源漏极，均设置于所述浅槽隔离结构围成的硅衬底区域内。
  3. 根据权利要求1或2所述的背栅调制器件，其特征在于，
    所述ONO层包括依次设置的隧穿氧化层、氮化层以及阻挡氧化层；其中，所述阻挡氧化层设置于所述硅衬底上。
  4. 根据权利要求1或2所述的背栅调制器件，其特征在于，
    所述第一侧墙为氮化硅层，
    所述第二侧墙为氧化硅层。
  5. 根据权利要求1或2所述的背栅调制器件，其特征在于，
    所述栅极由浮栅结构组成。
  6. 根据权利要求1或2所述的背栅调制器件，其特征在于，
    所述栅极由多晶硅和氮氧化硅组成。
  7. 一种存储器，其特征在于，所述存储器包括权利要求1～5中任一权利要求所述的背栅调制器件。
  8. 一种逻辑器件，其特征在于，所述逻辑器件包括权利要求1～4、6中任一权利要求所述的背栅调制器件。
  9. 一种背栅调制器件的制备方法，其特征在于，包括：
    提供硅衬底；
    在所述硅衬底中形成浅槽隔离结构；
    在由所述浅槽隔离结构包围的硅衬底的表面外延生长出一层牺牲层，以及在所述牺牲层上形成单晶硅层；
    在所述单晶硅层上形成栅极，以及在所述栅极的侧壁上形成第一侧墙和在所述第一侧墙的侧壁上形成第二侧墙；
    通过依次垂直刻蚀所述单晶硅层和所述牺牲层的方式露出所述牺牲层；
    通过刻蚀掉所述牺牲层形成空腔，并露出所述硅衬底和所述单晶硅层；
    在所述硅衬底与所述单晶硅层之间的所述空腔中形成ONO层；
    在所述浅槽隔离结构围成的硅衬底区域内形成第一源漏极和第二源漏极。
  10. 根据权利要求9所述的背栅调制器件的制备方法，其特征在于，在所述硅衬底与所述单晶硅层之间的所述空腔中形成ONO层包括：
    在露出的单晶硅层的表面生长隧穿氧化层和在露出的硅衬底的表面生长阻挡氧化层；
    在所述隧穿氧化层和所述阻挡氧化层之间填充氮化层。
PCT/CN2022/115094 2021-10-09 2022-08-26 一种背栅调制器件及其制备方法、存储器、逻辑器件 WO2023056798A1 (zh)

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CN1599081A (zh) * 2004-08-17 2005-03-23 北京大学 浮栅闪存场效应晶体管
US20070047364A1 (en) * 2005-08-31 2007-03-01 International Business Machines Corporation Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices
CN113035716A (zh) * 2021-02-08 2021-06-25 西安电子科技大学 基于22nm工艺的SONOS结构抗辐照FDSOI场效应管及其制备方法
CN113921612A (zh) * 2021-10-09 2022-01-11 广东省大湾区集成电路与系统应用研究院 一种背栅调制器件及其制备方法、存储器、逻辑器件

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US20070047364A1 (en) * 2005-08-31 2007-03-01 International Business Machines Corporation Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices
CN113035716A (zh) * 2021-02-08 2021-06-25 西安电子科技大学 基于22nm工艺的SONOS结构抗辐照FDSOI场效应管及其制备方法
CN113921612A (zh) * 2021-10-09 2022-01-11 广东省大湾区集成电路与系统应用研究院 一种背栅调制器件及其制备方法、存储器、逻辑器件

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