WO2023054602A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023054602A1
WO2023054602A1 PCT/JP2022/036488 JP2022036488W WO2023054602A1 WO 2023054602 A1 WO2023054602 A1 WO 2023054602A1 JP 2022036488 W JP2022036488 W JP 2022036488W WO 2023054602 A1 WO2023054602 A1 WO 2023054602A1
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WIPO (PCT)
Prior art keywords
line
power supply
power
power line
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/036488
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English (en)
French (fr)
Japanese (ja)
Inventor
淳 岡本
ウェンゼン ワン
紘宜 武野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
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Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Socionext Inc filed Critical Socionext Inc
Priority to JP2023551859A priority Critical patent/JPWO2023054602A1/ja
Priority to CN202280065644.1A priority patent/CN118044349A/zh
Publication of WO2023054602A1 publication Critical patent/WO2023054602A1/ja
Priority to US18/606,421 priority patent/US20240224492A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to semiconductor devices.
  • an isolation area may be provided to secure the space between the bit cell area and the peripheral circuit area in plan view.
  • BPR Buried Power Rail
  • a technique is known in which a power switch circuit is provided between a power line and a virtual power line in order to switch between supply and cutoff of a power supply voltage to a virtual power line of an internal circuit.
  • BS-PDN Backside-Power Delivery Network
  • a power supply wiring network is provided on the back surface of a semiconductor substrate and a power supply voltage is supplied through vias penetrating the back surface and front surface of the semiconductor substrate.
  • a technique of providing a wiring layer with a transistor for switching between supply and cutoff of a power supply voltage is known.
  • the present invention has been made in view of the above points, and it is an object of the present invention to appropriately arrange power switches in a semiconductor device using a wiring layer in which wiring of a power wiring network on the back surface of a substrate is provided.
  • a semiconductor device includes: a substrate having a first surface; a second surface facing the first surface; a first power supply line provided on the first surface; a first ground line provided on the first surface; a first region having the first power supply line and the first ground line; a second power supply line provided on the first surface; a second ground line provided on one surface, a third power supply line provided on the second surface, a fourth power supply line provided on the second surface, and the second power supply line; a second region electrically connected to the third power line and having vias provided in the substrate, the second power line, and the second ground line; a third region positioned between the first region and the second region; and a first switch transistor electrically connected between the third power line and the fourth power line. on the second surface side of the substrate.
  • FIG. 1 is a plan view showing an overview of the layout of a semiconductor device according to a first embodiment
  • FIG. 2 is a circuit block diagram showing an outline of a power switch circuit arranged in the bit cell area of FIG. 1;
  • FIG. 2 is a plan view showing an example of the layout of power supply wiring in a region where the power switch circuit of FIG. 1 is arranged;
  • FIG. 4 is a cross-sectional view showing an example of a cross section of a switch transistor of the power switch circuit PSW1 of FIG. 3;
  • FIG. 4 is a cross-sectional view showing another example of a cross section of a switch transistor of the power switch circuit PSW1 of FIG. 3;
  • FIG. 4 is a cross-sectional view showing another example of a cross section of a switch transistor of the power switch circuit PSW1 of FIG. 3;
  • FIG. 4 is a cross-sectional view showing still another example of the cross section of the switch transistor of the power switch circuit PSW1 of FIG. 3;
  • FIG. 2 is a diagram showing an example of bit cells arranged in a bit cell region of FIG. 1;
  • FIG. 2 is a diagram showing another example of bit cells arranged in the bit cell region of FIG. 1;
  • FIG. FIG. 4 is a plan view showing an example of a power switch circuit arranged across an isolation region and a bit cell region;
  • FIG. 8 is a cross-sectional view showing a cross section taken along line Y1-Y1′ of FIG. 7;
  • FIG. 8 is a cross-sectional view showing a cross section taken along line X1-X1′ of FIG. 7; 8 is a plan view showing a modification of the power switch circuit arranged in the bit cell region of FIG. 7;
  • FIG. FIG. 11 is a plan view showing an example of a power switch circuit arranged across an isolation region and a bit cell region in a semiconductor device according to a second embodiment;
  • FIG. 12 is a plan view showing a modification of the power switch circuit of FIG. 11;
  • symbols indicating signals may also be used as symbols indicating signal values, signal lines, or signal terminals.
  • a code indicating a power supply may also be used as a code indicating a power supply voltage, a power supply line to which the power supply voltage is supplied, or a power supply terminal.
  • FIG. 1 is a plan view showing an overview of the layout of the semiconductor device according to the first embodiment.
  • the semiconductor device 100 shown in FIG. 1 is, for example, an SRAM.
  • the semiconductor device 100 has a bit cell area BCA, and a peripheral circuit area PCA and a decoder area DECA arranged around the bit cell area BCA.
  • the peripheral circuit area PCA and the decoder area DECA are examples of the first area.
  • the bit cell area BCA is an example of the second area.
  • the peripheral circuit area PCA and the bit cell area BCA are arranged side by side in the X direction, and the decoder area DECA and the bit cell area BCA are arranged side by side in the Y direction.
  • the X direction is an example of a first direction.
  • the Y direction is an example of a second direction different from the first direction.
  • an isolation region SPA is arranged between the bit cell region BCA, the peripheral circuit region PCA and the decoder region DECA.
  • the separation area SPA is an example of a third area.
  • different power supply voltages are supplied to the bit cell area BCA, the peripheral circuit area PCA, and the decoder area DECA.
  • the peripheral circuit area PCA and the decoder area DECA a plurality of power supply lines extending in the X direction and arranged side by side in the Y direction are arranged. The positions and arrangement intervals of the power supply lines in the bit cell area BCA, the peripheral circuit area PCA and the decoder area DECA may be different.
  • a predetermined number of power switch circuits PSW1 are provided on the back surface BS (FIG. 4A) of the semiconductor substrate SUB of the semiconductor device 100, respectively.
  • a predetermined number of power switch circuits PSW2 are provided on the back surface BS of the semiconductor substrate SUB.
  • One or both of the power switch circuits PSW1 and PSW2 may be arranged on the back surface BS of the semiconductor substrate SUB in the isolation region SPA.
  • the back surface BS of the semiconductor substrate SUB is an example of a second surface facing the front surface of the semiconductor substrate SUB.
  • the power switch circuit PSW1 is an example of a second power switch circuit.
  • the power switch circuit PSW2 is an example of a first power switch circuit.
  • power switch circuits PSW1 and PSW2 are also referred to as power switch circuits PSW.
  • FIG. 2 is a circuit block diagram showing an overview of the power switch circuit PSW2 arranged in the bit cell area BCA of FIG.
  • the power switch circuits PSW1 arranged in the peripheral circuit area PCA and the decoder area DECA also have the same circuit configuration as in FIG.
  • the bit cell area BCA has a plurality of bit cells BC (that is, memory cells). Each bit cell BC is electrically connected to a virtual power supply line VVDD and a ground line VSS, and receives power from the virtual power supply line VVDD to operate.
  • the power switch circuit PSW2 has a switch transistor SWT and a control circuit CNTL.
  • the switch transistor SWT is, for example, a p-channel transistor, and operates by receiving a switch control signal SWCNT from the control circuit CNTL at its gate.
  • the switch transistor SWT of the power switch circuit PSW2 is an example of a first switch transistor.
  • the switch transistor SWT of the power switch circuit PSW1 is an example of a second switch transistor.
  • FIG. 2 shows one switch transistor SWT for simplification, a plurality of switch transistors SWT may be arranged between the power supply line VDD and the virtual power supply line VVDD.
  • the control circuit CNTL is, for example, a buffer circuit.
  • the control circuit CNTL sets the switch control signal SWCNT to low level in order to supply the power supply voltage from the power supply line VDD to the virtual power supply line VVDD.
  • the control circuit CNTL sets the switch control signal SWCNT to high level in order to stop the supply of the power supply voltage from the power supply line VDD to the virtual power supply line VVDD.
  • FIG. 3 is a plan view showing an example of the layout of the power wiring in the area where the power switch circuits PSW1 and PSW2 of FIG. 1 are arranged.
  • FIG. 3 is an enlarged view of an area where the peripheral circuit area PCA and the bit cell area BCA are arranged with the isolation area SPA interposed therebetween.
  • the Mint layer wiring and BPR are provided extending in the X direction, and the local wiring LI and the wiring on the back surface BS of the semiconductor substrate SUB are provided extending in the Y direction.
  • the Mint layer is provided on the surface side of the semiconductor substrate SUB.
  • the local wiring LI is provided between the semiconductor substrate SUB and the Mint layer.
  • the surface of the semiconductor substrate SUB is an example of the first surface.
  • the power supply lines, virtual power supply lines and ground lines wired to the peripheral circuit area PCA and decoder area DECA are denoted by VDD1, VVDD1 and VSS1, respectively.
  • a power supply line, a virtual power supply line and a ground line wired in the bit cell area BCA are denoted by VDD2, VVDD2 and VSS2, respectively.
  • a power supply line or a ground line wired in the peripheral circuit area PCA or the bit cell area BCA may be arranged on the separation area SPA side.
  • the circuits arranged in the peripheral circuit area PCA and the decoder area DECA are electrically connected to the virtual power supply line VVDD1 and the ground line VSS1.
  • Bit cells arranged in bit cell area BCA are electrically connected to virtual power supply line VVDD2 and ground line VSS2.
  • the power switch circuit PSW1 is electrically connected to the power line VDD1, the virtual power line VVDD1, and the ground line VSS1
  • the power switch circuit PSW2 is electrically connected to the power line VDD2, the virtual power line VVDD2, and the ground line. It is electrically connected to VSS2.
  • a ground line VSS1 (BPR) and a virtual power supply line VVDD1 (BPR) provided as BPR, a ground line VSS1 (BS) provided on the rear surface BS, a power supply line VDD1 (BS) and a virtual power supply line are provided.
  • a line VVDD1 (BS) is arranged.
  • Ground lines VSS1 (BPR) and VSS1 (BS) are connected to each other via TSV.
  • the virtual power lines VVDD1 (BPR) and VVDD1 (BS) are connected to each other via TSV.
  • peripheral circuit area PCA on the back surface BS of the semiconductor substrate SUB, there is a power switch circuit PSW1 having switch transistors (not shown) electrically connected to the power line VDD1 (BS) and the virtual power line VVDD1 (BS). be provided.
  • Power switch circuit PSW1 supplies power supply voltage VVDD1 to elements and circuits (not shown) provided in peripheral circuit area PCA.
  • a ground line VSS2 (BPR) and a virtual power supply line VVDD2 (BPR) provided as BPR, and a ground line VSS (BS) and a virtual power supply line VVDD2 (BS) provided on the back surface BS are arranged in the bit cell area BCA. ing.
  • Ground lines VSS2 (BPR) and VSS2 (BS) are connected to each other via TSV.
  • Virtual power lines VVDD2 (BPR) and VVDD2 (BS) are connected to each other via TSV.
  • the virtual power line VVDD2 (BPR) is connected to the virtual power line VVDD2 (Mint) of the Mint layer via the virtual power line VVDD2 of the local wiring LI.
  • the virtual power line VVDD2 (Mint) is an example of a first wiring.
  • a power supply line VDD2 (BS) provided on the back surface BS is arranged in the isolation area SPA.
  • the back surface BS of the semiconductor substrate SUB is provided with a power switch circuit PSW2 having a switch transistor (not shown) electrically connected to the power supply line VDD2 (BS) and the virtual power supply line VVDD2 (BS). be done.
  • the power switch circuit PSW2 supplies the power supply voltage VVDD2 to the bit cells BC (FIG. 5 or 6) provided in the bit cell area BCA.
  • the power supply line VDD1 (BS) of the power switch circuit PSW1 and the power supply line VDD2 (BS) of the power switch circuit PSW2 shown in FIG. 3 may be supplied with the same power supply voltage or may be supplied with different power supply voltages. good too.
  • the power supply lines VDD1 (BS) and VDD2 (BS) may be electrically connected to each other.
  • power line VDD1 (BS), virtual power line VVDD1 (BS), ground line VSS1 (BS), power line VDD2 (BS), virtual power line VVDD2 (BS) and ground line VSS2 (BS) are BS-PDN may be provided as
  • the virtual power line VVDD1 (BPR) is an example of a first power line.
  • the virtual power line VVDD2 (BPR) is an example of a second power line.
  • the virtual power line VVDD2 (BS) is an example of a third power line.
  • the power line VDD2 (BS) is an example of a fourth power line.
  • the virtual power line VVDD1 (BS) is an example of a fifth power line.
  • the power line VDD1 (BS) is an example of a sixth power line.
  • the ground line VSS1 (BPR) is an example of a first ground line.
  • the ground line VSS2 (BPR) is an example of a second ground line.
  • the ground line VSS1 (BS) is an example of a third ground line.
  • the ground line VSS2 (BS) is an example of a fourth ground line.
  • FIG. 4A is a cross-sectional view showing an example of a cross-section of a region including the switch transistor SWT of the power switch circuit PSW1 of FIG. 3.
  • FIG. 4A only the semiconductor substrate SUB and the structure on the back surface BS side of the semiconductor substrate SUB are shown, and illustration of transistors, wiring, etc. provided on the front surface side of the semiconductor substrate SUB is omitted.
  • the cross-sectional structure of the region including the switch transistor SWT of the power switch circuit PSW2 in FIG. 3 is also the same as in FIG. 4A.
  • the switch transistor SWT has a semiconductor layer SEML, a gate insulating film GINS, and a gate electrode GT which are stacked together.
  • a power supply line VDD1 (BS) is connected to one side of the semiconductor layer SEML with the gate electrode GT interposed therebetween.
  • a virtual power supply line VVDD1 (BS) is connected to the other side of the semiconductor layer SEML with the gate electrode GT interposed therebetween.
  • the switch transistor SWT is turned on or off by a control signal input to the gate electrode GT, and supplies power supply voltage from the power supply line VDD1 to the virtual power supply line VVDD1 when it is turned on.
  • one or both of the power supply line VDD1 and the virtual power supply line VVDD1 may be connected to a wiring provided in a wiring layer below the switch transistor SWT.
  • the wiring of the upper wiring layer and the wiring of the lower wiring layer are connected to each other through the via VIA (BS) provided by opening the insulating film INS.
  • FIG. 4A two wiring layers are provided on the back surface BS of the semiconductor substrate SUB, but three or more wiring layers may be provided.
  • the wirings of the two wiring layers stacked on each other may be connected via a via VIA (BS) provided by opening the insulating film INS.
  • VIA VIA
  • FIG. 4B is a cross-sectional view showing another example of the cross section of the switch transistor of the power switch circuit PSW1 of FIG. Also in FIG. 4B, only the semiconductor substrate SUB and the structure on the back surface BS side of the semiconductor substrate SUB are shown, and illustration of transistors, wiring, etc. provided on the front surface side of the semiconductor substrate SUB is omitted.
  • the cross-sectional structure of the region including the switch transistor SWT of the power switch circuit PSW2 of FIG. 3 is also the same as that of FIG. 4B.
  • the semiconductor layer SEML is provided in the same layer as the power supply line VDD1 (BS) and the virtual power supply line VVDD1 (BS), and the gate insulating film GINS and the gate electrode GT are provided on the back surface BS of the semiconductor layer SEML.
  • the power line VDD1 (BS) and the virtual power line VVDD1 (BS) are each connected to the semiconductor layer SEML.
  • the semiconductor layer SEML, the gate insulating film GINS, and the gate electrode GT are sequentially provided toward the back surface BS.
  • Other structures are the same as in FIG. 4A.
  • the gate electrode GT extends in the depth direction of FIG. 4B and is connected to wiring provided on the back surface BS.
  • FIG. 4C is a cross-sectional view showing another example of the cross section of the switch transistor of the power switch circuit PSW1 of FIG. Also in FIG. 4C, only the semiconductor substrate SUB and the structure on the back surface BS side of the semiconductor substrate SUB are shown, and illustration of the transistors, wiring, etc. provided on the front surface side of the semiconductor substrate SUB is omitted.
  • the cross-sectional structure of the region including the switch transistor SWT of the power switch circuit PSW2 of FIG. 3 is also the same as that of FIG. 4C.
  • FIG. 4C has the same structure as FIG. 4A except that the switch transistor SWT is provided in the second layer instead of the top layer closest to the semiconductor substrate SUB.
  • FIG. 4D is a cross-sectional view showing still another example of the cross section of the switch transistor SWT of the power switch circuit PSW1 of FIG. Also in FIG. 4D, only the semiconductor substrate SUB and the structure on the back surface BS side of the semiconductor substrate SUB are shown, and illustration of the transistors, wiring, etc. provided on the front surface side of the semiconductor substrate SUB is omitted.
  • the cross-sectional structure of the region including the switch transistor SWT of the power switch circuit PSW2 of FIG. 3 is also the same as that of FIG. 4D.
  • FIG. 4D is a diagram except that the semiconductor layer SEML, the gate insulating film GINS, and the gate electrode GT are sequentially provided from the back surface BS, and one of the semiconductor layers SEML is connected to the front surface side of the semiconductor substrate SUB via TSV. It has the same structure as 4A.
  • One end of the semiconductor layer SEML is connected to the virtual power line VVDD1 provided on the surface side of the semiconductor substrate SUB via TSV.
  • the other side of the semiconductor layer SEML is connected through a via VIA (BS) to a power supply line VVDD1 (BS) provided in a wiring layer below the switch transistor SWT.
  • the semiconductor layer SEML shown in FIGS. 4A to 4D may be provided using graphene or carbon nanotubes.
  • the switch transistor SWT in FIGS. 4A to 4D may be a thin film transistor (TFT).
  • FIG. 5 is a diagram showing an example of bit cells BC arranged in the bit cell area BCA of FIG.
  • FIG. 5A shows the wiring of the Mint layer and the layout of vias connected to the Mint layer
  • FIG. 5B the layout of the traces, gates, fins and vias is shown.
  • the circuit of the bit cell BC is shown in FIG. 5(C).
  • a via VIA1 indicated by a square connects the wiring of the Mint layer and each gate.
  • a via VIA2 indicated by a circle connects the wiring of the Mint layer and the local wiring LI.
  • a diamond-shaped via VIA3 connects the local wiring LI and the wiring of the BPR. The local wirings LI and the fins FIN are connected at overlapping positions in a plan view.
  • Rectangular broken lines shown in FIG. 5(B) indicate p-channel transistors P1 and P2, n-channel transistors N1 and N2, and transfer transistors T1 and T2.
  • the transfer transistors T1 and T2 are n-channel transistors.
  • Symbols Q and QB shown in FIGS. 5A to 5C indicate complementary storage nodes of bit cell BC.
  • Storage node Q is connected to bit line BL via transfer transistor T1.
  • Storage node QB is connected to bit line BLB via transfer transistor T2.
  • Two word lines WL provided in the Mint layer are connected to gates GT4 and GT1 of transfer transistors T1 and T2 via vias VIA1, respectively.
  • a virtual power supply line VVDD2 provided in the Mint layer is connected to local wirings LI2 and LI7 through vias VIA2.
  • Local line LI2 is connected to the source of p-channel transistor P1.
  • Local interconnection LI7 is connected to the source of p-channel transistor P2.
  • the wiring Q provided in the Mint layer is connected to the local wiring LI5 and the fins FIN3 and FIN4 via the via VIA2, and is connected to the gate GT3 via the via VIA1.
  • Fin FIN3 functions as the source and drain of p-channel transistor P1
  • fin FIN4 functions as the sources and drains of transfer transistor T1 and n-channel transistor N1.
  • the wiring QB provided in the Mint layer is connected to the local wiring LI4 and the fins FIN2 and FIN1 through the via VIA2, and is connected to the gate GT2 through the via VIA1.
  • the fin FIN2 functions as the source and drain of the p-channel transistor P2
  • the fin FIN1 functions as the sources and drains of the transfer transistor T2 and the n-channel transistor N2.
  • the bit line BLB provided in the Mint layer is connected to the local wiring LI1 and the fin FIN1 through the via VIA2.
  • a bit line BL provided in the Mint layer is connected to local wiring LI8 and fin FIN4 through via VIA2.
  • Ground lines VSS2 of two BPRs arranged on both sides in the Y direction in FIG. 6B are connected to local lines LI3 and LI6 via vias VIA3, respectively.
  • Local line LI3 is connected to the source of n-channel transistor N1.
  • Local line LI6 is connected to the source of n-channel transistor N2.
  • FIG. 6 is a diagram showing another example of the bit cell BC arranged in the bit cell area BCA of FIG. Elements similar to those in FIG. 5 are given the same reference numerals or the same patterns, and detailed descriptions thereof are omitted.
  • FIG. 6 has a layout similar to that of FIG. 5 except that virtual power line VVDD2 is provided in BPR.
  • the virtual power line VVDD2 of the local wirings LI2 and LI7 is connected to the virtual power line VVDD2 of the BPR via the via VIA3.
  • the virtual power supply line VVDD2 of the BPR is arranged between the ground lines VSS2 of the two BPRs and extends in the X direction like the ground lines VSS2 of the two BPRs.
  • FIG. 7 is a plan view showing an example of the power switch circuit PSW2 arranged across the isolation area SPA and the bit cell area BCA.
  • the switch transistor SWT of the power switch circuit PSW2 shown in FIG. 2 is provided in the separation area SPA.
  • the bit cells BC shown in FIG. 5 are arranged in the bit cell area BCA. It should be noted that some of the wirings and vias in the bit cell area BC in the bit cell area BCA are omitted from the drawing.
  • one side across the gate electrode GT is connected to the power supply line VDD2 (BS) on the back surface BS of the semiconductor substrate SUB.
  • the other side across the gate electrode GT is connected to the virtual power supply line VVDD2 (BS) on the back surface BS. Note that the wiring connected to the gate electrode GT is omitted in FIG.
  • the virtual power line VVDD2 (BS) on the back surface BS is connected to the virtual power line VVDD2 (Mint) on the Mint layer via the TSV and the virtual power line VVDD2 (BPR).
  • virtual power supply line VVDD2 (BPR) and ground line VSS2 (BPR) may extend over switch transistor PSW2 provided on back surface BS.
  • a plurality of ground lines VSS (BPR) in bit cell area BCA may be connected to each other via ground lines VSS2 (BS) and TSV on back surface BS.
  • FIG. 8 is a cross-sectional view showing a cross section along line Y1-Y1' in FIG.
  • the virtual power line VVDD2 (BS) on the back surface BS of the semiconductor substrate SUB is connected to the semiconductor layer SEML of the switch transistor SWT of the power switch circuit PSW2 through the via VIA (BS).
  • the virtual power line VVDD2 (BS) is connected to the virtual power line VVDD2 (BPR) of the BPR via the TSV.
  • FIG. 9 is a cross-sectional view showing a cross section along line X1-X1' in FIG.
  • the switch transistor SWT2 has a semiconductor layer SEML, a gate insulating film GINS, and a gate electrode GT, which are stacked together, similarly to FIG. 4A.
  • one side across the gate electrode GT is connected to the virtual power line VVDD2 (BS) on the back surface BS of the semiconductor substrate SUB.
  • the other side sandwiching the gate electrode GT is connected to the power supply line VDD2 (BS) on the back surface BS of the semiconductor substrate SUB.
  • the TSV connected to the virtual power line VVDD2 (BS) on the back surface BS may be connected through to the virtual power line VVDD2 (Mint) on the Mint layer.
  • the TSV may include a TSV that penetrates to the wiring of the BPR and a TSV that penetrates to the wiring of the Mint layer for connection.
  • FIG. 10 is a plan view showing a modification of the power switch circuit PSW2 arranged in the bit cell area BCA of FIG. Elements similar to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the semiconductor layer SEML and gate electrode GT of the switch transistor SWT are omitted. 10 is the same as the layout of FIG. 7 except that the switch transistor SWT of the power switch circuit PSW2 and the power supply line VDD2 (BS) on the back surface BS of the semiconductor substrate SUB are arranged at positions overlapping the bit cells BC.
  • the switch transistor SWT of the power switch circuit PSW2 and the power supply line VDD2 (BS) on the back surface BS of the semiconductor substrate SUB are arranged at positions overlapping the bit cells BC.
  • the switch transistor SWT may be arranged at a position overlapping the bit cell area BCA together with the virtual power supply line VVDD2 (BS). Also, the plurality of ground lines VSS (BPR) of the bit cell area BCA may be connected to the common ground line VSS2 (BS) of the back surface BS via TSV.
  • the wiring layer provided on the back surface BS of the semiconductor substrate SUB can be used to appropriately arrange the power switch circuits PSW (or PSW1, PSW2).
  • the power switch circuit PSW can be arranged in the bit cell area BCA or isolation area SPA.
  • the power switch circuits PSW1 and PSW2 can be arranged in the peripheral circuit area PCA and the bit cell area BCA, respectively.
  • a power supply voltage can be supplied from the power switch circuit PSW provided on the back surface BS to the virtual power lines VVDD of the peripheral circuit area PCA, the decoder area DECA and the bit cell area BCA. That is, the power supply voltage can be supplied to the SRAM from the power switch circuit PSW provided on the back surface BS.
  • FIG. 11 is a plan view showing an example of the power switch circuit PSW2 arranged across the isolation area SPA and the bit cell area BCA in the semiconductor device according to the second embodiment. Elements similar to those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. FIG. 11 is similar to FIG. 7 except that the virtual power line VVDD2 of the bit cell area BCA is provided using BPR.
  • the switch transistor SWT of the power switch circuit PSW2 and the power line VDD2 (BS) on the back surface BS of the semiconductor substrate SUB may be arranged at positions overlapping the bit cells BC.
  • power supply switch circuit PSW2 is arranged in bit cell area BCA
  • virtual power supply line VVDD2 (BPR) and ground line VSS2 (BPR) may be provided extending over switch transistor SWT.
  • a plurality of ground lines VSS (BPR) in bit cell area BCA may be connected to common ground line VSS2 (BS) on back surface BS via TSV.
  • FIG. 12 is a plan view showing a modification of the power switch circuit PSW2 of FIG. 11.
  • FIG. Elements similar to those in FIG. 11 are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the power line VDD2 (BS) connected to the power switch circuit PSW2 is connected to the power line VDD2 (BPR) provided on the surface of the semiconductor substrate SUB via TSV.
  • the power line VDD2 (BPR) is an example of a seventh power line.
  • the TSV that connects the power line VDD2 (BS) to the power line VDD2 (BPR) is arranged, for example, in the bit cell area BCA.
  • BCA bit cell area
  • the pentagons shown at the intersections of the power supply lines VDD2 (BS) extending in the Y direction and the power supply lines VDD2 (BS) extending in the X direction are vias VIA ( BS).
  • One or both of the power line VDD2 (BS) and the virtual power line VVDD2 (BS) may be arranged in a mesh pattern by wiring provided in a plurality of wiring layers on the back surface BS.
  • wirings of a plurality of wiring layers are connected to each other through vias VIA (BS).
  • the plurality of ground lines VSS2 (BPR) in the bit cell area BCA may be connected to the common ground line VSS2 (BS) on the back surface BS via TSVs.
  • the layout configuration illustrated in FIG. 12 may be applied to the other embodiments described above, and may be applied to the power supply line VDD1 (PSW1) or the virtual power supply line VVDD1 (PSW1) provided in the power switch circuit PSW1.
  • PSW1 power supply line
  • PSW1 virtual power supply line
  • the TSV connecting the power line VDD1 (BS) on the back surface BS of the semiconductor substrate SUB and the power line VDD1 (BPR) on the front surface is arranged in the peripheral circuit area PCA.
  • the wiring layer provided on the back surface BS of the semiconductor substrate SUB can be used to appropriately arrange the power switch circuit PSW2.
  • the power switch circuit PSW2 can be arranged in the bit cell area BCA or isolation area SPA.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/JP2022/036488 2021-09-30 2022-09-29 半導体装置 Ceased WO2023054602A1 (ja)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024252660A1 (ja) * 2023-06-09 2024-12-12 株式会社ソシオネクスト 半導体装置
WO2024252661A1 (ja) * 2023-06-09 2024-12-12 株式会社ソシオネクスト 半導体装置
TWI886843B (zh) * 2023-10-10 2025-06-11 台灣積體電路製造股份有限公司 記憶體裝置及其製造方法
WO2025169463A1 (ja) * 2024-02-09 2025-08-14 株式会社ソシオネクスト 半導体装置
WO2025169464A1 (ja) * 2024-02-09 2025-08-14 株式会社ソシオネクスト 半導体装置
WO2026074865A1 (ja) * 2024-10-04 2026-04-09 株式会社ソシオネクスト 半導体集積回路装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251835A (ja) * 2007-03-30 2008-10-16 Renesas Technology Corp 半導体装置
JP2016035966A (ja) * 2014-08-01 2016-03-17 株式会社東芝 半導体集積回路装置
JP2017028085A (ja) * 2015-07-22 2017-02-02 富士通株式会社 半導体装置および半導体装置の制御方法
WO2020065916A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251835A (ja) * 2007-03-30 2008-10-16 Renesas Technology Corp 半導体装置
JP2016035966A (ja) * 2014-08-01 2016-03-17 株式会社東芝 半導体集積回路装置
JP2017028085A (ja) * 2015-07-22 2017-02-02 富士通株式会社 半導体装置および半導体装置の制御方法
WO2020065916A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024252660A1 (ja) * 2023-06-09 2024-12-12 株式会社ソシオネクスト 半導体装置
WO2024252661A1 (ja) * 2023-06-09 2024-12-12 株式会社ソシオネクスト 半導体装置
TWI886843B (zh) * 2023-10-10 2025-06-11 台灣積體電路製造股份有限公司 記憶體裝置及其製造方法
WO2025169463A1 (ja) * 2024-02-09 2025-08-14 株式会社ソシオネクスト 半導体装置
WO2025169464A1 (ja) * 2024-02-09 2025-08-14 株式会社ソシオネクスト 半導体装置
WO2026074865A1 (ja) * 2024-10-04 2026-04-09 株式会社ソシオネクスト 半導体集積回路装置

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