WO2023053904A1 - 撮像装置 - Google Patents

撮像装置 Download PDF

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Publication number
WO2023053904A1
WO2023053904A1 PCT/JP2022/033862 JP2022033862W WO2023053904A1 WO 2023053904 A1 WO2023053904 A1 WO 2023053904A1 JP 2022033862 W JP2022033862 W JP 2022033862W WO 2023053904 A1 WO2023053904 A1 WO 2023053904A1
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Prior art keywords
pixel
signal
pixels
output
section
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Ceased
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PCT/JP2022/033862
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English (en)
French (fr)
Japanese (ja)
Inventor
嘉晃 佐藤
康夫 三宅
雄介 岡田
佳壽子 西村
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to CN202280061303.7A priority Critical patent/CN117917092A/zh
Priority to JP2023550523A priority patent/JPWO2023053904A1/ja
Publication of WO2023053904A1 publication Critical patent/WO2023053904A1/ja
Priority to US18/599,298 priority patent/US12289543B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/47—Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present disclosure relates to imaging devices.
  • non-destructive readout is a readout of pixel signals in which signal charges accumulated in pixels are not reset and signal charges are read out in an exposed state. Pixel information during exposure can be obtained by performing non-destructive readout.
  • Japanese Patent Application Laid-Open No. 2002-200001 discloses an imaging device that achieves a high dynamic range by performing non-destructive readout.
  • JP 2007-194687 A Japanese Patent No. 6459025 WO2007/099850
  • An imaging device includes a plurality of pixels arranged in a matrix and a signal processing circuit, wherein the plurality of pixels is a plurality of first pixels that output pixel signals according to incident light. and a plurality of pixels arranged in a column direction in at least two columns and arranged in a column different from the plurality of first pixels for outputting a reset signal corresponding to an output signal of each of the plurality of first pixels upon resetting.
  • the signal processing circuit is configured to process the pixel signal output by one of the plurality of first pixels and the one of the plurality of second pixels; A difference from a reference signal based on the reset signal output by at least two second pixels located in the same row as one pixel is output.
  • An imaging device includes a plurality of pixels arranged in a matrix and a signal processing circuit, wherein the plurality of pixels is a plurality of first pixels that output pixel signals according to incident light. a plurality of pixels arranged in a row direction in at least two rows and arranged in a row different from the plurality of first pixels for outputting a reset signal corresponding to an output signal of each of the plurality of first pixels upon resetting; wherein the signal processing circuit is configured to process the pixel signal output by one of the plurality of first pixels and the one of the plurality of second pixels; A difference from a reference signal based on the reset signal output by at least two second pixels located in the same column as one pixel is output.
  • An imaging device includes a plurality of pixels arranged in a matrix and a signal processing circuit, wherein the plurality of pixels is a plurality of first pixels that output pixel signals according to incident light. and pixels arranged in a column direction in at least one column and arranged in a column different from the plurality of first pixels for outputting a first reset signal corresponding to an output signal of each of the plurality of first pixels upon resetting.
  • the signal processing circuit outputs the pixel signal output from one of the plurality of first pixels and the plurality of second pixels.
  • the first reset signal output by at least one second pixel positioned in the same row as the one first pixel among the plurality of third pixels, and the same column as the one first pixel among the plurality of third pixels and the difference from the reference signal based on the second reset signal output by the at least one third pixel positioned at .
  • FIG. 1 is a block diagram showing the overall configuration of an imaging device according to Embodiment 1.
  • FIG. 2 is a diagram illustrating an example of a circuit configuration of an imaging pixel according to Embodiment 1.
  • FIG. 3 is a diagram illustrating an example of a circuit configuration of a reference pixel according to Embodiment 1.
  • FIG. 4 is a diagram schematically showing signal amplitudes during non-destructive readout.
  • FIG. 5A is a diagram for explaining the positions of pixels to be read.
  • FIG. 5B is a diagram showing the difference in resistance due to the difference in the position of the pixels to be read.
  • FIG. 5C is a diagram showing a difference in voltage due to a difference in the position of pixels to be read.
  • FIG. 5A is a diagram for explaining the positions of pixels to be read.
  • FIG. 5B is a diagram showing the difference in resistance due to the difference in the position of the pixels to be read.
  • FIG. 5C is a diagram showing a difference in voltage
  • FIG. 5D is a diagram showing the difference in signal amplitude due to the difference in the position of the pixels to be read.
  • 6 is a diagram illustrating an example of a circuit configuration from a pixel to a column signal processing unit according to Embodiment 1.
  • FIG. 7 is a timing chart for explaining an example of signal processing in the imaging device according to the first embodiment.
  • FIG. 8 is a block diagram showing the overall configuration of an imaging device according to Embodiment 2.
  • FIG. 9 is a diagram showing a first circuit configuration example of a reference signal generation unit according to the second embodiment.
  • FIG. 10 is a diagram showing a second circuit configuration example of the reference signal generation unit according to the second embodiment.
  • FIG. 11 is a block diagram showing the overall configuration of an imaging device according to Embodiment 3.
  • FIG. 12 is a diagram illustrating a circuit configuration example of a reference signal selection unit according to the third embodiment
  • FIG. FIG. 13 is a block diagram showing the overall configuration of an imaging device according to Embodiment 4.
  • FIG. 14 is a diagram illustrating an example of a circuit configuration from a pixel to a column signal processing unit according to Embodiment 4.
  • FIG. 15 is a timing chart for explaining an example of signal processing in the imaging device according to the fourth embodiment.
  • FIG. 16 is a block diagram showing the overall configuration of an imaging device according to Embodiment 5.
  • FIG. 17 is a block diagram showing the overall configuration of an imaging device according to Embodiment 6.
  • FIG. 18 is a block diagram showing the overall configuration of an imaging device according to Embodiment 7.
  • FIG. 19 is a diagram illustrating a circuit configuration example of a reference signal generation unit according to a seventh embodiment
  • FIG. 20 is a diagram illustrating an example of a circuit configuration from a pixel to a column signal processing unit according to Embodiment 7.
  • FIG. 21 is a timing chart for explaining an example of signal processing in the imaging device according to the seventh embodiment.
  • FIG. 22 is a block diagram showing the overall configuration of an imaging device according to Embodiment 8.
  • FIG. 23A is a layout diagram showing an example in which the reference pixel section is arranged in the horizontal direction of the imaging pixel section.
  • FIG. 23A is a layout diagram showing an example in which the reference pixel section is arranged in the horizontal direction of the imaging pixel section.
  • FIG. 23B is a layout diagram showing another example in which the reference pixel section is arranged in the horizontal direction of the imaging pixel section.
  • FIG. 24A is a layout diagram showing an example of arranging the reference pixel portion in the vertical direction of the imaging pixel portion.
  • FIG. 24B is a layout diagram showing another example in which the reference pixel section is arranged in the vertical direction of the imaging pixel section.
  • Patent Document 2 discloses that high-speed nondestructive readout is realized by taking a difference between a pixel signal output from a pixel and a reset signal output from a reference signal generation unit. disclosed.
  • a reference signal generator that outputs a reset signal is arranged, for example, in a vertical OB (Optical Black) area.
  • Patent Document 3 discloses a configuration in which one reference pixel is provided for each row.
  • An imaging device includes a plurality of pixels arranged in a matrix and a signal processing circuit, wherein the plurality of pixels is a plurality of first pixels that output pixel signals according to incident light. and a plurality of pixels arranged in a column direction in at least two columns and arranged in a column different from the plurality of first pixels for outputting a reset signal corresponding to an output signal of each of the plurality of first pixels upon resetting.
  • the signal processing circuit is configured to process the pixel signal output by one of the plurality of first pixels and the one of the plurality of second pixels; A difference from a reference signal based on the reset signal output by at least two second pixels located in the same row as one pixel is output.
  • the imaging device can improve image quality in nondestructive readout.
  • an imaging device includes a plurality of pixels arranged in a matrix and a signal processing circuit, wherein the plurality of pixels output pixel signals corresponding to incident light. and a first pixel arranged in a row direction in at least two rows and arranged in a row different from the plurality of first pixels for outputting a reset signal corresponding to an output signal of each of the plurality of first pixels upon resetting.
  • the signal processing circuit comprises: the pixel signal output by one of the plurality of first pixels; and the pixel signal output by one of the plurality of first pixels; A difference between a reference signal based on the reset signal output by at least two second pixels located in the same column as the one first pixel and a reference signal is output.
  • the imaging device can improve image quality in nondestructive readout.
  • the reset signals output by the at least two second pixels may be combined and output to the signal processing circuit.
  • a reference signal obtained by synthesizing reset signals output by two or more second pixels can be used for nondestructive readout. Therefore, even if one of the second pixels has a defect, the effect of the defect can be reduced by averaging the reset signals.
  • the imaging device further includes a selection circuit electrically connected to the at least two second pixels, and the selection circuit selects one of the reset signals output by the at least two second pixels. At least one may be selected and output to the signal processing circuit.
  • At least one of the reset signals output by the two or more second pixels can be selected and used as a reference signal for nondestructive readout. Therefore, even if one of the second pixels is defective, the effect of the defect can be reduced by selecting the reset signal output by the normal second pixel.
  • the imaging device may further include a buffer circuit provided after the at least two second pixels and before the signal processing circuit.
  • the signal can be output to the signal processing circuit at low impedance, and the drive capability of the signal output to the signal processing circuit can be increased.
  • the imaging device further includes an offset circuit provided after the at least two second pixels and before the signal processing circuit, and the offset circuit positively affects an input signal.
  • a signal to which a negative voltage is added may be output to the signal processing circuit as the reference signal.
  • each of the plurality of pixels may include a photoelectric conversion unit that converts light into signal charges
  • each of the second pixels may include a light shielding unit that blocks light from entering the photoelectric conversion unit. good.
  • the configurations of the first pixel and the second pixel can be made similar, so that the difference between the reset signal and the voltage at the time of resetting the first pixel can be reduced.
  • each of the first pixels may include a photoelectric conversion unit that converts light into signal charges
  • each of the second pixels may not include a photoelectric conversion unit that converts light into signal charges
  • the second pixel can output a reset signal without providing a mechanism such as a light shielding layer for preventing light from entering the photoelectric conversion element.
  • the degree of freedom in arranging pixels can be increased.
  • an imaging device includes a plurality of pixels arranged in a matrix and a signal processing circuit, wherein the plurality of pixels output pixel signals corresponding to incident light. and a first pixel arranged in a column direction in at least one column, and outputting a first reset signal corresponding to an output signal of each of the plurality of first pixels at the time of resetting, in a column different from the plurality of first pixels a plurality of second pixels arranged in a row direction in at least one row and outputting a second reset signal corresponding to an output signal of each of the plurality of first pixels upon resetting; and a plurality of third pixels arranged in a row different from the pixels, wherein the signal processing circuit processes the pixel signal output by one of the plurality of first pixels and the plurality of third pixels.
  • the reference signal based on the first reset signal output by the second pixel located in the same row as the first pixel and the second reset signal output by the third pixel located in the same column as the first pixel is By using it, in the non-destructive readout of the first pixel, it is possible to use a reference signal in which the deviation from the voltage at the time of resetting the first pixel due to the influence of the difference in pixel position in the column direction and the row direction is reduced. Moreover, by using the reference signal based on the first reset signal for the second pixel and the second reset signal for the third pixel, even if the second pixel or the third pixel has a defect, the effect of the defect can be reduced. Therefore, the imaging device according to this aspect can improve image quality in nondestructive readout.
  • the plurality of pixels are located in the same column as the at least one second pixel and in the same row as the at least one third pixel, and the output of each of the plurality of first pixels at reset further comprising at least one fourth pixel outputting a third reset signal corresponding to the signal, wherein the signal processing circuit outputs the pixel signal output by the one first pixel and the at least one second pixel output; output a difference between a reference signal based on the first reset signal, the second reset signal output by the at least one third pixel, and the third reset signal output by the at least one fourth pixel; You may
  • the reference signal based on the third reset signal output by the fourth pixel located in the same column as the second pixel and in the same row as the third pixel is generated.
  • ordinal numbers such as “first” and “second” do not mean the number or order of constituent elements unless otherwise specified. It is used for the purpose of distinguishing elements.
  • connection in the description of the circuit configuration in this specification means electrical connection unless otherwise specified.
  • Embodiment 1 Embodiment 1 will be described below.
  • FIG. 1 is a block diagram showing the overall configuration of an imaging device 200 according to this embodiment. First, the overall configuration of the imaging device 200 will be described with reference to FIG.
  • an imaging device 200 includes a pixel array section 10 including an imaging pixel section 11 and a reference pixel section 12, a control section 30, a vertical scanning section 40, a column signal processing section 50, a horizontal scanning It includes a section 60, a first switch section 70A, and a second switch section 70B.
  • the imaging device 200 also includes current sources 21 and vertical signal lines 22 arranged for each pixel column of the pixel array section 10 , output signal lines 23 , and scanning lines 24 arranged for each pixel row of the pixel array section 10 . And prepare.
  • the pixel array section 10 is a pixel section including a plurality of pixels arranged in a matrix. That is, in the pixel array section 10, a plurality of pixels are arranged along the column direction and the row direction.
  • the column direction is the direction in which the vertical signal lines 22 extend in FIG. 1, and is also called the “vertical direction”.
  • the row direction is the direction in which the scanning lines 24 extend in FIG. 1, and is also referred to as the "horizontal direction.”
  • a plurality of pixels included in the pixel array section 10 includes a plurality of imaging pixels 100 and a plurality of reference pixels 110 .
  • the imaging pixel 100 is an example of a first pixel
  • the reference pixel 110 is an example of a second pixel.
  • Each of the multiple imaging pixels 100 outputs a pixel signal corresponding to incident light to the multiple imaging pixels 100 .
  • Each of the plurality of reference pixels 110 outputs a reset signal corresponding to the output signal of each of the plurality of imaging pixels 100 upon reset.
  • the reset signals output by the multiple reference pixels 110 are signals simulating voltages after the reset operation of the multiple imaging pixels 100 .
  • the imaging pixel section 11 is a pixel section in which a plurality of imaging pixels 100 are arranged in a matrix.
  • the reference pixel section 12 is a pixel section in which a plurality of reference pixels 110 are arranged in a matrix.
  • the reference pixel section 12 is arranged, for example, at the end of the pixel array section 10 in the row direction.
  • the reference pixel section 12 is located on the row direction side of the imaging pixel section 11 . That is, in the pixel array section 10, the imaging pixel section 11 and the reference pixel section 12 are arranged along the row direction.
  • the plurality of reference pixels 110 are arranged in columns different from the plurality of imaging pixels 100, and are arranged in the column direction in at least two columns.
  • a pixel row in which a plurality of reference pixels 110 are arranged along the column direction in the reference pixel section 12 may be referred to as a "reference pixel row”. That is, the reference pixel section 12 includes a plurality of reference pixel columns.
  • the number of imaging pixels 100 arranged in the column direction in the imaging pixel section 11 is the same as the number of reference pixels 110 arranged in the column direction in the reference pixel section 12 .
  • the current source 21 is connected to the vertical signal line 22 and arranged corresponding to the vertical signal line 22 . That is, one current source 21 is connected to each vertical signal line 22 .
  • the current source 21 constitutes a source follower circuit together with an amplification transistor included in the imaging pixel 100 or the reference pixel 110 and has a function of amplifying a voltage corresponding to charges accumulated in the imaging pixel 100 or the reference pixel 110 .
  • the vertical signal line 22 is provided corresponding to each pixel column of the pixel array section 10 and connected to each of the imaging pixels 100 or the reference pixels 110 in the same pixel column of the pixel array section 10 .
  • the vertical signal lines 22 corresponding to each reference pixel column connected to the reference pixel 110 of the reference pixel section 12 are connected to each other via the output signal line 23 .
  • the output signal line 23 is connected to the second switch section 70B.
  • the output signal line 23 connects the vertical signal lines 22 corresponding to each reference pixel column to each other, so that the reset signals output by the reference pixels 110 located in the same row are synthesized and sent to the column signal processing unit 50 as a reference signal. output.
  • the scanning line 24 is provided corresponding to each pixel row of the pixel array section 10 and connected to each of the imaging pixels 100 and the reference pixels 110 in the same pixel row of the pixel array section 10 . Also, the scanning line 24 is connected to the vertical scanning section 40 . Although one scanning line 24 is shown for each pixel row in FIG. 1 for convenience, the scanning line 24 may include a plurality of signal lines.
  • the vertical scanning unit 40 applies a predetermined voltage to the scanning line 24, thereby controlling the reset operation, charge accumulation operation, and readout operation of the imaging pixels 100 and the reference pixels 110 for each pixel row of the pixel array unit 10.
  • the column signal processing unit 50 processes the difference signal between the pixel signal output from the imaging pixel 100 and the signal corresponding to the output signal of the imaging pixel 100 when the imaging pixel 100 is reset, or the pixel signal output from the imaging pixel 100 and the It generates a difference signal from the reference signal based on the reset signal output from the reference pixel 110 of the reference pixel section 12 connected via the 2-switch section 70B. Further, the column signal processing unit 50 performs processing such as adding a gain to the difference signal and AD conversion, and outputs the difference signal according to an instruction from the horizontal scanning unit 60, which will be described later.
  • the column signal processing section 50 is an example of a signal processing circuit.
  • the first switch section 70A switches between inputting and blocking of pixel signals from the imaging pixels 100 to the column signal processing section 50 .
  • One end of the first switch section 70A is connected to the vertical signal line 22 connected to the imaging pixel 100 of the imaging pixel section 11 .
  • the other end of the first switch section 70A is connected to the column signal processing section 50 .
  • the first switch section 70A is arranged corresponding to the vertical signal line 22 of each pixel column of the imaging pixel section 11 .
  • the second switch section 70B switches between inputting and blocking the reference signal from the reference pixel 110 to the column signal processing section 50 .
  • One end of the second switch section 70B is connected to the vertical signal line 22 connected to the reference pixel 110 of the reference pixel section 12 via the output signal line 23 .
  • the other end of the second switch section 70B is connected to the column signal processing section 50 .
  • the second switch section 70B forms a pair with the first switch section 70A and is arranged corresponding to the vertical signal line 22 of each pixel column of the imaging pixel section 11 .
  • the horizontal scanning unit 60 has a function of sequentially selecting the differential signals for one row held in the column signal processing unit 50 and reading them out to an output circuit (not shown) arranged on the output side of the column signal processing unit 50 . .
  • the control unit 30 supplies various control signals to, for example, the vertical scanning unit 40, the column signal processing unit 50, the horizontal scanning unit 60, the first switch unit 70A, and the second switch unit 70B, thereby controlling each unit. circuit.
  • FIG. 2 is a diagram showing an example of the circuit configuration of the imaging pixel 100 according to Embodiment 1.
  • the imaging pixel 100 includes, for example, a photoelectric conversion element 101, a reset transistor 102, an amplification transistor 103, a selection transistor 104, and a charge storage unit 105.
  • the photoelectric conversion element 101 is a photoelectric conversion unit that photoelectrically converts incident light into signal charges.
  • Signal charges are, for example, holes or electrons. Although the case where the signal charges are holes will be described below, the signal charges may be electrons.
  • the photoelectric conversion element 101 has, for example, an upper electrode, a lower electrode, and a photoelectric conversion film sandwiched between the upper electrode and the lower electrode.
  • the photoelectric conversion film contains, for example, organic molecules with high light absorption ability.
  • the thickness of the photoelectric conversion film is, for example, about 500 nm.
  • the photoelectric conversion film is formed using, for example, a spin coating method or a vacuum deposition method.
  • the organic molecule has a high light absorption function over the entire visible light wavelength range of about 400 nm to about 700 nm.
  • a pair of holes and electrons is generated in the photoelectric conversion film by the incidence of light, and one of the holes and the electrons is captured by the upper electrode by applying a bias voltage between the upper electrode and the lower electrode. are collected and the other is collected on the bottom electrode.
  • the photoelectric conversion element included in the imaging pixel 100 according to the present embodiment is not limited to being composed of the organic photoelectric conversion film described above. good.
  • the charge storage unit 105 is connected to the photoelectric conversion element 101 and stores signal charges generated by the photoelectric conversion element 101 . In the charge accumulating portion 105, signal charges corresponding to light incident on the imaging pixels 100 are accumulated.
  • the charge storage unit 105 is also called a "floating diffusion node (FD)".
  • the amplification transistor 103 has a gate connected to the charge storage unit 105 , a drain supplied with the power supply voltage VDD, and a source connected to the drain of the selection transistor 104 . Thereby, the amplification transistor 103 forms a source follower circuit together with the current source 21 shown in FIG. 1 when the selection transistor 104 is in a conducting state. At this time, the source of the amplification transistor 103 outputs a signal corresponding to the amount of signal charge accumulated in the charge accumulation unit 105 to the vertical signal line 22 via the selection transistor 104 .
  • the selection transistor 104 has a drain connected to the source of the amplification transistor 103 , a source connected to the vertical signal line 22 , and a gate connected to the selection control signal line included in the scanning line 24 .
  • a selection control signal Vsel is supplied to the gate of the selection transistor 104 from a selection control signal line.
  • the selection transistor 104 becomes conductive when the selection control signal Vsel is at high level, and outputs the pixel signal from the amplification transistor 103 to the vertical signal line 22 . Also, the selection transistor 104 becomes non-conductive when the selection control signal Vsel is at low level, and isolates the amplification transistor 103 and the vertical signal line 22 .
  • the reset transistor 102 has a drain supplied with a reset voltage VR, a source connected to the charge storage section 105, and a gate connected to a reset control signal line included in the scanning line 24.
  • a reset control signal Vrst is supplied to the gate of the reset transistor 102 from a reset control signal line.
  • the reset transistor 102 becomes conductive when the reset control signal Vrst is at high level, and resets the potential of the charge storage section 105 to the reset voltage VR.
  • FIG. 3 is a diagram showing an example of the circuit configuration of the reference pixel 110 according to Embodiment 1. As shown in FIG. A description of the same configuration as that of the imaging pixel 100 is omitted.
  • the reference pixel 110 includes, for example, a reset transistor 102, an amplification transistor 103, a selection transistor 104, and a charge storage section 115.
  • the reference pixel 110 differs from the imaging pixel 100 in that it includes a charge storage unit 115 instead of the charge storage unit 105 and does not include the photoelectric conversion element 101 connected to the charge storage unit 115 .
  • the reference pixel 110 may have a configuration in which the charge accumulation portion 115 and the photoelectric conversion element 101 are not connected and the signal charge of the photoelectric conversion element 101 is not accumulated in the charge accumulation portion 115 .
  • the reference pixel 110 may have a configuration in which the photoelectric conversion element 101 not connected to the charge storage unit 115 is provided in the region where the reference pixel 110 is formed. A configuration in which the photoelectric conversion element 101 is not provided may be employed.
  • the source of the amplification transistor 103 of the reference pixel 110 outputs a signal corresponding to the amount of signal charge accumulated in the charge accumulation section 115 to the vertical signal line 22 via the selection transistor 104 . Since the reference pixel 110 does not include the photoelectric conversion element 101 , the potential of the charge storage section 115 does not change due to light incident on the reference pixel 110 . Therefore, the reference pixel 110 corresponds to the output signal according to the voltage of the charge storage unit 105 in which the signal charge generated by the photoelectric conversion element 101 after the reset operation of the imaging pixel 100 is not stored, regardless of the light irradiation state.
  • the reset transistor 102 is supplied with the reset voltage VR in the same manner as in the imaging pixel 100. Therefore, the reference pixel 110 receives a voltage corresponding to the voltage when the charge storage unit 115 is reset to the reset voltage VR. A signal can be output to the vertical signal line 22 as a reset signal. Further, the reference pixel 110 having such a configuration can output a reset signal without providing a mechanism for preventing light from entering the photoelectric conversion element 101 such as a light shielding layer described below. Therefore, the configuration of the reference pixel 110 can be simplified, and the degree of freedom in arranging the reference pixel 110 can be increased.
  • the pixel array section 10 is provided with a light-shielding pixel, which is called an OB pixel and provided with a light-shielding layer on the light incident side of the photoelectric conversion element 101 of the pixel.
  • a light shielding layer is an example of a light shielding part.
  • the reference pixel 110 may have the same pixel circuit configuration as the imaging pixel 100 if the reference pixel 110 includes a light shielding layer that blocks light from entering the photoelectric conversion element 101, like the OB pixel.
  • each of the plurality of pixels of the pixel array section 10 that is, each of the plurality of imaging pixels 100 and the plurality of reference pixels 110 includes a photoelectric conversion element 101, and each of the plurality of reference pixels 110 includes a light shielding layer. good too.
  • the configurations of the reference pixel 110 and the imaging pixel 100 can be made similar, so that the difference between the reset signal and the voltage when the imaging pixel 100 is reset can be reduced.
  • the imaging pixel 100 outputs pixel signals non-destructively, for example, without a reset operation. That is, the image pickup pixel 100 does not reset the accumulated signal charges in the middle of the accumulation period in which the signal charges generated by the photoelectric conversion elements 101 are accumulated in the charge accumulation unit 105, and the signal charges accumulated at that time are reset. to output a pixel signal corresponding to the amount of Such a read operation without reset operation is called non-destructive read. Non-destructive readout can also be performed multiple times within one frame period.
  • the imaging pixel 100 outputs a pixel signal corresponding to the amount of signal charges accumulated during the entire accumulation period. After that, the accumulated signal charges are reset to the reset voltage VR, and the imaging pixel 100 outputs a signal corresponding to the reset voltage VR.
  • Such a read operation accompanied by a reset operation is called destructive read.
  • the pixel readout in destructive readout uses the difference between the output voltage of the pixel in the state of accumulating the signal charge and the output voltage after the reset operation as a signal.
  • the non-destructive readout since the pixels are accumulating signal charges, the reset operation cannot be performed. Therefore, the difference between a certain reference voltage and the pixel output voltage is used as a signal. The reference voltage determines the zero level of the signal. Therefore, if there is a difference from the voltage after the reset operation of the pixel, which is the actual zero level, the signal is reduced or an extra offset is added, thereby compressing the signal range.
  • FIG. 4 is a diagram schematically showing signal amplitudes during non-destructive readout.
  • the vertical direction in FIG. 4 represents the voltage output to the vertical signal line.
  • Each graph in FIG. 4 shows the signal voltage and the reference voltage at the time of reading out the accumulated signal of the pixel input to the column signal processing section.
  • Signal amplitude is the difference between the signal voltage and the reference voltage.
  • graphs of three patterns (a), (b) and (c) are shown as reference voltages.
  • (a) shows the case where the reference voltage is the voltage when the target pixel is destructively read, that is, the voltage after the reset operation of the target pixel.
  • (b) shows a case where the reference voltage is higher than (a).
  • (c) shows a case where the reference voltage is lower than (a).
  • the signal amplitude A when the reference voltage is (a) is the original signal level.
  • the signal amplitude B when the reference voltage is higher than (a) (b) the low signal level collapses and the signal amplitude decreases.
  • the signal amplitude C when the reference voltage is (c) lower than (a) has an unnecessary offset component. Therefore, the contrast of the image is lowered.
  • the imaging apparatus is used with a high gain, such as when shooting in a low-illuminance environment, the signal amplitude that can be handled becomes small. Therefore, such signal reduction and offset components cause significant image quality deterioration.
  • the voltage after the reset operation of the pixel may differ depending on the position of the pixel.
  • FIG. 5A is a diagram for explaining the positions of pixels to be read.
  • FIG. 5B is a diagram showing the difference in resistance due to the difference in the position of the pixels to be read.
  • FIG. 5C is a diagram showing a difference in voltage due to a difference in the position of pixels to be read.
  • FIG. 5D is a diagram showing the difference in signal amplitude due to the difference in the position of the pixels to be read.
  • 5B and 5C respectively show differences in resistance and voltage when the input section of the first switch section 70A is used as a starting point.
  • pixel A and pixel B are connected to the same vertical signal line 22 and their positions are different in the vertical direction. Since the vertical signal line 22 has a constant wiring resistance, the resistance value differs depending on the position of the pixel as shown in FIG. 5B. The resistance value of the pixel B, which is far from the input section of the first switch section 70A, is higher than the resistance value of the pixel A. Further, since the signal voltage is read while a constant current is passed through the vertical signal line 22 by the current source 21, a voltage change occurs according to the wiring resistance as shown in FIG. 5C. The voltage of the pixel B, which is far from the input section of the first switch section 70A, becomes lower than the voltage of the pixel A because the amount of voltage drop is large.
  • the signal voltage is also different.
  • the signal amplitude will be different between the A pixel and the B pixel.
  • 5A to 5D described the difference in pixel position in the vertical direction, but the voltage at the time of reset may differ depending on the horizontal direction and the position of the pixel due to differences in resistance between the vertical signal lines 22, etc. .
  • the imaging device 200 is provided with a reference pixel section 12 including reference pixel columns for generating reference voltages corresponding to the plurality of imaging pixels 100 included in the imaging pixel section 11 . That is, in the present embodiment, a voltage based on the reset signal of the reference pixel 110 is used as the reference voltage.
  • a voltage based on the reset signal of the reference pixel 110 is used as the reference voltage.
  • the influence of defects can be reduced by including a plurality of reference pixel columns in the reference pixel section 12 .
  • the vertical signal lines 22 corresponding to each of the plurality of reference pixel columns are coupled to reduce the influence of defects in individual reference pixels 110 and vertical signal lines 22 .
  • FIG. 6 is a circuit diagram showing an example of the circuit configuration from the pixels to the column signal processing section 50.
  • FIG. 7 is a timing chart for explaining an example of signal processing in the imaging device 200 according to the first embodiment.
  • FIG. 6 shows, as a pixel circuit, one imaging pixel 100 included in the imaging pixel section 11 in the same pixel row of the pixel array section 10 among the plurality of imaging pixels 100 and the plurality of reference pixels 110, and the reference pixel 100 .
  • One reference pixel 110 included in the pixel portion 12 is shown. Therefore, signal lines are connected to the imaging pixel 100 and the reference pixel 110 so that the same reset control signal Vrst and selection control signal Vsel are supplied to the imaging pixel 100 and the reference pixel 110 shown in FIG.
  • the vertical signal lines 22 provided corresponding to each of the plurality of reference pixel columns of the reference pixel section 12 are connected via output signal lines 23. It is connected.
  • a current source transistor 20 is a current source transistor and shows an exemplary configuration of the current source 21 .
  • Current source transistor 20 is conductive during read operations.
  • the imaging pixel 100 is connected to the first switch section 70A, and the reference pixel 110 is connected to the second switch section 70B.
  • Each of the first switch section 70A and the second switch section 70B is, for example, a transistor.
  • a control signal Vs is supplied to the gate of the first switch section 70A through a signal line from the control section 30 .
  • the first switch section 70A connects the output of the imaging pixel 100 to the node Vout1 when the control signal Vs is at high level.
  • a control signal Vn is supplied to the gate of the second switch section 70B through a signal line from the control section 30 .
  • the second switch section 70B connects the output of the reference pixel 110 to the node Vout1 when the control signal Vn is at high level.
  • the column signal processing unit 50 includes a capacitive element 51, a transistor 52, a transistor 53, a transistor 54, a node 55, a node Vout2, and an ADC (Analog-to-Digital Converter) circuit 56.
  • ADC Analog-to-Digital Converter
  • the node Vout1 is connected to one end of the capacitive element 51 .
  • the other end of capacitive element 51 is connected to node 55 .
  • a voltage amplitude of the node Vout1 is output as a signal to the node Vout2 through a circuit including a capacitive element 51, a transistor 52, a transistor 53 and a transistor .
  • the transistor 52 is a control transistor for setting the potential of the node 55 to a reference state.
  • a control signal Vamp is supplied to the gate of the transistor 52 through a signal line from the control section 30 .
  • One end of transistor 52 is connected to node 55 .
  • the other end of transistor 52 is connected to node Vout2.
  • the transistor 53 is a current source transistor.
  • a power supply voltage VDD is supplied to the source of the transistor 53 .
  • the drain of transistor 53 is connected to node Vout2.
  • Transistor 53 is conductive during read operations.
  • the transistor 54 is the input transistor of the source follower circuit.
  • the gate of transistor 54 is connected to node 55 .
  • the source of transistor 54 is connected to node Vout2.
  • the drain of transistor 54 is connected to ground.
  • Transistor 54 forms a source follower circuit together with transistor 53 .
  • the ADC circuit 56 AD-converts the voltage amplitude of the node Vout2 and outputs it to the subsequent circuit.
  • FIG. 7 shows a timing chart of signals and the like related to nondestructive readout.
  • FIG. 7 shows voltage levels of the horizontal synchronization signal HD, the selection control signal Vsel, the control signal Vs, the control signal Vn, the control signal Vamp, the node Vout1, the node 55 and the node Vout2 in order from the top.
  • the horizontal synchronizing signal HD is, for example, a signal indicating the timing of pixel row transition, which is transmitted from the control unit 30 to the vertical scanning unit 40 .
  • the selection control signal Vsel is set to high level to turn on the selection transistors 104 of the imaging pixels 100 and the reference pixels 110 in the same pixel row.
  • the control signal Vs and the control signal Vamp are set to high level to turn on the first switch section 70A and the transistor 52 .
  • the signal of the imaging pixel 100 is output to the node Vout1.
  • signal charges corresponding to incident light are accumulated in the charge accumulation unit 105 of the imaging pixel 100 . Therefore, the imaging pixel 100 outputs a pixel signal corresponding to the incident light.
  • the voltage of node 55 becomes a predetermined initial voltage.
  • the voltage of the node Vout1 changes from the voltage state at time T1 and converges to a voltage corresponding to the level of the pixel signal of the imaging pixel 100 . Also, the voltage of the node Vout2 converges from the voltage state at time T1 to the voltage in the equilibrium state when the transistor 52 is turned on. In the present embodiment, since the signal charges are holes, the voltage at the node Vout1 increases according to the signal charge amount. decrease accordingly.
  • control signal Vs and the control signal Vamp are set to low level to turn off the first switch section 70A and the transistor 52. As a result, the node 55 becomes floating.
  • the control signal Vn is set to high level to turn on the second switch section 70B.
  • the signal of the reference pixel 110 is output to the node Vout1.
  • the reference pixel 110 no signal charge is accumulated in the charge accumulation portion 115 according to incident light. Therefore, the reference pixel 110 outputs a reset signal corresponding to the output signal of the imaging pixel 100 when it is reset.
  • the selection transistors 104 of at least two reference pixels 110 in the same pixel row are in the ON state, the reference signal, which is a signal obtained by averaging the reset signals output from the at least two reference pixels 110, is output to the node Vout1.
  • the reset signals output by the at least two reference pixels 110 are combined and output to the column signal processing section 50 .
  • the voltage of the node Vout1 changes from the voltage corresponding to the level of the pixel signal of the imaging pixel 100 and converges to the voltage corresponding to the level of the reference signal. Accordingly, the voltage of node 55 in the floating state changes via capacitive element 51, the resistance of transistor 54 whose gate is connected to node 55 changes, and the voltage of node Vout2 changes. By the operation so far, a voltage corresponding to the output voltage difference between the imaging pixel 100 and the reference pixel 110 is output to the node 55 and the node Vout2.
  • the control signal Vn is set to a low level to turn off the second switch section 70B, so that the voltages of the node 55 and the node Vout2 are held, and the voltages of the node 55 and the node Vout2 are AD-converted by the ADC circuit 56 in the subsequent stage. Processing is performed.
  • the column signal processing unit 50 calculates the difference between the pixel signal output by the imaging pixel 100 and the reference signal based on the reset signal output by at least two reference pixels 110 located in the same row as the imaging pixel 100. to output
  • the voltage corresponding to the output signal of the reference pixel 110 in the same row as the imaging pixel 100 is used as the signal level reference voltage (in other words, the reference signal).
  • the reference voltage can reduce the influence due to the difference in pixel position in the column direction and simulate the voltage after the reset operation of the imaging pixels 100 in the row. Addition of ingredients can be reduced.
  • reference signals are generated based on reset signals output by at least two reference pixels 110 .
  • the vertical signal lines 22 corresponding to each of a plurality of reference pixel columns are coupled, and the outputs of at least two reference pixels 110 are averaged. /or the effects of defects in the vertical signal line 22 can be reduced.
  • Embodiment 2 Next, an imaging device according to Embodiment 2 will be described. In the following description of the second embodiment, differences from the first embodiment will be mainly described, and descriptions of common points will be omitted or simplified.
  • FIG. 8 is a block diagram showing the overall configuration of the imaging device 201 according to the second embodiment.
  • the imaging device 201 according to the present embodiment further includes a reference signal generation unit 80 after the plurality of reference pixels 110 and before the column signal processing unit 50. It differs from the imaging device 200 according to the first embodiment.
  • the reference signal generation section 80 is connected to the vertical signal line 25 and also connected to the second switch section 70B corresponding to each pixel column of the imaging pixel section 11 via the output signal line 23 .
  • the vertical signal lines 25 connect the vertical signal lines 22 arranged corresponding to the reference pixel columns of the reference pixel section 12 to each other.
  • the reference pixel 110 is connected to the reference signal generator 80 via the vertical signal line 22 and the vertical signal line 25 .
  • the reset signals of at least two reference pixels 110 in the same row are combined and averaged, as in the first embodiment.
  • the reference signal generator 80 is, for example, a buffer circuit or an offset circuit. A signal output from the reference pixel 110 is output to the column signal processing section 50 via the reference signal generating section 80 .
  • An example of the circuit configuration of the reference signal generation section 80 will be shown below, but the circuit configuration of the reference signal generation section 80 is not limited to the following example.
  • FIG. 9 is a diagram showing a first circuit configuration example of the reference signal generator according to the present embodiment.
  • the buffer circuit 80A may have, for example, a unity gain buffer configuration that feeds back the output of the amplifier 83 to the inverting input terminal.
  • Buffer circuit 80 A includes a switch 81 , a capacitive element 82 and an amplifier 83 .
  • the switch 81 is connected to the vertical signal line 25 and switches between inputting and blocking signals from the vertical signal line 25 to the amplifier 83 .
  • One end of the capacitive element 82 is connected to non-inverting input terminals of the switch 81 and the amplifier 83 .
  • the other end of the capacitive element 82 is connected to the ground. Since the switch 81 and the capacitive element 82 are provided in the signal input path from the reference pixel 110 to the non-inverting input terminal of the amplifier 83, the input signal can be sampled and held.
  • the amplifier 83 is, for example, an operational amplifier.
  • a non-inverting input terminal of the amplifier 83 is connected via the switch 81 to the vertical signal line 25 to which the signal from the reference pixel section 12 is output.
  • the output of amplifier 83 is fed back to the inverting input terminal of amplifier 83 .
  • the output of the amplifier 83 is also connected to the output signal line 23 .
  • the signal output by the reference pixel 110 of the reference pixel section 12, which is the input signal can be output at low impedance. Further, the buffer circuit 80A can increase the drive capability (that is, the output current) of the reference signal output to the output signal line 23. FIG. Therefore, the convergence of the voltage of the output destination of the buffer circuit 80A can be accelerated.
  • FIG. 10 is a diagram showing a second circuit configuration example of the reference signal generator according to the present embodiment.
  • the offset circuit 80B outputs a signal obtained by adding a positive or negative voltage to the input signal to the column signal processing section 50 as a reference signal.
  • the offset circuit 80B differs from the buffer circuit 80A in that it further includes a resistor 74, a switch 75, a current source 76, a current source 77 and a node 78.
  • the output of the amplifier 83 is connected to the ground via the resistor 74 via the node 78, and is also connected via the switch 75 to the inverting input terminal of the amplifier.
  • the output of the amplifier 83 is also connected to the output signal line 23 .
  • resistor 74 One end of the resistor 74 is connected to the ground. The other end of resistor 74 is connected to current source 76 and current source 77 via node 78 .
  • a switch 75 switches between inputting and cutting off feedback from the output of the amplifier 83 to the inverting input terminal of the amplifier 83 .
  • a current source 76 injects current into a node 78 to which a resistor 74 is connected.
  • Current source 77 draws current from node 78 to which resistor 74 is connected.
  • the current sources 76 and 77 are controlled so as not to operate simultaneously.
  • the operation of the offset circuit 80B is controlled by the controller 30, for example.
  • the switch 75 is turned off.
  • the current source 76 when the current source 76 is to be activated, current is supplied to the node 78 by the current source 76 , and a new current flows to the resistor 74 . voltage increases.
  • the current source 77 when the current source 77 is activated, current is drawn from the node 78 by the current source 77, and the current flowing through the resistor 74 is reduced. The voltage on line 23 goes low. Further, at this time, if the current sources 76 and 77 are left in a non-operating state, the voltage of the output signal line 23 does not change.
  • the amount of voltage change can be arbitrarily set.
  • the offset circuit 80B adjusts whether or not the current sources 76 and 77 are activated, and the amount of current flowing through the current sources 76 and 77, so that the input signal An arbitrary amount of positive or negative offset voltage can be added and output to the subsequent output signal line 23 . Therefore, even if the voltage of the reference pixel 110 deviates from the voltage after the reset operation of the imaging pixel 100, the reference signal can be finely adjusted by adding such an offset voltage.
  • the operation of the imaging device 201 is the same as that of the imaging device 200 described above, except that the output from the reference pixel 110 is output to the column signal processing section 50 via the reference signal generating section 80 .
  • Embodiment 3 Next, an imaging device according to Embodiment 3 will be described. In the following description of Embodiment 3, the differences from Embodiments 1 and 2 will be mainly described, and descriptions of common points will be omitted or simplified.
  • FIG. 11 is a block diagram showing the overall configuration of the imaging device 202 according to the third embodiment. As shown in FIG. 11, imaging device 202 according to the present embodiment is different from imaging device 200 according to Embodiment 1 in that it further includes reference signal selection section 90 electrically connected to reference pixel 110. different.
  • the reference signal selection section 90 is connected to the vertical signal line 22 corresponding to each reference pixel column of the reference pixel section 12 and the second switch section 70B.
  • the reference signal selection unit 90 selects at least one of the reset signals output to each of the plurality of vertical signal lines 22 corresponding to each reference pixel column of the reference pixel unit 12, and outputs it to the column signal processing unit 50 as a reference signal. do.
  • the reference signal selection section 90 is an example of a selection circuit. If more than one reset signal is selected, the two or more reset signals are combined.
  • FIG. 12 is a diagram showing a circuit configuration example of the reference signal selection section 90. As shown in FIG. FIG. 12 shows an example in which there are four reference pixel columns, but the number of reference pixel columns is not limited to four.
  • the reference signal selection section 90 can be composed of, for example, at least one switch group. In the example shown in FIG. 12 , the reference signal selection section 90 includes a switch group 91 and a switch group 92 .
  • the switches included in the switch group 91 are arranged, for example, corresponding to each reference pixel column.
  • the switch group 91 includes a plurality of switches composed of a switch 91A that switches between inputting and blocking of a signal from one of the adjacent vertical signal lines 22 and a switch 91B that switches between inputting and blocking of a signal from the other. Including pairs.
  • the output sides of switch 91A and switch 91B are combined and connected to one of switches in switch group 92 . Operations of the switch group 91 are controlled by a control signal 93 .
  • the switch group 92 includes a switch 92A that switches between the input and cutoff of a signal from one of the switch pairs of the adjacent switch group 91, and a switch 92B that switches between the input and cutoff of the signal from the other.
  • the output sides of switch 92A and switch 92B are coupled and connected to output signal line 23 .
  • the operation of switch group 92 is controlled by control signal 94 .
  • the control signal 93 selects which of the switches 91A and 91B of each switch pair should be turned on, and the control signal 94 selects which of the switches 92A and 92B should be turned on. .
  • the control signal 93 is high level, the switch 91A is turned on, and if the control signal 93 is low level, the switch 91B is turned on.
  • the control signal 94 is high level, the switch 92A is turned on, and when the control signal 94 is low level, the switch 92B is turned on.
  • the control signal 93 and the control signal 94 are input from the control section 30, for example.
  • the imaging device 202 since the imaging device 202 includes the reference signal selection unit 90, even if there is a defect in the reference pixel 110 and/or the vertical signal line 22 in a specific column in the reference pixel unit 12, the reference signal in another column can be detected. By selecting the reset signal output from the pixel 110 as the reference signal, the influence of the defect can be avoided.
  • the imaging device 202 may further include the reference signal generation unit 80 .
  • the output of the reference signal selection section 90 is input to the reference signal generation section 80 .
  • the influence of the defect of the reference pixel 110 can be avoided, the reference voltage can be output with low impedance, and the drivability of the output signal to the output signal line 23 can be improved.
  • the reset signal to be output to one vertical signal line 22 was selected, but it is not limited to this.
  • the reference signal selection unit 90 may, for example, select reset signals to be output to a plurality of vertical signal lines 22, combine the selected reset signals, and output the result as a reference signal.
  • the number of switch groups included in the reference signal selection section 90 may be one, or may be a switch group including switches arranged corresponding to each reference pixel column, like the switch group 91 . .
  • Each switch is controlled to be conductive or non-conductive by a control signal, for example.
  • Embodiment 4 Next, an imaging device according to Embodiment 4 will be described. In the following description of the fourth embodiment, the differences from the first to third embodiments will be mainly described, and descriptions of common points will be omitted or simplified.
  • FIG. 13 is a block diagram showing the overall configuration of the imaging device 203 according to the fourth embodiment.
  • an imaging device 203 according to the present embodiment has pixels including an imaging pixel portion 11 and a reference pixel portion 12A instead of a pixel array portion 10 including an imaging pixel portion 11 and a reference pixel portion 12. It differs from the imaging device 200 according to the first embodiment in that it includes an array section 10A.
  • the reference pixel section 12A is a pixel section in which a plurality of reference pixels 110 are arranged in a matrix.
  • the reference pixel section 12A is arranged, for example, at the end of the pixel array section 10A in the column direction.
  • the reference pixel section 12A is positioned on the column direction side of the imaging pixel section 11 . That is, in the pixel array section 10A, the imaging pixel section 11 and the reference pixel section 12A are arranged along the column direction.
  • the plurality of reference pixels 110 are arranged in a row different from that of the plurality of imaging pixels 100, and arranged in the row direction in at least two rows.
  • a pixel row in which a plurality of reference pixels 110 are arranged along the row direction in the reference pixel portion 12A may be referred to as a "reference pixel row”. That is, the reference pixel section 12A includes a plurality of reference pixel rows.
  • the number of imaging pixels 100 arranged in the column direction in the imaging pixel section 11 is the same as the number of reference pixels 110 arranged in the row direction in the reference pixel section 12A.
  • the reference pixels 110 of the reference pixel section 12A and the imaging pixels 100 of the imaging pixel section 11 arranged in the same column are connected to the same vertical signal line 22. Also, the reference pixel 110 and the imaging pixel 100 arranged in the same column are connected to the same current source 21 through the same vertical signal line 22 . Therefore, power consumption can be reduced.
  • Each vertical signal line 22 is also connected to the column signal processing section 50 .
  • the scanning line 24 is connected to each of the imaging pixels 100 or the reference pixels 110 in the same pixel row of the pixel array section 10A.
  • One of the plurality of reference pixel rows of the reference pixel section 12A is selected during the readout operation by a selection control signal from the vertical scanning section 40, for example. Therefore, at least one of the reset signals output by at least two reference pixels 110 connected to the same vertical signal line 22 is output to the column signal processing section 50 as a reference signal.
  • the reset signal output from the reference pixels 110 in another row can be selected as the reference signal. , the effect of defects can be avoided.
  • the circuit configured by the vertical scanning unit 40 and the selection transistor 104 of the reference pixel 110 is an example of a selection circuit.
  • FIG. 14 is a diagram showing an example of a circuit configuration from a pixel to a column signal processing section 50 according to the fourth embodiment.
  • FIG. 15 is a timing chart for explaining an example of signal processing in the imaging device 203 according to the fourth embodiment.
  • FIG. 14 shows, as a pixel circuit, one imaging pixel 100 included in the imaging pixel section 11 in the same pixel column of the pixel array section 10A among the plurality of imaging pixels 100 and the plurality of reference pixels 110, and the reference pixel 110.
  • One reference pixel 110 included in the pixel portion 12A is shown.
  • the reference pixel section 12A includes a plurality of reference pixel rows, and for example, one of them is selected during use. Which row is selected is determined, for example, by prior failure inspection or the like.
  • a current source transistor 20 is a current source transistor and shows a specific configuration of the current source 21.
  • the current source transistor 20 is connected to both the imaging pixel 100 and the reference pixel 110, but only one of them is connected at the same time by controlling the ON and OFF of the selection transistor 104 of each of the imaging pixel 100 and the reference pixel 110. is electrically connected to
  • the selection transistor 104 of the imaging pixel 100 may be referred to as a selection transistor 104A
  • the selection transistor 104 of the reference pixel 110 may be referred to as a selection transistor 104B.
  • the selection transistor 104A is controlled to be turned on and off by a selection control signal Vsel_A supplied to a selection control signal line included in the scanning line 24.
  • On/off control of the selection transistor 104B is performed by a selection control signal Vsel_B supplied to a selection control signal line included in the scanning line 24 .
  • the vertical signal line 22 is connected to one end of the capacitive element 51 .
  • Other configurations are the same as those in FIG. 6 described above.
  • FIG. 15 shows a timing chart of signals and the like related to nondestructive readout.
  • the control signal Vn in place of the control signal Vs, the control signal Vn, the selection control signal Vsel and the node Vout1 for the items of the timing chart of FIG. Twenty-two voltage levels are shown.
  • Other control signals and node types and operations in FIG. 15 are the same as those in the timing chart of FIG. 7, and redundant descriptions of operations will be omitted or simplified in the following description.
  • the selection control signal Vsel_A is a control signal that controls the selection transistor 104A of the imaging pixel 100.
  • a selection control signal Vsel_B is a control signal that controls the selection transistor 104B of the reference pixel 110 .
  • the same vertical signal line 22 is shared by the imaging pixels 100 and the reference pixels 110 in the same column. Therefore, which of the imaging pixel 100 and the reference pixel 110 is connected to the vertical signal line 22 is time-divisionally controlled by the selection control signal Vsel_A and the selection control signal Vsel_B.
  • the reset control signal Vrst the reset control signal Vrst_A and the reset control signal Vrst_B corresponding to the reset transistors 102 of the imaging pixel 100 and the reference pixel 110 are supplied at the same timing.
  • the selection control signal Vsel_A is set to high level to turn on the selection transistor 104A.
  • the control signal Vamp is set to high level to turn on the transistor 52 .
  • the pixel signal of the imaging pixel 100 is output to the vertical signal line 22 .
  • the voltage of node 55 becomes a predetermined initial voltage.
  • the voltage of the vertical signal line 22 changes from the voltage state at time T ⁇ b>1 and converges to a voltage corresponding to the level of the pixel signal of the imaging pixel 100 .
  • the voltage of the node Vout2 converges from the voltage state at time T1 to the voltage in the equilibrium state when the transistor 52 is turned on.
  • the selection control signal Vsel_A and the control signal Vamp are set to low level to turn off the selection transistor 104A and the transistor 52 .
  • the selection control signal Vsel_B is set to high level to turn on the selection transistor 104B.
  • the reset signal of the reference pixel 110 is output to the vertical signal line 22 as a reference signal.
  • the voltage of the vertical signal line 22 changes from the voltage corresponding to the level of the pixel signal of the imaging pixel 100 and converges to the voltage corresponding to the level of the reference signal.
  • the voltage of node 55 changes via capacitive element 51, and the voltage of node Vout2 changes.
  • a voltage corresponding to the output voltage difference between the imaging pixel 100 and the reference pixel 110 is output to the node 55 and the node Vout2.
  • the selection control signal Vsel_B is set to low level to turn off the selection transistor 104B, so that the voltages of the node 55 and the node Vout2 are held, and the ADC circuit 56 in the subsequent stage performs AD conversion processing. is carried out.
  • the column signal processing unit 50 is a signal selected from the pixel signal output by the imaging pixel 100 and the reset signal output by at least two reference pixels 110 located in the same column as the imaging pixel 100. Output the difference from the reference signal.
  • the voltage corresponding to the output signal of the reference pixel 110 in the same column as the imaging pixel 100 is used as the signal level reference voltage (in other words, the reference signal).
  • the reference voltage can reduce the influence of the pixel position difference in the row direction and simulate the voltage after the reset operation of the imaging pixels 100 in the corresponding column. Addition of the offset component can be reduced.
  • reference signals are generated based on reset signals output by at least two reference pixels 110 . This reduces the influence of the defective reference pixel 110 .
  • the reset signal output by one reference pixel 110 out of at least two reference pixels 110 located in the same column as the imaging pixel 100 is selected as the reference signal, but it is not limited to this.
  • the reset signals output by the two or more reference pixels 110 are synthesized and used as a reference signal. It may be output to the vertical signal line 22 . This can reduce the effects of defects in individual reference pixels 110 .
  • Embodiment 5 Next, an imaging device according to Embodiment 5 will be described.
  • the points of difference from the first to fourth embodiments will be mainly described, and the description of the common points will be omitted or simplified.
  • FIG. 16 is a block diagram showing the overall configuration of the imaging device 204 according to the fifth embodiment.
  • the reference pixel 110 of the reference pixel section 12A has a different vertical signal from the vertical signal line 22 connected to the imaging pixel 100 of the imaging pixel section 11. It differs from the imaging device 203 according to Embodiment 4 in that it is connected to the line 22A and that it further includes a first switch section 70A and a second switch section 70B.
  • the vertical signal line 22 is connected only to the imaging pixels 100 among the pixels arranged in the same column in the pixel array section 10A. Also, the vertical signal line 22 is connected to the current source 21 and the first switch section 70A.
  • the vertical signal line 22A is connected only to the reference pixel 110 among the pixels arranged in the same column in the pixel array section 10A. Also, the vertical signal line 22A is connected to the current source 21 and the second switch section 70B.
  • the vertical signal line 22 and the vertical signal line 22A are provided corresponding to each pixel column of the pixel array section 10A.
  • two current sources 21 are arranged for one pixel column of the pixel array section 10A.
  • the selection control signal Vsel_A and the selection control signal Vsel_B are supplied to the selection transistor 104A and the selection transistor 104B at the same timing as the selection control signal Vsel shown in FIG.
  • the timing at which the output signal from the imaging pixel 100 and the output signal from the reference pixel 110 are input to the column signal processing unit 50 is determined by the first switch unit 70A and the second switch unit 70B, as in the first embodiment. controlled.
  • a specific operation of the imaging device 204 according to this embodiment is the same as, for example, the timing chart shown in FIG.
  • the selection transistors 104 of the imaging pixel 100 and the reference pixel 110 can be turned on at the same time. Therefore, the imaging device 204 does not need to wait for the time from when the selection transistor 104A of the reference pixel 110 is turned on until the vertical signal line 22A converges. It is possible to increase the speed of destructive readout.
  • Embodiment 6 Next, an imaging device according to Embodiment 6 will be described. In the description of the sixth embodiment below, the differences from the first to fifth embodiments will be mainly described, and the description of the common points will be omitted or simplified.
  • FIG. 17 is a block diagram showing the overall configuration structure of the imaging device 205 according to the sixth embodiment. As shown in FIG. 17, an imaging device 205 according to the present embodiment differs from the imaging device 204 according to Embodiment 5 in that it further includes a reference signal generator 80C.
  • the reference signal generation section 80C is connected to the vertical signal line 22A connected to the reference pixel 110 of the reference pixel section 12A. Also, the reference signal generator 80C is connected to the second switch 70B via the output signal line 23 .
  • the configuration of the reference signal generation section 80C is, for example, the same configuration as the buffer circuit 80A shown in FIG. 9 or the offset circuit 80B shown in FIG.
  • the vertical signal line 22A is connected to the switch 81 instead of the vertical signal line 25 shown in FIGS.
  • the reference signal generator 80C includes, for example, multiple buffer circuits 80A or multiple offset circuits 80B.
  • Buffer circuit 80A or offset circuit 80B is arranged corresponding to vertical signal line 25 . That is, one buffer circuit 80A or one offset circuit 80B is connected to each vertical signal line 25 . Since the operation of the reference signal generator 80C is the same as that described in the second embodiment, the description is omitted.
  • the operation of the imaging device 205 is the same as that of the imaging device 204 described above, except that the output from the reference pixel 110 is output to the column signal processing unit 50 via the reference signal generation unit 80C.
  • Embodiment 7 Next, an imaging device according to Embodiment 7 will be described. In the following description of Embodiment 7, the differences from Embodiments 1 to 6 will be mainly described, and descriptions of common points will be omitted or simplified.
  • FIG. 18 is a block diagram showing the overall configuration of the imaging device 206 according to the seventh embodiment.
  • an imaging device 206 according to the present embodiment includes an imaging pixel section 11, a reference pixel section 12, and a reference pixel section 12 instead of the pixel array section 10 including the imaging pixel section 11 and the reference pixel section 12. It differs from the imaging device 200 according to the first embodiment in that it includes a pixel array section 10B including a section 12A and a reference pixel section 12B.
  • Imaging device 206 according to the present embodiment also differs from imaging device 200 according to Embodiment 1 in that it further includes reference signal generation section 180 and capacitive element 190 .
  • the imaging device 206 suppresses the influence of both the difference in voltage after the reset operation due to the difference in pixel position in the vertical direction and the difference in voltage after the reset operation due to the difference in pixel position in the horizontal direction. It is a configuration for the purpose of
  • the voltage difference after the reset operation due to the difference in pixel position in the vertical direction By adding this difference to the output signal of the reference pixel portion 12A located in the vertical direction of the imaging pixel portion 11, the influence of the voltage difference after the reset operation due to the difference in pixel position in both the vertical direction and the horizontal direction can be suppressed. It can be carried out.
  • the reference pixel section 12B is a pixel section in which a plurality of reference pixels 110 are arranged in a matrix.
  • the reference pixel section 12B is arranged, for example, at a corner of the pixel array section 10B.
  • the reference pixel section 12B is located on the diagonal side of the imaging pixel section 11 . That is, in the pixel array section 10B, the imaging pixel section 11 and the reference pixel section 12B are arranged in a diagonal direction.
  • reference pixels 110 included in the reference pixel section 12 are referred to as “reference pixels 110A”
  • reference pixels 110 included in the reference pixel section 12A are referred to as “reference pixels 110B”
  • reference pixels 110 included in the reference pixel section 12B are referred to as “reference pixels 110A”.
  • the included reference pixel 110 may be referred to as "reference pixel 110C.”
  • the reference pixel 110A is an example of a second pixel
  • the reference pixel 110B is an example of a third pixel
  • the reference pixel 110C is an example of a fourth pixel.
  • the reset signal output by the reference pixel 110A is referred to as “first reset signal”
  • the reset signal output by the reference pixel 110B is referred to as “second reset signal”
  • the reset signal output by the reference pixel 110C is referred to as “second reset signal”. It may be called a "third reset signal”.
  • the plurality of reference pixels 110C are arranged in a matrix so as to be positioned in the same column as the reference pixel column in the reference pixel section 12 and in the same row as the reference pixel row in the reference pixel section 12A. . That is, each of the plurality of reference pixels 110C is positioned in the same column as one of the plurality of reference pixels 110A and in the same row as one of the plurality of reference pixels 110B.
  • a reference pixel 110C located in the same column as each reference pixel column is also connected to the vertical signal line 22 corresponding to each reference pixel column connected to the reference pixel 110A.
  • the scanning line 24 corresponding to each reference pixel row connected to the reference pixel 110B is also connected to the reference pixel 110C located in the same row as each reference pixel row.
  • the reference signal generator 180 is connected to the vertical signal line 25 and the output signal line 23 . Signals output from the reference pixel 110A and the reference pixel 110C are output to the column signal processing section 50 via the reference signal generating section 180. FIG.
  • the output signal line 23 outputs the output of the reference pixel 110A of the reference pixel section 12 positioned in the horizontal direction of the imaging pixel section 11 and the reference pixel positioned in the diagonal direction of the imaging pixel section 11 as an output from the reference signal generation section 180. A difference from the output of the reference pixel 110C of the section 12B is output.
  • the capacitive element 190 is arranged corresponding to the vertical signal line 22 of each pixel column of the imaging pixel section 11 .
  • One end of the capacitive element 190 is connected to the output signal line 23 .
  • the other end of the capacitive element 190 is connected to the column signal processing section 50 .
  • FIG. 19 is a diagram showing a circuit configuration example of a reference signal generation unit according to this embodiment.
  • the difference output circuit 180A outputs, for example, the difference between the reset signal output by the reference pixel 110A and the reset signal output by the reference pixel 110C.
  • the differential output circuit 180A differs from the buffer circuit 80A shown in FIG. 9 in that it includes a capacitive element 84 and a switch 85 instead of the switch 81 and capacitive element 82.
  • the capacitive element 84 is located on the connection path between the amplifier 83 and the vertical signal line 25 through which the signals from the reference pixels 110A and 110C are output. One end of the capacitive element 84 is connected to the vertical signal line 25 . The other end of capacitive element 84 is connected to the non-inverting input terminal of amplifier 83 and switch 85 .
  • Switch 85 switches between inputting and cutting off power supply voltage VI to node 86 between amplifier 83 and capacitive element 84 .
  • the power supply voltage VI is a voltage for initializing the node 86, and sets the voltage of the node 86 to the power supply voltage VI when the switch 85 is on.
  • ON and OFF of the switch 85 is controlled by a control signal Vinit from the control section 30 . For example, the switch 85 is turned on when the control signal Vinit is at high level, and the switch 85 is turned off when the control signal Vinit is at low level.
  • FIG. 20 is a diagram showing an example of a circuit configuration from a pixel to a column signal processing section 50 according to the seventh embodiment.
  • FIG. 21 is a timing chart for explaining an example of signal processing in the imaging device 206 according to the seventh embodiment.
  • FIG. 20 illustration of circuits such as the reference signal generation unit 180 at the stage preceding the capacitive element 190 is omitted.
  • the circuit diagram shown in FIG. 20 is the same as the circuit diagram shown in FIG. 14 except that node 55 is connected to the other end of capacitive element 190 .
  • FIG. 21 shows a timing chart of signals and the like related to nondestructive readout.
  • the same selection control signal Vsel_A is supplied to the imaging pixels 100 and the reference pixels 110A located in the same row in the pixel array section 10B.
  • the same selection control signal Vsel_B is supplied to the reference pixels 110B and 110C located in the same row in the pixel array section 10B.
  • the selection control signal Vsel_A is set to high level to turn on the selection transistor 104A.
  • the control signal Vamp is set to high level to turn on the transistor 52 .
  • the pixel signal of the imaging pixel 100 is output to the vertical signal line 22 .
  • the voltage of node 55 becomes a predetermined initial voltage.
  • the voltage of the vertical signal line 22 changes from the voltage state at time T ⁇ b>1 and converges to a voltage corresponding to the level of the pixel signal of the imaging pixel 100 .
  • the voltage of the node Vout2 converges from the voltage state at time T1 to the voltage in the equilibrium state when the transistor 52 is turned on.
  • the selection control signal Vsel_A when the selection control signal Vsel_A is set to high level, the selection transistor 104 of the reference pixel 110A located in the same row as the imaging pixel 100 is also turned on at the same time. At time T2, the control signal Vinit is also brought to a high level to turn on the switch 85 . As a result, the first reset signal for the reference pixel 110A is output to the vertical signal line 25, and the voltage of the node 86 is reset to the power supply voltage VI.
  • the amplifier 83 Since the amplifier 83 has a unity-gain buffer configuration in which the output is fed back to the inverting input terminal, the same voltage as the voltage of the node 86 is output to the output signal line 23 at time T2.
  • the selection control signal Vsel_A, the control signal Vamp, and the control signal Vinit are set to low level to turn off the selection transistor 104A, the transistor 52, and the switch 85.
  • the selection control signal Vsel_B is set to high level to turn on the selection transistor 104B.
  • the second reset signal for the reference pixel 110B is output to the vertical signal line 22.
  • FIG. The voltage of the vertical signal line 22 changes from the voltage corresponding to the level of the pixel signal of the imaging pixel 100, and converges to the voltage corresponding to the level of the second reset signal of the reference pixel 110B. Accordingly, the voltage of node 55 changes via capacitive element 51, and the voltage of node Vout2 changes.
  • the node 86 is in a floating state because the switch 85 is off. Therefore, when the voltage of the vertical signal line 25 changes, the change is transmitted to the node 86 via the capacitive element 84 . Since the amplifier 83 has a unity-gain buffer configuration in which the output is fed back to the inverting input terminal, the same voltage as the voltage of the node 86 is output to the output signal line 23 .
  • the voltage of the vertical signal line 25 is the output voltage of the reference pixel 110A located in the same row as the imaging pixel 100.
  • the voltage of the vertical signal line 25 is the output voltage of the reference pixel 110C located in the same row as the reference pixel 110B, that is, the voltage at the end of the pixel in the vertical direction. Pixel output. Therefore, the difference in the signal voltage becomes the difference in the voltage after the reset operation due to the difference in pixel position in the vertical direction.
  • the selection control signal Vsel_B is set to a low level to turn off the selection transistor 104B, so that the voltages of the node 55 and the node Vout2 are held, and the AD conversion processing is performed by the ADC circuit 56 in the subsequent stage. be implemented.
  • the column signal processing unit 50 outputs the difference between the pixel signal output by the imaging pixel 100 and the reference signal.
  • the reference signal is a first reset signal output by the reference pixel 110A located in the same row as the imaging pixel 100, and a second reset signal output by the reference pixel 110B located in the same row as the imaging pixel 100.
  • the reference signal is, for example, a signal obtained by adding the difference between the voltage corresponding to the first reset signal and the voltage corresponding to the third reset signal to the voltage corresponding to the second reset signal.
  • the voltage corresponding to the output signal of the reference pixel 110B in the same column as the imaging pixel 100 is used as the signal level reference voltage. Furthermore, the influence of the difference in the output signals between the reference pixel 110A in the same row as the imaging pixel 100 and the reference pixel 110C in the same row as the reference pixel 110B is due to the difference in the voltage after the reset operation due to the difference in pixel position in the vertical direction. As an effect, it is removed from the reference voltage. As a result, the reference voltage can simulate the voltage after the reset operation of the imaging pixel 100 in consideration of the difference in pixel position in the vertical direction and the horizontal direction. Addition can be reduced.
  • the reference pixel 110A and the reference pixel 110B by providing a plurality of columns of the reference pixel 110A, and by providing a plurality of rows of the reference pixel 110B, it is possible to prevent the defect of the reference pixel 110A and/or the reference pixel 110B. We are trying to reduce the impact.
  • Embodiment 8 Next, an imaging device according to Embodiment 8 will be described. In the following description of the eighth embodiment, the differences from the first to seventh embodiments will be mainly described, and the description of the common points will be omitted or simplified.
  • FIG. 22 is a block diagram showing the overall configuration structure of the imaging device 207 according to the eighth embodiment.
  • the reference pixel 110B of the reference pixel section 12A has a different vertical signal from the vertical signal line 22 connected to the imaging pixel 100 of the imaging pixel section 11. It differs from the imaging device 206 according to Embodiment 7 in that it is connected to the line 22A and that it further includes a first switch section 70A and a second switch section 70B.
  • the connection configuration of the imaging pixel section 11, the reference pixel section 12A, the vertical signal line 22, the vertical signal line 22A, the first switch section 70A and the second switch section 70B is the same as that of the imaging device 204 according to the fifth embodiment.
  • the imaging device 207 can obtain the effects of both the fifth and seventh embodiments.
  • the imaging device 207 is capable of high-speed non-destructive readout, and the reference voltage simulates the voltage after the reset operation of the imaging pixel 100 in consideration of the difference in pixel positions in the vertical and horizontal directions. Therefore, it is possible to reduce the reduction in signal amplitude and the addition of unnecessary offset components.
  • the reference pixel section is one end in the row direction of the pixel array section, specifically the left end, or one end in the column direction of the pixel array section, specifically Although provided in the lower end portion, the arrangement of the reference pixel portion is not limited to this.
  • FIGS. 23A and 23B are layout diagrams showing an example of the case where the reference pixel section is arranged in the horizontal direction of the imaging pixel section.
  • the regions where the light shielding layer is provided are marked with halftone dots.
  • the reference pixel section 12 may be arranged on both the left and right sides of the imaging pixel section 11, that is, on both sides in the horizontal direction.
  • the imaging pixel unit 11 is also called an “effective pixel area”.
  • the reference pixel section 12 is also called a "reference pixel region”.
  • the pixel array section 10 may include a horizontal OB pixel section 13 including a plurality of OB pixels.
  • the horizontal OB pixel portion 13 is also called a “horizontal OB region”.
  • OB pixels are used, for example, as a reference for black.
  • the reference pixel section 12 may be arranged between the horizontal OB pixel section 13 and the imaging pixel section 11 .
  • the reference pixel section 12 is not provided with a light shielding layer, and the reference pixel 110 does not include the photoelectric conversion element 101 . Further, as shown in FIG.
  • the reference pixel portion 12 is arranged in a region further outside the horizontal OB pixel portion 13 so as to be horizontally aligned with the imaging pixel portion 11 with the horizontal OB pixel portion 13 interposed therebetween.
  • the reference pixel section 12 is provided with a light shielding layer
  • the reference pixel 110 is configured to include the light shielding layer and the photoelectric conversion element 101 .
  • FIGS. 24A and 24B are layout diagrams showing an example of arranging the reference pixel section in the vertical direction of the imaging pixel section.
  • the regions where the light shielding layer is provided are marked with halftone dots.
  • the reference pixel section 12A may be arranged, for example, both above and below the imaging pixel section 11, that is, on both sides in the vertical direction.
  • the pixel array section 10A may include a vertical OB pixel section 13A including a plurality of OB pixels.
  • the vertical OB pixel portion 13A is also called a "vertical OB region".
  • the reference pixel section 12A may be arranged between the vertical OB pixel section 13A and the imaging pixel section 11. As shown in FIG. In this case, for example, the reference pixel section 12 ⁇ /b>A is not provided with a light shielding layer, and the reference pixel 110 does not include the photoelectric conversion element 101 . Further, as shown in FIG.
  • the reference pixel section 12 may be arranged further outside the vertical OB pixel section 13A so as to be vertically aligned with the imaging pixel section 11 with the vertical OB pixel section 13A interposed therebetween. good.
  • the reference pixel section 12A is provided with a light shielding layer
  • the reference pixel 110 is configured to include the light shielding layer and the photoelectric conversion element 101 .
  • both ends of the pixel array section which are difficult to use as effective pixel areas due to a decrease in the accuracy of pixel signals, can be effectively used.
  • the reference pixel section 12 and the reference pixel section 12A may be provided with light shielding layers, and the reference pixel 110 may include the light shielding layer and the photoelectric conversion element 101.
  • the reference pixel section 12 and the horizontal OB pixel section 13 may be arranged only on one side of both sides of the imaging pixel section 11 in the horizontal direction.
  • the reference pixel section 12A and the vertical OB pixel section 13A may be arranged only on one side of both sides of the imaging pixel section 11 in the vertical direction.
  • the pixel signal is output first, and then the reference signal based on the reset signal is output, thereby outputting the difference signal.
  • the reference signal based on the reset signal may be output first, and then the pixel signal may be output to output the difference signal.
  • the period during which the control signal Vs and the control signal Vn are at high level may be switched.
  • the periods during which the selection control signal Vsel_A and the selection control signal Vsel_B are at high level may be interchanged.
  • the reference pixel section 12 includes at least two reference pixel columns, but the present invention is not limited to this.
  • the reference pixel section 12A includes at least two reference pixel rows, the number of reference pixel rows is not limited to this.
  • the number of reference pixel columns included in the reference pixel section 12 may be one.
  • the number of reference pixel rows included in the reference pixel section 12A may be one.
  • the number of reference pixels 110C included in the reference pixel section 12B may be one.
  • the pixel array section 10B includes the reference pixel section 12B, but the present invention is not limited to this.
  • the pixel array section 10B may not include the reference pixel section 12B.
  • the column signal processing unit 50 outputs the pixel signal output by the imaging pixel 100, the first reset signal output by the reference pixel 110A located in the same row as the imaging pixel 100, and the same column as the imaging pixel 100.
  • the reference signal is, for example, a signal obtained by synthesizing the first reset signal and the second reset signal, or one signal selected from the first reset signal and the second reset signal.
  • the imaging device according to the present disclosure is useful as various imaging devices. It can also be applied to applications such as digital cameras, digital video cameras, mobile phones with cameras, medical cameras such as electronic endoscopes, in-vehicle cameras, and robot cameras.

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