WO2023046103A1 - 一种放大器组件和相位移相方法 - Google Patents

一种放大器组件和相位移相方法 Download PDF

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Publication number
WO2023046103A1
WO2023046103A1 PCT/CN2022/121017 CN2022121017W WO2023046103A1 WO 2023046103 A1 WO2023046103 A1 WO 2023046103A1 CN 2022121017 W CN2022121017 W CN 2022121017W WO 2023046103 A1 WO2023046103 A1 WO 2023046103A1
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WIPO (PCT)
Prior art keywords
circuit
signal
amplifier
phase
adder
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Application number
PCT/CN2022/121017
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English (en)
French (fr)
Inventor
彭洋洋
李平
李阳
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广州慧智微电子股份有限公司
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Publication of WO2023046103A1 publication Critical patent/WO2023046103A1/zh
Priority to US18/479,104 priority Critical patent/US20240030874A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0294—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using vector summing of two or more constant amplitude phase-modulated signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/16—Networks for phase shifting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present application relates to phase shifter technology, in particular to an amplifier component and a phase shifting method.
  • the gain of the adder in the phase shifter is different for different phases, it is necessary to control the gain of the amplifier when the power amplification circuit of the subsequent stage of the adder performs power amplification.
  • the insertion phase of the amplifying circuit changes with the change of the gain under different gains, so it will significantly affect the phase shifting accuracy.
  • Embodiments of the present application are expected to provide an amplifier component and a phase shifting method.
  • the embodiment of the present application provides an amplifier component, including: a quadrature signal generator, an adder, and an amplification circuit; the output end of the quadrature signal generator is connected to the input end of the adder, so The quadrature signal generator is configured to generate quadrature signals; the output end of the adder is connected to the input end of the amplifying circuit, and the adder is configured to perform vector synthesis on the quadrature signals to output a first signal ;
  • the amplification circuit is configured to perform power amplification and phase compensation on the first signal, and output a second signal.
  • the amplifying circuit includes an amplifier and a phase compensation circuit; the amplifier is configured to amplify the power of the first signal; the phase compensation circuit is configured to perform phase compensation on the first signal compensate.
  • the input end of the phase compensation circuit is connected to the output end of the adder, the output end is connected to the amplifier, and the phase-compensated first signal is output.
  • the input terminal of the amplifier is connected to the output terminal of the adder, the output terminal is connected to the input terminal of the phase compensation circuit, and the amplified first signal is output.
  • the compensation phase of the phase compensation circuit is adjustable based on the gain and/or output power of the amplifier.
  • the phase compensation circuit has at least one compensation structure of "Pie type", "T type” and "L type”.
  • the amplifier component further includes a first isolation circuit, the input terminal of the first isolation circuit is connected to the output terminal of the amplification circuit, and is configured to isolate the output terminal of the amplification circuit , so as to isolate the interference of the lower-stage circuit of the amplifying circuit to the amplifying circuit.
  • the amplifier component further includes a second isolation circuit, the input end of the second isolation circuit is connected to the output end of the adder; the output end of the second isolation circuit is connected to the amplification circuit the input end of the adder; the second isolation circuit is configured to isolate the output end of the adder.
  • the amplifying circuit further includes an impedance matching circuit; the impedance matching circuit is configured to perform impedance matching on the input impedance, and/or output impedance, and/or interstage impedance of the amplifier.
  • the phase compensation circuit includes at least one of the following devices: an inductor, a capacitor, and a switch tube.
  • the amplifier is a differential amplifier.
  • phase shift method including:
  • a quadrature signal generator generates quadrature signals
  • the adder performs vector synthesis on the quadrature signals, and outputs the first signal
  • the amplifying circuit performs power amplification and phase compensation on the first signal, and outputs a second signal.
  • the embodiment of the present application provides another phase shifting method, including:
  • the amplifying circuit is controlled to perform power amplification and phase compensation on the first signal based on the second control signal, so that the amplifying circuit outputs a second signal.
  • the quadrature signal generator generates quadrature signals
  • the adder performs vector synthesis on the quadrature signals, and outputs the first signal
  • the amplifier circuit performs power amplification and phase compensation on the first signal
  • the output second signal is the in-phase signal after phase compensation, that is, the amplifying circuit can perform power amplification and phase compensation on the first signal, which reduces the influence of the amplifying circuit on the phase shifting accuracy due to the change of the insertion phase under different gains .
  • the present application provides a computer program product, including computer readable codes.
  • the controller in the amplifier component executes the above-mentioned third aspect. Steps of the phase-shifting method.
  • Fig. 1 is the composition circuit diagram of active phase shifter in the related art
  • FIG. 2 is a schematic diagram of the composition and structure of an amplifier component provided in an embodiment of the present application
  • FIG. 3 is a schematic diagram of the composition and structure of another amplifier component provided in the embodiment of the present application.
  • FIG. 4 is a schematic diagram of the composition and structure of another amplifier component provided in the embodiment of the present application.
  • FIG. 5 is a schematic diagram of the implementation flow of a phase shifting method provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of an implementation flow of another phase shifting method provided in the embodiment of the present application.
  • FIG. 7 is a schematic diagram of the implementation flow of another phase shifting method provided in the embodiment of the present application.
  • FIG. 8 is a schematic diagram of the implementation flow of another phase shifting method provided by the embodiment of the present application.
  • FIG. 9 is a schematic diagram of the implementation flow of another phase shifting method provided by the embodiment of the present application.
  • Fig. 10a is a schematic composition diagram of a phase compensation unit provided by an embodiment of the present application.
  • Fig. 10b is a schematic diagram of the composition and structure of a phase compensation unit provided by the embodiment of the present application.
  • Fig. 10c is a schematic diagram of the composition and structure of another phase compensation unit provided by the embodiment of the present application.
  • Fig. 10d is a schematic diagram of the composition and structure of another phase compensation unit provided by the embodiment of the present application.
  • Fig. 10e is a circuit diagram of a phase compensation unit provided by the embodiment of the present application.
  • FIG. 11 is a circuit diagram of an active phase shifter provided by an embodiment of the present application.
  • the terms “comprising”, “comprising” or any other variant thereof are intended to cover non-exclusive inclusion, so that a method or device comprising a series of elements not only includes the explicitly stated elements, but also include other elements not explicitly listed, or also include elements inherent in implementing the method or apparatus.
  • an element defined by the phrase “comprising a " does not exclude the presence of additional related elements (such as steps in the method or A unit in an apparatus, for example, a unit may be part of a circuit, part of a processor, part of a program or software, etc.).
  • Phase shifters are devices configured to generate multi-phase signals and are widely used in radio frequency systems. Phase shifters are mainly divided into active phase shifters and passive phase shifters. Among them, the characteristics of the active phase shifter are: small area, flexible and controllable, and can generate gain, but the linearity is limited. The characteristics of passive phase shifters are: stable phase, high linearity, but large area and loss.
  • Fig. 1 is the composition circuit diagram of the active phase shifter in the related art, as shown in Fig. 1, the active phase shifter comprises the interstage matching network (Inter stage Matching Network, IMN) 101, quadrature generator (Poly Phase Filter, PPF) 102, analog adder 103.
  • Inter stage Matching Network IMN
  • PPF Quadrature generator
  • the differential radio frequency signal is input to the input terminal of IMN 101, and IMN 101 performs network matching on the input differential radio frequency signal, and inputs the differential radio frequency signal after network matching into PPF 102, and generates four signals with the same amplitude and a phase interval of 90 degrees through PPF 102 quadrature signals (two positive output terminals I+, Q+ and two negative output terminals I-, Q-), and four quadrature signals with the same amplitude and a phase interval of 90 degrees are input to the analog adder 103, and the analog adder 103 responds to the external control signal to perform vector synthesis of four quadrature signals with the same amplitude and 90-degree phase interval, and outputs the radio frequency signal to the post-stage amplifier.
  • the IMN 101 includes a first inductor L1 and a second inductor L2, and L1 and L2 are connected in series with the input terminal and the input terminal of the PPF 102 respectively;
  • the PPF 102 is a two-order RC filter;
  • the analog adder 103 includes a quadrature path connected in sequence A selection unit 1031, a variable gain amplifier (Variable Gain Amplifier, VGA) 1032 and an adder 1033.
  • VGA variable Gain Amplifier
  • the two-stage RC filter includes eight resistors R1 to R8 and eight capacitors C4 to C11, wherein the series branch formed by series connection of R1 and R2 is connected to the input terminal and output terminal of the two-stage RC filter ( 1+); the series branch formed by R3 and R4 connected in series is connected between the input terminal and the output terminal (Q+) of the two-stage RC filter; the series branch formed by R5 and R6 connected in series is connected in the two-stage RC filter Between the input terminal and the third output terminal (1-); the series branch formed by R7 and R8 connected in series is connected between the input terminal of the two-stage RC filter and the fourth output terminal (Q-); C4 is connected across both ends of R3, the positive pole of C4 is connected to the input terminal; the negative pole of C5 is connected to the output terminal, the positive pole of C5 is connected to the common node of R1 and R2; the positive pole of C6 is connected to the input terminal, C6 The negative pole of C7 is connected to
  • the gain of the adder is different for different phase shifting phases, it is necessary to control the gain of the amplifying circuit in the case of performing power amplification by the amplifying circuit in the subsequent stage.
  • the insertion phase of the amplifying circuit at different gains changes with the gain of the amplifying circuit, which will significantly affect the phase shifting accuracy.
  • an embodiment of the present application provides an amplifier component.
  • the amplifier component includes: a quadrature signal generator 201 , an adder 202 and an amplification circuit 203 .
  • the output terminal of the quadrature signal generator 201 is connected to the input terminal of the adder 202, and the quadrature signal generator 201 is configured to generate quadrature signals.
  • the output end of the adder 202 is connected to the input end of the amplifying circuit 204, and the adder 202 is configured to perform vector synthesis on the quadrature signals to output a first signal.
  • the amplification circuit 203 is configured to perform power amplification and phase compensation on the first signal, and output a second signal.
  • the quadrature signals generated by the quadrature signal generator 201 may be four quadrature signals with the same amplitude and a phase interval of 90 degrees (two positive output terminals I+, Q+ and two negative output terminals I -, Q-); quadrature signal generator 201 can be able to generate four quadrature signals (two positive output terminals I+, Q+ and two negative output terminals I-, Q-) with the same amplitude and a phase interval of 90 degrees any generator.
  • quadrature signal generator 201 may be a two-stage RC filter.
  • the orthogonal signal may also include multiple sub-signals, for example, 8 sub-signals.
  • the phase difference between multiple sub-signals may also be other angles, for example, 45 degrees.
  • the amplifier component may further include a controller, and the controller may be an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a digital signal processor (Digital Signal Processor, DSP), Digital Signal Processing Device (Digital Signal Processing Device, DSPD), Programmable Logic Device (Programmable Logic Device, PLD), FPGA, Central Processing Unit (Central Processing Unit, CPU), controller, microcontroller, microprocessor at least one.
  • the controller may generate a first control signal for controlling the adder and a second control signal for controlling the amplifying circuit corresponding to the preset phase shift angle.
  • the preset phase shift angle may be determined according to an application scenario of the phase shifter. For example, in some application scenarios, the phase shifter needs to be shifted by 30° (degrees), and the corresponding preset phase shift angle is 30°.
  • both the first control signal and the second control signal may be switching signals for turning on or turning off the switching tube.
  • the first control signal and the second control signal may both be +12V (volt) voltage control signals or 0V voltage control signals.
  • the amplifying circuit 204 may include an amplifier and a phase compensation circuit for compensating the insertion phase of the amplifier.
  • the amplifier is configured to amplify the power of the first signal; the phase compensation circuit is configured to perform phase compensation on the first signal.
  • the input terminal of the phase compensation circuit is connected to the output terminal of the adder, the output terminal is connected to the amplifier, and the phase-compensated first signal is output.
  • the input end of the amplifier is connected to the output end of the adder, the output end is connected to the input end of the phase compensation circuit, and the amplified first signal is output.
  • the compensation phase of the phase compensation circuit is adjustable based on the gain and/or output power of the amplifier.
  • the phase compensation circuit has at least one compensation structure of "Pie type", "T type” and "L type".
  • the quadrature signal generator generates the quadrature signal
  • the controller Based on the first control signal, the quadrature signal is vector-combined, and the first signal is output;
  • the amplifying circuit performs power amplification and phase compensation on the first quadrature signal based on the second control signal, and the output second signal is:
  • the phase-compensated signal that is, different second control signals can be generated for different preset phase-shift angles, and the amplifying circuit can perform power amplification and phase compensation on the first signal based on different second control signals, reducing the cost of the amplifying circuit.
  • the embodiment of the present application provides another amplifier component. As shown in FIG. Two isolation circuits 306 .
  • the output terminal of the quadrature signal generator 301 is connected to the input terminal of the adder 302, and the quadrature signal generator 301 is configured to generate quadrature signals.
  • the output end of the adder 302 is connected to the input end of the second isolation circuit 306, and the adder 302 is configured to perform vector synthesis on the orthogonal signals to output the first signal.
  • the output terminal of the second isolation circuit 306 is connected to the input terminal of the amplifier 303, and the second isolation circuit 306 is configured to isolate the output terminal of the adder.
  • the output terminal of the amplifier 303 is connected to the input terminal of the phase compensation circuit 304, and the amplifier 303 is configured to amplify the power of the isolated first signal.
  • the output terminal of the phase compensation circuit 304 is connected to the first isolation circuit 305 and is configured to perform phase compensation on the isolated and amplified first signal, and output a second signal.
  • the first isolation circuit 306 is configured to isolate the output end of the amplification circuit, so as to isolate the interference of the lower-level circuit of the amplification circuit to the amplification circuit.
  • the amplifier component may further include a controller, the controller is respectively connected to the adder 302, the amplifier 303 and the phase compensation circuit 304, and the controller is configured to generate a first control signal based on a preset phase shift angle , the first sub-control signal and the second sub-control signal; the first control signal is configured to control the adder 302; the first sub-control signal is configured to control the gain of the amplifier 303; the second sub-control signal is configured to control the phase compensation circuit 304 Phase compensation angle.
  • the controller is respectively connected to the adder 302, the amplifier 303 and the phase compensation circuit 304, and the controller is configured to generate a first control signal based on a preset phase shift angle , the first sub-control signal and the second sub-control signal; the first control signal is configured to control the adder 302; the first sub-control signal is configured to control the gain of the amplifier 303; the second sub-control signal is configured to control the phase compensation circuit 304 Phase compensation angle.
  • the output end of the adder 302 is connected to the input end of the second isolation circuit 306, and the adder 302 is configured to perform vector synthesis on the quadrature signals based on the first control signal, and output the first signal.
  • the output terminal of the second isolation circuit 306 is connected to the input terminal of the amplifier 303, and the second isolation circuit 306 is configured to isolate the output terminal of the adder.
  • An output terminal of the amplifier 303 is connected to an input terminal of the phase compensation circuit 304, and the amplifier 303 is configured to amplify the power of the isolated first signal based on the first sub-control signal.
  • the output terminal of the phase compensation circuit 304 is connected to the first isolation circuit 305 and is configured to perform phase compensation on the isolated and amplified first signal based on the second sub-control signal, and output a second signal.
  • the first isolation circuit 305 is configured to isolate the output terminal of the amplifier circuit, so as to isolate the interference of the amplifier circuit from the lower circuit of the amplifier circuit.
  • the amplifier 303 includes a switch tube, and the switch tube can adjust the gain of the amplifier 303 in response to the first sub-control signal.
  • the second sub-control signal may be a switch signal determined according to the insertion phase of the amplifier 303 at a preset phase shift angle.
  • the phase compensation circuit 304 may perform phase compensation on the power amplified first signal in response to the switch signal determined based on the insertion phase, to obtain the third signal.
  • the second isolation circuit isolates the output end of the adder, and the amplifier performs power amplification on the isolated first signal; the phase compensation circuit performs phase compensation on the power amplified first signal; the first isolation circuit The output terminal of the amplifying circuit is isolated to isolate the interference of the lower circuit of the amplifying circuit to the amplifying circuit.
  • the obtained second signal has higher isolation and higher phase shift precision.
  • FIG 4 is a schematic diagram of the composition and structure of another amplifier component provided by the embodiment of the present application.
  • the amplifier component includes: a quadrature signal generator 401, an adder 402, an impedance matching circuit 403, an amplifier 404, a phase compensation circuit 405 , a first isolation circuit 406 and a second isolation circuit 407 .
  • the output terminal of the quadrature signal generator 401 is connected to the input terminal of the adder 402, and the quadrature signal generator 401 is configured to generate quadrature signals.
  • the output end of the adder 402 is connected to the input end of the second isolation circuit 407, and the adder 402 is configured to perform vector synthesis on the orthogonal signals and output the first signal.
  • the output end of the second isolation circuit 407 is connected to the input end of the impedance matching circuit 403, and the second isolation circuit 407 is configured to isolate the output end of the adder.
  • the impedance matching circuit 403 is connected to the amplifier 404 and configured to perform impedance matching on the input impedance, and/or the output impedance, and/or the interstage impedance of the amplifier 404 in response.
  • the output terminal of the amplifier 404 is connected to the input terminal of the phase compensation circuit 405 , and the amplifier 404 is configured to amplify the power of the isolated first signal based on the adjusted impedance matching circuit 403 .
  • the output end of the phase compensation circuit 405 is connected to the second isolation circuit 407 and is configured to perform phase compensation on the isolated and power amplified first signal.
  • the first isolation circuit 406 is configured to isolate the output terminal of the amplification circuit, so as to isolate the interference of the lower circuit of the amplification circuit to the amplification circuit.
  • the impedance matching circuit 403 may include devices such as resistors and capacitors to perform impedance matching on the input impedance, and/or output impedance, and/or inter-stage impedance of the amplifier 404 . Adjustment of the amplification factor of the amplifier 404 can be realized.
  • the gain of the amplifier can be adjusted by adjusting the input resistance of the impedance matching circuit of the amplifier or the adjustment resistance between the input terminal and the output terminal of the amplifier through the first sub-control signal, so that the output power of the amplifier can be meet power requirements.
  • the amplifier component further includes a controller, the controller is connected to the adder 402, the impedance matching circuit 403 and the phase compensation circuit 405, and the controller is configured to generate the first control signal based on the preset phase shift angle , the first sub-control signal and the second sub-control signal; the first control signal is used to control the adder 402; the first sub-control signal is used to control the gain of the amplifier 404; the second sub-control signal is used to control the phase compensation circuit 405 Phase compensation angle.
  • the controller is connected to the adder 402, the impedance matching circuit 403 and the phase compensation circuit 405, and the controller is configured to generate the first control signal based on the preset phase shift angle , the first sub-control signal and the second sub-control signal; the first control signal is used to control the adder 402; the first sub-control signal is used to control the gain of the amplifier 404; the second sub-control signal is used to control the phase compensation circuit 405 Phase compensation angle.
  • the phase compensation circuit includes at least one of the following devices: an inductor, a capacitor, and a switch tube.
  • the switching tube represents a semiconductor device that can be used for switching.
  • the switch tube may be a triode, or a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSET).
  • MOSET Metal-Oxide-Semiconductor Field-Effect Transistor
  • phase compensation circuit can be formed by combining inductors and capacitors in series and parallel. At the same time, by connecting the capacitor or inductor in series with the switch tube in the phase compensation circuit, the inductance of the inductor or the capacitive reactance of the capacitor in the phase compensation circuit can be changed, so that for different compensation phases, different switch tubes can be controlled to turn on or off.
  • the amplifier is a differential amplifier.
  • the amplifier may also be an amplifier with a single-end input, and in this case, the output signal of the adder is a single-end signal, not a differential signal.
  • the embodiment of the present application provides a phase shift method, as shown in Figure 5, the method includes:
  • Step S501 the quadrature signal generator generates quadrature signals
  • Step S502 the adder performs vector synthesis on the orthogonal signals, and outputs the first signal
  • Step S503 the amplifying circuit performs power amplification and phase compensation on the first signal, and outputs a second signal.
  • Fig. 6 is a schematic diagram of the implementation flow of another phase shifting method provided by the embodiment of the present application. As shown in Fig. 6, the flow includes:
  • Step S601 the quadrature signal generator generates quadrature signals
  • Step S602 the adder performs vector synthesis on the orthogonal signals, and outputs the first signal
  • Step S603 the amplifier of the amplification circuit amplifies the power of the first signal
  • Step S604 the phase compensation circuit of the amplification circuit performs phase compensation on the amplified first signal, and outputs a second signal.
  • FIG. 7 is a schematic diagram of the implementation flow of another phase shifting method provided in the embodiment of the present application. As shown in FIG. 7, the flow includes:
  • Step S701 the quadrature signal generator generates quadrature signals
  • Step S702 the adder performs vector synthesis on the orthogonal signals, and outputs the first signal
  • Step S704 the amplifier of the amplification circuit amplifies the power of the first signal
  • Step S705 the phase compensation circuit of the amplifying circuit performs phase compensation on the amplified first signal
  • Step S706 the first isolation circuit isolates the output end of the amplifying circuit, so as to isolate the interference of the lower-level circuit of the amplifying circuit to the amplifying circuit.
  • Fig. 8 is a schematic diagram of the implementation flow of another phase shifting method provided by the embodiment of the present application. As shown in Fig. 8, the flow should be applicable to the controller, and the flow includes:
  • Step S801 Obtain a preset phase shift angle
  • Step S802 Generate a first control signal and a second control signal based on a preset phase shift angle; the first control signal is used to control the adder; the second control signal is used to control the amplifier circuit;
  • Step S803 Control the adder based on the first control signal to perform vector synthesis on the quadrature signal generated by the quadrature signal generator, so that the adder outputs the first signal;
  • Step S804 Control the amplifying circuit to perform power amplification and phase compensation on the first signal based on the second control signal, so that the amplifying circuit outputs the second signal.
  • FIG. 9 is a schematic diagram of the implementation flow of another phase shifting method provided in the embodiment of the present application. As shown in FIG. 9, the flow includes:
  • Step S901 Obtain a preset phase shift angle
  • Step S902 Generate a first control signal based on a preset phase shift angle; the first control signal is used to control the adder;
  • the first control signal is determined according to a preset phase shift angle.
  • the first control signal may include a sub-control signal for controlling the polarity of the quadrature signal and a sub-control signal for controlling the magnitude of the quadrature signal.
  • Step S903 Determine the gain of the adder corresponding to the preset phase shift angle
  • the gain of the adder for different phase shift angles is different.
  • the corresponding gain of the adder is 20; when the phase shift angle is 50°, the corresponding gain of the adder may be 30.
  • a gain mapping table between the phase shift angle and the gain of the adder may be formed in advance, and then, according to the gain mapping The table directly determines the gain of the adder corresponding to the preset phase shift angle.
  • Step S904 Determine the target gain of the amplifier and the gain sub-control signal according to the gain of the adder
  • the target gain of the amplifier can be determined according to the power output requirement.
  • the gain sub-control signal can be directly generated according to the target gain of the amplifier.
  • Step S905 Obtain a mapping table of amplifier gain and insertion phase
  • mapping table of amplifier gain and insertion phase can be obtained through experiments, or can be obtained directly from the data sheet of the amplifier.
  • Step S906 Determine the insertion phase corresponding to the target gain of the amplifier based on the mapping table
  • Step S907 Determine the target compensation angle of the phase compensation circuit based on the insertion phase corresponding to the target gain of the amplifier;
  • the target compensation angle of the phase compensation circuit may be the insertion phase corresponding to the gain of the amplifier.
  • Step S908 Generate a phase sub-control signal based on the target compensation angle
  • Step S909 Control the adder based on the first control signal to perform vector synthesis on the quadrature signal generated by the quadrature signal generator, so that the adder outputs the first signal;
  • Step S910 Control the amplifier in the amplifying circuit to amplify the power of the first signal based on the gain sub-control signal;
  • Step S911 Control the phase compensation circuit in the amplifying circuit to perform phase compensation on the amplified first signal based on the phase sub-control signal, so that the amplifying circuit outputs the second signal.
  • the insertion phase corresponding to the gain of the amplifier is determined through the mapping table of the gain of the amplifier and the insertion phase; the target compensation angle of the phase compensation circuit is determined based on the insertion phase corresponding to the gain of the amplifier; the phase element is generated based on the target compensation angle
  • the control signal controls the phase compensation circuit in the amplifying circuit to perform phase compensation on the amplified first signal based on the phase sub-control signal, so that the amplifying circuit outputs the second signal.
  • the phase shift of the second signal is closer to the preset phase shift angle, that is, the phase shift accuracy is higher.
  • FIG 10a is a schematic diagram of the composition of a phase compensation unit provided by the embodiment of the present application.
  • the phase compensation unit can be an adjustable matching network 1001, and the adjustable matching network 1001 is reasonably designed so that it can be tuned
  • the adjustable matching network 1001 enables Zin to be adjusted to an impedance point that matches the load impedance Zload of the adjustable matching network 1001 without adding additional matching network components.
  • Figure 10b is a schematic diagram of the composition and structure of a phase compensation unit provided by the embodiment of the present application.
  • Z1 is connected between the input terminal and the ground terminal of the phase compensation unit; one end of Z2 is connected to the phase compensation unit.
  • the other end of Z2 is connected to one end of Z3, and the other end of Z3 is connected to the ground end; the common node of Z2 and Z3 is the output end of the phase compensation unit.
  • Fig. 10c is a schematic diagram of the composition and structure of another phase compensation unit provided by the embodiment of the present application. As shown in Fig. 10c, the series branch formed by connecting Z4 and Z5 in series is connected between the input terminal and the ground terminal of the phase compensation unit. The common node of Z4 and Z5 is used as the output end of the phase compensation unit.
  • Figure 10d is a schematic diagram of the composition and structure of another phase compensation unit provided by the embodiment of the present application. As shown in Figure 10d, the series branch formed by connecting Z6 and Z7 in series is connected between the input end and the output end of the phase compensation unit. One end of Z8 is connected to the ground terminal, and the other end of Z8 is connected to the common node of Z6 and Z7.
  • Z1, Z2, Z3, Z4, Z5, Z6, Z7 and Z8 can be inductors, capacitors, resistors and transmission lines, can be fixed reactance values, or can be reactance values, at least one of which is a variable reactance value .
  • the realization of the variable reactance can be realized by using but not limited to the electronically adjustable varactor, variable capacitor array, switched inductor or resistor array.
  • Fig. 10e is a circuit diagram of a phase compensation unit provided by the embodiment of the present application.
  • the third inductor L3, the twelfth capacitor C12 to the seventeenth capacitor C17, the first switch K1 to the twenty-fourth switch K24 wherein, C12, K1 to K4 are connected in series to form the first series branch; C13, K5 to K8 are connected in series to form the second series branch; C14, K9 to K12 are connected in series to form the third series branch; C15, K13 to K16 are connected in series to form the first series branch Four series branches; C16, K17 to K20 are connected in series to form the fifth series branch; C17, K21 to K24 are connected in series to form the sixth series branch; the first to third series branches are connected in parallel to form the first parallel branch across the Between the input terminal and the ground terminal of the phase compensation unit; L3 is connected between the input terminal and the output terminal of the phase compensation unit; the second parallel branch formed by the parallel connection of the
  • Fig. 11 is the composition circuit diagram of the active phase shifter that the embodiment of the present application provides, as shown in Fig. 11, active filter comprises the interstage matching network (Inter stage Matching Network, IMN) 1101, PPF 1102, analog Adder 1103, transformer TF3 1104, eighteenth capacitor C18, amplifier 1105, phase compensation circuit 1106, nineteenth capacitor C19, transformer TF4 1107 and twentieth capacitor C20, wherein the equal-amplitude differential radio frequency signal is input to IMN 1101 At the input end, IMN 1101 performs network matching on the input equal-amplitude differential radio frequency signal, and inputs the equal-amplitude differential radio frequency signal after network matching into PPF 1102, and generates four quadrature signals with the same amplitude and 90° phase interval through PPF 1102.
  • Inter stage Matching Network IMN
  • PPF 1102 the interstage Matching Network
  • analog Adder 1103 eighteenth capacitor C18
  • amplifier 1105 the equal-amplitude differential radio frequency signal
  • phase compensation circuit 1106 nineteenth capacitor C19
  • C18 is connected between the two input terminals of the amplifier 1105, configured to remove electromagnetic interference interference
  • C19 and C20 are respectively connected between the two input terminals and two output terminals of the transformer TF4 1107, configured to remove the transformer Electromagnetic interference generated by TF4 1107.
  • IMN 1101 includes a fourth inductance L4 and a fifth inductance L5, and L4 and L5 are respectively connected in series with the input terminal and input terminal of PPF 1102; PPF 1102 is a two-order RC filter; A selection unit 1103', a variable gain amplifier (Variable Gain Amplifier, VGA) 1103" and an adder 1103"'.
  • VGA Variable Gain Amplifier
  • the two-stage RC filter includes eight resistors R9 to R16 and eight capacitors C21 to C28, wherein the series branch formed by series connection of R9 and R10 is connected to the input and output terminals of the two-stage RC filter ( 1+); the series branch formed by R11 and R12 connected in series is connected between the input terminal and the output terminal (Q+) of the two-stage RC filter; the series branch formed by R13 and R14 connected in series is connected in the two-stage RC filter Between the input terminal and the third output terminal (1-); the series branch formed by R15 and R16 connected in series is connected between the input terminal of the two-stage RC filter and the fourth output terminal (Q-); C21 is connected across both ends of R11, the positive pole of C21 is connected to the input terminal; the negative pole of C22 is connected to the output terminal, the positive pole of C22 is connected to the common node of R9 and R10; the positive pole of C23 is connected to the input terminal, and the positive pole of C23 is connected to
  • the negative pole of C24 is connected to the common node of R13 and R14; the negative pole of C24 is connected to the third output terminal, the positive pole of C24 is connected to the common node of R11 and R12; C25 is connected across the two ends of R15, and the positive pole of C25 is connected to On the input terminal; the negative pole of C26 is connected on the fourth output terminal, the positive pole of C26 is connected on the common node of R14 and R14; the positive pole of C27 is connected on the input terminal, and the negative pole of C27 is connected on the common node of R9 and R10; The negative pole of C28 is connected to the output terminal, and the positive pole of C28 is connected to the common node of R15 and R16.
  • the embodiment of the present application also provides a computer program product.
  • the computer program product includes a non-transitory computer-readable storage medium storing a computer program.
  • the computer program enables the computer to execute any phase shifting method described in the above method embodiments. Some or all steps of the method.
  • the quadrature signal generator generates the quadrature signal; the adder performs vector synthesis on the quadrature signal, and outputs the first signal; the amplifier circuit performs power amplification and phase compensation on the first signal, and outputs second signal. That is to say, the amplifying circuit can perform power amplification and phase compensation on the first signal based on different control signals, which reduces the influence of the amplifying circuit on the phase shifting accuracy due to the change of the insertion phase under different gains.

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Abstract

一种放大器组件和相位移相方法，该放大器组件包括：正交信号发生器（201）、加法器（202）和放大电路（203）；正交信号发生器（201）的输出端与加法器（202）的输入端连接，正交信号发生器（201）配置为产生正交信号；加法器（202）的输出端与放大电路（203）的输入端连接，加法器（202）配置为对正交信号进行矢量合成，输出第一信号；放大电路（203）配置为对第一信号进行功率放大和相位补偿，输出第二信号。

Description

一种放大器组件和相位移相方法
相关申请的交叉引用
本申请要求在2021年9月23日提交中国专利局、申请号为202111116040.9、申请名称为“一种多相位移相器和多相位移相方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及移相器技术，尤其涉及一种放大器组件和相位移相方法。
背景技术
相关技术中，由于移相器中的加法器对不同相位的增益不同，在加法器的后级放大电路进行功率放大的情况下，需要控制放大器增益。放大电路在不同增益下的插入相位是随着增益变化而变化的，如此，会显著影响移相精度。
发明内容
本申请实施例期望提供一种放大器组件和相位移相方法。
第一方面，本申请实施例提供了一种放大器组件，包括：正交信号发生器、加法器和放大电路；所述正交信号发生器的输出端与所述加法器的输入端连接，所述正交信号发生器配置为产生正交信号；所述加法器的输出端与所述放大电路的输入端连接，所述加法器配置为对所述正交信号进行矢量合成，输出第一信号；所述放大电路，配置为对所述第一信号进行功率放大和相位补偿，输出第二信号。
在一种实施方式中，所述放大电路包括放大器、相位补偿电路；所述放大器，配置为对所述第一信号进行功率放大；所述相位补偿电路，配置为对所述第一信号进行相位补偿。
在一种实施方式中，所述相位补偿电路的输入端与所述加法器的输出端相连接，输出端与所述放大器相连接，输出相位补偿后的所述第一信号。
在一种实施方式中，所述放大器的输入端与所述加法器的输出端相连 接，输出端与所述相位补偿电路的输入端相连接，输出放大后的所述第一信号。
在一种实施方式中，所述相位补偿电路的补偿相位基于所述放大器的增益及/或输出功率可调节。
在一种实施方式中，所述相位补偿电路具有“派型”、“T型”、“L型”至少其一的补偿结构。
在一种实施方式中，所述放大器组件还包括第一隔离电路，所述第一隔离电路的输入端与所述放大电路的输出端相连接，配置为对所述放大电路的输出端进行隔离，以隔离所述放大电路下级电路对所述放大电路的干扰。
在一种实施方式中，所述放大器组件还包括第二隔离电路，所述第二隔离电路的输入端连接所述加法器的输出端；所述第二隔离电路的输出端连接所述放大电路的输入端；所述第二隔离电路，配置为对所述加法器的输出端进行隔离。
在一种实施方式中，所述放大电路还包括阻抗匹配电路；所述阻抗匹配电路，配置为对所述放大器的输入阻抗，及/或输出阻抗，及/或级间阻抗进行阻抗匹配。
在一种实施方式中，所述相位补偿电路包括以下至少一种器件：电感、电容和开关管。
在一种实施方式中，所述放大器为差分放大器。
第二方面，本申请实施例提供了一种相位移相方法，包括：
正交信号发生器产生正交信号；
加法器对所述正交信号进行矢量合成，输出第一信号；
放大电路对所述第一信号进行功率放大和相位补偿，输出第二信号。
第三方面，本申请实施例提供了另一种相位移相方法，包括：
获取预设移相角度；
基于预设移相角度生成第一控制信号和第二控制信号；所述第一控制信号用于控制加法器；所述第二控制信号用于控制放大电路；
基于所述第一控制信号控制所述加法器对正交信号发生器生成的正交信号进行矢量合成，使得所述加法器输出第一信号；
基于所述第二控制信号控制所述放大电路对所述第一信号进行功率放大和相位补偿，使得所述放大电路输出第二信号。
在本申请实施例中，正交信号发生器产生正交信号，加法器对正交信号进行矢量合成，输出第一信号；放大电路对第一信号进行功率放大和相位补偿，输出的第二信号，输出的第二信号为相位补偿后的同相信号，即，放大电路可以对第一信号进行功率放大和相位补偿，降低了放大电路对于不同增益下的插入相位的变化对移相精度的影响。
第四方面，本申请提供一种计算机程序产品，包括计算机可读代码，在所述计算机可读代码在放大器组件中运行的情况下，所述放大器组件中的控制器执行上述第三方面的相位移相方法的步骤。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，而非限制本申请。
根据下面参考附图对示例性实施例的详细说明，本申请的其它特征及方面将变得清楚。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，这些附图示出了符合本申请的实施例，并与说明书一起用于说明本申请的技术方案。
图1为相关技术中有源移相器的组成电路图；
图2为本申请实施例提供的一种放大器组件的组成结构示意图；
图3为本申请实施例提供的又一种放大器组件的组成结构示意图；
图4为本申请实施例提供的再一种放大器组件的组成结构示意图；
图5为本申请实施例提供的一种相位移相方法的实现流程示意图；
图6为本申请实施例提供的另一种相位移相方法的实现流程示意图；
图7为本申请实施例提供的再一种相位移相方法的实现流程示意图；
图8为本申请实施例提供的又一种相位移相方法的实现流程示意图；
图9为本申请实施例提供的其它一种相位移相方法的实现流程示意图；
图10a为本申请实施例提供的一种相位补偿单元的组成原理图；
图10b为本申请实施例提供的一种相位补偿单元的组成结构示意图；
图10c为本申请实施例提供的另一种相位补偿单元的组成结构示意图；
图10d为本申请实施例提供的再一种相位补偿单元的组成结构示意图；
图10e为本申请实施例提供的一种相位补偿单元电路图；
图11为本申请实施例提供的有源移相器的组成电路图。
通过上述附图，已示出本申请明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本申请构思的范围，而是通过参考特定实施例为本领域技术人员说明本申请的概念。
具体实施方式
以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所提供的实施例仅仅用以解释本申请，并不用于限定本申请。另外，以下所提供的实施例是用于实施本申请的部分实施例，而非提供实施本申请的全部实施例，在不冲突的情况下，本申请实施例记载的技术方案可以任意组合的方式实施。
需要说明的是，在本申请实施例中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的方法或者装置不仅包括所明确记载的要素，而且还包括没有明确列出的其他要素，或者是还包括为实施方法或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括该要素的方法或者装置中还存在另外的相关要素(例如方法中的步骤或者装置中的单元，例如的单元可以是部分电路、部分处理器、部分程序或软件等等)。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，U和/或W，可以表示：单独存在U，同时存在U和W，单独存在W这三种情况。另外，本文中术语“至少一种”表示多种中的任意一种或多种中的至少两种的任意组合，例如，包括U、W、V中的至少一种，可以表示包括从U、W和V构成的集合中选择的任意一个或多个元素。
移相器是配置为产生多相位信号的器件，在射频系统中应用广泛。移相器主要分为有源移相器及无源移相器。其中，有源移相器特点是：面积小，灵活可控，可以产生增益，但线性度受限。无源移相器的特点是：相位稳定，线性度高，但面积大，有损耗。
图1为相关技术中有源移相器的组成电路图，如图1所示，有源移相器包括依次连接的级间匹配网络(Inter stage Matching Network，IMN)101、正交产生器(Poly Phase Filter，PPF)102、模拟加法器103。其中，差分射频信号输入IMN 101的输入端，IMN 101对输入的差分射频信号进行网络匹配，并将网络匹配后的差分射频信号输入PPF 102，通过PPF 102生成四个幅度相同且相位间距90度的正交信号(两个正输出端I+、Q+和两个负输出端I-、Q-)，并将四个幅度相同且相位间距90度的正交信号输入模拟加法器103，模拟加法器103响应来自外部的控制信号对四个幅度相同且相位间距90度的正交信号进行矢量合成，输出射频信号给后级放大器。
这里，IMN 101包括第一电感L1和第二电感L2，L1和L2分别串联在PPF 102的输入端和输入端；PPF 102为两阶RC滤波器；模拟加法器103包括依次连接的正交通路选择单元1031、可变增益放大器(Variable Gain Amplifier，VGA)1032和加法器1033。
可以理解的是，两阶RC滤波器包括八个电阻R1至R8和八个电容C4至C11，其中，R1和R2串联形成的串联支路连接在两阶RC滤波器的输入端和输出端(1+)之间；R3和R4串联形成的串联支路连接在两阶RC滤 波器的输入端和输出端(Q+)之间；R5和R6串联形成的串联支路连接在两阶RC滤波器的输入端和第三输出端之间(1-)之间；R7和R8串联形成的串联支路连接在两阶RC滤波器的输入端和第四输出端之间(Q-)之间；C4跨接在R3的两端，C4的正极连接在输入端上；C5的负极连接在输出端上，C5的正极连接在R1与R2的公共节点上；C6的正极连接在输入端上，C6的负极连接在R5和R6的公共节点上；C7的负极连接在第三输出端上，C7的正极连接在R3和R4的公共节点上；C8跨接在R7的两端，C8的正极连接在输入端上；C9的负极连接在第四输出端上，C9的正极连接在R5与R6的公共节点上；C10的正极连接在输入端上，C10的负极连接在R1和R2的公共节点上；C11的负极连接在输出端上，C11的正极连接在R7和R8的公共节点上。
相关技术中，由于加法器对不同移相相位的增益不同，在后级通过放大电路进行功率放大的情况下，需要控制放大电路的增益。放大电路在不同增益下的插入相位(在指定的频率上，通过放大器的相对相位移)随着放大电路增益的变化而变化，会显著影响移相精度。
基于上述技术问题，本申请实施例提供了一种放大器组件，如图2所示，所述放大器组件包括：正交信号发生器201、加法器202和放大电路203。
正交信号发生器201的输出端与加法器202的输入端连接，正交信号发生器201配置为产生正交信号。
加法器202的输出端与所述放大电路204的输入端连接，加法器202配置为对所述正交信号进行矢量合成，输出第一信号。
放大电路203，配置为对所述第一信号进行功率放大和相位补偿，输出第二信号。
在一些可能的实施方式中，正交信号发生器201产生的正交信号可以是四个幅度相同且相位间距90度的正交信号(两个正输出端I+、Q+和两 个负输出端I-、Q-)；正交信号发生器201可以是能够生成四个幅度相同且相位间距90度的正交信号(两个正输出端I+、Q+和两个负输出端I-、Q-)的任一发生器。例如，正交信号发生器201可以是两阶RC滤波器。
其他实施例中，正交信号也可以包括多个子信号，例如，8个。多个子信号之间的相位差也可以为其他角度，例如为45度。
在一种可能的实施方式中，所述放大器组件还可以包括控制器，所述控制器可以是特定用途集成电路(Application Specific Integrated Circuit，ASIC)、数字信号处理器(Digital Signal Processor，DSP)、数字信号处理装置(Digital Signal Processing Device，DSPD)、可编程逻辑装置(Programmable Logic Device，PLD)、FPGA、中央处理器(Central Processing Unit，CPU)、控制器、微控制器、微处理器中的至少一种。控制器可以生成与预设移相角度对应的控制加法器的第一控制信号和控制放大电路的第二控制信号。预设移相角度可以是根据移相器的应用场景所确定的。例如，在一些应用场景下，需要移相器移相30°(度)，则对应的预设移相角度为30°。
可以理解的是，第一控制信号和第二控制信号可以均是用于开通或关断开关管的开关信号。例如，第一控制信号和第二控制信号可以是均是+12V(伏)的电压控制信号或0V的电压控制信号。
在一种可能的实施方式中，放大电路204可以包括放大器和用于对放大器的插入相位进行补偿的相位补偿电路。所述放大器，配置为对所述第一信号进行功率放大；所述相位补偿电路，配置为对所述第一信号进行相位补偿。
在一种可能的实施方式中，相位补偿电路的输入端与加法器的输出端相连接，输出端与放大器相连接，输出相位补偿后的第一信号。
在一种可能的实施方式中，放大器的输入端与加法器的输出端相连接，输出端与相位补偿电路的输入端相连接，输出放大后的第一信号。
在一种可能的实施方式中，相位补偿电路的补偿相位基于放大器的增 益及/或输出功率可调节。
在一种可能的实施方式中，相位补偿电路具有“派型”、“T型”、“L型”至少其一的补偿结构。
在本申请实施例中，正交信号发生器产生正交信号，控制器基于预设移相角度生成用于控制加法器的第一控制信号和用于控制放大电路的第二控制信号，加法器基于第一控制信号对正交信号进行矢量合成，输出第一信号；放大电路基于第二控制信号对第一正交信号进行功率放大和相位补偿，输出的第二信号，输出的第二信号为相位补偿后的信号，即，对于不同的预设移相角度可以生成不同的第二控制信号，放大电路可以基于不同的第二控制信号对第一信号进行功率放大和相位补偿，降低了放大电路对于不同增益下的插入相位的变化所引起的移相精度问题。
本申请实施例提供了又一种放大器组件，如图3所示，该放大器组件可以包括：正交信号发生器301、加法器302、放大器303、相位补偿电路304、第一隔离电路305和第二隔离电路306。
正交信号发生器301的输出端与加法器302的输入端连接，正交信号发生器301配置为产生正交信号。
加法器302的输出端与第二隔离电路306的输入端连接，加法器302配置为对正交信号进行矢量合成，输出第一信号。
第二隔离电路306的输出端与放大器303的输入端连接，第二隔离电路306配置为对加法器的输出端进行隔离。
放大器303的输出端与相位补偿电路304的输入端连接，放大器303配置为对隔离后的第一信号进行功率放大。
相位补偿电路304的输出端与第一隔离电路305连接，配置为对隔离和功率放大后的第一信号进行相位补偿，输出第二信号。
第一隔离电路306，配置为对放大电路的输出端进行隔离，以隔离放大 电路下级电路对放大电路的干扰。
在一种可能的实施方式中，放大器组件还可以包括控制器，控制器分别与加法器302、放大器303和相位补偿电路304相连接，控制器配置为基于预设移相角度生成第一控制信号、第一子控制信号和第二子控制信号；第一控制信号配置为控制加法器302；第一子控制信号配置为控制放大器303的增益；第二子控制信号配置为控制相位补偿电路304的相位补偿角度。
加法器302的输出端与第二隔离电路306的输入端连接，加法器302配置为基于第一控制信号对正交信号进行矢量合成，输出第一信号。
第二隔离电路306的输出端与放大器303的输入端连接，第二隔离电路306配置为对加法器的输出端进行隔离。
放大器303的输出端与相位补偿电路304的输入端连接，放大器303配置为基于第一子控制信号对隔离后的第一信号进行功率放大。
所述相位补偿电路304的输出端与所述第一隔离电路305连接，配置为基于所述第二子控制信号对隔离和功率放大后的所述第一信号进行相位补偿，输出第二信号。
第一隔离电路305，配置为对放大电路的输出端进行隔离，以隔离放大电路下级电路对放大电路的干扰。
在一种可能的实施方式中，放大器303包括开关管，开关管响应第一子控制信号可以调整放大器303的增益。
可以理解的是，第二子控制信号可以是根据放大器303在预设移相角度下的插入相位所确定的开关信号。
在一种可能的实施方式中，相位补偿电路304可以响应基于插入相位所确定的开关信号对功率放大后的第一信号进行相位补偿，得到第三信号。
本申请实施例中，第二隔离电路对加法器的输出端进行隔离，放大器对隔离后的第一信号进行功率放大；相位补偿电路对功率放大后的第一信号进行相位补偿；第一隔离电路对放大电路的输出端进行隔离，以隔离放 大电路下级电路对放大电路的干扰。得到的第二信号的隔离度较高、移相精度也较高。
图4为本申请实施例提供的再一种放大器组件的组成结构示意图，如图4所示，放大器组件包括：正交信号发生器401、加法器402，阻抗匹配电路403、放大器404、相位补偿电路405、第一隔离电路406和第二隔离电路407。
正交信号发生器401的输出端与加法器402的输入端连接，正交信号发生器401配置为产生正交信号。
加法器402的输出端与第二隔离电路407的输入端连接，加法器402配置为对正交信号进行矢量合成，输出第一信号。
第二隔离电路407的输出端与阻抗匹配电路403的输入端连接，第二隔离电路407，配置为对加法器的输出端进行隔离。
阻抗匹配电路403与放大器404连接，配置为响应于对放大器404的输入阻抗，及/或输出阻抗，及/或级间阻抗进行阻抗匹配。
放大器404的输出端与相位补偿电路405的输入端连接，放大器404配置为基于调整后的阻抗匹配电路403对隔离后的第一信号进行功率放大。
相位补偿电路405的输出端与第二隔离电路407连接，配置为对隔离和功率放大后的第一信号进行相位补偿。
第一隔离电路406，配置为对放大电路的输出端进行隔离，以隔离放大电路下级电路对放大电路的干扰。
可以理解的是，阻抗匹配电路403可以是包括电阻和电容等器件，对放大器404的输入阻抗，及/或输出阻抗，及/或级间阻抗进行阻抗匹配。可以实现对放大器404的放大倍数的调整。
本申请实施例中，通过第一子控制信号调整放大器的阻抗匹配电路的输入电阻或在放大器的输入端与输出端之间的调节电阻，可以实现放大器的增益的调整，使得放大器输出的功率能够满足功率需求。
在一些可能的实施方式中，放大器组件还包括控制器，控制器别与加法器402、阻抗匹配电路403和相位补偿电路405相连接，控制器配置为基于预设移相角度生成第一控制信号、第一子控制信号和第二子控制信号；第一控制信号用于控制加法器402；第一子控制信号用于控制放大器404的增益；第二子控制信号用于控制相位补偿电路405的相位补偿角度。
在一些可能的实施方式中，相位补偿电路包括以下至少一种器件：电感、电容和开关管。
这里，开关管表示可以用于开关作用的半导体器件。例如，开关管可以是三极管，也可以是金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSET)。
可以理解的是，电容上的电压不能突变，电容上的电流相位提前电压相位90°；电感上的电流不能突变，电感上的电压相位提前电流相位90°。基于此，为了实现相位补偿，可以通过电感和电容的串并联组合而构成相位补偿电路。同时，通过在相位补偿电路中将电容或电感和开关管进行串联连接，可以改变相位补偿电路中，电感的感抗或电容的容抗，使得对于不同的补偿相位，可以控制不同的开关管开通或关断。
在一些可能的实施方式中，放大器为差分放大器。其他实施例中，放大器也可以为单端输入的放大器，此时加法器输出信号为单端信号，非差分信号。
在上述实施例的基础上，本申请实施例提供了一种相位移相方法，如图5所示，方法包括：
步骤S501：正交信号发生器产生正交信号；
步骤S502：加法器对正交信号进行矢量合成，输出第一信号；
步骤S503：放大电路对第一信号进行功率放大和相位补偿，输出第二信号。
图6为本申请实施例提供的另一种相位移相方法的实现流程示意图，如图6所示，流程包括：
步骤S601：正交信号发生器产生正交信号；
步骤S602：加法器对正交信号进行矢量合成，输出第一信号；
步骤S603：放大电路的放大器对第一信号进行功率放大；
步骤S604：放大电路的相位补偿电路对功率放大后的第一信号进行相位补偿，输出第二信号。
图7为本申请实施例提供的再一种相位移相方法的实现流程示意图，如图7所示，流程包括：
步骤S701：正交信号发生器产生正交信号；
步骤S702：加法器对正交信号进行矢量合成，输出第一信号；
步骤S704：放大电路的放大器对第一信号进行功率放大；
步骤S705：放大电路的相位补偿电路对功率放大后的第一信号进行相位补偿；
步骤S706：第一隔离电路对放大电路的输出端进行隔离，以隔离放大电路下级电路对放大电路的干扰。
图8为本申请实施例提供的又一种相位移相方法的实现流程示意图，如图8所示，流程应可以应用于控制器，流程包括：
步骤S801：获取预设移相角度；
步骤S802：基于预设移相角度生成第一控制信号和第二控制信号；第一控制信号用于控制加法器；第二控制信号用于控制放大电路；
步骤S803：基于第一控制信号控制加法器对正交信号发生器生成的正交信号进行矢量合成，使得加法器输出第一信号；
步骤S804：基于第二控制信号控制放大电路对第一信号进行功率放大和相位补偿，使得放大电路输出第二信号。
图9为本申请实施例提供的其它一种相位移相方法的实现流程示意图， 如图9所示，流程包括：
步骤S901：获取预设移相角度；
步骤S902：基于预设移相角度生成第一控制信号；第一控制信号用于控制加法器；
可以理解的是，第一控制信号是根据预设移相角度所确定的。第一控制信号可以包括控制正交信号的极性的子控制信号和用于控制正交信号的幅值的子控制信号。
步骤S903：确定预设移相角度对应的加法器的增益；
可以理解的是，加法器对不同移相角度的增益是不同的。例如，在移相角度为30°的情况下，加法器对应的增益是20；在移相角度为50°的情况下，加法器对应的增益可以是30。
在一种可能的实施方式中，移相角度和加法器的增益可以存在一定的对应关系，即，可以预先形成移相角度与加法器的增益之间的增益映射表，进而，可以根据增益映射表直接确定预设移相角度对应的加法器的增益。
步骤S904：根据加法器的增益确定放大器的目标增益和增益子控制信号；
这里，由于放大器组件的输出功率需要满足功率输出需求，因此，在放大器组件的加法器的增益确定的情况下，可以根据功率输出需求确定放大器的目标增益。
可以理解的是，在确定放大器的目标增益后，可以直接根据放大器的目标增益来生成增益子控制信号。
步骤S905：获取放大器的增益与插入相位的映射表；
可以理解的是，放大器的增益与插入相位的映射表可以通过试验获得，也可以是直接通过放大器的数据手册获取。
步骤S906：基于映射表确定放大器的目标增益对应的插入相位；
步骤S907：基于放大器的目标增益对应的插入相位确定相位补偿电路 的目标补偿角度；
在一种可能的实施方式中，相位补偿电路的目标补偿角度可以是放大器的增益对应的插入相位。
步骤S908：基于目标补偿角度生成相位子控制信号；
步骤S909：基于第一控制信号控制加法器对正交信号发生器生成的正交信号进行矢量合成，使得加法器输出第一信号；
步骤S910：基于增益子控制信号控制放大电路中的放大器对第一信号进行功率放大；
步骤S911：基于相位子控制信号控制放大电路中的相位补偿电路对功率放大后的第一信号进行相位补偿，使得放大电路输出第二信号。
本申请实施例中，通过放大器的增益与插入相位的映射表，确定放大器的增益对应的插入相位；基于放大器的增益对应的插入相位确定相位补偿电路的目标补偿角度；基于目标补偿角度生成相位子控制信号，基于相位子控制信号控制放大电路中的相位补偿电路对功率放大后的第一信号进行相位补偿，使得放大电路输出第二信号。第二信号的相移与预设移相角度更加接近，即，移相精度更高。
图10a为本申请实施例提供的一种相位补偿单元的组成原理图，如图10a所示，相位补偿单元可以为可调匹配网络1001，可调匹配网络1001经过合理的设计，使得可以通过调谐可调匹配网络1001，使得Zin都能被调到与可调匹配网络1001的负载阻抗Zload匹配的阻抗点，而且不需要增加额外的匹配网络元件。
图10b为本申请实施例提供的一种相位补偿单元的组成结构示意图，如图10b所示，Z1跨接在相位补偿单元的输入端与接地端之间；Z2的一端连接在相位补偿单元的输入端上，Z2的另一端连接在Z3的一端上，Z3的另一端连接在接地端上；Z2和Z3的公共节点为相位补偿单元的输出端。
图10c为本申请实施例提供的另一种相位补偿单元的组成结构示意图， 如图10c所示，Z4和Z5串联形成的串联支路跨接在相位补偿单元的输入端与接地端之间，Z4和Z5的公共节点作为相位补偿单元的输出端。
图10d为本申请实施例提供的再一种相位补偿单元的组成结构示意图，如图10d所示，Z6和Z7串联形成的串联支路跨接在相位补偿单元的输入端与输出端之间，Z8的一端连接在接地端，Z8的另一端连接在Z6和Z7的公共节点上。
这里，Z1、Z2、Z3、Z4、Z5、Z6、Z7和Z8可以为电感、电容、电阻及传输线，可以为固定电抗值，也可以为可电抗值，其中至少有一个是可变电抗值。其中，可变电抗的实现可以用但不局限于电调变容管、可变电容阵列、开关电感或电阻阵列。
图10e为本申请实施例提供的一种相位补偿单元电路图，如图10e所示，第三电感L3、第十二电容C12至第十七电容C17、第一开关K1至第二十四开关K24，其中，C12、K1至K4串联形成第一串联支路；C13、K5至K8串联形成第二串联支路；C14、K9至K12串联形成第三串联支路；C15、K13至K16串联形成第四串联支路；C16、K17至K20串联形成第五串联支路；C17、K21至K24串联形成第六串联支路；第一至第三串联支路并联形成的第一并联支路跨接在相位补偿单元的输入端与接地端之间；L3跨接在相位补偿单元的输入端与输出端之间；第四至第六串联支路并联形成的第二并联支路跨接在相位补偿单元的输出端与接地端之间。可以看出，通过开关的闭合和断开的切换，可使得接入匹配网络的电容值发生改变，从而改变匹配网络的阻抗，达到可调匹配的功能。
图11为本申请实施例提供的有源移相器的组成电路图，如图11所示，有源滤波器包括依次连接的级间匹配网络(Inter stage Matching Network，IMN)1101、PPF 1102、模拟加法器1103、变压器TF3 1104、第十八电容C18、放大器1105、相位补偿电路1106、第十九电容C19、变压器TF4 1107和第二十电容C20，其中，等幅值差分射频信号输入IMN 1101的输入端， IMN 1101对输入的等幅值差分射频信号进行网络匹配，并将网络匹配后的等幅值差分射频信号输入PPF 1102，通过PPF 1102生成四个幅度相同且相位间距90°的正交信号(两个正输出端I+、Q+和两个负输出端I-、Q-)，并将四个幅度相同且相位间距90度的正交信号输入模拟加法器1103，模拟加法器1103响应来自外部的控制信号对四个幅度相同且相位间距90°的正交信号进行矢量合成，输出等相移的第一同相正交信号给TF3 1104，经TF3 1104对第一同相正交信号进行隔离后，输出隔离后的第一同相正交信号给放大器1105；经放大器1105进行功率放大，输出隔离和功率放大后的第一同相正交信号给相位补偿电路1106，经相位补偿电路进行相位补偿后，得到相位补偿后的同相正交信号；相位补偿后的同相正交信号经TF4 1107进行隔离，输出第二同相正交信号。
同时，C18跨接在放大器1105的两个输入端之间，配置为去除电磁干扰干扰；C19和C20分别跨接在变压器TF4 1107的两个输入端和两个输出端之间，配置为去除变压器TF4 1107产生的电磁干扰。
这里，IMN 1101包括第四电感L4和第五电感L5，L4和L5分别串联在PPF 1102的输入端和输入端；PPF 1102为两阶RC滤波器；模拟加法器1103包括依次连接的正交通路选择单元1103’、可变增益放大器(Variable Gain Amplifier，VGA)1103”和加法器1103”’。
可以理解的是，两阶RC滤波器包括八个电阻R9至R16和八个电容C21至C28，其中，R9和R10串联形成的串联支路连接在两阶RC滤波器的输入端和输出端(1+)之间；R11和R12串联形成的串联支路连接在两阶RC滤波器的输入端和输出端(Q+)之间；R13和R14串联形成的串联支路连接在两阶RC滤波器的输入端和第三输出端之间(1-)之间；R15和R16串联形成的串联支路连接在两阶RC滤波器的输入端和第四输出端之间(Q-)之间；C21跨接在R11的两端，C21的正极连接在输入端上；C22的负极连接在输出端上，C22的正极连接在R9与R10的公共节点上；C23 的正极连接在输入端上，C23的负极连接在R13和R14的公共节点上；C24的负极连接在第三输出端上，C24的正极连接在R11和R12的公共节点上；C25跨接在R15的两端，C25的正极连接在输入端上；C26的负极连接在第四输出端上，C26的正极连接在R14与R14的公共节点上；C27的正极连接在输入端上，C27的负极连接在R9和R10的公共节点上；C28的负极连接在输出端上，C28的正极连接在R15和R16的公共节点上。
上文对各个实施例的描述倾向于强调各个实施例之间的不同之处，其相同或相似之处可以互相参考，为了简洁，本文不再赘述。
本申请实施例还提供一种计算机程序产品，计算机程序产品包括存储了计算机程序的非瞬时性计算机可读存储介质，该计算机程序使得计算机执行如上述方法实施例中记载的任何一种相位移相方法的部分或全部步骤。
本申请所提供的各方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本申请所提供的各产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本申请所提供的各方法或移相器实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的实施方式，上述的实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本申请的保护之内。
工业实用性
在本申请实施例中，正交信号发生器产生正交信号；加法器对所述正交信号进行矢量合成，输出第一信号；放大电路对所述第一信号进行功率放大和相位补偿，输出第二信号。即放大电路可以基于不同的控制信号对第一信号进行功率放大和相位补偿，降低了放大电路对于不同增益下的插 入相位的变化对移相精度的影响。

Claims (19)

  1. 一种放大器组件，包括：正交信号发生器、加法器和放大电路；
    所述正交信号发生器的输出端与所述加法器的输入端连接，所述正交信号发生器配置为产生正交信号；
    所述加法器的输出端与所述放大电路的输入端连接，所述加法器配置为对所述正交信号进行矢量合成，输出第一信号；
    所述放大电路，配置为对所述第一信号进行功率放大和相位补偿，输出第二信号。
  2. 根据权利要求1所述的放大器组件，其中，
    所述放大电路包括放大器、相位补偿电路；
    所述放大器，配置为对所述第一信号进行功率放大；
    所述相位补偿电路，配置为对所述第一信号进行相位补偿。
  3. 根据权利要求1所述的放大器组件，其中，所述相位补偿电路的输入端与所述加法器的输出端相连接，输出端与所述放大器相连接，输出相位补偿后的所述第一信号。
  4. 根据权利要求1所述的放大器组件，其中，所述放大器的输入端与所述加法器的输出端相连接，输出端与所述相位补偿电路的输入端相连接，输出放大后的所述第一信号。
  5. 根据权利要求1所述的放大器组件，其中，所述相位补偿电路的补偿相位基于所述放大器的增益及/或输出功率可调节。
  6. 根据权利要求1所述的放大器组件，其中，所述相位补偿电路具有“派型”、“T型”、“L型”至少其一的补偿结构。
  7. 根据权利要求1所述的放大器组件，其中，所述放大器组件还包括第一隔离电路，所述第一隔离电路的输入端与所述放大电路的输出端相连接，配置为对所述放大电路的输出端进行隔离，以隔离所述放大电路下级 电路对所述放大电路的干扰。
  8. 根据权利要求1所述的放大器组件，其中，所述放大器组件还包括第二隔离电路，所述第二隔离电路的输入端连接所述加法器的输出端；所述第二隔离电路的输出端连接所述放大电路的输入端；
    所述第二隔离电路，配置为对所述加法器的输出端进行隔离。
  9. 根据权利要求2所述的放大器组件，其中，所述放大电路还包括阻抗匹配电路；
    所述阻抗匹配电路，配置为对所述放大器的输入阻抗，及/或输出阻抗，及/或级间阻抗进行阻抗匹配。
  10. 根据权利要求2所述的放大器组件，其中，所述相位补偿电路包括以下至少一种器件：电感、电容和开关管。
  11. 根据权利要求1所述的放大器组件，其中，所述放大器为差分放大器。
  12. 一种相位移相方法，包括：
    正交信号发生器产生正交信号；
    加法器对所述正交信号进行矢量合成，输出第一信号；
    放大电路对所述第一信号进行功率放大和相位补偿，输出第二信号。
  13. 根据权利要求12所述的方法，其中，
    所述放大电路包括放大器和相位补偿电路，
    对应地，所述放大电路对所述第一信号进行功率放大和相位补偿，输出第二信号，包括：
    所述放大器对所述第一信号进行功率放大；
    所述相位补偿电路对功率放大后的所述第一信号进行相位补偿，输出第二信号。
  14. 根据权利要求12所述的方法，其中，所述方法还包括：
    第一隔离电路对所述放大电路的输出端进行隔离，以隔离所述放大电 路下级电路对所述放大电路的干扰。
  15. 根据权利要求12所述的方法，其中，所述方法还包括：
    第一隔离电路对所述加法器的输出端进行隔离。
  16. 根据权利要求13所述的方法，其中，所述放大电路还包括阻抗匹配电路，
    所述阻抗匹配电路对所述放大器的输入阻抗，及/或输出阻抗，及/或级间阻抗进行阻抗匹配。
  17. 一种相位移相方法，包括：
    获取预设移相角度；
    基于预设移相角度生成第一控制信号和第二控制信号；所述第一控制信号用于控制加法器；所述第二控制信号用于控制放大电路；
    基于所述第一控制信号控制所述加法器对正交信号发生器生成的正交信号进行矢量合成，使得所述加法器输出第一信号；
    基于所述第二控制信号控制所述放大电路对所述第一信号进行功率放大和相位补偿，使得所述放大电路输出第二信号。
  18. 根据权利要求17所述的方法，其中，所述第二控制信号包括增益子控制信号和相位子控制信号；所述增益子控制信号用于控制所述放大电路的放大器的增益；所述相位子控制信号用于控制所述放大电路的相位补偿电路的相位补偿角度；基于预设移相角度生成第二控制信号，包括：
    确定所述预设移相角度对应的所述加法器的增益；
    根据所述加法器的增益确定所述放大器的目标增益和所述增益子控制信号；
    获取放大器的增益与插入相位的映射表；
    基于所述映射表确定所述目标增益对应的插入相位；
    基于所述放大器的目标增益对应的插入相位确定所述相位补偿电路的目标补偿角度；
    基于所述目标补偿角度生成所述相位子控制信号；
    对应地，所述基于所述第二控制信号控制所述放大电路对所述第一信号进行功率放大和相位补偿，使得所述放大电路输出第二信号，包括：基于所述增益子控制信号控制所述放大器对所述第一信号进行功率放大；
    基于所述相位子控制信号控制所述相位补偿电路对功率放大后的所述第一信号进行相位补偿，使得所述放大电路输出第二信号。
  19. 一种计算机程序产品，包括计算机可读代码，在所述计算机可读代码在放大器组件中运行的情况下，所述放大器组件中的控制器执行如权利要求17或18所述的相位移相方法中的步骤。
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