WO2023035658A1 - 半导体结构及其制作方法、存储器 - Google Patents

半导体结构及其制作方法、存储器 Download PDF

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WO2023035658A1
WO2023035658A1 PCT/CN2022/093536 CN2022093536W WO2023035658A1 WO 2023035658 A1 WO2023035658 A1 WO 2023035658A1 CN 2022093536 W CN2022093536 W CN 2022093536W WO 2023035658 A1 WO2023035658 A1 WO 2023035658A1
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grating
width
pattern
semiconductor structure
different
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PCT/CN2022/093536
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English (en)
French (fr)
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邱少稳
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • Embodiments of the present disclosure relate to but are not limited to a semiconductor structure, a manufacturing method thereof, and a memory.
  • the photolithography process is the process of transferring the mask pattern to the wafer through a series of steps such as alignment and exposure.
  • it is usually necessary to use multiple photolithography processes to achieve overlay, but due to various factors in the photolithography process that cannot achieve the ideal state, it will inevitably lead to exposure and development remaining on the pattern on the wafer and on the wafer.
  • the existing graphics cannot be completely aligned, so it is necessary to accurately measure the offset between the graphics left on the wafer after exposure and development and the existing graphics on the wafer, that is, the overlay error (overlay), so that the subsequent Effectively compensate and correct overlay errors in the process, so that the finally obtained semiconductor device has the desired effect.
  • Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory, which at least help to improve the electrical performance of the semiconductor structure and the memory.
  • a first aspect of an exemplary embodiment of the present disclosure provides a semiconductor structure.
  • the semiconductor structure may at least include: a first grating, a second grating, and a third grating stacked from bottom to top and arranged in different photoresist layers.
  • the overlay marking areas for setting the grating overlap, the first grating, the second grating and the third grating are all periodic structures, and the periodic structures adjacent to the The center distance of the grating is the grating period, and the grating width and/or the grating period of the first grating and the second grating are different.
  • first grating and the second grating are adjacent to different photoresist layers.
  • the first grating, the second grating and the third grating are all composed of periodically arranged gaps, bumps or holes.
  • the photoresist layer includes a core area and a peripheral area, the peripheral area is located between the core area and the scribe line, and the overlay mark area is located in the peripheral area.
  • the semiconductor structure further includes: a first pattern and a second pattern in the core area, the first pattern and the first grating are in the same photoresist layer, the second pattern and the second The grating is in another photoresist layer, the first grating and the first pattern have a grating structure with the same grating width and grating period, and the second grating and the second pattern have a grating width and/or grating Grating structures with different periods.
  • the first pattern includes word lines.
  • the second pattern includes a capacitor contact hole.
  • the grating width and grating period of the second grating are the same as the grating width and grating period of the third grating.
  • the center position of the second grating is misaligned with the center position of the first grating in the vertical direction, and the second grating does not overlap with the first grating in the vertical direction.
  • the grating period of the second grating is greater than the grating period of the first grating, and the center position of the second grating is used as the center position of some gratings in the first grating.
  • the grating width of the second grating is larger than the grating width of the first grating.
  • the grating width of the second grating is less than or equal to twice the grating width of the first grating.
  • a second aspect of exemplary embodiments of the present disclosure provides a memory, including the semiconductor structure described in any one of the above.
  • the third aspect of the exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the method for manufacturing a semiconductor structure at least includes: forming a first grating, a second grating, and a second grating stacked from bottom to top and arranged in different photoresist layers.
  • the third grating overlaps with the overlay mark area used to set the grating in the different photoresist layer, the first grating, the second grating and the third grating are all periodic structures, and the periodic structure
  • the distance between the centers of the adjacent gratings is the grating period, and the grating width or the grating period of the first grating is different from that of the second grating.
  • the manufacturing method further includes: forming a second pattern, the second grating and the second pattern are in the same photoresist layer, and the second pattern and the second grating are gratings with different grating periods structure, the grating width of the second grating is greater than the grating width of the second pattern.
  • setting the grating width and/or grating period of the first grating and the second grating to be different is beneficial to make the characteristics of the diffraction signal obtained by illuminating the first grating and the second grating different, so that the first grating
  • the diffraction signal of the second grating is distinguished from the diffraction signal of the second grating, avoiding the whole of the diffraction signal of the first grating and the diffraction signal of the second grating as the diffraction signal of the second grating, and ensuring that the diffraction signal used to calculate the overlay error is only It is composed of the diffraction signal of the second grating and the diffraction signal of the third grating, thereby realizing accurate measurement of overlay errors.
  • FIG. 1 to 4 are structural schematic diagrams of semiconductor structures provided by embodiments of the present disclosure.
  • FIG. 5 and FIG. 9 are structural schematic diagrams of some steps in the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure.
  • Post-development inspection refers to the measurement of critical dimension (CD) after development, which is generally used for detection
  • CD critical dimension
  • the qualitative inspection of the generated graphics by the ADI machine is used to judge whether the graphics are normal. Since it cannot be measured by transmitted light, ADI generally uses electron beams or scanning electron microscopes, etc.
  • Measurement by means of etching; post-etching inspection refers to CD measurement after etching, before and after photoresist removal in the etching process, full inspection or sampling inspection is carried out on the product respectively.
  • Overlay error can generally be measured by image recognition-based measurement technology (Image Based Overlay, IBO), scanning electron microscope (Scanning Electron microscope, SEM) and new diffraction measurement technology (In Die Metrology, IDM).
  • IBO Image Based Overlay
  • SEM scanning Electron microscope
  • IDM In Die Metrology
  • the IDM collects the zero-order diffracted light of different marking layers, and determines the overlay error of different marking layers according to the asymmetry of the light intensity distribution of the zero-order diffracting light.
  • the implementation of the present disclosure provides a semiconductor structure.
  • the first grating and the second grating have different grating widths and/or grating periods, so as to distinguish the diffraction signal corresponding to the first grating from the diffraction signal corresponding to the second grating.
  • 1 to 4 are schematic structural diagrams of semiconductor structures provided by embodiments of the present disclosure.
  • the semiconductor structure includes: a first grating 111, a second grating 211, and a third grating 311 stacked from bottom to top and arranged in different photoresist layers, and the overlay mark areas where the gratings are arranged in different photoresist layers overlap,
  • the first grating 111, the second grating 211, and the third grating 311 are all periodic structures, the distance between the centers of adjacent gratings in the periodic structure is the grating period, and the grating width and/or grating width of the first grating 111 and the second grating 211 Cycles are different.
  • the semiconductor structure includes a first photoresist layer 10, a second photoresist layer 20 and a third photoresist layer 30 stacked from bottom to top, the first photoresist layer 10 has a first engraved marking area 11, and the second photoresist layer 20 There is a second overlay mark area 21, the third photoresist layer 30 has a third overlay mark area 31, the first grating 111 is located in the first overlay mark area 11, and the second grating 211 is located in the second overlay mark area 21 Inside, the third grating 311 is located in the third overlay mark region 31, the first grating 111, the second grating 211 and the third grating 311 are all overlay marks, and in the stacking direction of the photoresist layer, the first overlay mark The projections of the area 11 and the second overlay marking area 21 are at least partially coincident.
  • the overlay mark areas of different film layers often overlap in the film layer stacking direction.
  • the measurement result may be affected by the lower film layer.
  • the first grating 111 and the second grating 211 are periodic structures with the same grating width and grating period, the characteristics of the first diffraction signal and the second diffraction signal are the same, and technicians cannot effectively distinguish the first diffraction signal from the second diffraction signal , the first diffraction signal and the second diffraction signal can only be regarded as the "second diffraction signal".
  • the first grating 111 and the second grating 211 are periodic structures with the same grating width and grating period, the characteristics of the first diffraction signal and the second diffraction signal are the same, and technicians cannot effectively distinguish the first diffraction signal from the second diffraction signal , the first diffraction signal and the second diffraction signal can only be regarded as the "second diffraction signal".
  • the first diffraction signal is the same as the second diffraction signal, and the first diffraction signal will not interfere with the identification of the second diffraction signal by technicians; if the first grating 111 and the second diffraction signal There is a deviation in the second grating 211, and the actual positions of the first diffraction signal and the second diffraction signal are different, but since the first diffraction signal and the second diffraction signal have the same parameters (width and spacing) except for the position, technicians cannot distinguish For the first diffraction signal and the second diffraction signal, only the whole of the first diffraction signal and the second diffraction signal can be regarded as the "second diffraction signal". At this time, there may be deviations in the measurement results.
  • the accuracy of the measurement results becomes lower and lower.
  • the first grating 111 and the second grating 211 are completely aligned.
  • the measured offset is the same or close to the actual offset, for example, the difference is not more than 0.5nm; with the first grating 111 and the second
  • the difference between the gratings 211 expands to 2.5nm or even 5nm, and the difference between the measured offset and the actual offset may expand to 1nm or even 2nm, and the measured offset is basically invalid at this time.
  • the second diffraction signal will also be transmitted through the third photoresist layer 30, and the first diffraction signal will also be transmitted through the second photoresist layer 20 and the third photoresist layer 30, but because the first diffraction signal and the second diffraction signal are not parallel light, and the width of the grating is generally much larger than the grating slit, therefore, most of the first diffraction signal and the second diffraction signal are transmitted out of the upper film layer, rather than being diffracted again, therefore, the first diffraction signal and the second diffraction signal
  • the position does not change or the change is small, and the main change is the signal strength (blocked by the film layer, the signal strength becomes weaker).
  • the measured offset is a relative value (relative to zero offset)
  • the influence caused by the second photoresist layer 20 and the third photoresist layer 30 will be eliminated by the subtraction calculation of the relative value.
  • the third photoresist layer 30 is the photoresist layer to be tested
  • the second photoresist layer 20 is the reference photoresist layer
  • the first photoresist layer 10 is the existing interference photoresist layer
  • the first photoresist layer 20 is the reference photoresist layer.
  • Layer 10 and second photoresist layer 20 are adjacent or non-adjacent photoresist layers
  • second photoresist layer 20 and third photoresist layer 30 are adjacent or non-adjacent photoresist layers.
  • the first photoresist layer 10 and the second photoresist layer 20 are adjacent, that is, the first grating 111 and the second grating 211 are located in different photoresist layers adjacent to each other, when the first photoresist layer When 10 is adjacent to the second photoresist layer 20, the light intensity loss suffered by the first diffraction signal when it is transmitted to the top of the second photoresist layer 20 is relatively small, which has a greater impact on the second diffraction signal.
  • the signal characteristic of the second diffraction signal is adjusted by a large amplitude to effectively distinguish the first diffraction signal from the second diffraction signal.
  • the first grating 111 and the second grating 211 are in separate different photoresist layers, and at least a fourth photoresist layer is provided between the first photoresist layer 10 and the second photoresist layer 20.
  • the engraving layer 40, the fourth photoresist layer 40 has a fourth overlay mark area 41 and a fourth grating 411 disposed in the fourth overlay mark area 41, the fourth grating 411 is located between the first grating 111 and the second grating 211 Between, the arrangement direction of the first grating 111 is parallel to the arrangement direction of the second grating 211 , and the arrangement direction of the fourth grating 411 is perpendicular to the arrangement direction of the second grating 211 .
  • Setting the fourth grating 411 is beneficial to reduce the light transmitted to the first photoresist layer 10, and to prevent the first diffraction signal from propagating to the second photoresist layer 20, so that the first diffraction signal of the third photoresist layer 30 is finally transmitted It has a lower light intensity, thereby weakening or even eliminating the influence of the first diffraction signal on the second diffraction signal.
  • intermediate film layers can also be arranged between the first photoresist layer 10 and the second photoresist layer 20, and are blocked by the intermediate film layer. If the light intensity loss of the first diffraction signal in the propagation process is large, the first diffraction signal If the influence of the signal is small, the difference between the first grating 111 and the second grating 211 can be small.
  • the characteristic difference between the first grating 111 and the second grating 211 can be adjusted according to the loss of the first diffraction signal during transmission, and the characteristic difference includes a grating width difference and/or a grating period difference.
  • the grating may have different appearances.
  • the grating may consist of periodically arranged gaps, bumps or holes, or the grating may contain periodically arranged gaps, bumps or holes.
  • the middle part of the grating generally follows a stricter periodic distribution, that is, the spacing between adjacent gratings is equal, the edge part of the grating is less periodic, and the distance between adjacent gratings may gradually increase or decrease.
  • Trend since this is a phenomenon limited by the current technological level, it cannot be used as evidence that it does not belong to the grating.
  • the multiple groups of gratings may have at least two arrangement directions, which are used to detect the offset of the photoresist layer to be tested compared with the reference photoresist layer in different directions.
  • the arrangement direction can be vertical or oblique.
  • the expressions of different groups of gratings can be the same or different.
  • the overlay mark includes a hole array, it can be considered that the overlay mark includes multiple groups of gratings arranged in different directions, and there is a common hole between the two groups of gratings.
  • the photoresist layer includes a core region and a peripheral region, the peripheral region is located between the core region and the scribe lines, and the overlay mark region is located in the peripheral region.
  • the peripheral area usually refers to the blank area between the core component and the dicing line. With the miniaturization of the semiconductor structure and the complexity of the core component, the area of the blank area may gradually shrink. There is a higher probability of projection coincidence in the direction.
  • the first overlay mark area 11 , the second overlay mark area 21 and the third overlay mark area 31 all belong to the overlay mark area and are located in the peripheral area.
  • the semiconductor structure further includes: a first pattern 112 and a second pattern 212 in the core area, the first pattern 112 and the first grating 111 are in the same photoresist layer, the second pattern 212 and the second grating 211 are in In another photoresist layer, the first grating 111 and the first pattern 112 have grating structures with the same grating width and grating period, and the second grating 211 and the second pattern 212 have grating structures with different grating widths and/or grating periods.
  • the embodiment of the present disclosure makes the diffraction signal of the second grating 211 different from the diffraction signal of the first grating 111 by adjusting the grating width and/or grating period of the second grating 211, so that according to the diffraction signal of the second grating 211
  • the offset between the second photoresist layer 20 and the third photoresist layer 30 can be accurately obtained through the diffraction signal of the third grating 311 .
  • the grating width and grating period of the second grating 211 can be set to be the same as the grating width and grating period of the third grating 311. In this background Next, if the grating width and/or grating period of the second grating 211 are adjusted, the grating width and/or grating period of the third grating 311 need to be adjusted synchronously to ensure a high accuracy of overlay error measurement.
  • the process steps of the peripheral area are the same as those of the core area, and the first grating 111 is at the bottom layer relative to the second grating 211 and the third grating 311, the characteristics of the first grating 111 are kept unchanged and the second grating 211 and the third grating are adjusted.
  • the three gratings 311 are beneficial to reduce the impact on subsequent film process steps and reduce adjustment costs.
  • the second grating 211 and the second pattern 212 are grating structures with the same grating width and grating period
  • the first grating 111 and the first pattern 112 are grating structures with different grating widths and/or grating periods, that is, That is, the grating width and/or grating period of the first grating 111 are adjusted, and the grating width and grating period of the second grating 211 are kept unchanged.
  • the number of film layers between the first photoresist layer 10 and the second photoresist layer 20 and between the second photoresist layer 20 and the third photoresist layer 30 may be different according to the application scene, in the actual process, it may The characteristics of the first grating 111, or the characteristics of the second grating 211 and the third grating 311 are adjusted according to actual needs, so as to reduce the impact on the overall film process and reduce the cost.
  • the center position aa of the second grating 211 is misaligned with the center position bb of the first grating 111 in the vertical direction, and the second grating 211 and the first grating 111 do not overlap in the vertical direction.
  • the center position bb of the first grating 111 is misaligned with the center position aa of the second grating 211, by controlling the second grating 211 and the first grating 111 not to overlap in the vertical direction, it is beneficial to avoid diffraction signals caused by grating overlap overlapping, thereby accurately distinguishing the first diffraction signal and the second diffraction signal.
  • the vertical direction refers to the stacking direction of the first photoresist layer 10 and the second photoresist layer 20
  • the central position of the grating refers to the central axis or central axis plane of each grating in the grating arrangement direction, and the multiple gratings
  • the above-mentioned first grating 111 , second grating 211 and third grating 311 are composed.
  • the non-overlapping of the second grating 211 and the first grating 111 in the vertical direction means that there is a gap between the first grating 111 and the second grating 211 in the arrangement direction of the first grating 111, thus, It is beneficial to further distinguish the first diffraction signal and the second diffraction signal, avoiding the indistinguishability of the first diffraction signal and the second diffraction signal due to continuity; in some other embodiments, the second grating 211 is perpendicular to the first grating 111 Non-overlapping means that, in the arrangement direction of the first gratings 111 , the boundaries of the first gratings 111 and the second gratings 211 coincide.
  • the center position of the grating in the second pattern 212 is vertically misaligned with the center position of the grating in the first pattern 112 , and the second pattern 212 and the first pattern 112 overlap at least partially in the vertical direction. It can be understood that if the grating features of the second grating 211 are different from those of the second pattern 212, the second pattern 212 and the second grating 211 cannot be formed by the same mask. Therefore, in the actual manufacturing process, it is possible to Cover the peripheral area first to form the second pattern 212 in the core area, and then form the second grating 211 in the peripheral area after covering the core area. That is to say, the second pattern 212 and the second grating 211 are respectively formed by different exposure, development and etching processes.
  • the grating period of the second grating 211 is greater than that of the first grating 111 , and the center position of the second grating 211 is used as the center position of some gratings in the first grating 111 .
  • controlling the first grating 111 and the second grating 211 to have different grating periods is beneficial to distinguish the The first diffraction signal and the second diffraction signal.
  • the grating width of the second grating 211 is greater than the grating width of the first grating 111, on the basis of changing the grating period of the second grating 211, further adjust the grating width of the second grating 211, It is beneficial to further distinguish the first diffraction signal and the second diffraction signal; in other embodiments, the grating width of the second grating 211 is smaller than the grating width of the first grating 111 .
  • the grating width of the second grating 211 is the width d of each grating in the grating arrangement direction.
  • the width of the second grating 211 is less than or equal to twice the width of the first grating 111 , or in other words, the width of the second grating 211 is less than or equal to twice the width of the second pattern 212 .
  • Setting the grating width of the second grating 211 and the grating width of the second pattern 212 has the above relationship, which is conducive to utilizing the same process steps to form the second pattern 212 and the second grating 211, and reduces the adjustment of the second grating 211 to the film layer preparation process. The impact, thereby reducing the process cost of the semiconductor structure.
  • the first pattern 112 includes a word line, for example, the word line may be a buried word line; in some embodiments, the second pattern 212 may be a bit line conductive layer or a capacitor contact hole.
  • setting the grating width and/or grating period of the first grating and the second grating to be different is beneficial to make the characteristics of the diffraction signal obtained by illuminating the first grating and the second grating different, so that the first grating Distinguish the diffraction signal of the grating from the diffraction signal of the second grating, avoid taking the entirety of the diffraction signal of the first grating and the diffraction signal of the second grating as the diffraction signal of the second grating, and ensure the diffraction signal used to calculate the overlay error It only consists of the diffraction signal of the first grating and the diffraction signal of the second grating, thereby realizing accurate measurement of overlay errors.
  • An embodiment of the present disclosure further provides a memory, including the semiconductor structure described in any one of the foregoing. Since the above-mentioned semiconductor structure can accurately measure the offset between the photoresist layer where the second grating is located and the photoresist layer where the third grating is located, and then adjust and correct it through the subsequent process, the memory prepared based on the above-mentioned semiconductor structure has better performance. electrical properties.
  • the method for manufacturing a semiconductor structure includes: forming a first grating 111 , a second grating 211 , and The third grating 311, the overlay marking area used to set the grating in different photoresist layers overlaps, the first grating 111, the second grating 211 and the third grating 311 are all periodic structures, and the centers of adjacent gratings in the periodic structures The distance is the grating period, and the grating width or grating period of the first grating 111 and the second grating 211 are different.
  • the second pattern 212 and the second grating 211 are respectively formed by different exposure, development and etching processes, the second grating 211 and the second pattern 212 are in the same photoresist layer, and the second pattern 212 and the second grating 211 are grating structures with different grating periods, and the grating width of the second grating 211 is greater than the grating width of the second pattern 212 .
  • the first mask 212a is used to form the second pattern 212
  • the second mask 211a is used to form Second grating 211; carry out deposition process, form patterned layer 212b and grating layer 211b simultaneously, when the opening width of second mask 211a is less than or equal to the twice of the thickness of patterned layer 212b, grating layer 211b is filled with second mask 211a opening.
  • the opening width of the second mask 211a is greater than the thickness of the pattern layer 212b and less than or equal to twice the thickness of the pattern layer 212b.
  • a maskless dry etching process is performed to remove the pattern layer 212b covering the top surface of the first mask 212a and the bottom of the opening of the first mask 212a to form the first sacrificial layer 212c, and remove the pattern layer 212b above the second mask 212a.
  • the second sacrificial layer 211c is formed by masking the grating layer 211b on the top surface of the mask 211a.
  • an etching process is performed to remove the first mask 212a and the second mask 211a, and the first sacrificial layer 212c and the second sacrificial layer 211c are retained; a deposition process is performed to form a first sacrificial layer 212c filled with gaps The third mask 212d and the fourth mask 211d filling the gap of the second sacrificial layer 211c.
  • the opening width of the second mask 211a is greater than twice the thickness of the pattern layer 212b and less than or equal to twice the thickness of the pattern layer 212b, and the opening width of the first mask 212a is greater than twice the thickness of the pattern layer 212b, therefore, the first The opening width of the mask 212a is greater than the opening width of the second mask 211a. In the case of the same overall width, in order to make the opening width of the second mask 211a smaller, it is necessary to set a single mask in the second mask 211a.
  • the width of the stripes is larger than the width of a single mask stripe in the first mask 212a, the opening width of the third mask 212d is smaller than the opening width of the fourth mask 211d, and the grating width of the third mask 212d is smaller than that of the fourth mask 211d.
  • the width of the grating, the period of the third mask 212d is smaller than the period of the fourth mask 211d, the third mask 212d and the fourth mask 211d are used to etch the underlying conductive layer 51 to form a bit line conductive layer.
  • the first sacrificial layer 211c and the second sacrificial layer 212c are removed, and the conductive layer 51 is etched using the third mask 212d and the fourth mask 211d to form the first bit line conductive layer located in the functional area 512 and the second bit line conductive layer 511 located in the peripheral area. Since the grating feature of the first bit line conductive layer 512 is the same as that of the third mask 212d, and the grating feature of the second bit line conductive layer 511 is the same as that of the fourth mask 211d, therefore, the first bit line conductive The opening width of the layer 512 is smaller than the opening width of the second bit line conductive layer 511 .
  • a first spacer 513 is formed on the sidewall of the first bit line conductive layer 512, and a second spacer 514 is formed on the side wall of the second bit line conductive layer 511;
  • the first capacitive contact hole in the gap between the layers 512 serves as the second pattern 212
  • the second capacitive contact hole filling the gap between the adjacent second bit line conductive layers 511 is formed to serve as the second grating 211 .
  • the first sidewall 513 and the second sidewall 514 can be formed by the same deposition process, and the thickness of the first sidewall 513 is the same as that of the second sidewall 514 .
  • the grating width of the second pattern 212 smaller than the grating width of the second grating 211.
  • the first capacitance contact hole and the second capacitance contact hole can also be formed by the same deposition process.
  • the first capacitance contact hole in the functional area is used to connect the drain of the word line to play the role of electrical connection.
  • the second capacitance contact hole in the peripheral area The contact hole may not be connected to the drain of the word line, and is only used as an overlay mark.
  • the buried word lines 60 in the functional area can be used as the first pattern, and the buried word lines 60 in the peripheral area can be used as the first grating.
  • in-situ processing is performed on the first bit line conductive layer and the second bit line conductive layer to form the first bit line conductive layer for isolation.
  • Sidewalls and second sidewalls such as doped polysilicon in the conductive layer of the bit line, oxidize or nitride the doped polysilicon to form silicon oxide or silicon nitride for electrical isolation; After the two sidewalls, conductive material can be filled to form the first capacitor contact hole and the second capacitor contact hole.
  • the width of the first capacitance contact hole is equal to the thickness of the pattern layer
  • the width of the second capacitance contact hole is equal to the opening width of the second mask, that is to say, the width of the second capacitance contact hole is greater than the width of the first capacitance contact hole.
  • the width of the contact hole is less than or equal to twice the width of the first capacitor contact hole.
  • the width of the first capacitance contact hole can also be equal to the width of the buried word line, in this case, the width of the second capacitance contact hole is greater than the width of the buried word line and less than or equal to the width of the buried word line twice the width.
  • setting the grating width and/or grating period of the first grating and the second grating to be different is beneficial to make the characteristics of the diffraction signal obtained by illuminating the first grating and the second grating different, so that the first grating Distinguish the diffraction signal of the grating from the diffraction signal of the second grating, avoid taking the entirety of the diffraction signal of the first grating and the diffraction signal of the second grating as the diffraction signal of the second grating, and ensure the diffraction signal used to calculate the overlay error It only consists of the diffraction signal of the first grating and the diffraction signal of the second grating, thereby realizing accurate measurement of overlay errors.

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Abstract

本公开实施例公布一种半导体结构及其制作方法、存储器，半导体结构至少可以包括：自下向上堆叠且设置于不同光刻层中的第一光栅、第二光栅以及第三光栅，不同光刻层中用于设置光栅的套刻标记区域重叠，第一光栅、第二光栅以及第三光栅均为周期性结构，周期性结构中相邻光栅的中心距离为光栅周期，第一光栅与第二光栅的光栅宽度和/或光栅周期不同。

Description

半导体结构及其制作方法、存储器
本公开基于申请号为202111050625.5、申请日为2021年09月08日、申请名称为“半导体结构及其制作方法、存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及但不限于一种半导体结构及其制作方法、存储器。
背景技术
光刻工艺是通过对准、曝光等一系列步骤将掩膜版图案转移到晶圆上的工艺过程。在半导体器件制程过程中，通常需要使用多次光刻工艺以实现套刻，而由于光刻工艺上的各种因素无法达到理想状态，必定导致曝光显影留存在晶圆上的图形与晶圆上已有图形无法完全对准，由此需要准确量测出曝光显影留存在晶圆上的图形与晶圆上已有图形之间的偏移量，即套刻误差(overlay)，才能在后续的工艺中对套刻误差进行有效的补偿及修正，使最终得到的半导体器件具有预期效果。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构及其制作方法、存储器，至少有利于提升半导体结构及存储器的电学性能。
本公开示例性的实施例的第一方面，提供一种半导体结构，半导体结构至少可以包括：自下向上堆叠且设置于不同光刻层中的第一光栅、第二光栅以及第三光栅，不同所述光刻层中用于设置光栅的套刻标记区域重叠，所述第一光栅、所述第二光栅以及所述第三光栅均为周期性结构，所述周期性结构中相邻所述光栅的中心距离为光栅周期，所述第一光栅与所述第二光栅的光栅宽度和/或所述光栅周期不同。
其中，所述第一光栅与所述第二光栅处于相邻的不同所述光刻层。
其中，所述第一光栅、所述第二光栅以及所述第三光栅均由周期性排列的间隙、凸块或孔洞组成。
其中，所述光刻层包括核心区和外围区，所述外围区位于所述核心区和切割道之间，所述套刻标记区域位于所述外围区内。
其中，半导体结构还包括：处于所述核心区的第一图案和第二图案，所述第一图案与所述第一光栅处于同一所述光刻层，所述第二图案与所述第二光栅处于另一所述光刻层，所述第一光栅与所述第一图案为光栅宽度和光栅周期相同的光栅结构，所述第二光栅与所述第二图案为光栅宽度和/或光栅周期不同的光栅结构。
其中，所述第一图案包括字线。
其中，所述第二图案包括电容接触孔。
其中，所述第二光栅的光栅宽度和光栅周期与所述第三光栅的光栅宽度和光栅周期相同。
其中，所述第二光栅的中心位置与所述第一光栅的中心位置在垂直方向上错位，所述第二光栅与所述第一光栅在所述垂直方向上不重叠。
其中，所述第二光栅的光栅周期大于所述第一光栅的光栅周期，所述第二光栅的中心位置作为所述第一光栅中部分光栅的中心位置。
其中，所述第二光栅的光栅宽度大于所述第一光栅的光栅宽度。
其中，所述第二光栅的光栅宽度小于等于所述第一光栅的光栅宽度的两倍。
本公开示例性的实施例第二方面，提供一种存储器，包括上述任一项所述的半导体结构。
本公开示例性的实施例第三方面，提供一种半导体结构的制作方法，半导体结构的制作方法至少包括：形成自下向上堆叠且设置于不同光刻层中的第一光栅、第二光栅以及第三光栅，不同所述光刻层中用于设置光栅的套刻标记区域重叠，所述第一光栅、所述第二光栅以及所述第三光栅均为周期性结构，所述周期性结构中相邻所述光栅的中心距离为光栅周期，所述第一光栅与所述第二光栅的光栅宽度或所述光栅周期不同。
其中，所述制作方法还包括：形成第二图案，所述第二光栅和所述第二图案处于同一所述光刻层，所述第二图案与所述第二光栅为光栅周期不同的光栅结构，所述第二光栅的光栅宽度大于所述第二图案的光栅宽度。
本公开实施例提供的技术方案至少具有以下优点：
上述技术方案中，设置第一光栅与第二光栅的光栅宽度和/或光栅周期不同，有利于使得对第一光栅和第二光栅进行光照所得到的衍射信号的特征不同，从而将第一光栅的衍射信号和第二光栅的衍射信号区别开来，避免将第一光栅的衍射信号和第二光栅的衍射信号的整体作为第二光栅的衍射信号，保证用于计算套刻误差的衍射信号仅由第二光栅的衍射信号和第三光栅的衍射信号组成，进而实现套刻误差的准确测量。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1至图4为本公开实施例提供的半导体结构的结构示意图；
图5和图9为本公开实施例提供的半导体结构的制作方法中部分步骤的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
关于套刻误差的检测，一般分为显影后检测(After Development Insprection，ADI)和刻蚀后检测(After Etching Inspection，AEI)，显影后检测指显影后关键尺寸(CD)测量，一般用于检测曝光机和显影机的性能指标，曝光和显影完成之后，通过ADI机台对所产生的图形的定性检查，判断图形是否正常，由于不能通过透射光测量，所以ADI一般通过电子束或扫描电镜等手段进行测量；刻蚀后检测指刻蚀后的CD测量，在刻蚀制程的光刻胶去除前后，分别对产品实施全检或抽样检查。
套刻误差一般可通过基于图像识别的测量技术(Image Based Overlay，IBO)、扫描式电子显微镜(Scanning Electron microscope，SEM)以及新型衍射测量技术(In Die Metrology，IDM)进行测量。IDM采集不同标记层的零阶衍射光线，并根据零阶衍射光线的光强分布的不对称性确定不同标记层的套刻误差。
本公开实施提供一种半导体结构，设置第一光栅与第二光栅具有不同的光栅宽度和/或光栅周期，以便于区分第一光栅对应的衍射信号与第二光栅对应的衍射信号，在测量第三光栅相对于第二光栅的套刻误差时，由于位于第二光栅下方的第一光栅也具有对应的衍射信号，通过控制第一光栅对应的衍射信号与第二光栅对应的衍射信号具有不同的特征，有利于保证用于计算套刻误差的衍射信号仅由第二光栅的衍射信号和第三光栅的衍射信号组成，进而实现套刻误差的准确测量。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1至图4为本公开实施例提供的半导体结构的结构示意图。
参考图1，半导体结构包括：自下向上堆叠且设置于不同光刻层中的第一光栅111、第二光栅211以及第三光栅311，不同光刻层中设置光栅的套刻标记区域重叠，第一光栅111、第二光栅211以及第三光栅311均为周期性结构，周期性结构中相邻光栅的中心距离为光栅周期，第一光栅111与第二光栅211的光栅宽度和/或光栅周期不同。
以下将结合附图对本公开实施例进行更为详细的说明。
半导体结构包括自下向上堆叠的第一光刻层10、第二光刻层20以及第三光刻层30，第一光刻层10具有第一套刻标记区域11，第二光刻层20具有第二套刻标记区域21，第三光刻层30具有第三套刻标记区域31，第一光栅111位于第一套刻标记区域11内，第二光栅211位于第二套刻标记区域21内，第三光栅311位于第三套刻标记区域31内，第一光栅111、第二光栅211以及第三光栅311均为套刻标记，在光刻层的堆叠方向上，第一套刻标记区域11和第二套刻标记区域21的投影至少部分重合。
由于芯片区域有限，不同膜层的套刻标记区域在膜层堆叠方向上往往重合，在利用IDM测量上方膜层的套刻误差时，测量结果可能会受到下方膜层的影响。
在第三光刻层30上方进行光照时，部分光线透过第三光刻层30并发生反射，反射光经过第三光栅311的衍射而形成第三衍射信号；部分光线会依次透过第三光刻层30和第二光刻层20并发生反射，反射光经过第二光栅211的衍射形成第二衍射信号；部分光线会依次透过第三光刻层30、第二光刻层20以及第一光刻层10并发生反射，反射光经过第一光栅111的衍射形成第一衍射信号。当第一光栅111和第二光栅211为光栅宽度和光栅周期相同的周期性结构时，第一衍射信号和第二衍射信号的特征相同，技术人员无法有效区分第一衍射信号和第二衍射信号，只能将第一衍射信号和第二衍射信号整体作为“第二衍射信号”，在测量第三光栅311和第二光栅211之间的套刻误差时，实际测量的是第一光栅111和第二光栅112的等效结构与第三光栅311的套刻误差。
若第一光栅111与第二光栅211完全对准，则第一衍射信号与第二衍射信号相同，第一衍射信号不会对技术人员识别第二衍射信号造成干扰；若第一光栅111与第二光栅211存在偏差，则第一衍射信号与第二衍射信号实际位置不同，但由于第一衍射信号和第二衍射信号除了位置以外的其他参数(宽度和间距)都相同，因此技术人员无法区分第一衍射信号和第二衍射信号，只能将第一衍射信号和第二衍射信号的整体作为“第二衍射信号”，此时，测量结果可能会存在偏差。
随着第一光栅111和第二光栅211之间偏差逐渐扩大，测量结果的准确率越来越低。理想情况下，第一光栅111和第二光栅211完全对准，此时，测量偏移量与实际偏移量相同或相近，例如差值不超过0.5nm；随着第一光栅111和第二光栅211之间的差值扩大到2.5nm甚至5nm，测量偏移量与实际偏移量的差值可能会扩大到1nm甚至2nm，此时测量偏移量基本无效。
第二衍射信号还会透射过第三光刻层30，第一衍射信号还会透射过第二光刻层20和第三光刻层30，但由于第一衍射信号和第二衍射信号并非平行光线，且光栅宽度一般远大于光栅缝隙，因此，第一衍射信号和第二衍射信号绝大部分是透射出上方膜层，而非再次发生衍射，因此，第一衍射信号和第二衍射信号的位置不会发生改变或改变较小，主要发生改变的是信号强度(受膜层阻隔，信号强度变弱)。此 外，由于测量偏移量是一个相对值(相对于零偏移量)，因此，第二光刻层20和第三光刻层30造成的影响会被相对值的减法计算消除。
本公开实施例中，第三光刻层30为待测光刻层，第二光刻层20为参考光刻层，第一光刻层10为现有的干扰光刻层，第一光刻层10与第二光刻层20为相邻或不相邻的光刻层，第二光刻层20和第三光刻层30为相邻或不相邻的光刻层。
在一些实施例中，第一光刻层10和第二光刻层20相邻，也就是说，第一光栅111与第二光栅211处于相邻的不同光刻层，当第一光刻层10和第二光刻层20相邻时，第一衍射信号透射至第二光刻层20上方所受到的光强损耗较小，对第二衍射信号的影响较大，此时，需要以较大的幅度调整第二衍射信号的信号特征，以有效区分第一衍射信号和第二衍射信号。
在一些实施例中，参考图2，第一光栅111和第二光栅211处于分离的不同光刻层内，第一光刻层10与第二光刻层20之间至少还设置有第四光刻层40，第四光刻层40具有第四套刻标记区域41以及设置于第四套刻标记区域41内的第四光栅411，第四光栅411位于第一光栅111和第二光栅211之间，第一光栅111的排列方向平行于第二光栅211的排列方向，第四光栅411的排列方向垂直于第二光栅211的排列方向。设置第四光栅411有利于减少透射至第一光刻层10的光线，以及抑制第一衍射信号传播至第二光刻层20上，使得最终透射出第三光刻层30的第一衍射信号具有较低的光强，从而减弱甚至消除第一衍射信号对第二衍射信号的影响。
第一光刻层10与第二光刻层20之间还可以设置有其他中间膜层，受中间膜层的阻隔，若第一衍射信号在传播过程中的光强损耗较大，第一衍射信号的影响较小，则第一光栅111与第二光栅211的区别可以较小。可以根据第一衍射信号在透射过程中的损耗调整第一光栅111与第二光栅211的特征差值，特征差值包括光栅宽度差值和/或光栅周期差值。
在不同实施例中，光栅可能具有不同的表现形式。光栅可以由周期性排列的间隙、凸块或孔洞组成，或者说，光栅包含周期性排列的间隙、凸块或孔洞。受制作工艺的影响，光栅的中间部分一般遵循更为严格的周期分布，即相邻光栅的间距相等，光栅的边缘部分周期性较差，相邻光栅的距离可能呈现逐渐变大或者变小的趋势，由于这属于受当前工艺水平限制而形成的现象，因此，不能将其作为不属于光栅的证据。
同一套刻标记区域内可能具有多组光栅，多组光栅具有至少两个排列方向，用以检测待测光刻层相较于参考光刻层在不同方向上的偏移量，不同组光栅的排列方向可以垂直或者斜交。其中，不同组光栅的表现形式可以相同或不同，当套刻标记包括孔洞阵列时，可以认为套刻标记包括排列方向不同的多组光栅，两组光栅之间具有一共用的孔洞。
在一些实施例中，光刻层包括核心区和外围区，外围区位于核心区和切割道之间，套刻标记区域位于外围区内。外围区通常指的是位于核心部件与切割道之间的空白区域，随着半导体结构的微缩和核心部件的复杂化，空白区域的面积可能逐渐缩小，不同膜层的套刻标记在膜层堆叠方向上投影重合的可能性较高。第一套刻标记区域11、第二套刻标记区域21以及第三套刻标记区域31都属于套刻标记区域，均位于外围区内。
在一些实施例中，半导体结构还包括：处于核心区的第一图案112和第二图案212，第一图案112与第一光栅111处于同一光刻层，第二图案212与第二光栅211处于另一光刻层，第一光栅111与第一图案112为光栅宽度和光栅周期相同的光栅结构，第二光栅211与第二图案212为光栅宽度和/或光栅周期不同的光栅结构。也就是说，本公开实施例通过调整第二光栅211的光栅宽度和/或光栅周期，使得第二光栅 211的衍射信号区别于第一光栅111的衍射信号，从而根据第二光栅211的衍射信号和第三光栅311的衍射信号准确获取第二光刻层20和第三光刻层30的偏移量。
为准确测量第二光刻层20和第三光刻层30的套刻误差，可设置第二光栅211的光栅宽度和光栅周期与第三光栅311的光栅宽度和光栅周期相同，在这一背景下，若调整第二光栅211的光栅宽度和/或光栅周期，则需要同步调整第三光栅311的光栅宽度和/或光栅周期，以保证套刻误差的测量具有较高的准确性。由于外围区的工艺步骤与核心区的工艺步骤相同，且第一光栅111相对于第二光栅211和第三光栅311处于底层，保持第一光栅111的特征不变而调整第二光栅211和第三光栅311，有利于减小对后续膜层工艺步骤的影响，降低调整成本。
在其他实施例中，第二光栅211和第二图案212为光栅宽度和光栅周期相同的光栅结构，第一光栅111与第一图案112为光栅宽度和/或光栅周期不同的光栅结构，也就是说，调整第一光栅111的光栅宽度和/或光栅周期，保持第二光栅211的光栅宽度和光栅周期不变。由于第一光刻层10与第二光刻层20之间以及第二光刻层20和第三光刻层30之间的膜层数量根据应用场景可能存在不同，在实际工艺过程中，可以根据实际需要调整第一光栅111的特征，或者调整第二光栅211和第三光栅311的特征，以减小对整体膜层工艺的影响，降低成本。
在一些实施例中，参考图3，第二光栅211的中心位置aa与第一光栅111的中心位置bb在垂直方向上错位，第二光栅211与第一光栅111在垂直方向上不重叠。在第一光栅111的中心位置bb与第二光栅211的中心位置aa错位的情况下，通过控制第二光栅211与第一光栅111在垂直方向上不重叠，有利于避免光栅重叠导致的衍射信号重叠，从而准确区分第一衍射信号和第二衍射信号。其中，垂直方向指的是第一光刻层10和第二光刻层20的堆叠方向，光栅的中心位置指的是每一条光栅在光栅排列方向上的中轴线或中轴面，多条光栅组成上述第一光栅111、第二光栅211以及第三光栅311。
在一些实施例中，第二光栅211与第一光栅111在垂直方向上不重叠指的是，在第一光栅111的排列方向，第一光栅111与第二光栅211之间具有间隙，如此，有利于进一步区分出第一衍射信号和第二衍射信号，避免第一衍射信号和第二衍射信号因连续而无法区分；在另一些实施例中，第二光栅211与第一光栅111在垂直方向上不重叠指的是，在第一光栅111的排列方向，第一光栅111与第二光栅211边界重合。
在一些实施例中，第二图案212中光栅的中心位置与第一图案112中光栅的中心位置在垂直方向上错位，第二图案212与第一图案112在垂直方向上至少部分重叠。可以理解的是，若第二光栅211的光栅特征与第二图案212的光栅特征不同，则第二图案212和第二光栅211无法通过同一掩膜形成，因此，在实际生产制造过程中，可以先遮盖外围区，以先形成核心区的第二图案212，在遮盖核心区，以后形成外围区的第二光栅211。也就是说，第二图案212和第二光栅211采用不同的曝光显影以及刻蚀工艺分别形成。
在一些实施例中，参考图4，第二光栅211的光栅周期大于第一光栅111的光栅周期，第二光栅211的中心位置作为第一光栅111中部分光栅的中心位置。在第二光栅211的中心位置作为第一光栅111的中心位置的情况下，控制第一光栅111与第二光栅211具有不同的光栅周期，有利于区分基于第一光栅111和第二光栅211形成的第一衍射信号和第二衍射信号。
继续参考图4，在一些实施例中，第二光栅211的光栅宽度大于第一光栅111的光栅宽度，在改变第二光栅211的光栅周期的基础上，进一步调节第二光栅211的光栅宽度，有利于进一步区分第一衍射信号和第二衍射信号；在其他实施例中，第二 光栅211的光栅宽度小于第一光栅111的光栅宽度。以第二光栅211为例，第二光栅211的光栅宽度为每一条光栅在光栅排列方向的宽度d。
在一些实施例中，第二光栅211的光栅宽度小于等于第一光栅111的光栅宽度的两倍，或者说，第二光栅211的光栅宽度小于等于第二图案212的光栅宽度的两倍。设置第二光栅211的光栅宽度与第二图案212的光栅宽度具有如上关系，有利于利用工同一工艺步骤形成第二图案212和第二光栅211，降低第二光栅211的调整对膜层制备工艺的影响，从而缩减半导体结构的工艺成本。
在一些实施例中，第一图案112包括字线，示例性地，字线可以是埋入式字线；在一些实施例中，第二图案212可以为位线导电层或电容接触孔。
本公开实施例中，设置第一光栅与第二光栅的光栅宽度和/或光栅周期不同，有利于使得对第一光栅和第二光栅进行光照所得到的衍射信号的特征不同，从而将第一光栅的衍射信号和第二光栅的衍射信号区别开来，避免将第一光栅的衍射信号和第二光栅的衍射信号的整体作为第二光栅的衍射信号，保证用于计算套刻误差的衍射信号仅由第一光栅的衍射信号和第二光栅的衍射信号组成，进而实现套刻误差的准确测量。
本公开实施例还提供一种存储器，包含上述任一项所述的半导体结构。由于上述半导体结构可准确测量出第二光栅所在光刻层与第三光栅所在光刻层的偏移量，进而通过后续工艺制程调整和修正，因此，基于上述半导体结构制备的存储器具有较优的电学性能。
本公开实施例还提供一种的半导体结构的制作方法，参考图1，半导体结构的制作方法包括：形成自下向上堆叠且设置于不同光刻层中的第一光栅111、第二光栅211以及第三光栅311，不同光刻层中用于设置光栅的套刻标记区域重叠，第一光栅111、第二光栅211以及第三光栅311均为周期性结构，周期性结构中相邻光栅的中心距离为光栅周期，第一光栅111与第二光栅211的光栅宽度或光栅周期不同。
在一些实施例中，参考图4，第二图案212和第二光栅211采用不同的曝光显影以及刻蚀工艺分别形成，，第二光栅211和第二图案212处于同一光刻层，第二图案212与第二光栅211为光栅周期不同的光栅结构，第二光栅211的光栅宽度大于第二图案212的光栅宽度。具体如下：
参考图4和图5，利用不同掩膜版，分别曝光显影形成第一掩膜212a和第二掩膜211a，第一掩膜212a用于形成第二图案212，第二掩膜211a用于形成第二光栅211；进行沉积工艺，同时形成图案层212b和光栅层211b，当第二掩膜211a的开口宽度小于等于图案层212b的厚度的两倍时，光栅层211b填充满第二掩膜211a的开口。在示例性实施例中，第二掩膜211a的开口宽度大于图案层212b的厚度且小于等于图案层212b的厚度的两倍。
参考图6，进行无掩膜干法刻蚀工艺，去除覆盖第一掩膜212a顶面和位于第一掩膜212a开口底部的图案层212b，形成第一牺牲层212c，以及去除高于第二掩膜211a顶面的光栅层211b，形成第二牺牲层211c。
参考图7，进行刻蚀工艺，去除第一掩膜212a和第二掩膜211a，保留第一牺牲层212c和第二牺牲层211c；进行沉积工艺，形成填充满第一牺牲层212c间隙的第三掩膜212d以及填充满第二牺牲层211c间隙的第四掩膜211d。
由于第二掩膜211a的开口宽度大于图案层212b的厚度且小于等于图案层212b的厚度的两倍，而第一掩膜212a的开口宽度大于图案层212b的厚度的两倍，因此，第一掩膜212a的开口宽度大于第二掩膜211a的开口宽度，在整体总宽度不变的情况下，为使得第二掩膜211a的开口宽度较小，需要设置第二掩膜211a中单一掩膜条的宽度大于第一掩膜212a中单一掩膜条的宽度，第三掩膜212d的开口宽度小于第四掩 膜211d的开口宽度，第三掩膜212d的光栅宽度小于第四掩膜211d的光栅宽度，第三掩膜212d的周期小于第四掩膜211d的周期，第三掩膜212d和第四掩膜211d用于刻蚀下方的导电层51以形成位线导电层。
参考图8，去除第一牺牲层211c以及第二牺牲层212c，并利用第三掩膜212d和第四掩膜211d对导电层51进行刻蚀工艺，形成位于功能区的第一位线导电层512和位于外围区的第二位线导电层511。由于第一位线导电层512的光栅特征与第三掩膜212d的光栅特征相同，第二位线导电层511的光栅特征与第四掩膜211d的光栅特征相同，因此，第一位线导电层512的开口宽度小于第二位线导电层511的开口宽度。
参考图9，在第一位线导电层512的侧壁形成第一侧墙513，在第二位线导电层511的侧壁形成第二侧墙514；形成填充满相邻第一位线导电层512之间空隙的第一电容接触孔，以作为第二图案212，以及形成填充满相邻第二位线导电层511之间空隙的第二电容接触孔，以作为第二光栅211。
第一侧墙513和第二侧墙514可采用同一沉积工艺形成，第一侧墙513的厚度和第二侧墙514的厚度相同。在第一位线导电层512的开口宽度小于第二位线导电层511的开口宽度，第一侧墙513的厚度和第二侧墙514的厚度相同的情况下，第二图案212的光栅宽度小于第二光栅211的光栅宽度。
第一电容接触孔和第二电容接触孔也可采用同一沉积工艺形成，功能区的第一电容接触孔用于连接字线的漏极，以起到电连接的作用，外围区的第二电容接触孔可以不与字线漏极连接，仅作为套刻标记使用。功能区的埋入式字线60可作为第一图案，外围区的埋入式字线60可作为第一光栅。
在其他实施例中，在形成第一位线导电层和第二位线导电层之后，对第一位线导电层和第二位线导电层进行原位加工，以形成用于隔离的第一侧墙和第二侧墙，例如位线导电层的掺杂多晶硅，对掺杂多晶硅进行氧化或氮化，可形成用于电隔离的氧化硅或氮化硅；在形成第一侧墙和第二侧墙之后，可填充导电材料，以形成第一电容接触孔和第二电容接触孔。在这一情况下，第一电容接触孔的宽度等于图案层的厚度，第二电容接触孔的宽度等于第二掩膜的开口宽度，也就是说，第二电容接触孔的宽度大于第一电容接触孔的宽度且小于等于第一电容接触孔的宽度的两倍。
其中，第一电容接触孔的宽度还可以等于埋入式字线的宽度，在这一情况下，第二电容接触孔的宽度大于埋入式字线的宽度且小于等于埋入式字线的宽度的两倍。
本公开实施例中，设置第一光栅与第二光栅的光栅宽度和/或光栅周期不同，有利于使得对第一光栅和第二光栅进行光照所得到的衍射信号的特征不同，从而将第一光栅的衍射信号和第二光栅的衍射信号区别开来，避免将第一光栅的衍射信号和第二光栅的衍射信号的整体作为第二光栅的衍射信号，保证用于计算套刻误差的衍射信号仅由第一光栅的衍射信号和第二光栅的衍射信号组成，进而实现套刻误差的准确测量。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方 式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构和半导体结构的制备方法中，有利于提升半导体结构的电学性能。

Claims (15)

  1. 一种半导体结构，包括：
    自下向上堆叠且设置于不同光刻层中的第一光栅、第二光栅以及第三光栅，不同所述光刻层中用于设置光栅的套刻标记区域重叠，所述第一光栅、所述第二光栅以及所述第三光栅均为周期性结构，所述周期性结构中相邻所述光栅的中心距离为光栅周期，所述第一光栅与所述第二光栅的光栅宽度和/或所述光栅周期不同。
  2. 根据权利要求1所述的半导体结构，其中，所述第一光栅与所述第二光栅处于相邻的不同所述光刻层。
  3. 根据权利要求1所述的半导体结构，其中，所述第一光栅、所述第二光栅以及所述第三光栅均由周期性排列的间隙、凸块或孔洞组成。
  4. 根据权利要求1所述的半导体结构，其中，所述光刻层包括核心区和外围区，所述外围区位于所述核心区和切割道之间，所述套刻标记区域位于所述外围区内。
  5. 根据权利要求4所述的半导体结构，还包括：处于所述核心区的第一图案和第二图案，所述第一图案与所述第一光栅处于同一所述光刻层，所述第二图案与所述第二光栅处于另一所述光刻层，所述第一光栅与所述第一图案为光栅宽度和光栅周期相同的光栅结构，所述第二光栅与所述第二图案为光栅宽度和/或光栅周期不同的光栅结构。
  6. 根据权利要求5所述的半导体结构，其中，所述第一图案包括字线。
  7. 根据权利要求5所述的半导体结构，其中，所述第二图案包括电容接触孔。
  8. 根据权利要求1所述的半导体结构，其中，所述第二光栅的光栅宽度和光栅周期与所述第三光栅的光栅宽度和光栅周期相同。
  9. 根据权利要求1所述的半导体结构，其中，所述第二光栅的中心位置与所述第一光栅的中心位置在垂直方向上错位，所述第二光栅与所述第一光栅在所述垂直方向上不重叠。
  10. 根据权利要求1所述的半导体结构，其中，所述第二光栅的光栅周期大于所述第一光栅的光栅周期，所述第二光栅的中心位置作为所述第一光栅中部分光栅的中心位置。
  11. 根据权利要求10所述的半导体结构，其中，所述第二光栅的光栅宽度大于所述第一光栅的光栅宽度。
  12. 根据权利要求11所述的半导体结构，其中，所述第二光栅的光栅宽度小于等于所述第一光栅的光栅宽度的两倍。
  13. 一种存储器，包括权利要求1至12中任一项所述的半导体结构。
  14. 一种半导体结构的制作方法，包括：
    形成自下向上堆叠且设置于不同光刻层中的第一光栅、第二光栅以及第三光栅，不同所述光刻层中用于设置光栅的套刻标记区域重叠，所述第一光栅、所述第二光栅以及 所述第三光栅均为周期性结构，所述周期性结构中相邻所述光栅的中心距离为光栅周期，所述第一光栅与所述第二光栅的光栅宽度或所述光栅周期不同。
  15. 根据权利要求14所述的半导体结构的制作方法，所述制作方法还包括：形成第二图案，所述第二光栅和所述第二图案处于同一所述光刻层，所述第二图案与所述第二光栅为光栅周期不同的光栅结构，所述第二光栅的光栅宽度大于所述第二图案的光栅宽度。
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