WO2023035270A1 - Procédé de préparation pour l'épitaxie de source/drain de grille tout autour de la structure, et grille tout autour de la structure - Google Patents

Procédé de préparation pour l'épitaxie de source/drain de grille tout autour de la structure, et grille tout autour de la structure Download PDF

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WO2023035270A1
WO2023035270A1 PCT/CN2021/118020 CN2021118020W WO2023035270A1 WO 2023035270 A1 WO2023035270 A1 WO 2023035270A1 CN 2021118020 W CN2021118020 W CN 2021118020W WO 2023035270 A1 WO2023035270 A1 WO 2023035270A1
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layer
gate
silicon layer
source
amorphous silicon
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PCT/CN2021/118020
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English (en)
Chinese (zh)
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徐敏
刘桃
汪大伟
王晨
张卫
徐赛生
吴春蕾
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上海集成电路制造创新中心有限公司
复旦大学
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Priority to PCT/CN2021/118020 priority Critical patent/WO2023035270A1/fr
Publication of WO2023035270A1 publication Critical patent/WO2023035270A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Definitions

  • the invention relates to the technical field of semiconductors, in particular to an epitaxial preparation method for source and drain of a ring-gate structure and a ring-gate structure.
  • SiGe source-drain selective epitaxy technology can provide effective compressive stress for the channel and improve the mobility of holes in PMOS devices, so that the mobility of holes matches the mobility of electrons and improves the overall performance.
  • SiGe source and drain epitaxy starts from multiple isolated surfaces (for example, in structure a in Figure 1, the gray value is the deepest The source and drain of the epitaxial growth), the epitaxial SiGe crystal planes overlap between adjacent gates (such as the structure b in Figure 1), and it is easy to form stacking faults (such as the structure c in Figure 1) to cause stress relaxation Relaxation, stress relaxation will lead to a decrease in the stress value in the channel, so that the hole mobility cannot be improved, the turn-on current of the device will be reduced, and the performance of the device will be affected.
  • structure a in Figure 1 the gray value is the deepest The source and drain of the epitaxial growth
  • the epitaxial SiGe crystal planes overlap between adjacent gates (such as the structure b in Figure 1)
  • stacking faults such as the structure c in Figure 1
  • stress relaxation will lead to a decrease in the stress value in the channel, so that the hole mobility cannot be improved, the turn-on current of the device will be reduced, and the performance of the device will
  • the invention provides an epitaxial preparation method for the source and drain of the ring gate structure and the ring gate structure to solve the problem of stress relaxation in the source/drain region.
  • an epitaxial preparation method for source and drain of a gate-all-around structure comprising:
  • a substrate is provided, and a plurality of fins are formed on the substrate, and grooves are formed between two adjacent fins along the channel direction;
  • a source/drain region of a ring gate structure is formed on the germanium silicon bulk layer.
  • the fins include stacked layers and dummy gates surrounding the stacked layers, and the stacked layers include alternately stacked sacrificial layers and nanolayers;
  • the height of the amorphous silicon layer matches the height of the stacked layers.
  • depositing an amorphous silicon layer on the substrate includes:
  • the insulating layer is etched away to obtain the amorphous silicon layer.
  • depositing an insulating layer in the groove includes:
  • the insulating layer is deposited in the groove by a flowable chemical vapor deposition method.
  • depositing an insulating layer in the groove includes:
  • the thickness of the amorphous silicon layer is 2-3 nm.
  • the amorphous silicon material is deposited by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition.
  • a gate-all-around structure including: a substrate, a plurality of fins, a single crystal silicon layer, and source/drain regions,
  • the plurality of fins are located on the substrate, along the channel direction, there are grooves between the plurality of fins, and the single crystal silicon layer covers the sidewalls and bottom surfaces of the grooves, so The source/drain region is set in the groove, and the source/drain region is located on the single crystal silicon layer.
  • the fins include stacked layers and dummy gates surrounding the stacked layers, and the stacked layers include alternately stacked sacrificial layers and nanometer layers;
  • the height of the single crystal silicon layer matches the height of the stacked layers.
  • sidewalls of the dummy gate and the sacrificial layer are covered with an isolation layer.
  • the thickness of the single crystal silicon layer is 2-3 nm.
  • the source/drain region is prepared by using the epitaxial preparation method for the source and drain of the gate-around structure described in the first aspect of the present invention and its alternatives.
  • the epitaxial preparation method of the source and drain of the ring gate structure and the ring gate structure provided by the present invention deposit the amorphous silicon layer in the groove, and then crystallize the amorphous silicon layer into a single crystal silicon layer through annealing treatment, and form the single crystal silicon layer
  • the present invention can prepare high-quality silicon germanium body without dislocation
  • the layer provides sufficient stress for the channel to increase the hole mobility of the gate-all-around device, thereby increasing the turn-on current of the gate-all-around device.
  • FIG. 1 is a partial structural schematic diagram of epitaxial growth source and drain in the prior art
  • FIG. 2 is a schematic flow diagram of an epitaxial preparation method for source and drain of a gate-all-around structure in an embodiment of the present invention
  • Fig. 3 is a schematic diagram 1 of different stages of growing source and drain regions in an embodiment of the present invention.
  • FIG. 4 is a second schematic diagram of different stages of growing source and drain regions in an embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of step S102 in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of different stages of forming an amorphous silicon layer in an embodiment of the present invention.
  • FIG. 7 is a first schematic flow diagram of step S1022 in an embodiment of the present invention.
  • FIG. 8 is a second schematic flow diagram of step S1022 in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of different stages of forming an insulating layer in an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a gate-all-around structure in an embodiment of the present invention.
  • an embodiment of the present invention provides an epitaxial preparation method for source and drain of a gate-around structure, including:
  • S101 Provide a substrate, and form a plurality of fins on the substrate, along the channel direction, there is a groove between two adjacent fins;
  • the substrate therein can be Si or SOI (English full name is Silicon On Insulator, Chinese full name is silicon on insulating substrate), and the fins therein can include alternately stacked nano-layers and sacrificial layers, wherein the nano-layers is Si, and the sacrificial layer is SiGe;
  • step S101 may specifically include:
  • a substrate is provided, and an epitaxial layer is formed on the substrate, and the epitaxial layer includes alternately stacked channel layers and sacrificial layers;
  • Forming a plurality of fins based on a plurality of fins can be, for example, the shape shown in structure A in FIG. 3 , including a substrate 201 and a fin 202 located on the substrate;
  • the epitaxial layer and the substrate can be etched to form a plurality of fins; then based on the plurality of fins and the etched substrate, a plurality of fins can be formed;
  • the amorphous silicon layer therein can specifically be, for example, the amorphous silicon layer 203 in structure B in FIG. )
  • the surface of the amorphous silicon layer can be in the shape of a right angle, that is, as shown in structure B in Figure 3, or it can be in the shape of a smooth arc.
  • the junction of the amorphous silicon layers on the bottom surface can be directly connected together in a right-angle shape, or can be connected together by using a smooth curved surface as a transition surface.
  • the thickness of the amorphous silicon layer is 2-3 nm;
  • step S103 the process of obtaining the single crystal silicon layer can be understood as, during the annealing process, the nano-layer in the fin and the substrate can be used as a seed layer due to contact with the amorphous silicon layer, and the leakage of single crystal silicon occurs, inducing
  • the amorphous silicon layer deposited in step S102 is crystallized again and converted into a continuous high-quality single crystal silicon layer to obtain the single crystal silicon layer 204 of structure C in FIG. 3; for example, in step S103, it can be carried out under N atmosphere Laser annealing, rapid melting and then recrystallization;
  • S104 Using the surface of the single crystal silicon layer as a starting surface, epitaxially grow silicon germanium material to form a silicon germanium bulk layer;
  • step S104 can specifically be understood as taking the surface of the U-shaped single crystal silicon layer as the starting surface for the epitaxial growth of the silicon-germanium bulk layer, and epitaxially growing the silicon-germanium material to form the bulk silicon-germanium layer, such as the structure in FIG. 3
  • S105 Forming a source/drain region of a gate-around structure on the SiGe bulk layer
  • step S105 includes:
  • An interlayer dielectric is deposited on the surface of the doped silicon germanium bulk layer to form a source/drain region of a gate-all-around device.
  • step S101 a plurality of fins are formed on the substrate to obtain the coated structure A; after depositing an amorphous silicon layer in step S102, the figure Structure B in 3; after the amorphous silicon layer is annealed in step S103, the amorphous silicon layer crystallizes to form a single crystal silicon layer, and structure C in Figure 3 is obtained; in step S104, the single crystal silicon layer is used as the initial surface, The silicon germanium material is epitaxially grown to form a silicon germanium bulk layer, which can wait until the structure D in Figure 3, and then form the source/drain region of the ring gate structure based on the structure D.
  • the present invention can prepare a high-quality silicon germanium bulk layer without dislocations, provide sufficient stress for the channel, and improve the ring
  • the hole mobility of the gate device can be improved, thereby increasing the turn-on current of the gate-all-around device.
  • the fin includes a stacked layer and a dummy gate surrounding the stacked layer, and the stacked layer includes alternately stacked sacrificial layers and nanolayers;
  • the height of the amorphous silicon layer matches the height of the stacked layers
  • the height of the amorphous silicon layer matches the height of the stacked layers, it can be understood that when the uppermost layer in the stacked layers is a nano-layer, the height of the amorphous silicon layer is equal to the height of the stacked layers; When the upper layer is a sacrificial layer, the height of the amorphous silicon layer can be equal to the height of the stacked layer, or can be equal to the height of the top nano-layer in the stacked layer; and then as long as the height of the amorphous silicon layer can satisfy: When the silicon germanium material is grown epitaxially, the silicon germanium material is not grown on the side surface of the isolated nanometer layer, and a silicon germanium bulk layer without overlapping stacking faults can be grown.
  • step S101 to step S104 can be shown in FIG. 4, for example, which includes sacrificial layer 2021, nanometer layer 2022, dummy gate 2023, and multilayer sacrificial layer 2021 and multilayer nanolayer 2022 are stacked alternately to form a stacked layer ;
  • Structures A to D in FIG. 4 correspond one-to-one to structures A to D in FIG. 3 , and the manufacturing method is the same as that of Structures A to D in FIG. 3 .
  • the height of the silicon layer is further limited, and the specific structure of the fin is further described.
  • step S101 includes:
  • a substrate is provided, and an epitaxial layer is formed on the substrate, and the epitaxial layer includes alternately stacked channel layers and sacrificial layers;
  • a part of the sacrificial layer 2021 and the dummy gate 2023 can be etched in the direction of the central axis of the corresponding fin, and the etched space can be used to deposit an isolation layer (For example, the isolation layer 2024 in FIG.
  • step S105 it may further include:
  • Introducing stress in the channel region can increase the mobility of holes in the fin and increase the turn-on current of the gate-all-around device.
  • multiple fins are PMOS fins, and then the same compressive stress can be introduced in the channel region, increasing the mobility of holes on the nano-layer in the PMOS fins, and improving the turn-on current of the gate-all-around device ;
  • the multiple fins include PMOS fins and NMOS fins, and then different stresses can be introduced into the channels of the PMOS fins and the channels of the NMOS fins, so that the current of the PMOS fins matches that of the NMOS fins. slice current;
  • the plurality of fins includes PMOS fins and NMOS fins, and then tensile stress can be introduced only in the channel region of the NMOS fins, reducing the mobility of holes on the nano-layer in the NMOS fins, Make the current of the PMOS fin match the current of the NMOS fin.
  • step S102 includes:
  • Step S1021 may specifically include: isotropically depositing amorphous silicon material 206 on the substrate to obtain the structure B1 in FIG. 6 ;
  • isotropic deposition can be, for example, low-pressure chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD), etc., can be based on the specific production process And choose the appropriate deposition method according to actual needs;
  • CVD chemical Vapor Deposition
  • PECVD plasma enhanced chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the height of the insulating layer 207 matches the height of the stacked layers; the insulating layer can be, for example, SiO 2 to obtain the structure B2 in FIG. 6 ;
  • the etching of the amorphous silicon material 206 is specifically to etch the amorphous silicon material 2-3nm, where the 2-3nm is the thickness of the etching, and the isolation protection of the insulating layer 207 will match the height of the stack layer Part of the amorphous silicon material is protected from being etched away, and then part of the amorphous silicon material higher than the stacked layer is etched away to obtain the structure B3 in Figure 6;
  • Step S1024 can be understood as, etching away the insulating layer 207 in the structure B3 in FIG. 6 to obtain the structure B4 in FIG. 6 .
  • step S1022 includes:
  • S10221 Deposit the insulating layer in the groove by using a flowable chemical vapor deposition method.
  • FCVD flowable chemical vapor deposition
  • step S1022 includes:
  • the deposition in step S10222 can be isotropic deposition to obtain the insulating material 208 of structure B21 in FIG.
  • Enhanced Chemical Vapor Deposition referred to as PECVD
  • PECVD Enhanced Chemical Vapor Deposition
  • the polishing can be chemical mechanical polishing (CMP for short), so as to obtain the polished insulating material 208 in the structure B22 in FIG. 9;
  • CMP chemical mechanical polishing
  • part of the insulating material in the insulating material 208 of the structure B22 is etched away to obtain the insulating layer 207 in the structure B23 .
  • Steps S10222 to S10224 in the above embodiment and the above step S10221 are two different methods of depositing the insulating layer.
  • the insulating layer can only be obtained after polishing and etching after deposition, and an appropriate method can be selected to deposit the insulating layer according to the process and actual needs.
  • an embodiment of the present invention also provides a gate-around structure, including: a substrate 201, a plurality of fins 202, a single crystal silicon layer 204 and a source/drain region 209,
  • the plurality of fins 202 are located on the substrate 201, along the channel direction, there are grooves between the plurality of fins 202, and the single crystal silicon layer 204 covers the sidewalls of the grooves
  • the source/drain region 209 is disposed in the groove, and the source/drain region 209 is located on the single crystal silicon layer 204 .
  • the fin 202 includes a stacked layer and a dummy gate 2023 surrounding the stacked layer, and the stacked layer includes alternately stacked sacrificial layers 2021 and nanometer layers 2022;
  • the height of the single crystal silicon layer 2024 matches the height of the stacked layers.
  • the sidewalls of the dummy gate 2023 and the sacrificial layer 2021 are covered with an isolation layer 2024 .
  • the thickness of the single crystal silicon layer 2024 is 2-3 nm.
  • the source/drain region 209 is prepared by using the epitaxial preparation method for the source and drain of the gate-around structure described above.

Abstract

La présente demande concerne un procédé de préparation pour l'épitaxie d'une source/drain d'une grille tout autour de la structure, et une grille tout autour de la structure. Le procédé comprend les étapes consistant à : fournir un substrat et former une pluralité d'ailettes sur le substrat, une rainure évidée étant présente entre une paire adjacente d'ailettes dans une direction d'un canal ; déposer une couche de silicium amorphe sur le substrat ; recuire la couche de silicium amorphe pour provoquer la cristallisation de la couche de silicium amorphe dans une couche de silicium monocristallin ; réaliser une croissance épitaxiale d'un matériau de silicium de germanium à l'aide d'une surface de la couche de silicium monocristallin en tant que surface de départ, et former une couche de corps de silicium de germanium ; et former une zone source/drain d'une grille tout autour de la structure au niveau de la couche de corps en silicium germanium. Au moyen du dépôt de la couche de silicium amorphe dans une rainure évidée, puis de la cristallisation de la couche de silicium amorphe qui a subi un traitement de recuit dans la couche de silicium monocristallin, et la croissance de la couche de corps de silicium de germanium à l'aide de la couche de silicium monocristallin comme surface de départ, une couche de corps en silicium de germanium de haute qualité exempte de dislocations peut être préparée, une quantité suffisante de contrainte est fournie pour le canal, la mobilité des trous d'un dispositif tout autour est améliorée, et un courant de mise sous tension de la grille tout autour du dispositif est en outre amélioré.
PCT/CN2021/118020 2021-09-13 2021-09-13 Procédé de préparation pour l'épitaxie de source/drain de grille tout autour de la structure, et grille tout autour de la structure WO2023035270A1 (fr)

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CN103855018A (zh) * 2012-12-04 2014-06-11 上海华虹宏力半导体制造有限公司 沟槽底部进行离子注入调节bv和改善导通电阻的方法
CN103943508A (zh) * 2014-03-27 2014-07-23 上海华力微电子有限公司 Pmos器件的制造方法
US20190341467A1 (en) * 2017-12-19 2019-11-07 International Business Machines Corporation Nanosheet device with close source drain proximity
CN111653610A (zh) * 2020-06-24 2020-09-11 上海华力集成电路制造有限公司 一种gaa结构的形成方法
CN111799331A (zh) * 2020-04-28 2020-10-20 中国科学院微电子研究所 一种半导体器件及其制作方法、集成电路及电子设备
CN112242342A (zh) * 2019-07-17 2021-01-19 上海新微技术研发中心有限公司 单晶硅局域soi衬底、光电器件及制备方法
CN113284806A (zh) * 2021-05-18 2021-08-20 复旦大学 环栅器件及其源漏制备方法、器件制备方法、电子设备

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103855018A (zh) * 2012-12-04 2014-06-11 上海华虹宏力半导体制造有限公司 沟槽底部进行离子注入调节bv和改善导通电阻的方法
CN103943508A (zh) * 2014-03-27 2014-07-23 上海华力微电子有限公司 Pmos器件的制造方法
US20190341467A1 (en) * 2017-12-19 2019-11-07 International Business Machines Corporation Nanosheet device with close source drain proximity
CN112242342A (zh) * 2019-07-17 2021-01-19 上海新微技术研发中心有限公司 单晶硅局域soi衬底、光电器件及制备方法
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CN111653610A (zh) * 2020-06-24 2020-09-11 上海华力集成电路制造有限公司 一种gaa结构的形成方法
CN113284806A (zh) * 2021-05-18 2021-08-20 复旦大学 环栅器件及其源漏制备方法、器件制备方法、电子设备

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