WO2023035270A1 - Preparation method for epitaxy of source/drain of gate all around structure, and gate all around structure - Google Patents

Preparation method for epitaxy of source/drain of gate all around structure, and gate all around structure Download PDF

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WO2023035270A1
WO2023035270A1 PCT/CN2021/118020 CN2021118020W WO2023035270A1 WO 2023035270 A1 WO2023035270 A1 WO 2023035270A1 CN 2021118020 W CN2021118020 W CN 2021118020W WO 2023035270 A1 WO2023035270 A1 WO 2023035270A1
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layer
gate
silicon layer
source
amorphous silicon
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PCT/CN2021/118020
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French (fr)
Chinese (zh)
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徐敏
刘桃
汪大伟
王晨
张卫
徐赛生
吴春蕾
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上海集成电路制造创新中心有限公司
复旦大学
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Priority to PCT/CN2021/118020 priority Critical patent/WO2023035270A1/en
Publication of WO2023035270A1 publication Critical patent/WO2023035270A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Definitions

  • the invention relates to the technical field of semiconductors, in particular to an epitaxial preparation method for source and drain of a ring-gate structure and a ring-gate structure.
  • SiGe source-drain selective epitaxy technology can provide effective compressive stress for the channel and improve the mobility of holes in PMOS devices, so that the mobility of holes matches the mobility of electrons and improves the overall performance.
  • SiGe source and drain epitaxy starts from multiple isolated surfaces (for example, in structure a in Figure 1, the gray value is the deepest The source and drain of the epitaxial growth), the epitaxial SiGe crystal planes overlap between adjacent gates (such as the structure b in Figure 1), and it is easy to form stacking faults (such as the structure c in Figure 1) to cause stress relaxation Relaxation, stress relaxation will lead to a decrease in the stress value in the channel, so that the hole mobility cannot be improved, the turn-on current of the device will be reduced, and the performance of the device will be affected.
  • structure a in Figure 1 the gray value is the deepest The source and drain of the epitaxial growth
  • the epitaxial SiGe crystal planes overlap between adjacent gates (such as the structure b in Figure 1)
  • stacking faults such as the structure c in Figure 1
  • stress relaxation will lead to a decrease in the stress value in the channel, so that the hole mobility cannot be improved, the turn-on current of the device will be reduced, and the performance of the device will
  • the invention provides an epitaxial preparation method for the source and drain of the ring gate structure and the ring gate structure to solve the problem of stress relaxation in the source/drain region.
  • an epitaxial preparation method for source and drain of a gate-all-around structure comprising:
  • a substrate is provided, and a plurality of fins are formed on the substrate, and grooves are formed between two adjacent fins along the channel direction;
  • a source/drain region of a ring gate structure is formed on the germanium silicon bulk layer.
  • the fins include stacked layers and dummy gates surrounding the stacked layers, and the stacked layers include alternately stacked sacrificial layers and nanolayers;
  • the height of the amorphous silicon layer matches the height of the stacked layers.
  • depositing an amorphous silicon layer on the substrate includes:
  • the insulating layer is etched away to obtain the amorphous silicon layer.
  • depositing an insulating layer in the groove includes:
  • the insulating layer is deposited in the groove by a flowable chemical vapor deposition method.
  • depositing an insulating layer in the groove includes:
  • the thickness of the amorphous silicon layer is 2-3 nm.
  • the amorphous silicon material is deposited by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition.
  • a gate-all-around structure including: a substrate, a plurality of fins, a single crystal silicon layer, and source/drain regions,
  • the plurality of fins are located on the substrate, along the channel direction, there are grooves between the plurality of fins, and the single crystal silicon layer covers the sidewalls and bottom surfaces of the grooves, so The source/drain region is set in the groove, and the source/drain region is located on the single crystal silicon layer.
  • the fins include stacked layers and dummy gates surrounding the stacked layers, and the stacked layers include alternately stacked sacrificial layers and nanometer layers;
  • the height of the single crystal silicon layer matches the height of the stacked layers.
  • sidewalls of the dummy gate and the sacrificial layer are covered with an isolation layer.
  • the thickness of the single crystal silicon layer is 2-3 nm.
  • the source/drain region is prepared by using the epitaxial preparation method for the source and drain of the gate-around structure described in the first aspect of the present invention and its alternatives.
  • the epitaxial preparation method of the source and drain of the ring gate structure and the ring gate structure provided by the present invention deposit the amorphous silicon layer in the groove, and then crystallize the amorphous silicon layer into a single crystal silicon layer through annealing treatment, and form the single crystal silicon layer
  • the present invention can prepare high-quality silicon germanium body without dislocation
  • the layer provides sufficient stress for the channel to increase the hole mobility of the gate-all-around device, thereby increasing the turn-on current of the gate-all-around device.
  • FIG. 1 is a partial structural schematic diagram of epitaxial growth source and drain in the prior art
  • FIG. 2 is a schematic flow diagram of an epitaxial preparation method for source and drain of a gate-all-around structure in an embodiment of the present invention
  • Fig. 3 is a schematic diagram 1 of different stages of growing source and drain regions in an embodiment of the present invention.
  • FIG. 4 is a second schematic diagram of different stages of growing source and drain regions in an embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of step S102 in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of different stages of forming an amorphous silicon layer in an embodiment of the present invention.
  • FIG. 7 is a first schematic flow diagram of step S1022 in an embodiment of the present invention.
  • FIG. 8 is a second schematic flow diagram of step S1022 in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of different stages of forming an insulating layer in an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a gate-all-around structure in an embodiment of the present invention.
  • an embodiment of the present invention provides an epitaxial preparation method for source and drain of a gate-around structure, including:
  • S101 Provide a substrate, and form a plurality of fins on the substrate, along the channel direction, there is a groove between two adjacent fins;
  • the substrate therein can be Si or SOI (English full name is Silicon On Insulator, Chinese full name is silicon on insulating substrate), and the fins therein can include alternately stacked nano-layers and sacrificial layers, wherein the nano-layers is Si, and the sacrificial layer is SiGe;
  • step S101 may specifically include:
  • a substrate is provided, and an epitaxial layer is formed on the substrate, and the epitaxial layer includes alternately stacked channel layers and sacrificial layers;
  • Forming a plurality of fins based on a plurality of fins can be, for example, the shape shown in structure A in FIG. 3 , including a substrate 201 and a fin 202 located on the substrate;
  • the epitaxial layer and the substrate can be etched to form a plurality of fins; then based on the plurality of fins and the etched substrate, a plurality of fins can be formed;
  • the amorphous silicon layer therein can specifically be, for example, the amorphous silicon layer 203 in structure B in FIG. )
  • the surface of the amorphous silicon layer can be in the shape of a right angle, that is, as shown in structure B in Figure 3, or it can be in the shape of a smooth arc.
  • the junction of the amorphous silicon layers on the bottom surface can be directly connected together in a right-angle shape, or can be connected together by using a smooth curved surface as a transition surface.
  • the thickness of the amorphous silicon layer is 2-3 nm;
  • step S103 the process of obtaining the single crystal silicon layer can be understood as, during the annealing process, the nano-layer in the fin and the substrate can be used as a seed layer due to contact with the amorphous silicon layer, and the leakage of single crystal silicon occurs, inducing
  • the amorphous silicon layer deposited in step S102 is crystallized again and converted into a continuous high-quality single crystal silicon layer to obtain the single crystal silicon layer 204 of structure C in FIG. 3; for example, in step S103, it can be carried out under N atmosphere Laser annealing, rapid melting and then recrystallization;
  • S104 Using the surface of the single crystal silicon layer as a starting surface, epitaxially grow silicon germanium material to form a silicon germanium bulk layer;
  • step S104 can specifically be understood as taking the surface of the U-shaped single crystal silicon layer as the starting surface for the epitaxial growth of the silicon-germanium bulk layer, and epitaxially growing the silicon-germanium material to form the bulk silicon-germanium layer, such as the structure in FIG. 3
  • S105 Forming a source/drain region of a gate-around structure on the SiGe bulk layer
  • step S105 includes:
  • An interlayer dielectric is deposited on the surface of the doped silicon germanium bulk layer to form a source/drain region of a gate-all-around device.
  • step S101 a plurality of fins are formed on the substrate to obtain the coated structure A; after depositing an amorphous silicon layer in step S102, the figure Structure B in 3; after the amorphous silicon layer is annealed in step S103, the amorphous silicon layer crystallizes to form a single crystal silicon layer, and structure C in Figure 3 is obtained; in step S104, the single crystal silicon layer is used as the initial surface, The silicon germanium material is epitaxially grown to form a silicon germanium bulk layer, which can wait until the structure D in Figure 3, and then form the source/drain region of the ring gate structure based on the structure D.
  • the present invention can prepare a high-quality silicon germanium bulk layer without dislocations, provide sufficient stress for the channel, and improve the ring
  • the hole mobility of the gate device can be improved, thereby increasing the turn-on current of the gate-all-around device.
  • the fin includes a stacked layer and a dummy gate surrounding the stacked layer, and the stacked layer includes alternately stacked sacrificial layers and nanolayers;
  • the height of the amorphous silicon layer matches the height of the stacked layers
  • the height of the amorphous silicon layer matches the height of the stacked layers, it can be understood that when the uppermost layer in the stacked layers is a nano-layer, the height of the amorphous silicon layer is equal to the height of the stacked layers; When the upper layer is a sacrificial layer, the height of the amorphous silicon layer can be equal to the height of the stacked layer, or can be equal to the height of the top nano-layer in the stacked layer; and then as long as the height of the amorphous silicon layer can satisfy: When the silicon germanium material is grown epitaxially, the silicon germanium material is not grown on the side surface of the isolated nanometer layer, and a silicon germanium bulk layer without overlapping stacking faults can be grown.
  • step S101 to step S104 can be shown in FIG. 4, for example, which includes sacrificial layer 2021, nanometer layer 2022, dummy gate 2023, and multilayer sacrificial layer 2021 and multilayer nanolayer 2022 are stacked alternately to form a stacked layer ;
  • Structures A to D in FIG. 4 correspond one-to-one to structures A to D in FIG. 3 , and the manufacturing method is the same as that of Structures A to D in FIG. 3 .
  • the height of the silicon layer is further limited, and the specific structure of the fin is further described.
  • step S101 includes:
  • a substrate is provided, and an epitaxial layer is formed on the substrate, and the epitaxial layer includes alternately stacked channel layers and sacrificial layers;
  • a part of the sacrificial layer 2021 and the dummy gate 2023 can be etched in the direction of the central axis of the corresponding fin, and the etched space can be used to deposit an isolation layer (For example, the isolation layer 2024 in FIG.
  • step S105 it may further include:
  • Introducing stress in the channel region can increase the mobility of holes in the fin and increase the turn-on current of the gate-all-around device.
  • multiple fins are PMOS fins, and then the same compressive stress can be introduced in the channel region, increasing the mobility of holes on the nano-layer in the PMOS fins, and improving the turn-on current of the gate-all-around device ;
  • the multiple fins include PMOS fins and NMOS fins, and then different stresses can be introduced into the channels of the PMOS fins and the channels of the NMOS fins, so that the current of the PMOS fins matches that of the NMOS fins. slice current;
  • the plurality of fins includes PMOS fins and NMOS fins, and then tensile stress can be introduced only in the channel region of the NMOS fins, reducing the mobility of holes on the nano-layer in the NMOS fins, Make the current of the PMOS fin match the current of the NMOS fin.
  • step S102 includes:
  • Step S1021 may specifically include: isotropically depositing amorphous silicon material 206 on the substrate to obtain the structure B1 in FIG. 6 ;
  • isotropic deposition can be, for example, low-pressure chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD), etc., can be based on the specific production process And choose the appropriate deposition method according to actual needs;
  • CVD chemical Vapor Deposition
  • PECVD plasma enhanced chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the height of the insulating layer 207 matches the height of the stacked layers; the insulating layer can be, for example, SiO 2 to obtain the structure B2 in FIG. 6 ;
  • the etching of the amorphous silicon material 206 is specifically to etch the amorphous silicon material 2-3nm, where the 2-3nm is the thickness of the etching, and the isolation protection of the insulating layer 207 will match the height of the stack layer Part of the amorphous silicon material is protected from being etched away, and then part of the amorphous silicon material higher than the stacked layer is etched away to obtain the structure B3 in Figure 6;
  • Step S1024 can be understood as, etching away the insulating layer 207 in the structure B3 in FIG. 6 to obtain the structure B4 in FIG. 6 .
  • step S1022 includes:
  • S10221 Deposit the insulating layer in the groove by using a flowable chemical vapor deposition method.
  • FCVD flowable chemical vapor deposition
  • step S1022 includes:
  • the deposition in step S10222 can be isotropic deposition to obtain the insulating material 208 of structure B21 in FIG.
  • Enhanced Chemical Vapor Deposition referred to as PECVD
  • PECVD Enhanced Chemical Vapor Deposition
  • the polishing can be chemical mechanical polishing (CMP for short), so as to obtain the polished insulating material 208 in the structure B22 in FIG. 9;
  • CMP chemical mechanical polishing
  • part of the insulating material in the insulating material 208 of the structure B22 is etched away to obtain the insulating layer 207 in the structure B23 .
  • Steps S10222 to S10224 in the above embodiment and the above step S10221 are two different methods of depositing the insulating layer.
  • the insulating layer can only be obtained after polishing and etching after deposition, and an appropriate method can be selected to deposit the insulating layer according to the process and actual needs.
  • an embodiment of the present invention also provides a gate-around structure, including: a substrate 201, a plurality of fins 202, a single crystal silicon layer 204 and a source/drain region 209,
  • the plurality of fins 202 are located on the substrate 201, along the channel direction, there are grooves between the plurality of fins 202, and the single crystal silicon layer 204 covers the sidewalls of the grooves
  • the source/drain region 209 is disposed in the groove, and the source/drain region 209 is located on the single crystal silicon layer 204 .
  • the fin 202 includes a stacked layer and a dummy gate 2023 surrounding the stacked layer, and the stacked layer includes alternately stacked sacrificial layers 2021 and nanometer layers 2022;
  • the height of the single crystal silicon layer 2024 matches the height of the stacked layers.
  • the sidewalls of the dummy gate 2023 and the sacrificial layer 2021 are covered with an isolation layer 2024 .
  • the thickness of the single crystal silicon layer 2024 is 2-3 nm.
  • the source/drain region 209 is prepared by using the epitaxial preparation method for the source and drain of the gate-around structure described above.

Abstract

Provided in the present application are a preparation method for epitaxy of a source/drain of a gate all around structure, and a gate all around structure. The method comprises: providing a substrate and forming a plurality of fins on the substrate, where a recessed groove is present between an adjacent pair of fins in a direction of a channel; depositing an amorphous silicon layer on the substrate; annealing the amorphous silicon layer to cause the amorphous silicon layer to crystallize into a monocrystalline silicon layer; performing epitaxial growth of a germanium silicon material using a surface of the monocrystalline silicon layer as a starting surface, and forming a germanium silicon body layer; and forming a source/drain area of a gate all around structure at the germanium silicon body layer. By means of depositing the amorphous silicon layer in a recessed groove, then crystallizing the amorphous silicon layer that has undergone annealing treatment into the monocrystalline silicon layer, and growing the germanium silicon body layer using the monocrystalline silicon layer as the starting surface, a high quality germanium silicon body layer free of dislocations can be prepared, a sufficient amount of stress is provided for the channel, hole mobility of a gate all around device is improved, and a turn-on current of the gate all around device is further improved.

Description

环栅结构源漏的外延制备方法以及环栅结构Epitaxial preparation method for source and drain of ring gate structure and ring gate structure 技术领域technical field
本发明涉及半导体技术领域，尤其涉及一种环栅结构源漏的外延制备方法以及环栅结构。The invention relates to the technical field of semiconductors, in particular to an epitaxial preparation method for source and drain of a ring-gate structure and a ring-gate structure.
背景技术Background technique
SiGe源漏选择性外延技术能够为沟道提供有效的压应力，提升PMOS器件中空穴的迁移率，从而使得空穴的迁移率与电子迁移率相匹配，提升整体性能。SiGe source-drain selective epitaxy technology can provide effective compressive stress for the channel and improve the mobility of holes in PMOS devices, so that the mobility of holes matches the mobility of electrons and improves the overall performance.
在先进节点的GAAFET(英文全称为Gate All Around FET)器件中，由于采用纳米片作为沟道，SiGe源漏外延起始于多个孤立表面(例如图1中的结构a中，灰度值最深的即为外延生长的源漏)，相邻栅极之间外延的SiGe晶面交叠(例如图1中的结构b)，容易形成层错(例如图1中的结构c)从而造成应力弛豫，应力驰豫将导致沟道中应力值减小，从而无法提升空穴迁移率，降低器件的开启电流，影响器件的性能。In advanced node GAAFET (Gate All Around FET) devices, due to the use of nanosheets as channels, SiGe source and drain epitaxy starts from multiple isolated surfaces (for example, in structure a in Figure 1, the gray value is the deepest The source and drain of the epitaxial growth), the epitaxial SiGe crystal planes overlap between adjacent gates (such as the structure b in Figure 1), and it is easy to form stacking faults (such as the structure c in Figure 1) to cause stress relaxation Relaxation, stress relaxation will lead to a decrease in the stress value in the channel, so that the hole mobility cannot be improved, the turn-on current of the device will be reduced, and the performance of the device will be affected.
发明内容Contents of the invention
本发明提供一种环栅结构源漏的外延制备方法以及环栅结构，以解决源/漏区应力弛豫的问题。The invention provides an epitaxial preparation method for the source and drain of the ring gate structure and the ring gate structure to solve the problem of stress relaxation in the source/drain region.
根据本发明的第一方面，提供了一种环栅结构源漏的外延制备方法，包括：According to the first aspect of the present invention, there is provided an epitaxial preparation method for source and drain of a gate-all-around structure, comprising:
提供一衬底，在所述衬底上形成多个鳍片，沿沟道方向，相邻的两个鳍片之间具有凹槽；A substrate is provided, and a plurality of fins are formed on the substrate, and grooves are formed between two adjacent fins along the channel direction;
在所述衬底上淀积非晶硅层；depositing an amorphous silicon layer on the substrate;
对所述非晶硅层进行退火，以使所述非晶硅层结晶形成单晶硅层；annealing the amorphous silicon layer to crystallize the amorphous silicon layer to form a single crystal silicon layer;
以所述单晶硅层的表面为起始表面，外延生长锗硅材料，形成锗硅体层；Using the surface of the single crystal silicon layer as a starting surface, epitaxially grow a silicon germanium material to form a silicon germanium bulk layer;
在所述锗硅体层形成环栅结构的源/漏区。A source/drain region of a ring gate structure is formed on the germanium silicon bulk layer.
可选的，所述鳍片包括堆叠层与环绕于所述堆叠层上的伪栅极，所述堆 叠层包括交替层叠的牺牲层以及纳米层；Optionally, the fins include stacked layers and dummy gates surrounding the stacked layers, and the stacked layers include alternately stacked sacrificial layers and nanolayers;
所述非晶硅层的高度匹配于所述堆叠层的高度。The height of the amorphous silicon layer matches the height of the stacked layers.
可选的，在所述衬底上淀积非晶硅层，包括：Optionally, depositing an amorphous silicon layer on the substrate includes:
在所述衬底上淀积非晶硅材料；depositing an amorphous silicon material on the substrate;
在所述凹槽内淀积绝缘层，所述绝缘层的高度匹配于所述堆叠层的高度；depositing an insulating layer in the groove, the height of the insulating layer matching the height of the stacked layers;
基于所述绝缘层，刻蚀掉所述非晶硅材料中高于所述堆叠层的部分非晶硅材料；Based on the insulating layer, etching away part of the amorphous silicon material higher than the stacked layer in the amorphous silicon material;
刻蚀掉所述绝缘层，得到所述非晶硅层。The insulating layer is etched away to obtain the amorphous silicon layer.
可选的，在所述凹槽内淀积绝缘层，包括：Optionally, depositing an insulating layer in the groove includes:
采用可流动性化学气相淀积法，在所述凹槽内淀积所述绝缘层。The insulating layer is deposited in the groove by a flowable chemical vapor deposition method.
可选的，在所述凹槽内淀积绝缘层，包括：Optionally, depositing an insulating layer in the groove includes:
在所述凹槽内淀积绝缘材料；depositing an insulating material within the groove;
对所述绝缘材料进行抛光处理；polishing the insulating material;
刻蚀掉所述绝缘材料中高于所述堆叠层的部分绝缘材料，得到所述绝缘层。Etching away a part of the insulating material higher than the stacked layer in the insulating material to obtain the insulating layer.
可选的，所述非晶硅层的厚度为2-3nm。Optionally, the thickness of the amorphous silicon layer is 2-3 nm.
可选的，所述非晶硅材料采用低压化学气相淀积法或等离子增强化学气相淀积法进行淀积。Optionally, the amorphous silicon material is deposited by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition.
根据本发明的第二方面，提供了一种环栅结构，包括：衬底、多个鳍片、单晶硅层和源/漏区，According to a second aspect of the present invention, a gate-all-around structure is provided, including: a substrate, a plurality of fins, a single crystal silicon layer, and source/drain regions,
所述多个鳍片位于所述衬底之上，沿沟道方向，所述多个鳍片之间具有凹槽，所述单晶硅层覆盖于所述凹槽的侧壁与底面，所述源/漏区设于所述凹槽内，所述源/漏区位于单晶硅层之上。The plurality of fins are located on the substrate, along the channel direction, there are grooves between the plurality of fins, and the single crystal silicon layer covers the sidewalls and bottom surfaces of the grooves, so The source/drain region is set in the groove, and the source/drain region is located on the single crystal silicon layer.
可选的，所述鳍片包括堆叠层与环绕于所述堆叠层上的伪栅极，所述堆叠层包括交替层叠的牺牲层以及纳米层；Optionally, the fins include stacked layers and dummy gates surrounding the stacked layers, and the stacked layers include alternately stacked sacrificial layers and nanometer layers;
所述单晶硅层的高度匹配于所述堆叠层的高度。The height of the single crystal silicon layer matches the height of the stacked layers.
可选的，所述伪栅极与所述牺牲层的侧壁覆盖有隔离层。Optionally, sidewalls of the dummy gate and the sacrificial layer are covered with an isolation layer.
可选的，所述单晶硅层的厚度为2-3nm。Optionally, the thickness of the single crystal silicon layer is 2-3 nm.
可选的，所述源/漏区是利用本发明第一方面及其可选方案所述的环栅结构源漏的外延制备方法制备的。Optionally, the source/drain region is prepared by using the epitaxial preparation method for the source and drain of the gate-around structure described in the first aspect of the present invention and its alternatives.
本发明提供的环栅结构源漏的外延制备方法以及环栅结构，通过在凹槽淀积非晶硅层，然后将非晶硅层经过退火处理结晶成单晶硅层，以单晶硅层为起始表面生长锗硅体层的方法，相比于部分方案中，以多个孤立的表面为起始表面而产生大量的层错，本发明能够制备出无位错高质量的硅锗体层，为沟道提供足够的应力，提升环栅器件的空穴迁移率，进而提高环栅器件的开启电流。The epitaxial preparation method of the source and drain of the ring gate structure and the ring gate structure provided by the present invention, deposit the amorphous silicon layer in the groove, and then crystallize the amorphous silicon layer into a single crystal silicon layer through annealing treatment, and form the single crystal silicon layer Compared with the method of growing silicon germanium body layer as the starting surface, a large number of stacking faults are generated by using multiple isolated surfaces as the starting surface, the present invention can prepare high-quality silicon germanium body without dislocation The layer provides sufficient stress for the channel to increase the hole mobility of the gate-all-around device, thereby increasing the turn-on current of the gate-all-around device.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.
图1是现有技术中外延生长源漏的部分结构示意图；FIG. 1 is a partial structural schematic diagram of epitaxial growth source and drain in the prior art;
图2是本发明一实施例中环栅结构源漏的外延制备方法的流程示意图一；FIG. 2 is a schematic flow diagram of an epitaxial preparation method for source and drain of a gate-all-around structure in an embodiment of the present invention;
图3是本发明一实施例中生长源漏区的不同阶段示意图一；Fig. 3 is a schematic diagram 1 of different stages of growing source and drain regions in an embodiment of the present invention;
图4是本发明一实施例中生长源漏区的不同阶段示意图二；FIG. 4 is a second schematic diagram of different stages of growing source and drain regions in an embodiment of the present invention;
图5是本发明一实施例中步骤S102的流程示意图；FIG. 5 is a schematic flow chart of step S102 in an embodiment of the present invention;
图6是本发明一实施例中形成非晶硅层的不同阶段示意图；6 is a schematic diagram of different stages of forming an amorphous silicon layer in an embodiment of the present invention;
图7是本发明一实施例中步骤S1022的流程示意图一；FIG. 7 is a first schematic flow diagram of step S1022 in an embodiment of the present invention;
图8是本发明一实施例中步骤S1022的流程示意图二；FIG. 8 is a second schematic flow diagram of step S1022 in an embodiment of the present invention;
图9是本发明一实施例中形成绝缘层的不同阶段示意图；9 is a schematic diagram of different stages of forming an insulating layer in an embodiment of the present invention;
图10是本发明一实施例中环栅结构的结构示意图。FIG. 10 is a schematic structural diagram of a gate-all-around structure in an embodiment of the present invention.
附图标记说明：Explanation of reference signs:
201-衬底；201 - Substrate;
202-鳍片；2021-牺牲层；2022-纳米层；2023-伪栅极；2024-隔离层；202-fin; 2021-sacrifice layer; 2022-nanometer layer; 2023-dummy gate; 2024-isolation layer;
203-非晶硅层；203-amorphous silicon layer;
204-单晶硅层；204 - monocrystalline silicon layer;
205-硅锗体层；205-silicon germanium bulk layer;
206-非晶硅材料；206-amorphous silicon material;
207-绝缘层；207 - insulating layer;
208-绝缘材料；208 - insulating material;
209-源/漏区。209 - source/drain region.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and not necessarily Used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.
下面以具体地实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。The technical solution of the present invention will be described in detail below with specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.
请参考图2，本发明一实施例提供了一种环栅结构源漏的外延制备方法，包括：Please refer to FIG. 2 , an embodiment of the present invention provides an epitaxial preparation method for source and drain of a gate-around structure, including:
S101：提供一衬底，在所述衬底上形成多个鳍片，沿沟道方向，相邻的两个鳍片之间具有凹槽；S101: Provide a substrate, and form a plurality of fins on the substrate, along the channel direction, there is a groove between two adjacent fins;
其中的衬底可以为Si，也可以为SOI(英文全称为Silicon On Insulator，中文全称为绝缘衬底上的硅)，其中的鳍片可以包括交替堆叠的纳米层和牺牲层，其中的纳米层为Si，牺牲层为SiGe；The substrate therein can be Si or SOI (English full name is Silicon On Insulator, Chinese full name is silicon on insulating substrate), and the fins therein can include alternately stacked nano-layers and sacrificial layers, wherein the nano-layers is Si, and the sacrificial layer is SiGe;
一种举例中，步骤S101具体可以包括：In one example, step S101 may specifically include:
提供一衬底，在衬底上形成外延层，外延层包括交替层叠的沟道层与牺 牲层；A substrate is provided, and an epitaxial layer is formed on the substrate, and the epitaxial layer includes alternately stacked channel layers and sacrificial layers;
刻蚀外延层，形成多个鳍部；Etching the epitaxial layer to form a plurality of fins;
基于多个鳍部形成多个鳍片，可例如图3中结构A所示形貌，包括衬底201以及位于衬底上的鳍片202；Forming a plurality of fins based on a plurality of fins can be, for example, the shape shown in structure A in FIG. 3 , including a substrate 201 and a fin 202 located on the substrate;
再一种举例中，可以刻蚀外延层和衬底，形成多个鳍部；进而基于多个鳍部以及刻蚀后的衬底，形成多个鳍片；In another example, the epitaxial layer and the substrate can be etched to form a plurality of fins; then based on the plurality of fins and the etched substrate, a plurality of fins can be formed;
S102：在所述衬底上淀积非晶硅层；S102: Depositing an amorphous silicon layer on the substrate;
其中的非晶硅层具体可例如图3中结构B中的非晶硅层203；进一步地，位于鳍片202与衬底201的连接处(例如结构B中的虚线圈O和O'圈示)的非晶硅层的表面可以呈直角形，即图3中结构B所示，也可以为平滑的圆弧形，进一步可以理解为，覆盖于鳍片侧面的非晶硅层与覆盖于衬底表面的非晶硅层交界处，可以直接连接在一起，呈直角状，也可以采用光滑的曲面作为过渡面连接在一起。The amorphous silicon layer therein can specifically be, for example, the amorphous silicon layer 203 in structure B in FIG. ) The surface of the amorphous silicon layer can be in the shape of a right angle, that is, as shown in structure B in Figure 3, or it can be in the shape of a smooth arc. The junction of the amorphous silicon layers on the bottom surface can be directly connected together in a right-angle shape, or can be connected together by using a smooth curved surface as a transition surface.
进一步举例中，所述非晶硅层的厚度为2-3nm；In a further example, the thickness of the amorphous silicon layer is 2-3 nm;
S103：对所述非晶硅层进行退火，以使所述非晶硅层结晶形成单晶硅层；S103: Annealing the amorphous silicon layer to crystallize the amorphous silicon layer to form a single crystal silicon layer;
步骤S103中，得到单晶硅层的过程可以理解为，在退火过程中，鳍片中的纳米层以及衬底由于与非晶硅层接触，可以作为种子层，发生单晶硅的漏出，诱导步骤S102中淀积的非晶硅层再次结晶，转化为连续高质量的单晶硅层，得到图3中结构C的单晶硅层204；例如，步骤S103中，可以在N 2氛围下进行激光退火，进行快速融化后再重结晶； In step S103, the process of obtaining the single crystal silicon layer can be understood as, during the annealing process, the nano-layer in the fin and the substrate can be used as a seed layer due to contact with the amorphous silicon layer, and the leakage of single crystal silicon occurs, inducing The amorphous silicon layer deposited in step S102 is crystallized again and converted into a continuous high-quality single crystal silicon layer to obtain the single crystal silicon layer 204 of structure C in FIG. 3; for example, in step S103, it can be carried out under N atmosphere Laser annealing, rapid melting and then recrystallization;
S104：以所述单晶硅层的表面为起始表面，外延生长锗硅材料，形成锗硅体层；S104: Using the surface of the single crystal silicon layer as a starting surface, epitaxially grow silicon germanium material to form a silicon germanium bulk layer;
一种举例中，步骤S104具体可以理解为，以U形单晶硅层的表面为外延生长硅锗体层的起始表面，外延生长硅锗材料，形成硅锗体层，例如图3中结构D中的硅锗体层205；In one example, step S104 can specifically be understood as taking the surface of the U-shaped single crystal silicon layer as the starting surface for the epitaxial growth of the silicon-germanium bulk layer, and epitaxially growing the silicon-germanium material to form the bulk silicon-germanium layer, such as the structure in FIG. 3 The silicon germanium bulk layer 205 in D;
S105：在所述锗硅体层形成环栅结构的源/漏区；S105: Forming a source/drain region of a gate-around structure on the SiGe bulk layer;
一种举例中，步骤S105包括：In one example, step S105 includes:
对硅锗体层205进行掺杂，得到需要的掺杂类型；Doping the silicon germanium bulk layer 205 to obtain the required doping type;
在掺杂后的硅锗体层表面淀积层间电介质，形成环栅器件的源/漏区。An interlayer dielectric is deposited on the surface of the doped silicon germanium bulk layer to form a source/drain region of a gate-all-around device.
以上步骤S101至S105的制备方法可例如图13中所示，步骤S101中， 在衬底上形成多个鳍片，得到涂中的结构A；步骤S102中淀积非晶硅层后，得到图3中的结构B；步骤S103中对非晶硅层退火后，非晶硅层结晶形成单晶硅层，得到图3中的结构C；步骤S104中，以单晶硅层为起始表面，外延生长硅锗材料，形成硅锗体层，可等到图3中的结构D，进而基于结构D形成环栅结构的源/漏区.The preparation method of the above steps S101 to S105 can be, for example, as shown in FIG. 13. In step S101, a plurality of fins are formed on the substrate to obtain the coated structure A; after depositing an amorphous silicon layer in step S102, the figure Structure B in 3; after the amorphous silicon layer is annealed in step S103, the amorphous silicon layer crystallizes to form a single crystal silicon layer, and structure C in Figure 3 is obtained; in step S104, the single crystal silicon layer is used as the initial surface, The silicon germanium material is epitaxially grown to form a silicon germanium bulk layer, which can wait until the structure D in Figure 3, and then form the source/drain region of the ring gate structure based on the structure D.
以上实施方式中，通过在凹槽内淀积非晶硅层，然后将非晶硅层经过退火处理结晶成单晶硅层，以单晶硅层为起始表面生长锗硅体层的方法，相比于部分方案中，以多个孤立的表面为起始表面而产生大量的层错，本发明能够制备出无位错高质量的硅锗体层，为沟道提供足够的应力，提升环栅器件的空穴迁移率，进而提高环栅器件的开启电流。In the above embodiments, by depositing an amorphous silicon layer in the groove, and then crystallizing the amorphous silicon layer into a single crystal silicon layer through annealing treatment, the single crystal silicon layer is used as the method of growing a silicon germanium layer on the initial surface, Compared with some schemes, where a large number of stacking faults are generated by using multiple isolated surfaces as the starting surface, the present invention can prepare a high-quality silicon germanium bulk layer without dislocations, provide sufficient stress for the channel, and improve the ring The hole mobility of the gate device can be improved, thereby increasing the turn-on current of the gate-all-around device.
一种实施方式中，所述鳍片包括堆叠层与环绕于所述堆叠层上的伪栅极，所述堆叠层包括交替层叠的牺牲层以及纳米层；In one embodiment, the fin includes a stacked layer and a dummy gate surrounding the stacked layer, and the stacked layer includes alternately stacked sacrificial layers and nanolayers;
所述非晶硅层的高度匹配于所述堆叠层的高度；The height of the amorphous silicon layer matches the height of the stacked layers;
其中非晶硅层的高度匹配于堆叠层的高度，可以理解为，当堆叠层中最上面的一层为纳米层时，非晶硅层的高度与堆叠层的高度相等；当堆叠层中最上面的一层为牺牲层时，非晶硅层的高度可以与堆叠层的高度相等，也可以为与堆叠层中最上方的纳米层的高度相等；进而只要非晶硅层的高度可以满足：在外延生长硅锗材料时，不会以孤立的纳米层的侧面为起始表面生长硅锗材料，能够生长出无交叠层错的硅锗体层。Wherein the height of the amorphous silicon layer matches the height of the stacked layers, it can be understood that when the uppermost layer in the stacked layers is a nano-layer, the height of the amorphous silicon layer is equal to the height of the stacked layers; When the upper layer is a sacrificial layer, the height of the amorphous silicon layer can be equal to the height of the stacked layer, or can be equal to the height of the top nano-layer in the stacked layer; and then as long as the height of the amorphous silicon layer can satisfy: When the silicon germanium material is grown epitaxially, the silicon germanium material is not grown on the side surface of the isolated nanometer layer, and a silicon germanium bulk layer without overlapping stacking faults can be grown.
进而，步骤S101至步骤S104对应形成的结构可例如图4中所示，其中包括牺牲层2021、纳米层2022、伪栅极2023，多层牺牲层2021和多层纳米层2022交替堆叠形成堆叠层；Furthermore, the corresponding structure formed from step S101 to step S104 can be shown in FIG. 4, for example, which includes sacrificial layer 2021, nanometer layer 2022, dummy gate 2023, and multilayer sacrificial layer 2021 and multilayer nanolayer 2022 are stacked alternately to form a stacked layer ;
图4中的结构A至结构D与图3中的结构A至结构D一一对应，其制作方法与图3中的结构A至结构D相同，其区别在于，对非晶硅层以及单晶硅层的高度进行了进一步地限制，且对鳍片的具体结构进行了进一步的描述。Structures A to D in FIG. 4 correspond one-to-one to structures A to D in FIG. 3 , and the manufacturing method is the same as that of Structures A to D in FIG. 3 . The height of the silicon layer is further limited, and the specific structure of the fin is further described.
一种举例中，步骤S101包括：In one example, step S101 includes:
提供一衬底，在衬底上形成外延层，外延层包括交替层叠的沟道层与牺牲层；A substrate is provided, and an epitaxial layer is formed on the substrate, and the epitaxial layer includes alternately stacked channel layers and sacrificial layers;
刻蚀外延层，形成多个鳍部；Etching the epitaxial layer to form a plurality of fins;
在所述多个鳍部周部淀积伪栅极材料，得到图4中的伪栅极2023；Depositing a dummy gate material on the periphery of the plurality of fins to obtain the dummy gate 2023 in FIG. 4 ;
进一步举例中，基于图4中的结构A，可以将其中的牺牲层2021以及伪栅极2023向对应的鳍片的中轴线的方向刻蚀一部分，刻蚀出的空间可以用来淀积隔离层(可例如图10中的隔离层2024)，以将最终形成的栅极与源漏区隔离开；还可以其中的纳米层2022向偏离堆叠层的中轴线的方向外延生长一部分，然后在伪栅极2023以及牺牲层的侧壁淀积隔离层，可以根据需求选择适合的工艺，以使得最终制造的环栅器件达到更好的性能。As a further example, based on the structure A in FIG. 4, a part of the sacrificial layer 2021 and the dummy gate 2023 can be etched in the direction of the central axis of the corresponding fin, and the etched space can be used to deposit an isolation layer (For example, the isolation layer 2024 in FIG. 10) to isolate the finally formed gate from the source and drain regions; it is also possible to epitaxially grow a part of the nano-layer 2022 in the direction away from the central axis of the stacked layer, and then place a dummy gate An isolation layer is deposited on the sidewalls of the electrode 2023 and the sacrificial layer, and an appropriate process can be selected according to requirements, so that the gate-all-around device finally manufactured can achieve better performance.
一种举例中，步骤S105之后还可包括：In one example, after step S105, it may further include:
对鳍片中的纳米层形成应力。Stresses are created on the nanolayers in the fins.
在沟道区引入应力，可增大鳍片中空穴的迁移率，提升环栅器件的开启电流。Introducing stress in the channel region can increase the mobility of holes in the fin and increase the turn-on current of the gate-all-around device.
一种举例中，多个鳍片均为PMOS鳍片，进而可以在沟道区引入相同的压应力，增大PMOS鳍片中纳米层上的空穴的迁移率，提升环栅器件的开启电流；In one example, multiple fins are PMOS fins, and then the same compressive stress can be introduced in the channel region, increasing the mobility of holes on the nano-layer in the PMOS fins, and improving the turn-on current of the gate-all-around device ;
再一种举例中，多个鳍片包括PMOS鳍片和NMOS鳍片，进而可以分别在PMOS鳍片的沟道以及NMOS鳍片的沟道引入不同的应力，使得PMOS鳍片的电流匹配NMOS鳍片的电流；In another example, the multiple fins include PMOS fins and NMOS fins, and then different stresses can be introduced into the channels of the PMOS fins and the channels of the NMOS fins, so that the current of the PMOS fins matches that of the NMOS fins. slice current;
又一种举例中，多个鳍片包括PMOS鳍片和NMOS鳍片，进而可以只在NMOS鳍片的沟道区引入张应力，减小NMOS鳍片中纳米层上的空穴的迁移率，使得PMOS鳍片的电流与NMOS鳍片的电流匹配。In another example, the plurality of fins includes PMOS fins and NMOS fins, and then tensile stress can be introduced only in the channel region of the NMOS fins, reducing the mobility of holes on the nano-layer in the NMOS fins, Make the current of the PMOS fin match the current of the NMOS fin.
请参考图5和图6，一种实施方式中，步骤S102，包括：Please refer to FIG. 5 and FIG. 6, in an implementation manner, step S102 includes:
S1021：在所述衬底上淀积非晶硅材料；S1021: Depositing an amorphous silicon material on the substrate;
步骤S1021具体可以包括：在衬底上各向同性淀积非晶硅材料206，得到图6中的结构B1；Step S1021 may specifically include: isotropically depositing amorphous silicon material 206 on the substrate to obtain the structure B1 in FIG. 6 ;
进一步举例中，各向同性淀积可以例如低压化学气相淀积(Chemical Vapor Deposition，简称CVD)、等离子体增强化学气相淀积(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)等，可以根据具体的生产工艺以及实际需求选择适合的淀积方法；In a further example, isotropic deposition can be, for example, low-pressure chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD), etc., can be based on the specific production process And choose the appropriate deposition method according to actual needs;
S1022：在所述凹槽内淀积绝缘层；S1022: Deposit an insulating layer in the groove;
所述绝缘层207的高度匹配于所述堆叠层的高度；绝缘层可以例如SiO 2，得到图6中的结构B2； The height of the insulating layer 207 matches the height of the stacked layers; the insulating layer can be, for example, SiO 2 to obtain the structure B2 in FIG. 6 ;
S1023：基于所述绝缘层，刻蚀掉所述非晶硅材料中高于所述堆叠层的部分非晶硅材料；S1023: Based on the insulating layer, etch away a part of the amorphous silicon material higher than the stacked layer in the amorphous silicon material;
其中对于非晶硅材料206的刻蚀，具体为，刻蚀非晶硅材料2-3nm，此处的2-3nm为刻蚀的厚度，通过绝缘层207的隔离保护，将匹配于堆叠层高度的部分非晶硅材料保护起来，避免被刻蚀掉，进而刻蚀掉高于堆叠层的部分非晶硅材料，得到图6中的结构B3；The etching of the amorphous silicon material 206 is specifically to etch the amorphous silicon material 2-3nm, where the 2-3nm is the thickness of the etching, and the isolation protection of the insulating layer 207 will match the height of the stack layer Part of the amorphous silicon material is protected from being etched away, and then part of the amorphous silicon material higher than the stacked layer is etched away to obtain the structure B3 in Figure 6;
S1024：刻蚀掉所述绝缘层，得到所述非晶硅层；S1024: Etching away the insulating layer to obtain the amorphous silicon layer;
步骤S1024可以理解为，将图6中结构B3中的绝缘层207刻蚀干净，得到图6中的结构B4。Step S1024 can be understood as, etching away the insulating layer 207 in the structure B3 in FIG. 6 to obtain the structure B4 in FIG. 6 .
请参考图7，一种实施方式中，步骤S1022，包括：Please refer to FIG. 7, in an implementation manner, step S1022 includes:
S10221：采用可流动性化学气相淀积法，在所述凹槽内淀积所述绝缘层。S10221: Deposit the insulating layer in the groove by using a flowable chemical vapor deposition method.
其中可流动性化学气相淀积法(Flowable CVD，简称FCVD)可以直接在凹槽内淀积得到高度匹配于堆叠层高度的绝缘层；Among them, flowable chemical vapor deposition (Flowable CVD, referred to as FCVD) can be directly deposited in the groove to obtain an insulating layer whose height matches the height of the stacked layer;
请参考图8和图9，一种实施方式中，步骤S1022，包括：Please refer to FIG. 8 and FIG. 9, in one implementation manner, step S1022 includes:
S10222：在所述凹槽内淀积绝缘材料；S10222: Depositing an insulating material in the groove;
步骤S10222中的淀积，可以为各向同性淀积，得到图8中结构B21的绝缘材料208，例如低压化学气相淀积(Chemical Vapor Deposition，简称CVD)、等离子体增强化学气相淀积(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)等，可以根据具体的生产工艺以及实际需求选择适合的淀积方法；The deposition in step S10222 can be isotropic deposition to obtain the insulating material 208 of structure B21 in FIG. Enhanced Chemical Vapor Deposition, referred to as PECVD), etc., can choose a suitable deposition method according to the specific production process and actual needs;
也可以为各向异性垂直淀积高度匹配于堆叠层的绝缘材料；Anisotropic vertical deposition of insulating materials whose height matches the stacked layers is also possible;
S10223：对所述绝缘材料进行抛光处理；S10223: Polishing the insulating material;
其中的抛光可以为化学机械抛光(Chemical Mechanical Polishing，简称CMP)，进而得到图9中结构B22中抛光后的绝缘材料208；The polishing can be chemical mechanical polishing (CMP for short), so as to obtain the polished insulating material 208 in the structure B22 in FIG. 9;
S10224：刻蚀掉所述绝缘材料中高于所述堆叠层的部分绝缘材料，得到所述绝缘层；S10224: Etching away a part of the insulating material higher than the stacked layer in the insulating material to obtain the insulating layer;
即图9中，将结构B22的绝缘材料208中的部分绝缘材料刻蚀掉，得到结构B23中的绝缘层207。That is, in FIG. 9 , part of the insulating material in the insulating material 208 of the structure B22 is etched away to obtain the insulating layer 207 in the structure B23 .
以上实施方式中的步骤S10222至S10224与前文中的步骤S10221为两种不同的淀积绝缘层的方法，步骤S10221可以直接淀积得到所需形貌的绝缘 层，而步骤S10222至S10224需要在淀积后经过抛光和刻蚀，才可以得到绝缘层，可以根据工艺以及实际需求选择合适的方法淀积绝缘层。Steps S10222 to S10224 in the above embodiment and the above step S10221 are two different methods of depositing the insulating layer. The insulating layer can only be obtained after polishing and etching after deposition, and an appropriate method can be selected to deposit the insulating layer according to the process and actual needs.
请参考图10，本发明一实施例还提供了一种环栅结构，包括：衬底201、多个鳍片202、单晶硅层204和源/漏区209，Please refer to FIG. 10 , an embodiment of the present invention also provides a gate-around structure, including: a substrate 201, a plurality of fins 202, a single crystal silicon layer 204 and a source/drain region 209,
所述多个鳍片202位于所述衬底201之上，沿沟道方向，所述多个鳍片202之间具有凹槽，所述单晶硅层204覆盖于所述凹槽的侧壁与底面，所述源/漏区209设于所述凹槽内，所述源/漏区209位于单晶硅层204之上。The plurality of fins 202 are located on the substrate 201, along the channel direction, there are grooves between the plurality of fins 202, and the single crystal silicon layer 204 covers the sidewalls of the grooves On the bottom surface, the source/drain region 209 is disposed in the groove, and the source/drain region 209 is located on the single crystal silicon layer 204 .
一种实施方式中，所述鳍片202包括堆叠层与环绕于所述堆叠层上的伪栅极2023，所述堆叠层包括交替层叠的牺牲层2021以及纳米层2022；In one embodiment, the fin 202 includes a stacked layer and a dummy gate 2023 surrounding the stacked layer, and the stacked layer includes alternately stacked sacrificial layers 2021 and nanometer layers 2022;
所述单晶硅层2024的高度匹配于所述堆叠层的高度。The height of the single crystal silicon layer 2024 matches the height of the stacked layers.
一种实施方式中，所述伪栅极2023与所述牺牲层2021的侧壁覆盖有隔离层2024。In one embodiment, the sidewalls of the dummy gate 2023 and the sacrificial layer 2021 are covered with an isolation layer 2024 .
一种实施方式中，所述单晶硅层2024的厚度为2-3nm。In one implementation manner, the thickness of the single crystal silicon layer 2024 is 2-3 nm.
一种实施方式中，所述源/漏区209是利用前文所述的环栅结构源漏的外延制备方法制备的。In one implementation manner, the source/drain region 209 is prepared by using the epitaxial preparation method for the source and drain of the gate-around structure described above.
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (12)

  1. 一种环栅结构源漏的外延制备方法，其特征在于，包括：An epitaxial preparation method for source and drain of a gate-around structure, characterized in that it comprises:
    提供一衬底，在所述衬底上形成多个鳍片，沿沟道方向，相邻的两个鳍片之间具有凹槽；A substrate is provided, and a plurality of fins are formed on the substrate, and grooves are formed between two adjacent fins along the channel direction;
    在所述衬底上淀积非晶硅层；depositing an amorphous silicon layer on the substrate;
    对所述非晶硅层进行退火，以使所述非晶硅层结晶形成单晶硅层；annealing the amorphous silicon layer to crystallize the amorphous silicon layer to form a single crystal silicon layer;
    以所述单晶硅层的表面为起始表面，外延生长锗硅材料，形成锗硅体层；Using the surface of the single crystal silicon layer as a starting surface, epitaxially grow a silicon germanium material to form a silicon germanium bulk layer;
    在所述锗硅体层形成环栅结构的源/漏区。A source/drain region of a ring gate structure is formed on the germanium silicon bulk layer.
  2. 根据权利要求1所述的环栅结构源漏的外延制备方法，其特征在于，所述鳍片包括堆叠层与环绕于所述堆叠层上的伪栅极，所述堆叠层包括交替层叠的牺牲层以及纳米层；The epitaxial preparation method for source and drain of a gate-all-round structure according to claim 1, wherein the fins include stacked layers and dummy gates surrounding the stacked layers, and the stacked layers include alternately stacked sacrificial gates. layers and nanolayers;
    所述非晶硅层的高度匹配于所述堆叠层的高度。The height of the amorphous silicon layer matches the height of the stacked layers.
  3. 根据权利要求2所述的环栅结构源漏的外延制备方法，其特征在于，在所述衬底上淀积非晶硅层，包括：The epitaxial preparation method for the source and drain of the ring gate structure according to claim 2, characterized in that depositing an amorphous silicon layer on the substrate comprises:
    在所述衬底上淀积非晶硅材料；depositing an amorphous silicon material on the substrate;
    在所述凹槽内淀积绝缘层，所述绝缘层的高度匹配于所述堆叠层的高度；depositing an insulating layer in the groove, the height of the insulating layer matching the height of the stacked layers;
    基于所述绝缘层，刻蚀掉所述非晶硅材料中高于所述堆叠层的部分非晶硅材料；Based on the insulating layer, etching away part of the amorphous silicon material higher than the stacked layer in the amorphous silicon material;
    刻蚀掉所述绝缘层，得到所述非晶硅层。The insulating layer is etched away to obtain the amorphous silicon layer.
  4. 根据权利要求3所述的环栅结构源漏的外延制备方法，其特征在于，在所述凹槽内淀积绝缘层，包括：The epitaxial preparation method for the source and drain of the ring gate structure according to claim 3, wherein depositing an insulating layer in the groove comprises:
    采用可流动性化学气相淀积法，在所述凹槽内淀积所述绝缘层。The insulating layer is deposited in the groove by a flowable chemical vapor deposition method.
  5. 根据权利要求3所述的环栅结构源漏的外延制备方法，其特征在于，在所述凹槽内淀积绝缘层，包括：The epitaxial preparation method for the source and drain of the ring gate structure according to claim 3, wherein depositing an insulating layer in the groove comprises:
    在所述凹槽内淀积绝缘材料；depositing an insulating material within the groove;
    对所述绝缘材料进行抛光处理；polishing the insulating material;
    刻蚀掉所述绝缘材料中高于所述堆叠层的部分绝缘材料，得到所述绝缘层。Etching away a part of the insulating material higher than the stacked layer in the insulating material to obtain the insulating layer.
  6. 根据权利要求1所述的环栅结构源漏的外延制备方法，其特征在于，所述非晶硅层的厚度为2-3nm。The epitaxial preparation method for source and drain of a ring-gate structure according to claim 1, characterized in that the thickness of the amorphous silicon layer is 2-3 nm.
  7. 根据权利要求1所述的环栅结构源漏的外延制备方法，其特征在于，所述非晶硅材料采用低压化学气相淀积法或等离子增强化学气相淀积法进行淀积。The epitaxial preparation method for source and drain of a gate-around structure according to claim 1, wherein the amorphous silicon material is deposited by a low-pressure chemical vapor deposition method or a plasma-enhanced chemical vapor deposition method.
  8. 一种环栅结构，其特征在于，包括：衬底、多个鳍片、单晶硅层和源/漏区，A ring gate structure, characterized in that it includes: a substrate, a plurality of fins, a single crystal silicon layer and a source/drain region,
    所述多个鳍片位于所述衬底之上，沿沟道方向，所述多个鳍片之间具有凹槽，所述单晶硅层覆盖于所述凹槽的侧壁与底面，所述源/漏区设于所述凹槽内，所述源/漏区位于单晶硅层之上。The plurality of fins are located on the substrate, along the channel direction, there are grooves between the plurality of fins, and the single crystal silicon layer covers the sidewalls and bottom surfaces of the grooves, so The source/drain region is set in the groove, and the source/drain region is located on the single crystal silicon layer.
  9. 根据权利要求8所述的环栅结构，其特征在于，所述鳍片包括堆叠层与环绕于所述堆叠层上的伪栅极，所述堆叠层包括交替层叠的牺牲层以及纳米层；The gate-all-around structure according to claim 8, wherein the fins comprise stacked layers and dummy gates surrounding the stacked layers, and the stacked layers comprise alternately stacked sacrificial layers and nanolayers;
    所述单晶硅层的高度匹配于所述堆叠层的高度。The height of the single crystal silicon layer matches the height of the stacked layers.
  10. 根据权利要求9所述的环栅结构，其特征在于，所述伪栅极与所述牺牲层的侧壁覆盖有隔离层。The gate-all-around structure according to claim 9, wherein the sidewalls of the dummy gate and the sacrificial layer are covered with an isolation layer.
  11. 根据权利要求8所述的环栅结构，其特征在于，所述单晶硅层的厚度为2-3nm。The gate-all-around structure according to claim 8, wherein the thickness of the single crystal silicon layer is 2-3 nm.
  12. 根据权利要求8所述的环栅结构，其特征在于，所述源/漏区是利用权利要求1至7任一项所述的环栅结构源漏的外延制备方法制备的。The gate-all-around structure according to claim 8, wherein the source/drain region is prepared by using the epitaxial preparation method for source and drain of the gate-all-around structure according to any one of claims 1 to 7.
PCT/CN2021/118020 2021-09-13 2021-09-13 Preparation method for epitaxy of source/drain of gate all around structure, and gate all around structure WO2023035270A1 (en)

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