CN111799331A - Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment - Google Patents
Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 54
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 166
- 239000000758 substrate Substances 0.000 claims description 133
- 229910052732 germanium Inorganic materials 0.000 claims description 123
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 123
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 49
- 229910052710 silicon Inorganic materials 0.000 claims description 49
- 239000010703 silicon Substances 0.000 claims description 49
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 claims description 45
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 29
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 11
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, an integrated circuit and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device has the advantages of simple technology, small manufacturing difficulty and low production cost, and can prevent the lateral corrosion of the source drain layer when the nanowire is released. The semiconductor device includes: a gate-all-around transistor; the ring gate transistor comprises a channel layer and a source drain structure connected with the channel layer; the source-drain structure comprises a source-drain layer and a liner layer, and the liner layer is formed between the source-drain layer and the channel layer; the material of the liner layer is the same as that of the channel layer; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the channel layer is smaller than the first threshold.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof, an integrated circuit and electronic equipment.
Background
The stacked nanowire or sheet ring gate device is a novel semiconductor transistor, has good gate control capability, can increase working current and reduce short channel effect, and therefore has wide application prospect.
The release of the stacked nanowire/sheet is one of the key technologies for realizing the integration of the gate-all-around device, and currently, an inner side wall technology is generally adopted to prevent the lateral corrosion of the nanowire to the source drain layer when the nanowire is released. However, the inner side wall has complex technical process and high manufacturing difficulty, and the production cost of the gate-all-around device is increased.
Disclosure of Invention
The invention aims to provide a semiconductor device, a manufacturing method thereof, an integrated circuit and electronic equipment, and provides the semiconductor device which is simple in technology, small in manufacturing difficulty and low in production cost and can prevent lateral corrosion of a source drain layer when a nanowire is released.
In order to achieve the above object, the present invention provides a semiconductor device.
The semiconductor device includes:
a gate-all-around transistor;
the ring gate transistor comprises a channel layer and a source drain structure connected with the channel layer;
the source-drain structure comprises a source-drain layer and a liner layer, and the liner layer is formed between the source-drain layer and the channel layer;
the material of the liner layer is the same as that of the channel layer; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the channel layer is smaller than the first threshold.
Optionally, the semiconductor device further comprises a substrate, the substrate comprising a base and a fin formed on the base;
the liner layer is formed in the first region of the fin portion; the channel layer is formed in the second area of the fin part; the source-drain layer is formed on one side, away from the channel layer, of the liner layer on the first region;
the second area is flush with the first area, or the second area protrudes from the first area.
Optionally, the substrate includes a first substrate on which the channel layer is formed;
or the substrate comprises a first substrate and a second substrate formed on the first substrate, and the second substrate is a germanium-silicon substrate; the channel layer is formed on the second substrate.
Optionally, the thickness of the germanium-silicon substrate is 300nm-3 um;
and/or the mass percentage of germanium in the germanium-silicon substrate is 30-75%.
Optionally, the target element is silicon, and the first threshold is 13% -15%;
the channel layer is a silicon channel layer, and the liner layer is a silicon liner layer;
or, the channel layer is a silicon channel layer, and the silicon liner layer is a germanium-silicon liner layer.
Optionally, the target element is germanium, and the first threshold is 13% -15%;
the channel layer is a germanium channel layer, and the liner layer is a germanium liner layer;
or, the channel layer is a germanium channel layer, and the liner layer is a germanium-silicon liner layer.
Optionally, the target element is germanium, and the first threshold is 13% -15%;
the channel layer is a germanium-silicon channel layer, and the backing layer is a germanium-silicon backing layer.
Optionally, the channel layer is a plurality of layers, and the height of each channel layer is greater than or equal to 5nm and less than or equal to 30 nm.
Optionally, the spacer layer has a thickness of 3nm to 15 nm.
Optionally, the liner layer contains dopant ions;
the concentration of the doped ions is 5X 1018 cm-3-1X 1021 cm-3.
Optionally, the source drain layer comprises a plurality of germanium-silicon source drain layers which are stacked; the mass percent of germanium in the multilayer germanium-silicon source drain layer is 35-75%; or the like, or, alternatively,
the source drain layer comprises a plurality of germanium tin source drain layers which are arranged in a stacked mode; the mass percentage of tin in the multilayer germanium-tin source drain layer is 2-15%.
Optionally, the manufacturing method of the semiconductor device includes: forming a gate-all-around transistor;
forming a gate all around transistor includes:
forming a channel layer and a sacrificial layer;
forming a source drain structure connected with the channel layer and the sacrificial layer;
removing the sacrificial layer to obtain a gate-all-around transistor;
the source-drain structure comprises a source-drain layer and a liner layer, and the liner layer is formed between the source-drain layer and the channel layer; the material of the liner layer is the same as that of the channel layer; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the material of the channel layer is smaller than the first threshold.
Optionally, the manufacturing method further includes, before forming the gate-all-around transistor:
forming a substrate; wherein the substrate comprises a first substrate;
forming the channel layer and the sacrificial layer includes:
forming a channel layer and a sacrificial layer on a first substrate; the first substrate comprises a first base part and a first fin part formed on the first base part, and the channel layer and the sacrificial layer are formed on the first fin part;
or, the manufacturing method further comprises the following steps before the gate-all-around transistor is formed:
forming a substrate; wherein the substrate comprises a first substrate and a second substrate formed on the first substrate;
forming the channel layer and the sacrificial layer includes:
forming a channel layer and a sacrificial layer on a second substrate; the second substrate comprises a second base part and a second fin part formed on the second base part, and the channel layer and the sacrificial layer are formed on the second fin part.
Optionally, the first fin portion or the second fin portion has a first region and a second region, and the second region is flush with the first region, or the second region protrudes from the first region; the channel layer and the sacrificial layer are formed on the second area;
the forming of the source drain structure connected with the channel layer and the sacrificial layer comprises the following steps:
forming a pad layer connected to the channel layer and the sacrificial layer on the first region;
and forming a source drain layer on one side of the liner layer, which is far away from the channel layer and the sacrificial layer, on the first region.
Optionally, the target element is silicon, and the first threshold is 13% -15%;
forming the channel layer and the sacrificial layer includes:
forming a silicon channel layer and a germanium-silicon sacrificial layer;
forming a pad layer connected to the channel layer and the sacrificial layer on the first region includes:
forming a silicon liner layer connected with the silicon channel layer and the germanium-silicon sacrificial layer on the first region;
or, on the first region, forming a pad layer connected to the channel layer and the sacrificial layer includes:
forming a silicon-germanium pad layer connected with the silicon channel layer and the silicon-germanium sacrificial layer on the first region; wherein, the difference between the mass percent of the germanium element of the germanium-silicon sacrificial layer and the mass percent of the germanium element in the germanium-silicon liner layer is more than 20-23%.
Optionally, the target element is germanium, and the first threshold is 13% -15%;
forming the channel layer and the sacrificial layer includes:
forming a germanium channel layer and a germanium-silicon sacrificial layer;
forming a pad layer connected to the channel layer and the sacrificial layer on the first region includes:
forming a germanium pad layer connected with the germanium channel layer and the germanium-silicon sacrificial layer on the first region;
or, on the first region, forming a pad layer connected to the channel layer and the sacrificial layer includes:
forming a germanium-silicon liner layer connected with the germanium channel layer and the germanium-silicon sacrificial layer on the first region; wherein, the difference between the mass percent of the germanium in the germanium-silicon pad layer and the mass percent of the germanium in the germanium-silicon sacrificial layer is more than 20-23%.
Optionally, the target element is germanium, and the first threshold is 13% -15%;
forming the channel layer and the sacrificial layer includes:
forming a germanium-silicon channel layer and a germanium-silicon sacrificial layer;
forming a pad layer connected to the channel layer and the sacrificial layer on the first region includes:
forming a germanium-silicon liner layer connected with the germanium-silicon channel layer and the germanium-silicon sacrificial layer on the first region; the absolute value of the difference between the mass percent of the germanium element in the germanium-silicon lining layer and the mass percent of the germanium element in the germanium-silicon sacrificial layer is greater than 20% -23%, and the absolute value of the difference between the mass percent of the germanium element in the germanium-silicon channel layer and the mass percent of the germanium element in the germanium-silicon sacrificial layer is greater than 20% -23%.
Optionally, the channel layer is a silicon channel layer;
forming a source drain layer on the first region on a side of the pad layer facing away from the channel layer and the sacrificial layer includes:
on the first region, sequentially forming a plurality of germanium-silicon source drain layers on one side of the backing layer, which is far away from the silicon channel layer and the sacrificial layer, wherein the plurality of germanium-silicon source drain layers are stacked; wherein the mass percent of germanium elements in the multilayer germanium-silicon source and drain layers is 35-75%;
or, the channel layer is a germanium-silicon channel layer;
forming a source drain layer on the first region on a side of the pad layer facing away from the channel layer and the sacrificial layer includes:
on the first region, sequentially forming a multilayer germanium-silicon source drain layer or a multilayer germanium-tin source drain layer on one side of the backing layer, which is far away from the germanium-silicon channel layer and the sacrificial layer, wherein the multilayer germanium-silicon source drain or the multilayer germanium-tin source drain are stacked; wherein the mass percent of germanium element in the multilayer germanium-silicon source drain layer is 35-75%, and the mass percent of tin element in the multilayer germanium-tin source drain layer is 2-15%;
or, the channel layer is a germanium channel layer;
forming a source drain layer on the first region on a side of the pad layer facing away from the channel layer and the sacrificial layer includes:
and on the first region, sequentially forming a multilayer germanium-tin source drain layer on one side of the liner layer, which is far away from the germanium channel layer and the sacrificial layer, wherein the mass percentage of tin elements in the multilayer germanium-tin source drain layer is 2-15%.
The invention also provides an integrated circuit comprising the semiconductor device provided by the technical scheme.
The invention also provides electronic equipment comprising the semiconductor device or the integrated circuit in the technical scheme.
Compared with the prior art, in the semiconductor device provided by the embodiment of the invention, the liner layer is formed between the channel layer and the source drain layer, and the material of the liner layer is the same as that of the channel layer; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the channel layer is smaller than the first threshold. At this time, the selection ratio of the pad layer is close to that of the channel layer. When releasing the nanowire, a sacrificial layer is generally provided with a large selection ratio to a channel layer. In the embodiment of the invention, the selection ratio of the liner layer is similar to that of the channel layer, so that the sacrificial layer has higher selection ratio to the liner layer when the sacrificial layer is etched. Because the liner layer is arranged between the source drain layer and the channel layer, the source drain layer is not corroded when the sacrificial layer is etched. Therefore, when the nanowire is released, the source drain layer is not corroded, and the formed liner layer is simple in technology, low in manufacturing difficulty and low in production cost.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is another schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a substrate according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure after forming a layer of sacrificial material and a layer of channel material on a substrate according to an embodiment of the invention;
FIG. 5 is a schematic diagram illustrating a fin formed after processing the structure of FIG. 4 according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram after a pad layer and a source/drain layer are formed in an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a semiconductor device after a sacrificial layer is removed in the process of manufacturing the semiconductor device according to the embodiment of the invention.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
The technical problems that the technical process of the inner side wall is complex, the manufacturing difficulty is high, and the production cost of a gate-all-around device is increased due to the inner side wall technology in the prior art are solved. An embodiment of the invention discloses a semiconductor device, and referring to fig. 1 or fig. 2, wherein fig. 1 shows a schematic structural diagram of a semiconductor device, and fig. 2 also shows a schematic structural diagram of a semiconductor device, and the number of layers of a channel layer of a gate-all-around transistor included in the semiconductor device is shown to be three.
Referring to fig. 1 or 2, the semiconductor device includes: and a gate all around transistor. The gate-all-around transistor includes a channel layer 10 and a source-drain structure 20 connected to the channel layer 10. The source-drain structure 20 includes a source-drain layer 201 and a pad layer 202, and the pad layer 202 is formed between the source-drain layer 201 and the channel layer 10. The liner layer 202 is made of the same material as the channel layer 10; alternatively, the absolute value of the difference between the mass percentage of the target element contained in the material 202 of the pad layer and the mass percentage of the target element contained in the channel layer 10 is smaller than the first threshold. In this semiconductor device, a pad layer 202 is formed between the channel layer 10 and the source-drain layer 201. When releasing the nanowire, the sacrificial layer is generally provided to have a large selection ratio to the channel layer 10. In the embodiment of the present invention, the selection ratio of the pad layer 202 is similar to that of the channel layer 10, which can also ensure that the sacrificial layer has a higher selection ratio to the pad layer 202 when etching the sacrificial layer. Since the liner layer 202 is provided between the source-drain layer 201 and the channel layer 10, the source-drain layer 201 is not corroded when the sacrificial layer is etched. Therefore, when the nanowire is released, the source drain layer is not corroded, and the formed liner layer is simple in technology, low in manufacturing difficulty and low in production cost.
In one possible implementation, the semiconductor device further includes a substrate. The substrate includes a base and a fin formed on the base. The liner layer is formed in the first region of the fin portion; the channel layer is formed in the second region of the fin portion. The source and drain layers are formed on the first region on the side of the liner layer away from the channel layer. When the source and drain are etched back, only the fin portion can be etched, and a part of the fin portion can also be etched. For example, when etching back the source and drain, the second region is flush with the first region when only the fin is etched. For another example, when a portion of the fin is etched back during source-drain etching, the second region protrudes from the first region.
As an example, when the channel layer is a silicon channel layer, the substrate includes at least a first substrate. The first substrate may be a Silicon substrate or an SOI (Silicon-On-Insulator) substrate. At this time, because the first substrate and the silicon channel layer are made of the same or similar materials, the first substrate can avoid excessive corrosion of the etching solution when the sacrificial layer is etched. Specifically, the first substrate has a base portion and a fin portion formed on the base portion.
For example, referring to fig. 1, a schematic structural diagram of a semiconductor device in which only a fin portion is etched and a second region and a first region are flush when source and drain are etched back is shown. The substrate shown in fig. 1 includes a first substrate 501, and a second substrate 502 including a base 5021 and a fin 5022. The fin 5022 includes a first region 50221 and a second region 50222. A source/drain layer is formed in the first region 50221, and a channel layer is formed in the second region 50222. It can be seen that the second region 50222 is flush with the first region 50221.
For another example, referring to fig. 2, a schematic structural diagram of a semiconductor device in which a portion of a fin is etched away and the second region 50222 protrudes from the first region 50221 when source and drain etching is performed is shown. The substrate shown in fig. 2 includes a first substrate 501, and a second substrate 502 formed on the first substrate 501, the second substrate including a base 5021 and a fin 5022. The fin 5022 includes a first region 50221 and a second region 50222. A channel layer is formed in the second region 50222, and a source-drain layer is formed in the first region 50221. It can be seen that the second region 50222 protrudes from the first region 50221.
Referring to fig. 1 or 2, as another example, when the channel layer 10 is a germanium-silicon channel layer or a germanium channel layer, the substrate may include a first substrate 501 and a second substrate 502. A second substrate 502 is formed on the first substrate 501, and the second substrate 502 includes a base 5021 and a fin 5022 formed on the base 5021. At this time, in order to avoid lattice defects of the germanium-silicon channel layer or the germanium channel layer, the second substrate 502 may be provided as a germanium-silicon substrate. According to the lattice requirement of the germanium-silicon channel layer or the germanium channel layer, the mass percentage of germanium in the germanium-silicon substrate is 30% -75%. When the semiconductor device forms a fin-shaped structure, the back-etching depth of a source-drain region needs to be larger than that of a gate-all-around structure, namely, the second substrate 502 needs to be etched, at the moment, the second substrate 502 needs to be set to have a certain thickness, and in order to meet the requirements, the thickness of the second substrate 502 can be set to be 300nm-3 um. The thickness of the first substrate 501 may be set according to actual requirements, which is not limited in the embodiment of the present invention.
Referring to fig. 1 or fig. 2, in one possible implementation, the source-drain layer 201 of the gate-all-around transistor is made of the same material as the channel layer 10. At this time, when the sacrificial layer is etched, the sacrificial layer has a sufficient selection ratio with respect to the source-drain layer 201. Therefore, in this case, the liner layer 202 between the source-drain layer 201 and the channel layer 10 may not be provided.
Referring to fig. 1 or fig. 2, as an example, the source/drain layer 201 is a stacked structure, and the number of layers of the stacked structure may be determined according to specific requirements, for example: the source and drain layers 201 are three-layer stacked structures. For another example, the source/drain layer 201 has a five-layer stacked structure.
As a specific example, the source drain layer includes a plurality of germanium-silicon source drain layers, and the plurality of germanium-silicon source drain layers are stacked; the mass percentage of germanium in the multilayer germanium-silicon source and drain layers is 35-75%. At this time, the germanium contents in the multilayer germanium-silicon source drain layers are different, and the germanium contents can be set in a mode that the mass percentage of germanium is gradually increased from bottom to top. For example, the source drain layer includes three germanium-silicon source drain layers, and the three germanium-silicon source drain layers are a first germanium-silicon source drain layer, a second germanium-silicon source drain layer and a third germanium-silicon source drain layer from bottom to top. The mass percentage of the germanium of the first germanium-silicon source and drain layer is 38%, the mass percentage of the germanium of the second germanium-silicon source and drain layer is 53%, and the mass percentage of the germanium of the third germanium-silicon source and drain layer is 67%. It can be understood that, in the embodiment of the present invention, the specific germanium mass percentage of each germanium-silicon source drain layer in the multilayer germanium-silicon source drain layer is not specifically limited, as long as the above set requirements are met.
As another specific example, the source and drain layers include a plurality of germanium-tin source and drain layers, and the plurality of germanium-tin source and drain layers are stacked; the mass percentage of tin in the multilayer germanium-tin source drain layer is 2-15%. At this time, the tin content in the multilayer germanium-tin source drain layer is different, and the tin content can be set in a mode that the tin content is gradually increased from bottom to top. For example, the source drain layer includes three germanium tin source drain layers, and the three germanium tin source drain layers are a first germanium tin source drain layer, a second germanium tin source drain layer and a third germanium tin source drain layer from bottom to top. The mass percentage of the germanium of the first germanium tin source drain layer is 3%, the mass percentage of the germanium of the second germanium tin source drain layer is 7%, and the mass percentage of the germanium of the third germanium tin source drain layer is 12%. It can be understood that, in the embodiment of the present invention, the mass percentage of the specific tin in each germanium-tin source drain layer in the multilayer germanium-tin source drain layer is not specifically limited, as long as the above set requirements are met.
Referring to fig. 1 or fig. 2, in another possible implementation manner, when the source-drain layer 201 and the channel layer 10 are made of different materials, and when the sacrificial layer is etched, etching liquid may corrode the source-drain layer 201, at this time, since the liner layer 202 is located between the channel layer 10 and the source-drain layer 201, when the sacrificial layer is etched, the liner layer 202 serves as an isolation layer between the source-drain layer 201 and the channel layer 10, and the etching liquid may not corrode the source-drain layer 201.
Referring to fig. 1 or 2, in practical applications, the channel layer 10 may be a germanium channel layer, a germanium-silicon channel layer, or a silicon channel layer; the liner layer 202 is made of the same material as the channel layer 10; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the channel layer is smaller than the first threshold. At this time, the pad layer 202 may be provided as a silicon germanium pad layer, a germanium pad layer, or a silicon substrate.
Referring to fig. 1 or 2, for example, when the target element is silicon and the first threshold is 13% to 15%, the channel layer is a silicon channel layer and the pad layer is a silicon pad layer. Or the channel layer is a silicon channel layer, and the liner layer is a germanium-silicon liner layer. In this case, the sacrificial layer is a silicon germanium sacrificial layer.
Referring to fig. 1 or 2, when the pad layer 202 is a silicon pad layer, the pad layer 202 and the channel layer 10 are made of the same material, so that the sacrificial layer has a sufficient selectivity with respect to the pad layer 202 when the sacrificial layer is etched. For example, when the pad layer 202 is a sige pad layer, the mass percentage of ge in the sige pad layer may be set to be 20% less than that in the sige sacrificial layer, so as to ensure that the sige pad layer and the sige pad layer have a sufficient selectivity.
Referring to fig. 1 or 2, when the channel layer 10 is a silicon channel layer, the source drain layer 201 may be a silicon germanium source drain layer 201. At this time, the germanium content in the germanium-silicon source drain layer can be determined according to the specific stress requirement or the number of layers of the germanium-silicon source drain layer. For example: the mass percentage of germanium in the germanium-silicon source drain layer can be set to be 35% -75%. When the germanium-silicon source and drain layers are prepared, source and drain epitaxy can be carried out by adopting a plurality of layers of germanium-silicon materials with 35-75% of germanium by mass, and the number of layers of the gradual change structure can be three or five.
Referring to fig. 1 or fig. 2, for another example, when the target element is germanium and the first threshold is 13% to 15%, the channel layer is a germanium channel layer and the liner layer is a germanium liner layer; or, the channel layer is a germanium channel layer, and the liner layer is a germanium-silicon liner layer. In this case, the sacrificial layer is a silicon germanium sacrificial layer.
When the pad layer 202 is a germanium pad layer, the pad layer 202 and the channel layer 10 are made of the same material, so that the sacrificial layer has a sufficient selectivity with respect to the pad layer 202 when etching the sacrificial layer.
When the channel layer is a germanium channel layer and the spacer layer 202 is a silicon germanium spacer layer, the mass percent of germanium in the silicon germanium sacrificial layer is typically set to less than 70% in the semiconductor device. At this time, in order to satisfy the sufficient selection ratio of the sacrificial layer with respect to the pad layer 202 when releasing the nanowire, the mass percentage of germanium in the sige pad layer may be set to be greater than 90%.
Referring to fig. 1 or 2, when the channel layer 10 is a germanium channel layer, the source and drain layers 201 may be germanium tin source and drain layers. At this time, the germanium content in the germanium tin source drain layer can be determined according to the specific stress requirement or the number of layers of the germanium tin source drain layer. For example: the mass percentage of tin in the germanium-tin source drain layer can be set to be 2-15%. When the germanium-tin source drain layer is prepared, source drain epitaxy can be performed by adopting a plurality of layers of germanium-tin materials, wherein the percentage of tin in the germanium-tin materials is 2% -15%. The number of layers of the graded structure can be three or five.
Referring to fig. 1 or 2, for another example, the target element is germanium, and the first threshold is 13% -15%; the channel layer is a germanium-silicon channel layer, and the backing layer is a germanium-silicon backing layer. In this case, the sacrificial layer is a silicon germanium sacrificial layer.
Where the liner layer 202 is a silicon germanium liner layer, the mass percent of germanium in the silicon germanium liner layer may be the same as the mass percent of the silicon germanium channel layer. At this time, the sacrificial layer has a sufficient selectivity with respect to the pad layer 202 when the sacrificial layer is etched. It is understood that in the case where the liner layer 202 is a silicon germanium liner layer, the mass percentage of germanium in the silicon germanium liner layer may also be set to be different from the mass percentage of germanium in the silicon germanium channel layer. For example, in this case, the difference between the mass percentage of germanium in the sige foundation layer and the mass percentage of germanium in the sige channel layer may be less than 15%, and the difference between the mass percentage of germanium in the sige foundation layer and the mass percentage of germanium in the sige sacrificial layer may be greater than 23%, and usually, the difference between the mass percentage of germanium in the sige channel layer and the mass percentage of germanium in the sige sacrificial layer is greater than 30% or more.
Referring to fig. 1 or 2, when the channel layer 10 is a silicon germanium channel layer, the source drain layer 201 may be a silicon germanium source drain layer. At this time, the germanium content in the germanium-silicon source drain layer is determined according to the specific stress requirement or the number of layers of the germanium-silicon source drain layer. For example, the germanium mass percentage in the germanium-silicon source and drain layers is 35% -75%. When the germanium-silicon source and drain layers are prepared, source and drain epitaxy is carried out by adopting a plurality of germanium-silicon materials with 35-75% of germanium in mass percent, the number of layers of the gradual change structure can be three or five, and certainly, the gradual change structure can also be set into other numerical value layers according to requirements.
Referring to fig. 1 or 2, when the channel layer 10 is a silicon germanium channel layer, the source/drain layer 201 may also be a tin germanium source/drain layer. At this time, the mass percentage of germanium in the germanium tin source drain layer is determined according to the specific stress requirement or the number of layers of the germanium tin source drain layer. For example: the mass percentage of tin in the germanium-tin source drain layer can be set to be 2% -15%. When the germanium-tin source drain layer is prepared, a plurality of layers of germanium-tin materials with tin mass percent of 2% -15% can be adopted for source drain epitaxy, and the number of layers of the gradual change structure can be three or five.
Referring to fig. 1 or 2, the height of each channel layer 10 may be set to be greater than 5nm and less than or equal to 30nm according to the performance requirements of the semiconductor device. It can be understood that the liner layer 202 is used to block corrosion of the source/drain layer 201 by the etching solution when the sacrificial layer is etched, so that the liner layer 202 needs a certain thickness, but the liner layer 202 is too thick and may have a certain performance influence on the device, so that the thickness range of the liner layer 202 needs to satisfy both the blocking effect and the performance requirement of the device. The spacer layer 202 may be 3nm-15nm thick, for example. For another example, the thickness of the pad layer 202 is specifically 5 nm. Under the condition of meeting the thickness, the liner layer 202 can not only block the corrosion of the etching liquid to the source drain layer 201 when the channel is released, but also ensure the performance of the device. In practical applications, when the semiconductor device is a PMOS device, the pad layer 202 may contain dopant ions with a doping concentration of 5 × 1018cm-3 to 1 × 1021cm-3 in order to ensure the device performance.
The embodiment of the invention also discloses a manufacturing method of the semiconductor device, which comprises the following steps: and forming a gate-all-around transistor.
Forming a gate all around transistor includes: a channel layer and a sacrificial layer are formed.
Referring to fig. 3-7, and in fig. 3-7, the substrates 50 shown each include a first substrate 501 and a second substrate 502.
In an actual manufacturing process, forming the channel layer and the sacrificial layer includes the steps of:
referring to fig. 3, step S1, a substrate 50 is provided. In practical applications, the substrate 50 includes at least a first substrate 501 when the channel layer is a silicon channel layer. The first substrate 501 may be a Silicon substrate or an SOI (Silicon-On-Insulator) substrate. At this time, since the first substrate 501 and the silicon channel layer are made of the same material, the etching solution does not excessively corrode the first substrate 501 when the sacrificial layer is etched. When the channel layer is a silicon germanium channel layer or a germanium channel layer, the substrate may include a first substrate 501 and a second substrate 502, the second substrate 502 being formed on the first substrate 501, and the silicon germanium channel layer or the germanium channel layer being formed on the second substrate 502. At this time, in order to avoid lattice defects of the germanium-silicon channel layer or the germanium channel layer, the second substrate 502 may be provided as a germanium-silicon substrate. To meet the lattice requirements of a germanium-silicon channel layer or a germanium channel layer, the second substrate may have a germanium mass percentage of 30-75%.
In step S2, referring to fig. 4, a stacked structure of the sacrificial material layers 61 and the channel material layers 11 is alternately formed on the substrate 50 by epitaxy. The stacked structure of the sacrificial material layer 61 and the channel material layer 11 may be a plurality of layers or a single layer as required, and fig. 3 shows a schematic diagram that the stacked structure of the sacrificial material layer 61 and the channel material layer 11 is three layers. According to different requirements, in the embodiment of the present invention, the channel material layer 11 may be a germanium channel material layer, a germanium-silicon channel material layer, or a silicon channel material layer. Sacrificial material layer 61 may be a silicon germanium sacrificial material layer.
In step S3, referring to fig. 5, the stacked structure of the sacrificial material layers 61 and the channel material layers 21 alternately formed as described above is patterned to obtain a plurality of sacrificial layers 60 and channel layers 10. As an example, the patterning of the stacked structure of the alternately formed sacrificial material layers 61 and channel material layers 21 includes etching a fin structure by a sidewall transfer or the like, and at least a portion of the substrate remains at the bottom of the fin. For example, a portion of the second substrate 5021 remains. At this time, the thickness of a portion of the second substrate 5021 should be greater than 20 nm. It is understood that the second substrate 5021 serves to reduce the excessive etching effect of the etchant substrate. In order to meet the function of the semiconductor device structure when the sacrificial layer 60 and the channel layer 10 are formed in the semiconductor device, the back-etching depth of the source and drain regions may need to be greater than that of the gate-all-around structure, that is, the second substrate 502 or the first substrate 501 needs to be etched. In this case, the second substrate 502 or the first substrate 501 needs to have a certain thickness. For example: the thickness of the second substrate 502 may be set to 300nm-3 um. The thickness of the first substrate may be set according to the requirements of the device, which is not limited in the embodiments of the present invention.
As one possible implementation manner, when patterning the stacked structure of the sacrificial material layer 61 and the channel material layer 21 alternately formed as described above, in order to reduce the possibility of leakage between the source and drain, the substrate may be simultaneously patterned. For example, when the substrate includes only the first substrate, the first substrate includes a first base and a first fin formed on the first base after patterning the substrate. At this time, a sacrificial layer and a channel layer are formed on the first fin portion. Referring to fig. 4, for another example, when the substrate 50 includes the first substrate 501 and the second substrate 502, the second substrate 502 is formed on the first substrate 501, and after patterning the substrates, the second substrate 502 includes a second base 5021 and a second fin 5022 formed on the second base 5021. At this time, the sacrificial layer 60 and the channel layer 10 are formed on the second fin 5022.
In a possible implementation manner, when the target element is silicon and the first threshold is 13% -15%, the channel layer is a silicon channel layer and the sacrificial layer is a germanium-silicon sacrificial layer.
In another possible implementation manner, when the target element is germanium and the first threshold is 13% -15%, the channel layer is a germanium channel layer, and the sacrificial layer is a germanium-silicon sacrificial layer.
In yet another possible implementation manner, when the target element is germanium and the first threshold is 13% -15%, the channel layer is a germanium-silicon channel layer, and the sacrificial layer is a germanium-silicon sacrificial layer.
For example, the first fin portion or the second fin portion has a first region and a second region, and the second region is flush with the first region or protrudes from the first region; the channel layer and the sacrificial layer are formed on the second region.
Referring to fig. 6, fig. 6 shows a schematic structural diagram after a pad layer and a source drain layer are formed. While the structure shown in fig. 6 has the first region 50221 flush with the second region 50222, it is understood that the second region 50222 may also protrude from the first region 50221. The substrate in fig. 6 includes a first substrate 501 and a second substrate 502 formed over the first substrate 501. The second substrate 502 includes a base 5021 and a fin 5022 the fin 5022 includes a first region 50221 and a second region 50222. The channel layers 10 and the sacrificial layers 60 are alternately formed on the second region 50222.
After forming the channel layer and the sacrificial layer, forming the gate-all-around transistor further includes:
in step S4, referring to fig. 6, the source-drain structure 20 connected to the channel layer 10 and the sacrificial layer 60 is formed. Specifically, the source-drain structure 20 connected to the channel layer 10 and the sacrificial layer 60 may be formed by: on the first region 50221, a pad layer 202 connected to the channel layer 10 and the sacrificial layer 60 is formed; on the first region 50221, a source-drain layer 201 is formed on a side of the pad layer 202 facing away from the channel layer 10 and the sacrificial layer 60. The channel layer 10 may be a germanium channel layer, a germanium-silicon channel layer, or a silicon channel layer. At this time, in order to satisfy the requirement of sufficient selectivity between the sacrificial layer 60 and the liner layer 202, the liner layer 202 may be a silicon germanium liner layer, a germanium liner layer or a silicon liner layer.
For example, the target element is germanium, the first threshold is 13% to 15%, the channel layer is a germanium channel layer, and after the germanium channel layer and the germanium-silicon sacrificial layer are formed, a germanium pad layer connected to the germanium channel layer and the germanium-silicon sacrificial layer is formed on the first region 50221. Or forming a germanium-silicon pad layer connected with the germanium channel layer and the germanium-silicon sacrificial layer on the first region 50221; wherein, the difference between the mass percent of the germanium in the germanium-silicon pad layer and the mass percent of the germanium in the germanium-silicon sacrificial layer is more than 20-23%.
After the forming the liner layer, the manufacturing method of the semiconductor device further comprises the following steps: and forming a germanium-tin source drain layer on one side of the liner layer, which is far away from the germanium channel layer and the sacrificial layer, on the first region, wherein the mass percentage of tin elements in the germanium-tin source drain layer is 2-15%.
As another example, the target element is germanium and the first threshold is 13% -15%. The channel layer is a germanium-silicon channel layer. After the germanium-silicon channel layer and the germanium-silicon sacrificial layer are formed, a germanium-silicon pad layer connected with the germanium-silicon channel layer and the germanium-silicon sacrificial layer is formed on the first region. Wherein the absolute value of the difference between the mass percent of the germanium element in the germanium-silicon pad layer and the mass percent of the germanium element in the germanium-silicon sacrificial layer is more than 20% -23%. The absolute value of the difference between the mass percent of the germanium element in the germanium-silicon channel layer and the mass percent of the germanium element in the germanium-silicon sacrificial layer is more than 20% -23%.
After the forming the liner layer, the manufacturing method of the semiconductor device further comprises the following steps: and forming a germanium-silicon source drain layer or a germanium-tin source drain layer on one side of the backing layer, which is deviated from the germanium-silicon channel layer and the sacrificial layer, on the first region. Wherein the mass percent of germanium element in the germanium-silicon source drain layer is 35-75%, and the mass percent of tin element in the germanium-tin source drain layer is 2-15%.
As another example, the target element is silicon, the first threshold is 13% -15%; the channel layer is a silicon channel layer. After the silicon channel layer and the silicon germanium sacrificial layer are formed, the manufacturing method of the semiconductor device further comprises the following steps: and forming a silicon liner layer connected with the silicon channel layer and the silicon germanium sacrificial layer on the first region. Or, a silicon germanium pad layer connected with the silicon channel layer and the silicon germanium sacrificial layer is formed on the first region. Wherein, the difference between the mass percent of the germanium element of the germanium-silicon sacrificial layer and the mass percent of the germanium element in the germanium-silicon liner layer is more than 20-23%.
After the forming the liner layer, the manufacturing method of the semiconductor device further comprises the following steps: and forming a germanium-silicon source drain layer on one side of the liner layer on the first region, which is far away from the silicon channel layer and the sacrificial layer, wherein the mass percentage of germanium elements in the germanium-silicon source drain layer is 35-75%.
In the above, the mass percentage of the target element in the pad layer is set so as to satisfy the sufficient selection ratio of the sacrificial layer to the pad layer. So that the liner layer is not excessively corroded by the etching solution when the sacrificial layer is etched.
Step S5, referring to fig. 7, removes the sacrificial layer 60. Specifically, the sacrificial layer 60 is etched by selecting a suitable etching solution, and at this time, the etching solution does not significantly corrode the channel layer 10 due to a sufficient selection ratio between the sacrificial layer 60 and the channel layer 10. In the embodiment of the invention, the material of the liner layer is the same as that of the channel layer; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the channel layer is smaller than the first threshold. The sacrificial layer 60 also has a sufficiently high selectivity to the liner layer 202.
Step S6 is to form a gate-all-around structure around the channel layer 10. The structure after the gate-all-around structure is formed is shown in fig. 1 or fig. 2. The gate-all-around structure includes a passivation layer 40 formed around the channel layer 10, a high-K dielectric layer 301 formed around the passivation layer 40, and a metal gate layer 302. The passivation layer 40 is used to reduce interface defects, improve the gate control capability of the device, reduce the leakage current of the semiconductor device, and improve the reliability of the semiconductor device. As an example, the passivation layer 40 may be an ozone passivation layer. It is understood that the passivation layer 40 may be a passivation layer of other materials. The high-K dielectric layer 301 may be a dielectric layer formed of any one of HfO2, ZrO2, Al2O3, HfO2, or a stack thereof. The metal gate layer 302 may be a metal gate layer such as TaN, TiN, TiAl, W, or a stack thereof. It is understood that the passivation layer 40, the high-K dielectric layer 301 and the metal gate layer 302 may be optimized according to device characteristics.
The invention also discloses an integrated circuit which comprises the semiconductor device provided by the technical scheme.
Compared with the prior art, in the semiconductor device provided by the embodiment of the invention, the liner layer is formed between the channel layer and the source drain layer, and the material of the liner layer is the same as that of the channel layer; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the channel layer is smaller than the first threshold. At this time, the selection ratio of the pad layer is close to that of the channel layer. When releasing the nanowire, a sacrificial layer is generally provided with a large selection ratio to a channel layer. In the embodiment of the invention, the selection ratio of the liner layer is similar to that of the channel layer, so that the sacrificial layer has higher selection ratio to the liner layer when the sacrificial layer is etched. Because the liner layer is arranged between the source drain layer and the channel layer, the source drain layer is not corroded when the sacrificial layer is etched. Therefore, when the nanowire is released, the source drain layer is not corroded, and the formed liner layer is simple in technology, low in manufacturing difficulty and low in production cost.
The invention also discloses electronic equipment which comprises the semiconductor device or the integrated circuit in the technical scheme.
Compared with the prior art, in the semiconductor device provided by the embodiment of the invention, the lining layer is formed between the channel layer and the source drain layer, and the material of the lining layer is the same as that of the channel layer; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the channel layer is smaller than the first threshold. At this time, the selection ratio of the pad layer is close to that of the channel layer. When releasing the nanowire, a sacrificial layer is generally provided with a large selection ratio to a channel layer. In the embodiment of the invention, the selection ratio of the liner layer is similar to that of the channel layer, so that the sacrificial layer has higher selection ratio to the liner layer when the sacrificial layer is etched. Because the liner layer is arranged between the source drain layer and the channel layer, the source drain layer is not corroded when the sacrificial layer is etched. Therefore, when the nanowire is released, the source drain layer is not corroded, and the formed liner layer is simple in technology, low in manufacturing difficulty and low in production cost.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (20)
1. A semiconductor device, characterized in that the semiconductor device comprises:
a gate-all-around transistor;
the ring gate transistor comprises a channel layer and a source drain structure connected with the channel layer;
the source-drain structure comprises a source-drain layer and a gasket layer, and the gasket layer is formed between the source-drain layer and the channel layer;
the liner layer and the channel layer are made of the same material; or the absolute value of the difference between the mass percentage of the target element contained in the material of the liner layer and the mass percentage of the target element contained in the channel layer is smaller than a first threshold.
2. The semiconductor device of claim 1, further comprising a substrate comprising a base and a fin formed on the base;
the liner layer is formed in a first region of the fin portion; the channel layer is formed in the second area of the fin part; the source drain layer is formed on one side, away from the channel layer, of the liner layer on the first region;
the second area is flush with the first area, or the second area protrudes from the first area.
3. The semiconductor device according to claim 2, wherein the substrate comprises a first substrate, and the channel layer is formed over the first substrate;
or, the substrate comprises a first substrate and a second substrate formed on the first substrate, and the second substrate is a germanium-silicon substrate; the channel layer is formed on the second substrate.
4. The semiconductor device according to claim 3, wherein the thickness of the silicon germanium substrate is 300nm-3 um;
and/or the mass percentage of germanium in the germanium-silicon substrate is 30-75%.
5. The semiconductor device according to claim 1, wherein the target element is silicon, and the first threshold value is 13% to 15%;
the channel layer is a silicon channel layer, and the liner layer is a silicon liner layer;
or, the channel layer is a silicon channel layer, and the liner layer is a germanium-silicon liner layer.
6. The semiconductor device according to claim 1, wherein the target element is germanium, and the first threshold is 13% to 15%;
the channel layer is a germanium channel layer, and the liner layer is a germanium liner layer;
or, the channel layer is a germanium channel layer, and the liner layer is a germanium-silicon liner layer.
7. The semiconductor device according to claim 1, wherein the target element is germanium, and the first threshold is 13% to 15%;
the channel layer is a germanium-silicon channel layer, and the backing layer is a germanium-silicon backing layer.
8. The semiconductor device according to any one of claims 1 to 7, wherein the channel layer is a multilayer, and a height of each of the channel layers is greater than or equal to 5nm and less than or equal to 30 nm.
9. The semiconductor device according to any one of claims 1 to 7, wherein the thickness of the pad layer is 3nm to 15 nm.
10. The semiconductor device according to claims 1 to 7, wherein the liner layer contains a dopant ion;
the concentration of the doped ions is 5 multiplied by 1018cm-3-1×1021cm-3。
11. The semiconductor device according to claims 1 to 7, wherein the source drain layer comprises a plurality of germanium-silicon source drain layers, and the plurality of germanium-silicon source drain layers are stacked; the mass percentage of germanium in the multilayer germanium-silicon source drain layer is 35-75%; or the like, or, alternatively,
the source drain layer comprises a plurality of germanium tin source drain layers which are arranged in a stacked mode; the mass percentage of tin in the multilayer germanium-tin source drain layer is 2% -15%.
12. A method for manufacturing a semiconductor device, the method comprising: forming a gate-all-around transistor;
the forming of the gate-all-around transistor comprises:
forming a channel layer and a sacrificial layer;
forming a source drain structure connected with the channel layer and the sacrificial layer;
removing the sacrificial layer to obtain the gate all around transistor;
the source-drain structure comprises a source-drain layer and a gasket layer, and the gasket layer is formed between the source-drain layer and the channel layer;
the liner layer and the channel layer are made of the same material; or the absolute value of the difference between the mass percentage of the target element contained in the material of the pad layer and the mass percentage of the target element contained in the material of the channel layer is smaller than a first threshold.
13. The method for manufacturing a semiconductor device according to claim 12, further comprising, before forming the gate-all-around transistor:
forming a substrate; wherein the substrate comprises a first substrate;
the forming of the channel layer and the sacrificial layer includes:
forming the channel layer and the sacrificial layer on the first substrate; the first substrate comprises a first base part and a first fin part formed on the first base part, and the channel layer and the sacrificial layer are formed on the first fin part;
or, the manufacturing method of the semiconductor device further comprises the following steps before the gate-all-around transistor is formed:
forming a substrate; wherein the substrate includes a first substrate and a second substrate formed on the first substrate;
the forming of the channel layer and the sacrificial layer includes:
forming the channel layer and the sacrificial layer on the second substrate; the second substrate comprises a second base part and a second fin part formed on the second base part, and the channel layer and the sacrificial layer are formed on the second fin part.
14. The method of claim 13, wherein the first fin or the second fin has a first region and a second region, the second region being flush with the first region or protruding from the first region; the channel layer and the sacrificial layer are formed on a second region;
the forming of the source drain structure connected with the channel layer and the sacrificial layer comprises the following steps:
forming a pad layer connected to the channel layer and the sacrificial layer on the first region;
and forming the source drain layer on one side of the liner layer, which is deviated from the channel layer and the sacrificial layer, on the first region.
15. The method for manufacturing a semiconductor device according to claim 14, wherein the target element is silicon, and the first threshold value is 13% to 15%;
the forming of the channel layer and the sacrificial layer includes:
forming a silicon channel layer and a germanium-silicon sacrificial layer;
the forming, on the first region, a liner layer connected to the channel layer and the sacrificial layer includes:
forming a silicon liner layer connected with the silicon channel layer and the germanium-silicon sacrificial layer on the first region;
or, the forming, on the first region, a liner layer connected to the channel layer and the sacrificial layer includes:
forming a silicon-germanium pad layer connected with the silicon channel layer and the silicon-germanium sacrificial layer on the first region; the difference between the mass percent of the germanium element of the germanium-silicon sacrificial layer and the mass percent of the germanium element in the germanium-silicon lining layer is more than 20% -23%.
16. The method for manufacturing a semiconductor device according to claim 14, wherein the target element is germanium, and the first threshold value is 13% to 15%;
the forming of the channel layer and the sacrificial layer includes:
forming a germanium channel layer and a germanium-silicon sacrificial layer;
the forming, on the first region, a liner layer connected to the channel layer and the sacrificial layer includes:
forming a germanium pad layer connected with the germanium channel layer and the germanium-silicon sacrificial layer on the first region;
or, the forming, on the first region, a liner layer connected to the channel layer and the sacrificial layer includes:
forming a germanium-silicon liner layer connected with the germanium channel layer and the germanium-silicon sacrificial layer on the first region; wherein, the difference between the mass percent of the germanium in the germanium-silicon pad layer and the mass percent of the germanium in the germanium-silicon sacrificial layer is more than 20% -23%.
17. The method for manufacturing a semiconductor device according to claim 14, wherein the target element is germanium, and the first threshold value is 13% to 15%;
the forming of the channel layer and the sacrificial layer includes:
forming a germanium-silicon channel layer and a germanium-silicon sacrificial layer;
the forming, on the first region, a liner layer connected to the channel layer and the sacrificial layer includes:
forming a germanium-silicon liner layer connected with the germanium-silicon channel layer and the germanium-silicon sacrificial layer on the first region; the absolute value of the difference between the mass percent of the germanium element in the germanium-silicon lining layer and the mass percent of the germanium element in the germanium-silicon sacrificial layer is greater than 20% -23%, and the absolute value of the difference between the mass percent of the germanium element in the germanium-silicon channel layer and the mass percent of the germanium element in the germanium-silicon sacrificial layer is greater than 20% -23%.
18. The method for manufacturing a semiconductor device according to claim 14,
the channel layer is a silicon channel layer;
forming the source and drain layers on the first region on a side of the liner layer facing away from the channel layer and the sacrificial layer includes:
on the first region, sequentially forming a plurality of germanium-silicon source drain layers on one side of the liner layer, which is far away from the silicon channel layer and the sacrificial layer, wherein the plurality of germanium-silicon source drain layers are stacked; wherein the mass percent of germanium elements in the multilayer germanium-silicon source drain layer is 35-75%;
or, the channel layer is a germanium-silicon channel layer;
forming the source and drain layers on the first region on a side of the liner layer facing away from the channel layer and the sacrificial layer includes:
on the first region, sequentially forming a multilayer germanium-silicon source drain layer or a multilayer germanium-tin source drain layer on one side of the backing layer, which is far away from the germanium-silicon channel layer and the sacrificial layer, wherein the multilayer germanium-silicon source drain or the multilayer germanium-tin source drain are stacked; wherein the mass percent of germanium element in the multilayer germanium-silicon source drain layer is 35-75%, and the mass percent of tin element in the multilayer germanium-tin source drain layer is 2-15%;
or, the channel layer is a germanium channel layer;
forming the source and drain layers on the first region on a side of the liner layer facing away from the channel layer and the sacrificial layer includes:
and on the first region, sequentially forming a plurality of germanium-tin source drain layers on one side of the liner layer, which is far away from the germanium channel layer and the sacrificial layer, wherein the mass percentage of tin elements in the plurality of germanium-tin source drain layers is 2-15%.
19. An integrated circuit comprising the semiconductor device according to any one of claims 1 to 11.
20. An electronic device comprising the semiconductor device according to any one of claims 1 to 11 or the integrated circuit according to claim 19.
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