CN110838521B - P-type semiconductor device and method of manufacturing the same - Google Patents

P-type semiconductor device and method of manufacturing the same Download PDF

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CN110838521B
CN110838521B CN201911132869.0A CN201911132869A CN110838521B CN 110838521 B CN110838521 B CN 110838521B CN 201911132869 A CN201911132869 A CN 201911132869A CN 110838521 B CN110838521 B CN 110838521B
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germanium
silicon epitaxial
gate
semiconductor device
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CN110838521A (en
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翁文寅
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

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Abstract

The invention discloses a P-type semiconductor device, comprising: an embedded germanium-silicon epitaxial layer is formed in the grid structure and the semiconductor substrate formed on the two sides of the grid structure; the source region and the drain region are formed in the embedded germanium-silicon epitaxial layer; forming a first contact hole at the top of the source drain region; a bottom contact structure is formed in the bottom area of the first opening of the first contact hole, and the top area of the first opening is filled with a fourth metal layer; the bottom contact structure is formed by overlapping a second germanium-silicon layer and a third germanium layer, and a fourth metal layer is overlapped on the bottom contact structure; the bottom contact structure has a P + doping concentration greater than that of the surface of the embedded germanium-silicon epitaxial layer. The invention discloses a manufacturing method of a P-type semiconductor device. The invention can reduce the source-drain contact resistance and the channel resistance of the device and improve the performance of the device.

Description

P-type semiconductor device and method of manufacturing the same
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a P-type semiconductor device; the invention also relates to a manufacturing method of the P-type semiconductor device.
Background
As shown in fig. 1, it is a flow chart of a manufacturing method of a conventional P-type semiconductor device; fig. 2 is a schematic diagram of a device structure of a conventional P-type semiconductor device, in which fig. 1 only shows a schematic diagram of a process structure before opening a contact hole, and a schematic diagram of a subsequent process structure is omitted; the manufacturing method of the prior P-type semiconductor device comprises the following steps:
step one, completing the process before etching the opening of the contact hole, wherein the formed device structure comprises the following steps:
a gate structure formed on the surface of the semiconductor substrate 1.
An embedded germanium-silicon epitaxial layer 9 is formed in the semiconductor substrate 1 at two sides of the gate structure.
In the conventional method, the P-type semiconductor device is a fin transistor.
The fin type transistor comprises a fin body which is of a nano-strip or nano-sheet structure and is formed by etching the semiconductor substrate 1.
The fin bodies on the same semiconductor substrate 1 are arranged in parallel, and dielectric layers are isolated among the fin bodies. Fig. 2 is a cross-sectional structural view along one of the fins.
The gate structure covers the top surface and the side surfaces of the fin body for a portion of the length.
Generally, the gate structure includes a gate dielectric layer 3 and a gate conductive material layer 5 stacked together. The material of the gate dielectric layer 3 comprises a high dielectric constant material (HK), and the gate conductive material layer 5 is a Metal Gate (MG), i.e., the gate structure is HKMG, which is often used in process nodes below 28 nm. And a dummy gate structure is adopted in the forming process of the metal gate, the embedded germanium-silicon epitaxial layer 9, the source region and the drain region are formed on two sides of the dummy gate structure in a self-aligned manner, the dummy gate structure is removed after the interlayer film 8 is formed and before the second step, and the metal gate is formed in a removal area of the dummy gate structure. In fig. 2, a work function layer 4 may be further included between the metal gate 5 and the gate dielectric layer 3, and a barrier layer may be further included; the top of the metal gate 5 further comprises a mask layer 6, and a side wall 7 is formed on the side face of the gate structure. Can also be: the gate dielectric layer 3 is made of a gate oxide layer, and the gate conductive material layer 5 is a polysilicon gate; or, the gate dielectric layer 3 is made of a high dielectric constant material, and the gate conductive material layer 5 is a polysilicon gate; or, the gate dielectric layer 3 is made of a gate oxide layer, and the gate conductive material layer 5 is a metal gate.
The embedded germanium-silicon epitaxial layer 9 is formed in the fin body on two sides of the gate structure. The embedded germanium-silicon epitaxial layer 9 is filled in the groove 2. The groove 2 is of a sigma structure.
The source region is composed of a P + region formed in the embedded silicon germanium epitaxial layer 9 at the first side of the gate structure.
The drain region is composed of a P + region formed in the embedded silicon germanium epitaxial layer 9 at the second side of the gate structure.
An interlayer film 8 overlies the source region, the drain region and the gate structure.
Step two, defining a forming area of the contact hole by photoetching, and etching the interlayer film 8 to form an opening penetrating through the contact hole of the interlayer film 8; the contact holes include contact holes at the top of the source region, the drain region, and the gate structure. A first opening 10 is shown in fig. 2 on top of the source and drain regions.
The first opening 10 exposes the embedded sige epitaxial layer 9 at the bottom.
And step three, filling metal layers in the openings to form the contact holes.
Subsequent back end of line (BEOL) processing is then performed.
As shown in fig. 2, the etching process of the first opening 10 may generate loss on the embedded sige-si epitaxial layer 9, which may reduce the volume and the top doping concentration of the embedded sige-si epitaxial layer 9, and may reduce the source-drain contact resistance and the channel on-resistance of the device.
Disclosure of Invention
The invention aims to provide a P-type semiconductor device which can reduce source-drain contact resistance of the device. Therefore, the invention also provides a manufacturing method of the P-type semiconductor device.
In order to solve the above technical problem, the present invention provides a P-type semiconductor device comprising:
a gate structure formed on a surface of the semiconductor substrate.
And embedded germanium-silicon epitaxial layers are formed in the semiconductor substrate on two sides of the grid structure.
The source region is composed of a P + region formed in the embedded germanium-silicon epitaxial layer on the first side of the grid structure.
The drain region is composed of a P + region formed in the embedded germanium-silicon epitaxial layer on the second side of the grid structure.
An interlayer film covers the source region, the drain region and the gate structure.
A first contact hole is formed through the interlayer film on top of the source region and the drain region.
The first contact hole comprises a first opening penetrating through the interlayer film, the first opening exposes the embedded germanium-silicon epitaxial layer at the bottom, a bottom contact structure is formed on the surface of the embedded germanium-silicon epitaxial layer in the bottom area of the first opening, and the top area of the first opening is filled with a fourth metal layer; the bottom contact structure is formed by overlapping a second germanium-silicon layer and a third germanium layer, and the fourth metal layer is overlapped on the bottom contact structure.
The bottom contact structure is doped with P + and the doping concentration of the bottom contact structure is greater than that of the surface of the embedded germanium-silicon epitaxial layer.
The fourth metal layer and the third germanium layer, the second germanium-silicon layer and the embedded germanium-silicon epitaxial layer form Schottky contact, the embedded germanium-silicon epitaxial layer, the second germanium-silicon layer and the third germanium layer form a superposed structure with a gradually-increased valence band, and the valence band of the superposed structure is gradually increased to reduce the barrier height of the Schottky contact.
The channel region is formed in the semiconductor substrate between the embedded germanium-silicon epitaxial layers, the embedded germanium-silicon epitaxial layers generate compressive stress on the channel region, and the bottom contact structure increases the compressive stress on the channel region.
In a further improvement, the P-type semiconductor device is a fin transistor.
The fin type transistor comprises a fin body, the fin body is of a nano-strip or nano-sheet structure, and the fin body is formed by etching the semiconductor substrate.
In a further improvement, the gate structure covers a portion of the length of the top surface and the sides of the fin.
The embedded germanium-silicon epitaxial layer is formed in the fin bodies on two sides of the grid structure.
The further improvement is that the grid structure comprises a grid dielectric layer and a grid conductive material layer which are superposed;
the gate dielectric layer is made of a gate oxide layer; or the material of the gate dielectric layer comprises a high dielectric constant material.
The grid conductive material layer is a polysilicon grid; or, the grid conductive material layer is a metal grid.
In a further improvement, the fin bodies on the same semiconductor substrate are arranged in parallel, and dielectric layers are isolated among the fin bodies.
In a further improvement, the embedded germanium-silicon epitaxial layer is filled in the groove.
In a further improvement, the groove is in a sigma structure.
In a further refinement, the fourth metal layer comprises a TiN and Ti stack formed on a bottom surface and sides of a top region in the first opening and a tungsten layer completely filling the top region in the first opening formed with the TiN and Ti stack.
In order to solve the above technical problem, the method for manufacturing a P-type semiconductor device provided by the present invention comprises the following steps:
step one, completing the process before etching the opening of the contact hole, wherein the formed device structure comprises the following steps:
a gate structure formed on a surface of the semiconductor substrate.
And embedded germanium-silicon epitaxial layers are formed in the semiconductor substrate on two sides of the grid structure.
The source region is composed of a P + region formed in the embedded germanium-silicon epitaxial layer on the first side of the grid structure.
The drain region is composed of a P + region formed in the embedded germanium-silicon epitaxial layer on the second side of the grid structure.
An interlayer film covers the source region, the drain region and the gate structure.
Step two, defining a forming area of the contact hole by photoetching, and etching the interlayer film to form an opening of the contact hole penetrating through the interlayer film; and enabling the contact holes at the tops of the source region and the drain region to be first contact holes, wherein the openings corresponding to the first contact holes are first openings.
The first opening exposes the embedded germanium-silicon epitaxial layer at the bottom.
And thirdly, forming a bottom contact structure on the surface of the embedded germanium-silicon epitaxial layer in the bottom region of the first opening by adopting an epitaxial growth process, wherein the bottom contact structure is formed by overlapping a second germanium-silicon layer and a third germanium layer.
The bottom contact structure is doped with P + and the doping concentration of the bottom contact structure is greater than that of the surface of the embedded germanium-silicon epitaxial layer.
The channel region is formed in the semiconductor substrate between the embedded germanium-silicon epitaxial layers, the embedded germanium-silicon epitaxial layers generate compressive stress on the channel region, and the bottom contact structure increases the compressive stress on the channel region.
Filling a fourth metal layer in the top area of the first opening; the fourth metal layer overlies the bottom contact structure.
The fourth metal layer and the third germanium layer, the second germanium-silicon layer and the embedded germanium-silicon epitaxial layer form Schottky contact, the embedded germanium-silicon epitaxial layer, the second germanium-silicon layer and the third germanium layer form a superposed structure with a gradually-increased valence band, and the valence band of the superposed structure is gradually increased to reduce the barrier height of the Schottky contact.
In a further improvement, the P-type semiconductor device is a fin transistor.
The fin type transistor comprises a fin body, the fin body is of a nano-strip or nano-sheet structure, and the fin body is formed by etching the semiconductor substrate.
In a further improvement, the gate structure covers the top surface and the side surfaces of the fin body with partial length;
the embedded germanium-silicon epitaxial layer is formed in the fin bodies on two sides of the grid structure.
The further improvement is that the grid structure comprises a grid dielectric layer and a grid conductive material layer which are overlapped.
The gate dielectric layer is made of a gate oxide layer; or the material of the gate dielectric layer comprises a high dielectric constant material.
The grid conductive material layer is a polysilicon grid.
Or, the gate conductive material layer is a metal gate, a dummy gate structure is adopted in the forming process of the metal gate, the embedded germanium-silicon epitaxial layer, the source region and the drain region are formed on two sides of the dummy gate structure in a self-aligning manner, the dummy gate structure is removed after the interlayer film is formed and before the second step, and then the metal gate is formed in the removal region of the dummy gate structure.
In a further improvement, the fin bodies on the same semiconductor substrate are arranged in parallel, and dielectric layers are isolated among the fin bodies.
In a further improvement, the embedded germanium-silicon epitaxial layer is filled in the groove.
The further improvement is that the fourth metal layer comprises a TiN and Ti stack layer and a tungsten layer, and the fourth step comprises the following sub-steps:
forming a TiN and Ti stack on a bottom surface and sides of a top region in the first opening;
forming a tungsten layer completely fills the top region in the first opening formed with the superimposed layer of TiN and Ti.
In the invention, from the viewpoint of reducing the source-drain contact resistance of the device, a bottom contact structure formed by overlapping a second germanium-silicon layer and a third germanium layer is added in the bottom region of a first opening of a first contact hole corresponding to the tops of a source-drain region, namely the top of the source region and the drain region, and the bottom contact structure can solve the technical problem of the invention and can obtain an unexpected technical effect at the same time, which is now described as follows:
the bottom contact structure can realize the doping concentration independent of the embedded germanium-silicon epitaxial layer, so that the bottom contact structure is doped with P + and the doping concentration is greater than the P + doping concentration of the surface of the embedded germanium-silicon epitaxial layer; in the prior art, the top of the embedded germanium-silicon epitaxial layer is subjected to loss due to the etching of the first opening, and the doping concentration of the top surface of the embedded germanium-silicon epitaxial layer is reduced, so that the doping concentration of the top surface of the embedded germanium-silicon epitaxial layer can be improved, and the contact resistance can be reduced.
In addition, in the prior art, after the top of the embedded germanium-silicon epitaxial layer is lost, the volume and the stress on a channel region are reduced; the bottom contact structure of the invention can increase the volume of the whole epitaxial layer, so that the volume of the whole epitaxial layer is not influenced by the opening etching process of the contact hole, the compressive stress on a channel region cannot be reduced, the compressive stress on the channel region can be increased, and the channel resistance can be reduced.
In addition, the fourth metal layer and the third germanium layer, the second germanium-silicon layer and the embedded germanium-silicon epitaxial layer in the first contact hole of the invention form a schottky contact, while the embedded germanium-silicon epitaxial layer, the second germanium-silicon layer and the third germanium layer form a superimposed structure with a gradually rising valence band, namely a gradually rising valence band towards the fourth metal layer, and the barrier height of the schottky contact can be reduced by utilizing the gradually rising valence band of the superimposed structure, so that the contact resistance can be further reduced.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a flowchart of a method of manufacturing a conventional P-type semiconductor device;
FIG. 2 is a schematic diagram of a prior art P-type semiconductor device;
FIG. 3 is a schematic diagram of the device structure of a P-type semiconductor device according to an embodiment of the present invention;
FIG. 4 is a band diagram of a Schottky contact at the bottom of a first contact hole of a P-type semiconductor device in accordance with an embodiment of the present invention;
fig. 5 is a flowchart of a method of manufacturing a P-type semiconductor device according to an embodiment of the present invention.
Detailed Description
Fig. 3 is a schematic view of a device structure of a P-type semiconductor device according to an embodiment of the present invention, fig. 3 only shows a schematic view of a process structure before opening a contact hole, and a schematic view of a subsequent process structure is omitted; as shown in fig. 4, it is a band diagram of the schottky contact at the bottom of the first contact hole of the P-type semiconductor device according to the embodiment of the present invention; the P-type semiconductor device of the embodiment of the invention comprises:
a gate structure formed on the surface of the semiconductor substrate 1.
An embedded germanium-silicon epitaxial layer 9 is formed in the semiconductor substrate 1 at two sides of the gate structure.
In the embodiment of the invention, the P-type semiconductor device is a fin transistor.
The fin type transistor comprises a fin body which is of a nano-strip or nano-sheet structure and is formed by etching the semiconductor substrate 1.
The fin bodies on the same semiconductor substrate 1 are arranged in parallel, and dielectric layers are isolated among the fin bodies. Fig. 3 is a cross-sectional view of the fin along one of the strips.
The gate structure covers the top surface and the side surfaces of the fin body for a portion of the length.
The grid structure comprises a grid dielectric layer 3 and a grid conductive material layer 5 which are formed in an overlapping mode. In the embodiment of the invention, the material of the gate dielectric layer 3 comprises a high dielectric constant material; the gate conductive material layer 5 is a metal gate, i.e., the gate structure is HKMG, which is often used in process nodes below 28 nm. In fig. 3, a work function layer 4 may be further included between the metal gate 5 and the gate dielectric layer 3, and a barrier layer may be further included; the top of the metal gate 5 further comprises a mask layer 6, and a side wall 7 is formed on the side face of the gate structure.
In other embodiments can also be: the gate dielectric layer 3 is made of a gate oxide layer, and the gate conductive material layer 5 is a polysilicon gate; or, the gate dielectric layer 3 is made of a high dielectric constant material, and the gate conductive material layer 5 is a polysilicon gate; or, the gate dielectric layer 3 is made of a gate oxide layer, and the gate conductive material layer 5 is a metal gate.
The embedded germanium-silicon epitaxial layer 9 is formed in the fin bodies on two sides of the gate structure. The embedded germanium-silicon epitaxial layer 9 is filled in the groove 2. The groove 2 is in a sigma structure.
The source region is composed of a P + region formed in the embedded sige epitaxial layer 9 on the first side of the gate structure.
The drain region is composed of a P + region formed in the embedded ge-si epitaxial layer 9 at the second side of the gate structure.
An interlayer film 8 overlies the source region, the drain region and the gate structure.
A first contact hole is formed through the interlayer film 8 on top of the source region and the drain region.
The first contact hole comprises a first opening 10 penetrating through the interlayer film 8, the first opening 10 exposes the embedded germanium-silicon epitaxial layer at the bottom, a bottom contact structure 11 is formed on the surface of the embedded germanium-silicon epitaxial layer in the bottom area of the first opening 10, and the top area of the first opening 10 is filled with a fourth metal layer; the bottom contact structure 11 is formed by stacking a second germanium-silicon layer and a third germanium layer, and the fourth metal layer is stacked on the bottom contact structure 11.
The bottom contact structure 11 is doped with P + and the doping concentration is greater than the P + doping concentration of the surface of the embedded germanium-silicon epitaxial layer 9.
The fourth metal layer comprises TiN and Ti superimposed layers formed on the bottom surface and the side surfaces of the top area in the first opening 10, and a tungsten layer completely filling the top area in the first opening 10 formed with the TiN and Ti superimposed layers.
The fourth metal layer and the third germanium layer, the second germanium-silicon layer and the embedded germanium-silicon epitaxial layer 9 form a schottky contact, the embedded germanium-silicon epitaxial layer 9, the second germanium-silicon layer and the third germanium layer form a stacked structure with gradually rising valence bands, and the valence bands of the stacked structure are gradually raised to reduce the barrier height of the schottky contact.
As shown in fig. 4, a solid line 101 represents a valence band curve formed in the embedded sige epitaxial layer 9, the second sige layer, and the third sige layer, and a solid line 102 is a fermi level line of the fourth metal layer; since the band gap width of germanium is smaller than that of silicon germanium, the valence band curve rises in the flat band in the direction toward the fourth metal layer; when a schottky contact is formed, the valence band curve at the contact location decreases. Curve 101a corresponds to the valence band curve at the schottky contact formed only by the embedded sige epitaxial layer 9 in the conventional device, and it can be seen that the valence band curve at the schottky contact of the device according to the embodiment of the present invention is raised by a value as a whole compared to curve 101 a. SBH denotes the barrier height of the schottky contact, SBH1 is the barrier height of the schottky contact of the device of the embodiment of the present invention, and SBH2 is the barrier height of the schottky contact of the conventional device, and it can be seen that SBH1 is lower than SBH2, so the schottky contact of the embodiment of the present invention is reduced.
A channel region is formed in the semiconductor substrate 1 between the embedded germanium-silicon epitaxial layers 9, the embedded germanium-silicon epitaxial layers 9 generate compressive stress on the channel region, and the bottom contact structure 11 increases the compressive stress on the channel region.
In the embodiment of the present invention, starting from reducing the source-drain contact resistance of the device, a bottom contact structure 11 formed by stacking a second germanium-silicon layer and a third germanium layer is added to the bottom region of the first opening 10 of the first contact hole corresponding to the top of the source-drain region, i.e., the top of the source region and the drain region, and the bottom contact structure 11 can solve the technical problem of the present invention and can obtain an unexpected technical effect, which is now described as follows:
the bottom contact structure 11 can realize the doping concentration independent of the embedded germanium-silicon epitaxial layer 9, so that the bottom contact structure 11 can be doped with P + and the doping concentration is greater than the P + doping concentration of the surface of the embedded germanium-silicon epitaxial layer 9; in the prior art, the top of the embedded sige epitaxial layer 9 is damaged due to the etching of the first opening 10, and the doping concentration of the top surface of the embedded sige epitaxial layer 9 is reduced, so that the embodiment of the present invention can increase the doping concentration of the top surface of the embedded sige epitaxial layer 9, thereby reducing the contact resistance.
In addition, in the prior art, after the top of the embedded germanium-silicon epitaxial layer 9 is lost, the volume and the stress on the channel region are reduced; the bottom contact structure 11 of the embodiment of the present invention increases the volume of the whole epitaxial layer, so that the volume of the whole epitaxial layer is not affected by the etching process of the contact hole opening, and not only the compressive stress on the channel region is not reduced, but also the compressive stress on the channel region is increased, thereby reducing the channel resistance.
In addition, the fourth metal layer and the third germanium layer, the second germanium-silicon layer and the embedded germanium-silicon epitaxial layer 9 in the first contact hole of the embodiment of the invention form a schottky contact, and the embedded germanium-silicon epitaxial layer 9, the second germanium-silicon layer and the third germanium layer form a stacked structure with gradually rising valence band, that is, the valence band gradually rises towards the fourth metal layer, and the gradually rising valence band of the stacked structure can be used for reducing the barrier height of the schottky contact, which can further reduce the contact resistance.
Fig. 5 is a flowchart showing a method of manufacturing a P-type semiconductor device according to an embodiment of the present invention; the manufacturing method of the P-type semiconductor device comprises the following steps:
step one, completing the process before etching the opening of the contact hole, wherein the formed device structure comprises the following steps:
a gate structure formed on the surface of the semiconductor substrate 1.
An embedded germanium-silicon epitaxial layer 9 is formed in the semiconductor substrate 1 at two sides of the gate structure.
In the method of the embodiment of the invention, the P-type semiconductor device is a fin transistor.
The fin type transistor comprises a fin body which is of a nano-strip or nano-sheet structure and is formed by etching the semiconductor substrate 1.
The fin bodies on the same semiconductor substrate 1 are arranged in parallel, and dielectric layers are isolated among the fin bodies. Fig. 3 is a cross-sectional structural view along one of the fins.
The gate structure covers the top surface and the side surfaces of the fin body for a portion of the length.
In the method of the embodiment of the invention, the gate structure comprises a gate dielectric layer 3 and a gate conductive material layer 5 which are overlapped. The material of the gate dielectric layer 3 comprises a high dielectric constant material. The gate conductive material layer 5 is a metal gate, a dummy gate structure is adopted in the forming process of the metal gate, the embedded germanium-silicon epitaxial layer 9, the source region and the drain region are formed on two sides of the dummy gate structure in a self-aligning manner, the dummy gate structure is removed after the interlayer film 8 is formed and before the second step, and then the metal gate is formed in a removing area of the dummy gate structure. In fig. 3, a work function layer 4 may be further included between the metal gate 5 and the gate dielectric layer 3, and a barrier layer may be further included; the top of the metal gate 5 further comprises a mask layer 6, and a side wall 7 is formed on the side face of the gate structure. In other embodiments the method can also be: the gate dielectric layer 3 is made of a gate oxide layer, and the gate conductive material layer 5 is a polysilicon gate; or, the gate dielectric layer 3 is made of a high dielectric constant material, and the gate conductive material layer 5 is a polysilicon gate; or, the gate dielectric layer 3 is made of a gate oxide layer, and the gate conductive material layer 5 is a metal gate.
The embedded germanium-silicon epitaxial layer 9 is formed in the fin bodies on two sides of the gate structure. The embedded germanium-silicon epitaxial layer 9 is filled in the groove 2. The groove 2 is in a sigma structure.
The source region is composed of a P + region formed in the embedded silicon germanium epitaxial layer 9 at the first side of the gate structure.
The drain region is composed of a P + region formed in the embedded ge-si epitaxial layer 9 at the second side of the gate structure.
An interlayer film 8 overlies the source region, the drain region and the gate structure.
Step two, defining a forming area of the contact hole by photoetching, and etching the interlayer film 8 to form an opening penetrating through the contact hole of the interlayer film 8; the contact holes at the tops of the source region and the drain region are made to be first contact holes, and the openings corresponding to the first contact holes are first openings 10.
The first opening 10 exposes the embedded silicon germanium epitaxial layer at the bottom.
The contact hole also includes a contact hole at the top of the gate structure, the contact hole at the top of the gate structure and its opening not shown in fig. 3.
And thirdly, forming a bottom contact structure 11 on the surface of the embedded germanium-silicon epitaxial layer in the bottom region of the first opening 10 by adopting an epitaxial growth process, wherein the bottom contact structure 11 is formed by overlapping a second germanium-silicon layer and a third germanium layer.
The bottom contact structure 11 is doped with P + and the doping concentration is greater than the P + doping concentration of the surface of the embedded germanium-silicon epitaxial layer 9.
A channel region is formed in the semiconductor substrate 1 between the embedded germanium-silicon epitaxial layers 9, the embedded germanium-silicon epitaxial layers 9 generate compressive stress on the channel region, and the bottom contact structure 11 increases the compressive stress on the channel region.
Filling a fourth metal layer in the top area of the first opening 10; the fourth metal layer is superimposed on the bottom contact structure 11.
The fourth metal layer comprises a TiN and Ti superposed layer and a tungsten layer, and the fourth step comprises the following sub-steps:
forming a TiN and Ti stack on the bottom surface and sides of the top region in the first opening 10;
forming a tungsten layer completely fills the top region in the first opening 10 formed with a superimposed layer of TiN and Ti.
The fourth metal layer and the third germanium layer, the second germanium-silicon layer and the embedded germanium-silicon epitaxial layer 9 form a schottky contact, the embedded germanium-silicon epitaxial layer 9, the second germanium-silicon layer and the third germanium layer form an overlapped structure with a gradually-rising valence band, and the valence band of the overlapped structure is gradually raised to reduce the barrier height of the schottky contact.
Followed by a subsequent BEOL.
The present invention has been described in detail with reference to the specific examples, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A P-type semiconductor device, comprising:
a gate structure formed on a surface of the semiconductor substrate;
forming embedded germanium-silicon epitaxial layers in the semiconductor substrate on two sides of the grid structure;
the source region consists of a P + region formed in the embedded germanium-silicon epitaxial layer on the first side of the grid structure;
the drain region consists of a P + region formed in the embedded germanium-silicon epitaxial layer on the second side of the grid structure;
an interlayer film covers the source region, the drain region and the gate structure;
forming a first contact hole through the interlayer film on top of the source region and the drain region;
the first contact hole comprises a first opening penetrating through the interlayer film, the first opening exposes the embedded germanium-silicon epitaxial layer at the bottom, a bottom contact structure is formed on the surface of the embedded germanium-silicon epitaxial layer in the bottom area of the first opening, and the top area of the first opening is filled with a fourth metal layer; the bottom contact structure is formed by overlapping a second germanium-silicon layer and a third germanium layer, and the fourth metal layer is overlapped on the bottom contact structure;
the bottom contact structure is doped with P + and the doping concentration of the bottom contact structure is greater than that of the P + on the surface of the embedded germanium-silicon epitaxial layer;
the fourth metal layer and the third germanium layer, the second germanium-silicon layer and the embedded germanium-silicon epitaxial layer form a Schottky contact, the embedded germanium-silicon epitaxial layer, the second germanium-silicon layer and the third germanium layer form a superposed structure with a gradually-rising valence band, and the valence band of the superposed structure is gradually raised to reduce the barrier height of the Schottky contact;
the channel region is formed in the semiconductor substrate between the embedded germanium-silicon epitaxial layers, the embedded germanium-silicon epitaxial layers generate compressive stress on the channel region, and the bottom contact structure increases the compressive stress on the channel region.
2. The P-type semiconductor device of claim 1, wherein: the P-type semiconductor device is a fin transistor;
the fin type transistor comprises a fin body, the fin body is of a nano-strip or nano-sheet structure, and the fin body is formed by etching the semiconductor substrate.
3. The P-type semiconductor device of claim 2, wherein: the grid electrode structure covers the top surface and the side face of the fin body with partial length;
the embedded germanium-silicon epitaxial layer is formed in the fin bodies on two sides of the grid structure.
4. The P-type semiconductor device of claim 3, wherein: the grid structure comprises a grid dielectric layer and a grid conductive material layer which are superposed;
the gate dielectric layer is made of a gate oxide layer; or, the material of the gate dielectric layer comprises a high dielectric constant material;
the grid conductive material layer is a polysilicon grid; or, the grid conductive material layer is a metal grid.
5. The P-type semiconductor device of claim 2, wherein: the fin bodies on the same semiconductor substrate are arranged in parallel, and dielectric layers are isolated among the fin bodies.
6. The P-type semiconductor device of claim 3, wherein: the embedded germanium-silicon epitaxial layer is filled in the groove.
7. The P-type semiconductor device of claim 6, wherein: the groove is of a sigma structure.
8. The P-type semiconductor device of claim 1, wherein: the fourth metal layer comprises a TiN and Ti superimposed layer and a tungsten layer, the TiN and Ti superimposed layer is formed on the bottom surface and the side face of the top area in the first opening, and the tungsten layer completely fills the top area in the first opening formed with the TiN and Ti superimposed layer.
9. A method for manufacturing a P-type semiconductor device is characterized by comprising the following steps:
step one, completing the process before etching the opening of the contact hole, wherein the formed device structure comprises the following steps:
a gate structure formed on a surface of the semiconductor substrate;
forming embedded germanium-silicon epitaxial layers in the semiconductor substrate on two sides of the grid structure;
the source region consists of a P + region formed in the embedded germanium-silicon epitaxial layer on the first side of the grid structure;
the drain region consists of a P + region formed in the embedded germanium-silicon epitaxial layer on the second side of the grid structure;
an interlayer film covers the source region, the drain region and the gate structure;
step two, defining a forming area of the contact hole by photoetching, and etching the interlayer film to form an opening of the contact hole penetrating through the interlayer film; the contact holes at the tops of the source region and the drain region are made to be first contact holes, and the openings corresponding to the first contact holes are first openings;
the first opening exposes the embedded germanium-silicon epitaxial layer at the bottom;
forming a bottom contact structure on the surface of the embedded germanium-silicon epitaxial layer in the bottom region of the first opening by adopting an epitaxial growth process, wherein the bottom contact structure is formed by overlapping a second germanium-silicon layer and a third germanium layer;
the bottom contact structure is doped with P + and the doping concentration of the bottom contact structure is greater than that of the P + on the surface of the embedded germanium-silicon epitaxial layer;
a channel region is formed in the semiconductor substrate between the embedded germanium-silicon epitaxial layers, the embedded germanium-silicon epitaxial layers generate compressive stress on the channel region, and the bottom contact structure increases the compressive stress on the channel region;
filling a fourth metal layer in the top area of the first opening; the fourth metal layer is superposed on the bottom contact structure;
the fourth metal layer and the third germanium layer, the second germanium-silicon layer and the embedded germanium-silicon epitaxial layer form Schottky contact, the embedded germanium-silicon epitaxial layer, the second germanium-silicon layer and the third germanium layer form a superposed structure with a gradually-increased valence band, and the valence band of the superposed structure is gradually increased to reduce the barrier height of the Schottky contact.
10. The method for manufacturing a P-type semiconductor device according to claim 9, wherein: the P-type semiconductor device is a fin transistor;
the fin type transistor comprises a fin body, the fin body is of a nano-strip or nano-sheet structure, and the fin body is formed by etching the semiconductor substrate.
11. The method for manufacturing a P-type semiconductor device according to claim 10, wherein: the grid electrode structure covers the top surface and the side face of the fin body with partial length;
the embedded germanium-silicon epitaxial layer is formed in the fin bodies on two sides of the grid structure.
12. The method for manufacturing a P-type semiconductor device according to claim 11, wherein: the grid structure comprises a grid dielectric layer and a grid conductive material layer which are overlapped;
the gate dielectric layer is made of a gate oxide layer; or, the material of the gate dielectric layer comprises a high dielectric constant material;
the gate conductive material layer is a polysilicon gate;
or, the gate conductive material layer is a metal gate, a dummy gate structure is adopted in the forming process of the metal gate, the embedded germanium-silicon epitaxial layer, the source region and the drain region are formed on two sides of the dummy gate structure in a self-aligned mode, the dummy gate structure is removed after the interlayer film is formed and before the second step, and then the metal gate is formed in a removal area of the dummy gate structure.
13. The method for manufacturing a P-type semiconductor device according to claim 10, wherein: the fin bodies on the same semiconductor substrate are arranged in parallel, and dielectric layers are isolated among the fin bodies.
14. The method for manufacturing a P-type semiconductor device according to claim 11, wherein: the embedded germanium-silicon epitaxial layer is filled in the groove.
15. The method for manufacturing a P-type semiconductor device according to claim 9, wherein: the fourth metal layer comprises a TiN and Ti superposed layer and a tungsten layer, and the fourth step comprises the following sub-steps:
forming a TiN and Ti stack on a bottom surface and sides of a top region in the first opening;
forming a tungsten layer completely fills the top region in the first opening formed with the superimposed layer of TiN and Ti.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009526A (en) * 2009-06-26 2011-01-13 Toshiba Corp Semiconductor device and method of manufacturing the same
CN102511081A (en) * 2009-09-24 2012-06-20 国际商业机器公司 Method and structure for forming high-performance FETs with embedded stressors
CN108470770A (en) * 2018-03-21 2018-08-31 上海华力集成电路制造有限公司 Fin transistor and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009526A (en) * 2009-06-26 2011-01-13 Toshiba Corp Semiconductor device and method of manufacturing the same
CN102511081A (en) * 2009-09-24 2012-06-20 国际商业机器公司 Method and structure for forming high-performance FETs with embedded stressors
CN108470770A (en) * 2018-03-21 2018-08-31 上海华力集成电路制造有限公司 Fin transistor and its manufacturing method

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