WO2023030788A1 - Elektronikanordnung mit einem leistungshalbleiterbauelement zwischen zwei schaltungsträgern und verfahren zu deren herstellung - Google Patents
Elektronikanordnung mit einem leistungshalbleiterbauelement zwischen zwei schaltungsträgern und verfahren zu deren herstellung Download PDFInfo
- Publication number
- WO2023030788A1 WO2023030788A1 PCT/EP2022/071346 EP2022071346W WO2023030788A1 WO 2023030788 A1 WO2023030788 A1 WO 2023030788A1 EP 2022071346 W EP2022071346 W EP 2022071346W WO 2023030788 A1 WO2023030788 A1 WO 2023030788A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- power semiconductor
- semiconductor component
- circuit carrier
- layer
- contact
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 239000000969 carrier Substances 0.000 title abstract description 16
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000000654 additive Substances 0.000 claims abstract description 12
- 230000000996 additive effect Effects 0.000 claims abstract description 12
- 239000007858 starting material Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 2
- 238000010276 construction Methods 0.000 claims 1
- 230000000930 thermomechanical effect Effects 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 239000000843 powder Substances 0.000 description 5
- 230000001419 dependent effect Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/27312—Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
- H01L2224/27442—Manufacturing methods by blanket deposition of the material of the layer connector in solid form using a powder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/2755—Selective modification
- H01L2224/27552—Selective modification using a laser or a focussed ion beam [FIB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29016—Shape in side view
- H01L2224/29017—Shape in side view being non uniform along the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
- H01L2224/29082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/29124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29193—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/291 - H01L2224/29191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29317—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/29324—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29347—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/29393—Base material with a principal constituent of the material being a solid not provided for in groups H01L2224/293 - H01L2224/29391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Definitions
- the invention relates to an electronic arrangement between a power semiconductor component and two circuit carriers, which is characterized in particular by good thermomechanical properties and advantageous production. Furthermore, the invention relates to a method for forming an electronic arrangement according to the invention.
- An electronic arrangement with the features of the preamble of claim 1 is known from DE 102015 205 704 A1 of the applicant.
- the known electronics arrangement has a circuit carrier in the form of a DBG (direct bonded copper) which is connected via a soldered connection to an underside of a power semiconductor component designed as a transistor. The electrical contacting of the top side of the power semiconductor component with the circuit carrier takes place via bonding wire connections.
- DBG direct bonded copper
- the electronic arrangement according to the invention between a power semiconductor component and a circuit carrier, comprising the power semiconductor component and the circuit carrier, with the features of claim 1 has the advantage that it enables a particularly compact arrangement of a power semiconductor component arranged between two circuit carriers with good thermomechanical properties at the same time.
- the advantages mentioned are achieved in an electronic arrangement according to the invention with the features of claim 1 in that the power semiconductor component is electrically contacted on the side facing away from the circuit carrier in the area of at least one contact area with a further circuit carrier, that on at least one contact area and/or one connection area a connection layer produced in the additive process is arranged, and that the connection layer is connected to the connection area and/or the contact area by means of a soldered connection.
- the connecting layer has a lower modulus of elasticity in a direction perpendicular to the surface of the power semiconductor component than in a direction parallel to the surface of the power semiconductor component. In other words, this means that direction-dependent, different elasticities of the connecting layer are generated.
- connection layer is also preferably made for the connecting layer to be formed from a plurality of layers of a metallic starting material, and for at least some of the layers to have gaps or free spaces in a direction running parallel to the surface of the power semiconductor component.
- the gaps or free spaces serve in particular to achieve different moduli of elasticity in the two mentioned directions running perpendicularly to the surface of the power semiconductor component and, if necessary, improved cooling or improved heat dissipation.
- the connection layer is produced in particular by successive layers of the connection layer being produced by the application of a metallic powder, which after the application is selectively through a laser beam (or a photon beam) can be melted.
- the melted material then solidifies to form part of the bonding layer, while the unmelted material is removed from the region of the bonding layer in a subsequent processing step.
- the metallic powder preferably consists of or contains copper and/or aluminum and/or a copper alloy and/or an aluminum alloy. Alternatively or additionally, the metallic powder contains a composite comprising carbon.
- the additive structure allows the materials mentioned to be mixed into a powder mixture in order to produce different alloys through the melting process.
- other additive manufacturing methods known per se from the prior art can of course also be used to produce the connecting layer.
- the connecting layer has a smaller modulus of elasticity in a plane running perpendicular to the surface of the power semiconductor component than in a plane running parallel to the plane of the power semiconductor component, in particular by forming the connecting layer with a herringbone pattern.
- a herringbone pattern enables the mentioned different, direction-dependent elasticity of the connecting layer.
- other geometries of the connection layer are also possible in order to realize the different (direction-dependent) elasticities.
- At least a first layer of the connecting layer formed on the contact area or the contact area is formed as a full-surface layer.
- a further preferred configuration for improving the soldered connection provides that at least one layer of the connecting layer has gaps or free spaces on the side facing the connection area.
- a further embodiment of the invention provides that the circuit carrier and the further circuit carrier are electrically contacted with one another in the area outside the power semiconductor component, optionally with the interposition of a contact element, and in that at least one connection layer produced in the additive process is arranged in the area of the contact
- the power semiconductor component is a transistor and the circuit carrier and the further circuit carrier are each a substrate.
- the invention also includes a method for forming an electronic arrangement, in particular the electronic arrangement according to the invention described so far, the method according to the invention having at least the following steps: First, a connecting layer is built up on and/or in the area of a contact area of the power semiconductor component and/or on a connection area of the Circuit carrier and / or the other circuit carrier in the additive process. The circuit carrier and the further circuit carrier are then brought into contact with the power semiconductor component being interposed. Finally, a soldered connection is formed between the connection layer and the connection area or the contact area.
- a preferred development of the method provides that a solder is applied to the connection layer by dispensing.
- FIG. 1 shows, in a simplified longitudinal section, an electronics arrangement between a power semiconductor component designed as a transistor and circuit carriers arranged on opposite sides of the power semiconductor component, each in the form of a substrate.
- FIG. 1 shows an electronic arrangement 100, which comprises a power semiconductor component 10 in the form of a transistor 12, a circuit carrier 14 in the form of a substrate 16 and a further circuit carrier 18, also in the form of a substrate 20, the power semiconductor component 10 having the both circuit carriers 14 and 18 is electrically contacted. Furthermore, the planes of the power semiconductor component 10 and the two circuit carriers 14 and 18 run parallel to one another.
- power semiconductor component 10 On the side facing circuit carrier 14, power semiconductor component 10 has two separate contact regions 22, 24 formed by metallization, and on the side facing further circuit carrier 18 a single contact region 26 also formed by metallization. Furthermore, connection areas 28 , 30 , 32 in the form of conductor track sections 34 are provided on the two circuit carriers 14 and 18 , assigned to the respective contact area 22 , 24 and 26 .
- connection areas 28, 30 and 32 and the contact areas 22, 24 and 26 connecting layers 36, 38 and 40 produced using the additive method are arranged.
- the connecting layers 36, 38 and 40 which are preferably produced by building up metallic starting material (metal powder) in layers and then selectively melting the starting material using an electron beam (laser beam), are applied in particular to the connection areas 28, 30 or 32, alternatively or additionally to the contact areas 22, 24 and 26 of the power semiconductor element 10 is generated.
- connection between the connection layers 36, 38 and 40 and the circuit carriers 14 and 18 as well as the power semiconductor component 10 is made by soldered connections, not shown in FIG.
- the solder connections are always made on the side or the Element formed on which no structure of the connecting layer 36, 38, 40 has taken place.
- gaps 42 or free spaces are formed in the connecting layers 36, 38 and 40 in a plane running perpendicular to the plane of the power semiconductor component 10 and the circuit carriers 14 and 18 or parallel to the plane of the drawing in FIG.
- the connecting layers 36, 38 and 40 each form a herringbone pattern 44 in such a way that, corresponding to the double arrow 45, the connecting layers 36, 38 and 40 have a lower rigidity or have a lower modulus of elasticity than in the direction of the plane of the power semiconductor component 10 or the circuit carriers 14 and 18.
- thermomechanical stresses running in the direction of the double arrow 45 are at least partially absorbed or equalized by the connecting layer 36, 38, 40 in the sense of a spring element and a Forwarding corresponding voltages to the power component 10 or the circuit carrier 14, 18 is reduced.
- the two circuit carriers 14 and 18 are electrically contacted with one another in a region outside of the power semiconductor component 10 .
- a contact element 46 in the form of a soldered connector 48 is additionally provided between the two circuit carriers 14 and 18 .
- Connecting layers 54 and 56 are also formed between the contact element 46 and conductor track sections 50 , 52 of the two circuit carriers 14 and 18 and are arranged between the conductor track sections 48 and 50 and the contact element 46 .
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202280058880.0A CN117882178A (zh) | 2021-08-30 | 2022-07-29 | 带有在两个电路载体之间的功率半导体结构元件的电子布置结构及制造电子布置结构的方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102021209486.4 | 2021-08-30 | ||
DE102021209486.4A DE102021209486A1 (de) | 2021-08-30 | 2021-08-30 | Elektronikanordnung und Verfahren zu deren Herstellung |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2023030788A1 true WO2023030788A1 (de) | 2023-03-09 |
Family
ID=83059165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2022/071346 WO2023030788A1 (de) | 2021-08-30 | 2022-07-29 | Elektronikanordnung mit einem leistungshalbleiterbauelement zwischen zwei schaltungsträgern und verfahren zu deren herstellung |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN117882178A (de) |
DE (1) | DE102021209486A1 (de) |
WO (1) | WO2023030788A1 (de) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1329951A2 (de) * | 2002-01-16 | 2003-07-23 | Delphi Technologies, Inc. | Elektrisch isolierende, thermisch leitende, doppelseitige, vorgehäuste Komponente |
EP2871675A1 (de) * | 2013-11-06 | 2015-05-13 | Mitsubishi Electric R & D Centre Europe B.V. | Druckverbindung für einen Halbleiterchip mittels flexibler Nanodrähte und entsprechendes Herstellungsverfahren |
EP2945189A1 (de) * | 2013-01-09 | 2015-11-18 | Hitachi, Ltd. | Halbleiterbauelement und verfahren zur herstellung davon |
US20160181217A1 (en) * | 2014-12-23 | 2016-06-23 | Intel Corporation | Formation of solder and copper interconnect structures and associated techniques and configurations |
DE102015205704A1 (de) | 2015-03-30 | 2016-10-06 | Robert Bosch Gmbh | Kontaktanordnung und Verfahren zu Herstellung der Kontaktanordnung |
US20160315059A1 (en) * | 2015-04-24 | 2016-10-27 | Stmicroelectronics S.R.L. | Method of producing bumps in electronic components, corresponding component and computer program product |
US20190371703A1 (en) * | 2017-09-14 | 2019-12-05 | Shindengen Electric Manufacturing Co., Ltd. | Electronic module and method for manufacturing electronic module |
EP3739624A1 (de) * | 2019-05-13 | 2020-11-18 | Infineon Technologies Austria AG | Halbleiteranordnung mit einem zwischen zwei trägern eingekapselten komprimierbaren kontaktelement und entsprechendes herstellungsverfahren |
-
2021
- 2021-08-30 DE DE102021209486.4A patent/DE102021209486A1/de active Pending
-
2022
- 2022-07-29 WO PCT/EP2022/071346 patent/WO2023030788A1/de active Application Filing
- 2022-07-29 CN CN202280058880.0A patent/CN117882178A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1329951A2 (de) * | 2002-01-16 | 2003-07-23 | Delphi Technologies, Inc. | Elektrisch isolierende, thermisch leitende, doppelseitige, vorgehäuste Komponente |
EP2945189A1 (de) * | 2013-01-09 | 2015-11-18 | Hitachi, Ltd. | Halbleiterbauelement und verfahren zur herstellung davon |
EP2871675A1 (de) * | 2013-11-06 | 2015-05-13 | Mitsubishi Electric R & D Centre Europe B.V. | Druckverbindung für einen Halbleiterchip mittels flexibler Nanodrähte und entsprechendes Herstellungsverfahren |
US20160181217A1 (en) * | 2014-12-23 | 2016-06-23 | Intel Corporation | Formation of solder and copper interconnect structures and associated techniques and configurations |
DE102015205704A1 (de) | 2015-03-30 | 2016-10-06 | Robert Bosch Gmbh | Kontaktanordnung und Verfahren zu Herstellung der Kontaktanordnung |
US20160315059A1 (en) * | 2015-04-24 | 2016-10-27 | Stmicroelectronics S.R.L. | Method of producing bumps in electronic components, corresponding component and computer program product |
US20190371703A1 (en) * | 2017-09-14 | 2019-12-05 | Shindengen Electric Manufacturing Co., Ltd. | Electronic module and method for manufacturing electronic module |
EP3739624A1 (de) * | 2019-05-13 | 2020-11-18 | Infineon Technologies Austria AG | Halbleiteranordnung mit einem zwischen zwei trägern eingekapselten komprimierbaren kontaktelement und entsprechendes herstellungsverfahren |
Also Published As
Publication number | Publication date |
---|---|
CN117882178A (zh) | 2024-04-12 |
DE102021209486A1 (de) | 2023-03-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE112009000447B4 (de) | Halbleitervorrichtung und Verfahren zu ihrer Herstellung | |
DE102005049687B4 (de) | Leistungshalbleiterbauteil in Flachleitertechnik mit vertikalem Strompfad und Verfahren zur Herstellung | |
DE10033977A1 (de) | Zwischenverbindungsstruktur zum Einsatz von Halbleiterchips auf Schichtträgern | |
WO2005081315A2 (de) | Halbleiterbauteil mit einem stapel aus halbleiterchips und verfahren zur herstellung desselben | |
AT10735U1 (de) | Verfahren zur herstellung einer leiterplatte sowie verwendung und leiterplatte | |
EP1508168B1 (de) | Halbleiterbauelement und verfahren zum herstellen einer halbleiterbauelementanordnung mit dem halbleiterbauelement | |
WO2013013964A1 (de) | Trägervorrichtung, elektrische vorrichtung mit einer trägervorrichtung und verfahren zur herstellung dieser | |
EP0745274B1 (de) | Verfahren zur herstellung einer dreidimensionalen schaltungsanordnung | |
DE102004041088A1 (de) | Halbleiterbauteil in Flachleitertechnik mit einem Halbleiterchip | |
EP0741504A2 (de) | Metallleiterplatte und Verfahren zur Herstellung | |
DE19507547C2 (de) | Verfahren zur Montage von Chips | |
DE102007031490B4 (de) | Verfahren zur Herstellung eines Halbleitermoduls | |
DE3635375C2 (de) | ||
DE102020204406A1 (de) | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung | |
WO2023030788A1 (de) | Elektronikanordnung mit einem leistungshalbleiterbauelement zwischen zwei schaltungsträgern und verfahren zu deren herstellung | |
DE102006060899A1 (de) | Anschlussdraht, Verfahren zur Herstellung eines solchen und Baugruppe | |
DE112018006382T5 (de) | Halbleitereinheit und Verfahren zur Herstellung einer Halbleitereinheit | |
DE4425943B4 (de) | Verfahren zur Herstellung eines mehrschichtigen Leiter- bzw. Anschlusselements und Leiter- bzw. Anschlusselement | |
DE102014116030A1 (de) | Verfahren zur Herstellung einer Verbindung und Anordnung für eine Chipzusammenstellung mit Direktverbindung | |
DE102007002807B4 (de) | Chipanordnung | |
WO2022002596A1 (de) | Formdraht, leiterplatte, leistungselektronik und verfahren zur herstellung einer leiterplatte | |
DE102012213555B4 (de) | Verfahren zur Herstellung eines Leistungshalbleitermoduls | |
EP4047648A1 (de) | Leistungsmodul mit einem mittels sintern und löten mit einem substrat verbundenen leistungs-bauelement und entsprechendes herstellungsverfahren | |
DE102021209484A1 (de) | Elektronikanordnung und Verfahren zu deren Herstellung | |
EP2287899A1 (de) | Lötverbindung mit einer mehrschichtigen lötbaren Schicht |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 22758477 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 202280058880.0 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2022758477 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 2022758477 Country of ref document: EP Effective date: 20240402 |