WO2023028902A1 - 半导体器件及其制作方法、nand存储器件 - Google Patents

半导体器件及其制作方法、nand存储器件 Download PDF

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Publication number
WO2023028902A1
WO2023028902A1 PCT/CN2021/115852 CN2021115852W WO2023028902A1 WO 2023028902 A1 WO2023028902 A1 WO 2023028902A1 CN 2021115852 W CN2021115852 W CN 2021115852W WO 2023028902 A1 WO2023028902 A1 WO 2023028902A1
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region
groove
gate
opening
insulating layer
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PCT/CN2021/115852
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English (en)
French (fr)
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姚兰
华子群
石艳伟
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长江存储科技有限责任公司
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Priority to CN202180004313.2A priority Critical patent/CN114175217A/zh
Priority to PCT/CN2021/115852 priority patent/WO2023028902A1/zh
Priority to US17/877,708 priority patent/US20230061535A1/en
Publication of WO2023028902A1 publication Critical patent/WO2023028902A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • the present application relates to the technical field of semiconductor devices, in particular to a semiconductor device, a manufacturing method thereof, and a NAND storage device.
  • 3D NAND three-dimensional NAND
  • CMOS Complementary Metal-Oxide Semiconductor
  • the present application provides a semiconductor device, a manufacturing method thereof, and a NAND storage device, so as to solve the problem of how to improve the performance of the transistor device and reduce the difficulty of the manufacturing process of the transistor device while reducing the size of the transistor device.
  • the present application provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device includes: forming a substrate, the substrate includes a first active region and an isolation region located around the first active region, the second An active region includes a first source region, a first channel region and a first drain region connected in sequence; a patterned first hard mask layer is formed on the substrate, and the patterned first hard mask layer Including a first opening, the first opening is used to expose the first channel region and a part of the isolation region; a first groove is formed between the isolation region and the first channel region through the first opening, and the first groove is partially located in the isolation region region, and does not penetrate the isolation region; forming a first gate insulating layer covering the first groove and the first channel region; forming a first gate insulating layer in the first opening and the first groove on the first gate insulating layer gate; removing the patterned first hard mask layer.
  • forming the first gate in the first opening and the first groove on the first gate insulating layer specifically includes: depositing a gate on the first gate insulating layer in the first opening and the first groove material; removing the gate material located outside the first opening by chemical mechanical polishing, so as to obtain the first gate.
  • the substrate further includes a shallow trench formed in the isolation region and located at the periphery of the first active region, and before the patterned first hard mask layer is formed on the substrate, it further includes: in the shallow trench of the isolation region forming a shallow trench isolation structure; forming a first groove between the isolation region and the first channel region through the first opening, specifically including: forming a groove between the shallow trench isolation structure and the first channel region through the first opening.
  • the first groove, the depth of the first groove in the longitudinal direction perpendicular to the substrate is smaller than the depth of the shallow trench isolation structure in the longitudinal direction.
  • forming the first groove between the shallow trench isolation structure and the first channel region through the first opening specifically includes: forming a patterned second hard mask layer on the patterned first hard mask layer , the patterned second hard mask layer includes a second opening, the second opening communicates with the first opening, and part of the shallow trench isolation structure is exposed through the first opening and the second opening; selectively removing the first opening and the part of the shallow trench isolation structure exposed by the second opening, so as to obtain the first groove between the shallow trench isolation structure and the first channel region, and wherein the patterned second hard mask layer is used for During the process of selectively removing the part of the shallow trench isolation structure exposed by the first opening and the second opening, the remaining shallow trench isolation structure is protected from being removed.
  • the substrate further includes a second active region, the first active region and the second active region are separated by an isolation region, and the second active region includes a second source region, a second channel region connected in sequence and the second drain region, the patterned first hard mask layer further includes a third opening, the third opening is used to expose the second channel region, and a part of the isolation region, on the first gate insulating layer on the first
  • it also includes: forming a second groove between the isolation region and the second channel region through the third opening, the second groove is partly located in the isolation region, and does not penetrating through the isolation region; forming a second gate insulating layer covering the second groove and the second channel region, and the thickness of the second gate insulating layer is different from that of the first gate insulating layer.
  • the depth of the second groove in the longitudinal direction perpendicular to the substrate is smaller than the depth of the first groove in the longitudinal direction.
  • the present application also provides a semiconductor device, which includes: a substrate, the substrate includes a first active region and an isolation region located around the first active region, the first active region includes sequentially connected first source region, first channel region and first drain region; a first groove located between the isolation region and the first channel region, the first groove part is located in the isolation region, and does not through the isolation region; covering the first groove and the first gate insulating layer of the first channel region; the first gate on the first gate insulating layer, the first gate covering the first channel region, and filling first groove.
  • the substrate further includes a second active region, the first active region and the second active region are separated by an isolation region, and the second active region includes a second source region, a second channel region connected in sequence and the second drain region, the semiconductor device further includes: a second groove located between the isolation region and the second channel region, the second groove is partly located in the isolation region and does not penetrate through the isolation region; covering the second groove and the second gate insulating layer of the second channel region, the thickness of the second gate insulating layer is different from the thickness of the first gate insulating layer.
  • the semiconductor device further includes a second gate, and the second gate covers the second channel region and fills the second groove.
  • the depth of the second groove in the longitudinal direction perpendicular to the substrate is smaller than the depth of the first groove in the longitudinal direction.
  • the present application also provides a NAND storage device, which includes an electrically connected storage array and peripheral devices, the storage array includes a plurality of memory cell strings, the peripheral device includes: a substrate, and the substrate includes a first An active region and an isolation region located around the first active region, the first active region includes a first source region, a first channel region and a first drain region connected in sequence; The first groove between the channel regions, the first groove part is located in the isolation region, and does not penetrate the isolation region; the first gate insulating layer covering the first groove and the first channel region; located in the first gate The first grid on the pole insulating layer covers the first channel region and fills the first groove.
  • the substrate further includes a second active region, the first active region and the second active region are separated by the isolation region, and the second active region includes a second source region, a second ditch connected in sequence
  • the peripheral device also includes: a second groove located between the isolation region and the second channel region, the second groove is partly located in the isolation region and does not penetrate through the isolation region; covering the second The groove and the second gate insulating layer of the second channel region, the thickness of the second gate insulating layer is different from the thickness of the first gate insulating layer.
  • the peripheral device further includes a second gate, and the second gate covers the second channel region and fills the second groove.
  • the depth of the second groove in the longitudinal direction perpendicular to the substrate is smaller than the depth of the first groove in the longitudinal direction.
  • the memory array further includes: a stacked structure located on peripheral devices, wherein each memory cell string includes a channel layer and a storage function layer running through the stack structure, and the storage function layer is located between the channel layer and the stack structure between.
  • the interconnection layer disposed on the side of the stack structure facing the peripheral device, wherein the memory cell string is electrically connected to the interconnection layer, and the interconnection layer is electrically connected to the substrate in the first source region, the first drain The substrate and/or the first gate in the polar region.
  • the beneficial effects of the present application are: different from the prior art, the semiconductor device and its manufacturing method, and the NAND storage device provided by the present application can increase the effective length of the gate to improve the control of the gate to the transistor channel, and further improve the control of the transistor channel. While the size of the device is reduced, it can improve the saturation current, leakage current and other electrical characteristic parameters of the transistor device, improve the performance of the transistor device, and do not need to etch the gate material layer to form the gate, avoiding the problem of passing through due to the reduction in the size of the transistor device. The process difficulty of etching the gate material layer to form the gate increases, which leads to the problem of increased production cost and reduces the production cost.
  • FIG. 1 is a schematic flow diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application
  • FIG. 2 is a schematic top view of a substrate provided in an embodiment of the present application.
  • Fig. 3 is a schematic cross-sectional structure taken along the line O-O' in Fig. 2;
  • Fig. 4 is a schematic cross-sectional structure taken along the line P-P' in Fig. 2;
  • FIG. 5 is a schematic top view of the structure after step S1223 provided by the embodiment of the present application is completed;
  • Fig. 6 is a schematic cross-sectional structure taken along the line O-O' in Fig. 5;
  • Fig. 7 is a schematic cross-sectional structure taken along the line R-R' in Fig. 5;
  • FIG. 8 is a schematic top view of the structure after step S13 provided by the embodiment of the present application is completed;
  • Fig. 9 is a schematic cross-sectional structure taken along the line O-O' in Fig. 8;
  • Fig. 10 is a schematic cross-sectional structure taken along the line R-R' in Fig. 8;
  • Fig. 11 is another top view structural diagram after step S13 provided by the embodiment of the present application is completed;
  • Fig. 12 is a schematic cross-sectional structure taken along the line O-O' in Fig. 11;
  • Fig. 13 is a schematic cross-sectional structure taken along the line R-R' in Fig. 11;
  • Fig. 14 is another top view structural diagram after step S132 provided by the embodiment of the present application is completed;
  • Fig. 15 is a schematic cross-sectional structure taken along the line O-O' in Fig. 14;
  • Fig. 16 is a schematic cross-sectional structure taken along the line R-R' in Fig. 14;
  • FIG. 17 is a schematic top view of the structure after step S14 provided by the embodiment of the present application is completed;
  • Fig. 18 is a schematic cross-sectional structure taken along the line O-O' in Fig. 17;
  • Fig. 19 is a schematic cross-sectional structure taken along the line R-R' in Fig. 17;
  • FIG. 20 is another schematic flowchart of the method for manufacturing a semiconductor device provided by the embodiment of the present application.
  • Fig. 21 is a top view structural diagram after step S151 provided by the embodiment of the present application is completed;
  • Fig. 22 is a schematic cross-sectional structure taken along the line O-O' in Fig. 21;
  • Fig. 23 is a schematic cross-sectional structure taken along the line R-R' in Fig. 21;
  • Fig. 24 is a schematic top view of the structure after step S152 provided by the embodiment of the present application is completed;
  • Fig. 25 is a schematic cross-sectional structure taken along the line O-O' in Fig. 24;
  • Fig. 26 is a schematic cross-sectional structure taken along the line R-R' in Fig. 24;
  • Fig. 27 is a schematic top view of the structure after step S16 provided by the embodiment of the present application is completed;
  • Fig. 28 is a schematic cross-sectional structure taken along the line O-O' in Fig. 27;
  • Fig. 29 is a schematic cross-sectional structure taken along the line R-R' in Fig. 27;
  • Fig. 30 is another schematic top view of the structure after step S16 provided by the embodiment of the present application is completed;
  • Fig. 31 is a schematic cross-sectional structure taken along the line O-O' in Fig. 30;
  • Fig. 32 is a schematic cross-sectional structure taken along the line R-R' in Fig. 30;
  • Fig. 33 is another top view structural diagram after step S23 provided by the embodiment of the present application is completed;
  • Fig. 34 is a schematic cross-sectional structure taken along the line O-O' in Fig. 33;
  • Fig. 35 is a schematic cross-sectional structure taken along the line R-R' in Fig. 33;
  • FIG. 36 is a schematic cross-sectional structure diagram of a NAND storage device provided by an embodiment of the present application.
  • FIG. 1 is a schematic flow diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application.
  • the specific flow of the method for manufacturing a semiconductor device can be as follows:
  • Step S11 forming a substrate, the substrate includes a first active region and an isolation region located around the first active region, the first active region includes a first source region, a first channel region and a first drain area.
  • the aforementioned semiconductor device may specifically be a semiconductor device having at least one transistor, wherein the transistor may specifically be a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET).
  • MOSFET Metal Oxide Semiconductor Field-Effect Transistor
  • the number of the above-mentioned first active regions may be one or more, and each first active region may correspond to an active region of a transistor in the above-mentioned semiconductor device.
  • the substrate in the first source region, the substrate in the first channel region and the substrate in the first drain region may respectively correspond to the The source, channel, and drain of a transistor.
  • the above-mentioned first active region 212 may be located on the top of the substrate 21, and in the first active region 212, the above-mentioned first source region 2121 and the above-mentioned
  • the first drain region 2123 can be respectively located at opposite ends of the first active region 212 (for example, the opposite ends of the top), and corresponding to the above-mentioned first channel region 2122 can be located in the first source region 212 in the above-mentioned first active region 212.
  • the region between the electrode region 2121 and the first drain region 2123 is not limited to the electrode region 2121 and the first drain region 2123 .
  • the initial active region of the initial substrate can be doped with P-type to form the middle active region, and then the opposite ends of the middle active region can be doped with N-type to form the above-mentioned The first active region 212 .
  • the initial active region of the initial substrate can be doped with N-type to form the middle active region, and then the opposite ends of the middle active region can be doped with P-type to form The above-mentioned first active region 212 .
  • the above-mentioned initial substrate is the substrate 21 before the formation of the first active region 212, and the initial substrate may specifically be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, silicon on insulator (Silicon On Insulator, SOI) substrate or germanium on insulator (Germanium On Insulator, GOI) substrate, etc.
  • a semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, silicon on insulator (Silicon On Insulator, SOI) substrate or germanium on insulator (Germanium On Insulator, GOI) substrate, etc.
  • the isolation region 211 is used to separate the first active region 212 from other structures (for example, other active Regions) are electrically isolated to facilitate subsequent independent control of transistors formed based on the first active region 212 .
  • the multiple first active regions 212 can be arranged at intervals and separated by the above-mentioned isolation regions 211, so as to ensure the active operation of different transistors in the above-mentioned semiconductor device. Galvanic isolation between source regions.
  • both the above-mentioned isolation region 211 and the above-mentioned first active region 212 may be located on the top of the above-mentioned substrate 21, and the depth of the above-mentioned isolation region 211 in the vertical direction Z perpendicular to the substrate 21 is not less than that of the above-mentioned first active region 212 Depth in longitudinal direction Z.
  • the cross-sectional width of the first active region 212 may gradually increase from top to bottom.
  • the cross-sectional shape of the first active region 212 may be positive trapezoidal.
  • Step S12 forming a patterned first hard mask layer on the substrate.
  • the patterned first hard mask layer includes a first opening for exposing the first channel region and part of the isolation region.
  • step S12 may specifically include:
  • Step S1221 sequentially forming a first hard mask layer and a photoresist layer on the substrate.
  • Step S1222 Exposing and developing to pattern the photoresist layer.
  • Step S1223 Etching the first hard mask layer according to the patterned photoresist layer to obtain a patterned hard mask layer.
  • step S1223 is completed are shown in FIG. 5 , FIG. 6 and FIG. 7 .
  • the first opening 24A opened on the patterned first hard mask layer 24 is used to define the gate formation positions of at least some transistors in the semiconductor device.
  • the number of the above-mentioned first openings 24A may also be multiple, and the multiple first openings 24A may correspond to the multiple transistors in the above-mentioned semiconductor device, that is, Each first opening 24A is used to define a gate formation position of a corresponding transistor in the aforementioned semiconductor device.
  • the material of the first hard mask layer 24 may be, but not limited to, silicon nitride, and the shape of the first opening 24A may be a rectangle or an "I" shape.
  • first opening 24A may be used to expose part of the first channel region 2122 of the first active region 212 , or to expose the entire first channel region 2122 of the first active region 212 .
  • the above-mentioned first opening 24A can be used to expose the entire junction region CC where the above-mentioned first channel region 2122 is connected to the above-mentioned isolation region 211, or to expose the part where the above-mentioned first channel region 2122 is connected to the above-mentioned isolation region 211 Junction zone CC.
  • the first opening 24A may expose a part of the first channel region 2122 of the first active region 212 and the entire boundary region CC where the first channel region 2122 of the first active region 212 connects to the isolation region 211 . Furthermore, after the first hard mask layer 24 is etched, the remaining photoresist layer 25 on the first hard mask layer 24 may be removed to obtain the patterned first hard mask layer 24 .
  • Step S13 forming a first groove between the isolation region and the first channel region through the first opening, the first groove is partly located in the isolation region and does not penetrate through the isolation region.
  • FIG. 8 the structural diagrams after the above step S13 is completed are shown in FIG. 8 , FIG. 9 and FIG. 10 .
  • the depth of the first groove 22 in the longitudinal direction Z perpendicular to the substrate 21 may not be greater than the depth of the first channel region 2122 in the longitudinal direction Z, so as to prevent the substrate 21 located below the first channel region 2122 from The exposure of the first groove 22 reduces the influence on the performance of the transistor formed based on the first active region 212 in subsequent steps.
  • step S13 it may also include:
  • Step A forming a shallow trench isolation structure in the shallow trench of the isolation region.
  • the above step S13 may specifically include: forming a first groove between the shallow trench isolation structure and the first channel region through the first opening, the depth of the first groove in the longitudinal direction perpendicular to the substrate is smaller than the shallow trench isolation structure. The depth of the trench isolation structure in the longitudinal direction.
  • the above substrate 21 may include a shallow trench 213 formed in the isolation region 211 and located around the first active region 212 .
  • the shallow trench 213 is used to isolate the first active region 212 from other structures around the first active region 212 , so as to independently control the transistors formed based on the first active region 212 later.
  • the above-mentioned shallow trench 213 can be formed by etching part of the substrate 21 in the above-mentioned isolation region 211, and then an insulating material (for example, silicon oxide) is filled in the shallow trench 213 to obtain the above-mentioned trench.
  • an insulating material for example, silicon oxide
  • the above-mentioned shallow trench 213 may be located on the top of the above-mentioned substrate 21, and the depth of the above-mentioned shallow trench 213 in the vertical direction Z perpendicular to the substrate 21 is not less than the depth of the above-mentioned first active region 212 in the vertical direction Z. on the depth.
  • the sidewall of the shallow trench 213 may be inclined, and the top dimension of the shallow trench 213 may be smaller than the bottom dimension.
  • the sidewall of the STI structure 23 is inclined, and the top size of the STI structure 23 is smaller than the bottom size.
  • the above-mentioned step S13 may specifically include:
  • Step S131 forming a patterned second hard mask layer on the patterned first hard mask layer, the patterned second hard mask layer includes a second opening, the second opening communicates with the first opening, and Part of the shallow trench isolation structure is exposed through the first opening and the second opening.
  • Step S132 Selectively remove the part of the shallow trench isolation structure exposed by the first opening and the second opening to obtain the first groove located between the shallow trench isolation structure and the first channel region, and wherein the pattern The second hard mask layer is used to protect the remaining shallow trench isolation structure from being removed during the process of selectively removing the part of the shallow trench isolation structure exposed by the first opening and the second opening.
  • step S132 is completed are shown in FIG. 14 , FIG. 15 and FIG. 16 .
  • the second opening 30A on the patterned second hard mask layer 30 communicates with the first opening 24A on the patterned first hard mask layer 24, and the above-mentioned shallow trench isolation structure 23 and the above-mentioned first trench
  • the junction area CC where the track area 2122 is connected may be exposed through the first opening 24A and the second opening 30A.
  • the first groove 22 is located at the junction region CC where the shallow trench isolation structure 23 is connected to the first channel region 2122 .
  • the patterned second hard mask layer is used to protect the remaining shallow trench isolation structure 23 during the process of selectively removing the shallow trench isolation structure 23 exposed by the first opening 24A and the second opening. are not removed.
  • the remaining shallow trench isolation structure 23 may include the shallow trench isolation structure 23 exposed by other openings on the patterned first hard mask layer 24 .
  • Step S14 forming a first gate insulating layer covering the first groove and the first channel region.
  • step S14 is completed are shown in FIG. 17 , FIG. 18 and FIG. 19 .
  • the first gate insulating layer 26 is used to electrically isolate the gate and the channel of the transistor formed based on the first active region 212 . Specifically, methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition can be used to deposit on the substrate 21 at least the first groove 22 and the first trench.
  • the first gate insulating layer 26 (for example, a silicon oxide layer) of the channel region 2122 .
  • the first gate insulating layer 26 may also cover the patterned first hard mask layer 24 in addition to covering the inner wall surface of the first groove 22 and the first channel region 2122 .
  • Step S15 forming a first gate in the first opening and the first groove on the first gate insulating layer.
  • step S15 may specifically include:
  • Step S151 depositing a gate material in the first opening and the first groove on the first gate insulating layer.
  • FIG. 21 the structural diagrams after the above step S151 is completed are shown in FIG. 21 , FIG. 22 and FIG. 23 .
  • the first opening 24A will be filled with the gate material 27, and at the same time, the remaining space in the first groove 22 will be filled with the gate material. 27 filling.
  • Step S152 removing the gate material outside the first opening by chemical mechanical polishing to obtain a first gate.
  • FIG. 24 the structural diagrams after the above step S152 is completed are shown in FIG. 24 , FIG. 25 and FIG. 26 .
  • the sacrificial material overflowing the first opening 24A can be removed by chemical mechanical polishing to obtain the gate layer 28 with the first gate 281, and the first gate 281 can have a flat top surface, so that The stability of the structure formed on the first gate 281 in subsequent steps.
  • the first gate insulating layer 26 on the patterned first hard mask layer 24 is also will be removed to expose the top surface of the above-mentioned patterned first hard mask layer 24 .
  • the patterned hard mask layer is used to define the formation position of the gate, that is, the formation position of the gate is defined to be located in the corresponding opening on the patterned hard mask layer, thereby realizing the formation of the gate.
  • Self-alignment Afterwards, the gate is formed by simple and easy-to-implement methods such as deposition and chemical mechanical polishing. Compared with using an etching method to form a gate, the technical solutions of the embodiments of the present application can reduce the difficulty of etching to form a gate due to the reduction in size of transistor devices. Thus, production costs are reduced.
  • Step S16 removing the patterned first hard mask layer.
  • FIG. 27 the structural diagrams after the above step S16 is completed are shown in FIG. 27 , FIG. 28 and FIG. 29 .
  • the patterned first hard mask layer 24 may be removed by an etching method (eg, a wet etching method).
  • an etching method eg, a wet etching method.
  • the first gate insulating layer 26 located around the gate layer 28 may also be removed.
  • the first gate 281 covers the first channel region 2122 of the first active region 212 and fills the first groove between the first channel region 2122 and the isolation region 211 twenty two.
  • the gate of the formed transistor can wrap the channel on the opposite two sides and the top surface of the channel, that is, it is equivalent to increasing the The effective length of the gate or channel in the transistor is conducive to improving the performance of parameters such as the saturation current and leakage current of the transistor.
  • the first source region 2121 , the first channel region 2122 and the first drain region 2123 in the above-mentioned first active region 212 may be linear in the first lateral direction Y parallel to the substrate 21 distribution, and the two side ends of the first gate 281 in the second horizontal direction X parallel to the substrate 21 and perpendicular to the first horizontal direction Y can extend to part of the isolation regions on both sides of the first channel region 2122 211 (for example, part of the shallow trench isolation structure 23).
  • the number of transistors included in the above-mentioned semiconductor device may be multiple, and the multiple transistors may be divided into at least one transistor type (for example, high-voltage transistor type, low-voltage transistor type, and ultra-low-voltage transistor type, etc.), wherein the gate conduction voltage of the high-voltage transistor type transistor is higher than the gate conduction voltage of the low-voltage transistor type transistor, and the gate conduction voltage of the low-voltage transistor type transistor The turn-on voltage is higher than the gate turn-on voltage of the ultra-low voltage transistor type transistor.
  • the multiple transistors may be divided into at least one transistor type (for example, high-voltage transistor type, low-voltage transistor type, and ultra-low-voltage transistor type, etc.)
  • the gate conduction voltage of the high-voltage transistor type transistor is higher than the gate conduction voltage of the low-voltage transistor type transistor
  • the gate conduction voltage of the low-voltage transistor type transistor The turn-on voltage is higher than the gate turn-on voltage of the ultra-low voltage transistor
  • the above-mentioned first active region 212 can be used to form one of the transistor types of transistors (for example, high-voltage transistor type transistors), that is, when the number of the above-mentioned first active regions 212 is multiple, based on The multiple transistors formed by the multiple first active regions 212 belong to the same transistor type.
  • multiple transistors of the same transistor type can be fabricated simultaneously through the above steps S11 to S16, or multiple transistors of the same transistor type can be fabricated through the above steps S11 to S16 one by one or multiple times. .
  • the above-mentioned substrate 21 may further include a second active region 214, and the second active region 214 and the above-mentioned first active region 212 are formed by the above-mentioned
  • the isolation region 211 is separated, and the second active region 214 may include a second source region, a second channel region and a second drain region connected in sequence.
  • the above-mentioned second active region 214 may also correspond to the active region of a transistor in the above-mentioned semiconductor device, and the above-mentioned first active region 212 and the above-mentioned second active region
  • the difference between the source region 214 is that in the above-mentioned semiconductor device, the transistor formed based on the first active region 212 and the transistor formed based on the second active region 214 belong to different transistor types, for example, based on the first active region
  • the transistors formed at 212 may be of high voltage transistor type, while the transistors formed based on the second active region 214 may be of low voltage transistor type.
  • the patterned first hard mask layer 24 may further include a third opening for exposing the second channel region of the second active region 214 and part of the isolation region 211 .
  • step S15 it may further include:
  • Step S17 forming a second groove between the isolation region and the second channel region through the third opening, the second groove is partly located in the isolation region and does not penetrate through the isolation region.
  • the specific implementation manner of the above-mentioned step S17 can refer to the specific implementation manner of the above-mentioned step S13, and only need to replace the first opening, the first channel region and the first groove in the specific implementation manner of the above-mentioned step S13 with the first Three openings, the second channel region and the second groove can obtain the specific implementation manner of the above-mentioned step S17, so it will not be repeated here.
  • Step S18 Forming a second gate insulating layer covering the second groove and the second channel region.
  • the specific implementation manner of the above-mentioned step S18 can refer to the specific implementation manner of the above-mentioned step S14, and it is only necessary to separate the first groove, the first channel region and the first gate insulating layer in the specific implementation manner of the above-mentioned step S14 By replacing the second groove, the second channel region and the second gate insulating layer, the specific implementation manner of the above-mentioned step S18 can be obtained, so details will not be repeated here.
  • the substrate 21 may further include a third active region 215, the third active region 215, the first active region 212 and The second active region 214 is separated by the isolation region 211 , and the third active region 215 may include a third source region, a third channel region and a third drain region connected in sequence.
  • the above-mentioned third active region 215 can also correspond to the active region of a transistor in the above-mentioned semiconductor device, and, similar to the above-mentioned first active region 215
  • the difference between an active region 212 and the above-mentioned second active region 214 is: in the above-mentioned semiconductor device, the transistor formed based on the third active region 215, the transistor formed based on the first active region 212 and the transistor formed based on the second
  • the transistors formed in the active region 214 belong to different transistor types, for example, the transistors formed based on the first active region 212 may belong to the high-voltage transistor type, and the transistors formed based on the second active region 214 may belong to the low-voltage transistor type,
  • the transistors formed based on the third active region 215 may belong to ultra-low voltage transistors.
  • the patterned first hard mask layer 24 may further include a fourth opening, which is used to expose the third channel region of the third active region 215, and the isolation region 211 and the first channel region. The junction region where the three channel regions are connected.
  • the above-mentioned third active region 215 may further include:
  • Step S19 forming a third groove between the isolation region and the third channel region through the fourth opening, the third groove is partly located in the isolation region and does not penetrate through the isolation region.
  • the specific implementation manner of the above-mentioned step S19 can refer to the specific implementation manner of the above-mentioned step S13, and only need to replace the first opening, the first channel region and the first groove in the specific implementation manner of the above-mentioned step S13 with the first Four openings, the third channel region and the third groove can obtain the specific implementation manner of the above-mentioned step S19, so it will not be repeated here.
  • Step S20 forming a third gate insulating layer covering the third groove and the third channel region.
  • the specific implementation manner of the above-mentioned step S20 can refer to the specific implementation manner of the above-mentioned step S14, and it is only necessary to separate the first groove, the first channel region and the first gate insulating layer in the specific implementation manner of the above-mentioned step S14
  • the specific implementation manner of the above step S20 can be obtained by replacing the third groove, the third channel region and the third gate insulating layer, so details will not be repeated here.
  • the above step S17 may specifically include: forming a patterned third hard mask layer on the patterned first hard mask layer 24, the patterned The third hard mask layer includes a fifth opening, the fifth opening communicates with the third opening on the patterned first hard mask layer 24, and the shallow trench isolation structure 23 and the second active region
  • the junction region connected to the second channel region of 214 can be exposed through the third opening and the fifth opening; the shallow trench isolation structure 23 exposed by the third opening and the fifth opening is selectively removed to obtain the The above-mentioned second groove 31 in the boundary area where the shallow trench isolation structure 23 is connected with the above-mentioned second channel region.
  • the patterned third hard mask layer is used to protect the remaining shallow trench isolation structure 23 during the process of selectively removing the shallow trench isolation structure 23 exposed by the third opening and the fifth opening. be removed.
  • the remaining shallow trench isolation structure 23 may include the shallow trench isolation structure 23 exposed by other openings (for example, the first opening 24A and the fourth opening) on the patterned first hard mask layer 24 .
  • the above step S19 may specifically include: forming a patterned fourth hard mask layer on the patterned first hard mask layer 24, the patterned The fourth hard mask layer includes a sixth opening, the sixth opening communicates with the fourth opening on the patterned first hard mask layer 24, and the shallow trench isolation structure 23 is connected to the third active region
  • the junction region connected to the third channel region of 215 can be exposed through the fourth opening and the sixth opening; the shallow trench isolation structure 23 exposed by the fourth opening and the sixth opening is selectively removed to obtain the The above-mentioned third groove 32 in the boundary area where the shallow trench isolation structure 23 is connected with the above-mentioned third channel region.
  • the patterned fourth hard mask layer is used to protect the remaining shallow trench isolation structure 23 during the process of selectively removing the shallow trench isolation structure 23 exposed by the fourth opening and the sixth opening. be removed.
  • the remaining shallow trench isolation structure 23 may include the shallow trench isolation structure 23 exposed by other openings (for example, the first opening 24A and the third opening) on the patterned first hard mask layer 24 .
  • the second groove 31 is vertically
  • the depth H2 in the longitudinal direction Z of the substrate 21 is different from the depth H1 of the first groove 22 in the longitudinal direction Z; and/or, the thickness of the second gate insulating layer 33 is different from that of the first gate insulating layer 26 thickness.
  • the gate turn-on voltage of the transistor formed based on the above-mentioned first active region 212 is greater than the gate turn-on voltage of the transistor formed based on the above-mentioned second active region 214, for example, based on the above-mentioned first active
  • the transistor formed in the region 212 belongs to the high-voltage transistor type
  • the transistor formed based on the above-mentioned second active region 214 belongs to the low-voltage transistor type
  • the depth H2 is smaller than the depth H1 of the first groove 22 in the longitudinal direction Z
  • the thickness of the second gate insulating layer 33 is smaller than the thickness of the first gate insulating layer 26 .
  • the third groove 32 is perpendicular to the substrate
  • the depth H3 of the longitudinal direction Z of 21 is different from the depth H1 of the first groove 22 in the longitudinal direction Z; and/or, the thickness of the third gate insulating layer 34 is different from the thickness of the first gate insulating layer.
  • the third groove 32 is vertically
  • the depth H3 in the longitudinal direction Z of the substrate 21 is different from the depth H2 of the second groove 31 in the longitudinal direction Z; and/or, the thickness of the third gate insulating layer 34 is different from that of the second gate insulating layer 33 thickness.
  • the gate turn-on voltage of the transistor formed based on the above-mentioned first active region 212 may be greater than the gate turn-on voltage of the transistor formed based on the above-mentioned second active region 214, based on the above-mentioned first
  • the gate turn-on voltage of the transistor formed based on the second active region 214 may be greater than the gate turn-on voltage of the transistor formed based on the above-mentioned third active region 215 .
  • the transistor formed based on the above-mentioned first active region 212 may belong to the high-voltage transistor type
  • the transistor formed based on the above-mentioned second active region 214 may belong to the low-voltage transistor type
  • the transistor formed based on the above-mentioned third active region 215 May be of the ultra-low voltage transistor type.
  • the depth H3 of the third groove 32 in the longitudinal direction Z perpendicular to the substrate 21 may be smaller than the depth H2 of the second groove 32 in the longitudinal direction Z, and the second groove 31 is perpendicular to the substrate 21.
  • the depth H2 in the longitudinal direction Z may be smaller than the depth H1 of the first groove 22 in the longitudinal direction Z.
  • the thickness of the third gate insulating layer 34 may be smaller than the thickness of the second gate insulating layer 33, and the thickness of the second gate insulating layer 33 may be smaller than that of the first gate insulating layer 26. thickness.
  • the groove between the channel and the above-mentioned isolation region 211 that is, the above-mentioned first groove 22, second groove 31 or third groove 32 ) is deeper, it is more beneficial to improve the control ability of the gate to the channel of the transistor, thereby improving the performance of the transistor.
  • the first groove 22, the second groove 31 and the third groove 32 may have the same depth in the longitudinal direction Z perpendicular to the substrate 21, and the first groove 22, the second groove
  • the groove 31 and the third groove 32 can be formed through the same process (for example, one etching process). That is, the above-mentioned step S13 , step S17 and step S19 may be the same etching process step, so that the above-mentioned first groove 22 , second groove 31 and third groove 32 can be formed by one-step etching.
  • the first gate insulating layer 26, the second gate insulating layer 33 and the third gate insulating layer 34 have the same thickness, then the first gate insulating layer 26 , The second gate insulating layer 33 and the third gate insulating layer 34 can also be formed through the same process (for example, one deposition process). That is, the above-mentioned step S14, step S18 and step S20 may be the same deposition process step, so that the above-mentioned first gate insulating layer 26, second gate insulating layer 33 and third gate insulating layer 34 can be formed by one-step deposition .
  • the first gate insulating layer 33 and the third gate insulating layer 34 can be gradually formed in the order of gradually decreasing thickness.
  • the first groove 22, the second groove 31 and the third groove 32 can be gradually formed in the order of decreasing depth. groove 31 and a third groove 32 .
  • step S12, step S13, step S15, step S16, step S17 and step S18 can be executed sequentially , forming the first groove 22 , the first gate insulating layer 26 , the second groove 31 , the second gate insulating layer 33 , the third groove 32 and the third gate insulating layer 34 step by step.
  • step S18 it may further include:
  • the specific implementation manner of the above-mentioned step S21 can refer to the specific implementation manner of the above-mentioned step S15, and only the first gate insulating layer, the first opening, the first groove and the first The gate is replaced by the second gate insulating layer, the third opening, the second groove and the second gate, respectively, so that the specific implementation manner of the above step S21 can be obtained, so it will not be repeated here.
  • step S20 it may also include:
  • the specific implementation manner of the above-mentioned step S22 can refer to the specific implementation manner of the above-mentioned step S15, and only the first gate insulating layer, the first opening, the first groove and the first The gates are respectively replaced with the third gate insulating layer, the fourth opening, the third groove and the third gate, and the specific implementation manner of the above-mentioned step S22 can be obtained, so details will not be repeated here.
  • FIG. 30 the structural diagram after the above step S22 is completed can be shown in FIG. 30 , FIG. 31 and FIG. 32 , where the first gate 281 , the second gate 282 and the third gate 283 are separated and insulated.
  • the second gate 282 covers the second channel region and fills the second groove 31 between the isolation region 211 and the second channel region.
  • the third gate 283 covers the third channel region and fills the third groove 32 between the isolation region 211 and the third channel region.
  • the gates (for example, the first gate 281, the second gate 282, and the third gate 283) of different transistors in the above-mentioned semiconductor device can be formed by the same process, or can be formed by multiple processes. .
  • the first gate 281 , the second gate 282 and the third gate 283 can be formed through the same process. That is, the above-mentioned step S15, step S21 and step S22 may be the same process step, so that the above-mentioned gate layer 28 including the first gate 281, the second gate 282 and the third gate 283 can be formed through one process step .
  • transistors with gate insulating layers of different thicknesses, and grooves between the channel and the above-mentioned isolation region 211 have transistors with different depths, which can meet the diversification requirements of transistors with different operating voltages on the thickness of the gate insulating layer and the contact area between the gate and the side of the channel in the semiconductor device. .
  • the above-mentioned semiconductor device may specifically be a peripheral circuit chip of a memory (for example, 3D NAND memory), and multiple transistors may be integrated in the peripheral circuit chip, and the multiple transistors may belong to different transistor types.
  • a memory for example, 3D NAND memory
  • the method for manufacturing the above-mentioned semiconductor device may further include:
  • Step S23 forming spacers on the side surfaces of the first gate.
  • step S23 is completed are shown in FIG. 33 , FIG. 34 and FIG. 35 .
  • the side surfaces (for example, front, rear, left, and right four side surfaces) of each gate (for example, the first gate 281 , the second gate 281 and the third gate 281 ) of the gate layer 28 ), the above-mentioned sidewall 35 is formed by sequentially adopting a deposition process and an etching process.
  • the material of the side wall can be insulating material such as silicon oxide, and the side wall 35 is used to protect the above gate, and can reduce the hot carrier injection (Hot Carrier Injection, HCI) effect.
  • the above-mentioned semiconductor device may include high-voltage transistor-type transistors, low-voltage transistor-type transistors, and ultra-low-voltage transistor-type transistors at the same time, and the specific process of forming the semiconductor device may be as follows:
  • Step S1-1 forming a substrate, the substrate includes a first active region, a second active region, a third active region and an isolation region, and the isolation region combines the first active region, the second active region and the third active region
  • the active regions are separated, and the first active region includes a first source region, a first channel region and a first drain region connected in sequence, and the second active region includes a second source region, a first drain region connected in sequence.
  • the third active region includes a third source region, a third channel region and a third drain region connected in sequence.
  • Step S1-2 forming a patterned first hard mask layer on the substrate, the patterned first hard mask layer includes a first opening, a third opening and a fourth opening, the first opening is used to expose the first The channel region and part of the isolation region, the third opening is used to expose the second channel region and part of the isolation region, and the fourth opening is used to expose the third channel region and part of the isolation region.
  • Step S1-3 forming a first groove between the isolation region and the first channel region through the first opening, the first groove is partly located in the isolation region and does not penetrate through the isolation region.
  • Step S1-4 forming a first gate insulating layer covering the first groove and the first channel region.
  • Step S1-5 forming a second groove between the isolation region and the second channel region through the third opening, the second groove is partly located in the isolation region and does not penetrate through the isolation region.
  • Step S1-6 forming a second gate insulating layer covering the second groove and the second channel region.
  • Step S1-7 forming a third groove between the isolation region and the third channel region through the fourth opening, the third groove is partly located in the isolation region and does not penetrate through the isolation region.
  • Step S1-8 forming a third gate insulating layer covering the third groove and the third channel region.
  • Step S1-9 forming the first gate in the first opening and the first groove on the first gate insulating layer, forming the second gate in the third opening and the second groove on the second gate insulating layer A gate, and a third gate is formed in the fourth opening and the third groove on the third gate insulating layer.
  • Step S1-10 removing the patterned first hard mask layer.
  • Step S1-11 forming sidewalls on the side surfaces of the first gate, the side surfaces of the second gate, and the side surfaces of the third gate.
  • first active region, the second active region and the third active region may have different sizes, for example, the cross-sectional area of the first active region, the cross-sectional area of the second active region and the third active region
  • the cross-sectional area of the source region may decrease sequentially.
  • first groove, the second groove and the third groove may have different depths, for example, the depth of the first groove, the depth of the second groove and the depth of the third groove may decrease sequentially.
  • the first gate insulating layer, the second gate insulating layer and the third gate insulating layer may have different thicknesses, for example, the thickness of the first gate insulating layer, the thickness of the second gate insulating layer and the thickness of the third gate insulating layer The thickness of the gate insulating layer may be sequentially reduced.
  • the specific implementation manner of the above step S1-1 can refer to the specific implementation manner of the above step S11
  • the specific implementation manner of the above step S1-2 can refer to the specific implementation manner of the above step S12
  • the specific implementation manner of the above step S1-3 please refer to the specific implementation mode of the above-mentioned step S13, for the specific implementation mode of the above-mentioned step S1-4, please refer to the specific implementation mode for the above-mentioned step S14, for the specific implementation mode of the above-mentioned step S1-5, please refer to the specific implementation mode for the above-mentioned step S17
  • the specific implementation of the above step S1-6 please refer to the specific implementation of the above step S18, for the specific implementation of the above step S1-7, please refer to the specific implementation of the above step S19, for the specific implementation of the above step S1-8, please refer to the above For the specific implementation of step S20, the specific implementation of the above-mentioned steps S1-9 can refer
  • the manufacturing method of the semiconductor device in this embodiment by forming a substrate, the substrate includes a first active region and an isolation region located around the first active region, and the first active region includes sequentially connected The first source region, the first channel region and the first drain region, and a patterned first hard mask layer is formed on the substrate, the patterned first hard mask layer includes a first opening, the first An opening is used to expose the first channel region and part of the isolation region, and then a first groove is formed between the isolation region and the first channel region through the first opening, the first groove is partially located in the isolation region, and does not penetrating through the isolation region, and then forming a first gate insulating layer covering the first groove and the first channel region, and forming a first gate in the first opening and the first groove on the first gate insulating layer; Then remove the patterned first hard mask layer, so that the effective length of the gate can be increased to improve the control of the gate to the transistor channel, and then the saturation current and leakage of the transistor device can be improved while
  • the current and other electrical characteristic parameters improve the performance of the transistor device, and there is no need to form the gate by etching the gate material layer, which avoids the increase in the process difficulty of forming the gate by etching the gate material layer due to the reduction in the size of the transistor device. And then cause the problem that production cost increases, reduce production cost.
  • the semiconductor device manufactured according to the above-mentioned method embodiment of the present application is shown in FIG. 27 , FIG. 28 and FIG. 29 .
  • the semiconductor device includes: a substrate 21 including a first active region 212 and a The isolation region 211 around the region 212, the first active region 212 includes a first source region 2121, a first channel region 2122 and a first drain region 2123 connected in sequence; between the isolation region 211 and the first channel region 2122 Between the first groove 22, the first groove 22 is partly located in the isolation region 211, and does not penetrate the isolation region 211; the first gate insulating layer 26 covering the first groove 22 and the first channel region 2122; The first gate 281 on the first gate insulating layer 26 covers the first channel region 2122 and fills the first groove 22 .
  • the above-mentioned substrate 21 may further include a second active region 214, and the first active region 212 and the second active region 214 are separated by the above-mentioned isolation region. 211 , and the second active region 214 includes a second source region, a second channel region and a second drain region connected in sequence.
  • the above-mentioned semiconductor device may further include a second groove 31 located between the above-mentioned isolation region 211 and the above-mentioned second channel region, and the second groove 31 is partially located in the above-mentioned isolation region 211 and does not penetrate through the isolation region 211 .
  • the above-mentioned semiconductor device further includes a second gate insulating layer 33 covering the above-mentioned second groove 31 and the above-mentioned second channel region.
  • the thickness of the second gate insulating layer 33 is different from that of the first gate insulating layer 26 , for example, the thickness of the second gate insulating layer 33 may be smaller than the thickness of the first gate insulating layer 26 .
  • the above-mentioned semiconductor device may further include a second gate 282 covering the above-mentioned second channel region and the above-mentioned second groove 31 .
  • the depth of the second groove 31 in the longitudinal direction Z perpendicular to the substrate 21 is smaller than the depth of the first groove 22 in the longitudinal direction Z.
  • the above-mentioned substrate 21 may further include a shallow trench disposed in the isolation region 211 and located around the first active region 212 .
  • the aforementioned peripheral device 200 may further include a shallow trench isolation structure 23 located in the shallow trench.
  • the above-mentioned first groove 22 may be specifically located between the shallow trench isolation structure 23 and the first channel region, and the depth of the first groove 22 in the longitudinal direction Z perpendicular to the substrate 21 may be smaller than that of the shallow trench isolation structure. 23 Depth in longitudinal direction Z.
  • the above-mentioned semiconductor device may further include spacers disposed on the side surfaces of the first gate 281 .
  • the semiconductor device provided by this embodiment improves the control of the gate to the transistor channel by increasing the effective length of the gate, so that the saturation current, Electrical characteristic parameters such as leakage current improve the performance of transistor devices, and there is no need to etch the gate material layer to form the gate, which avoids the increased process difficulty of forming the gate by etching the gate material layer due to the reduction in the size of the transistor device , which in turn leads to the problem of increased production costs and reduces production costs.
  • FIG. 36 is a schematic structural diagram of a NAND storage device provided by an embodiment of the present application.
  • the NAND memory device may include an electrically connected memory array 100 and a peripheral device 200, wherein the memory array 100 may include a plurality of memory cell strings 101, and the peripheral device 200 may include the semiconductor in any of the above-mentioned embodiments. device.
  • the above-mentioned peripheral device 200 may include: a substrate 21, the substrate 21 includes a first active region 212 and an isolation region 211 located around the first active region 212, the first active region 212 includes sequentially connected first The source region, the first channel region and the first drain region; the first groove 22 located between the isolation region 211 and the first channel region, the first groove 22 is partly located in the isolation region 211 and does not penetrate through The isolation region 211; the first gate insulating layer 26 covering the first groove 22 and the first channel region 2122; the first gate 281 located on the first gate insulating layer 26, the first gate 281 covering the first The channel region 2122 fills the first groove 22 .
  • the above-mentioned first groove 22 may be located between the isolation region 211 and the first active region 212 and surround the first active region 212 .
  • the substrate 21 may further include a second active region 214, the first active region 212 and the second active region 214 are separated by the isolation region 211, and the second active region 214 It includes a second source region, a second channel region and a second drain region connected in sequence.
  • the peripheral device 200 may further include a second groove 31 located between the isolation region 211 and the second channel region, the second groove 31 is partially located in the isolation region 211 and does not penetrate through the isolation region 211 . Further, the peripheral device 200 further includes a second gate insulating layer 33 covering the second groove 31 and the second channel region. Wherein, the thickness of the second gate insulating layer 33 is different from that of the first gate insulating layer 26 , for example, the thickness of the second gate insulating layer 33 may be smaller than the thickness of the first gate insulating layer 26 .
  • the above-mentioned peripheral device 200 may further include a second gate 282, the second gate 282 covers the above-mentioned second channel region, and fills the gap between the above-mentioned isolation region 211 and the above-mentioned second channel region.
  • the second groove 31 may further include a second gate 282 covers the above-mentioned second channel region, and fills the gap between the above-mentioned isolation region 211 and the above-mentioned second channel region.
  • the depth of the second groove 31 in the longitudinal direction Z perpendicular to the substrate 21 is smaller than the depth of the first groove 22 in the longitudinal direction Z.
  • the aforementioned substrate 21 may further include a shallow trench disposed in the isolation region 211 and located around the first active region 212 .
  • the aforementioned peripheral device 200 may further include a shallow trench isolation structure 23 located in the shallow trench.
  • the above-mentioned first groove 22 may be specifically located between the shallow trench isolation structure 23 and the first channel region, and the depth of the first groove 22 in the longitudinal direction Z perpendicular to the substrate 21 may be smaller than that of the shallow trench isolation structure. 23 Depth in longitudinal direction Z.
  • the aforementioned peripheral device 200 may further include a spacer 35 disposed on a side surface of the first gate 281 .
  • peripheral device 200 for each structure of the peripheral device 200 in this embodiment, reference may be made to the specific implementation manners described in the foregoing semiconductor device embodiments, so details are not repeated here.
  • the memory array 100 may further include: a stacked structure 102 located on the peripheral device 200, wherein each memory cell string 101 includes a channel layer and a storage function layer running through the stacked structure 102, and the storage The functional layer is located between the channel layer and the stacked structure.
  • the above-mentioned stacked structure 102 may include several layers of gate layers 1021 and gate insulating layers 1022 arranged alternately in the longitudinal direction Z.
  • the above-mentioned memory array 100 may further include an interconnection layer 104 disposed on the side of the stack structure 102 facing the peripheral device 200, wherein the memory cell string 101 is electrically connected to the interconnection layer 104, and the interconnection The layer 104 may be electrically connected to the substrate 21 in the first source region, the substrate 21 in the first drain region and/or the first gate 281 of the peripheral device 200 described above.
  • the memory array 100 may further include an interlayer dielectric layer disposed between the stack structure 102 and the interconnection layer 104 , and a plurality of conductive contacts 103 formed in the interlayer dielectric layer.
  • the plurality of conductive contacts 103 may include bit line contacts, the bit line contacts may extend in the longitudinal direction Z, and one end thereof is electrically connected to the memory cell string 101 , and the other end thereof is electrically connected to the interconnection layer 104 .
  • the NAND memory device cited in this embodiment is an example of a wafer bonding (Wafer bonding) architecture in which peripheral devices and memory arrays are bonded
  • the above-mentioned NAND memory device can also be Other possible NAND architectures, such as peripheral circuit devices under the array (periphery under core array, PUC) architecture, peripheral circuit devices next to the array (periphery near core array, PNC) architecture, etc., the embodiment of the present application does not do this Specific limits.
  • the NAND storage device improves the control of the gate to the transistor channel by increasing the effective length of the gate, so that the saturation current of the transistor device can be improved while the size of the transistor device is reduced , leakage current and other electrical characteristic parameters, improve the performance of the transistor device, and do not need to form the gate by etching the gate material layer, avoiding the process difficulty of forming the gate by etching the gate material layer due to the reduction in the size of the transistor device Large, which in turn leads to the problem of increased production costs and reduces production costs.

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Abstract

公开一种半导体器件及其制作方法、NAND存储器件，包括：形成衬底；在衬底上形成图案化的第一硬掩模层；通过第一硬掩模层上的第一开口在隔离区和第一沟道区之间形成第一凹槽；形成覆盖第一凹槽和第一沟道区的第一栅极绝缘层；在第一栅极绝缘层上于第一开口和第一凹槽中形成第一栅极；去除图案化的第一硬掩模层。

Description

半导体器件及其制作方法、NAND存储器件 技术领域
本申请涉及半导体器件技术领域，具体涉及一种半导体器件及其制作方法、NAND存储器件。
背景技术
随着技术的发展，半导体工业不断寻找新的生产方式，以使得存储器件中的每一存储器裸片具有更多数量的存储器单元。其中，3D NAND(三维与非门)存储器件由于其存储密度高、成本低等优点，已成为目前较为前沿、且极具发展潜力的存储器技术。
目前，为了提高3D NAND存储器件的存储密度和容量，一般通过垂直堆叠多层存储单元的方式来实现在更小的空间内容纳更高的存储容量。然而，随着3D NAND存储器件中堆叠层数的增加，对CMOS(Complementary Metal-Oxide Semiconductor，互补性氧化金属半导体)工艺要求越来越高，特别是尺寸缩小方面。
因此，如何在晶体管器件尺寸缩小的同时，提高晶体管器件的性能，并降低晶体管器件的制造工艺难度，是目前亟需解决的问题。
技术问题
本申请提供了一种半导体器件及其制作方法、NAND存储器件，以解决如何在晶体管器件尺寸缩小的同时，提高晶体管器件的性能，并降低晶体管器件的制造工艺难度的问题。
技术解决方案
为了解决上述问题，本申请提供了一种半导体器件的制作方法，该半导体器件的制作方法包括：形成衬底，衬底包括第一有源区以及位于第一有源区周边的隔离区，第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区；在衬底上形成图案化的第一硬掩模层，图案化的第一硬掩模层包括第一开口，第一开口用于露出第一沟道区、以及部分隔离区；通过第一开口在隔离区与第一沟道区之间形成第一凹槽，第一凹槽部分位于隔离区 中，且不贯穿隔离区；形成覆盖第一凹槽和第一沟道区的第一栅极绝缘层；在第一栅极绝缘层上于第一开口和第一凹槽中形成第一栅极；去除图案化的第一硬掩模层。
其中，在第一栅极绝缘层上于第一开口和第一凹槽中形成第一栅极，具体包括：在第一栅极绝缘层上于第一开口和第一凹槽中沉积栅极材料；通过化学机械抛光去除位于第一开口外部的栅极材料，以得到第一栅极。
其中，衬底还包括形成于隔离区且位于第一有源区周边的浅沟槽，在衬底上形成图案化的第一硬掩模层之前，还包括：在隔离区的浅沟槽中形成浅沟槽隔离结构；通过第一开口在隔离区与第一沟道区之间形成第一凹槽，具体包括：通过第一开口在浅沟槽隔离结构与第一沟道区之间形成第一凹槽，第一凹槽在垂直于衬底的纵向上的深度小于浅沟槽隔离结构在纵向上的深度。
其中，通过第一开口在浅沟槽隔离结构与第一沟道区之间形成第一凹槽，具体包括：在图案化的第一硬掩模层上形成图案化的第二硬掩模层，图案化的第二硬掩模层包括第二开口，第二开口与第一开口相连通，且部分浅沟槽隔离结构通过第一开口和第二开口暴露出来；选择性地去除第一开口和第二开口暴露出来的部分浅沟槽隔离结构，以得到位于浅沟槽隔离结构与第一沟道区之间的第一凹槽，且其中，图案化的第二硬掩模层用于在选择性地去除第一开口和第二开口暴露出来的部分浅沟槽隔离结构的过程中，保护剩余浅沟槽隔离结构不被去除。
其中，衬底还包括第二有源区，第一有源区和第二有源区由隔离区分隔开，且第二有源区包括依次连接的第二源极区、第二沟道区和第二漏极区，图案化的第一硬掩模层还包括第三开口，第三开口用于露出第二沟道区、以及部分隔离区，在第一栅极绝缘层上于第一开口和第一凹槽中形成第一栅极之前，还包括：通过第三开口在隔离区与第二沟道区之间形成第二凹槽，第二凹槽部分位于隔离区中，且不贯穿隔离区；形成覆盖第二凹槽和第二沟道区的第二栅极绝缘层，第二栅极绝缘层的厚度与第一栅极绝缘层的厚度不同。
其中，在形成覆盖第二凹槽和第二沟道区的第二栅极绝缘层之后，还包括：在第二栅极绝缘层上于第三开口和第二凹槽中形成第二栅极。
其中，第二凹槽在垂直于衬底的纵向上的深度小于第一凹槽在纵向上的深度。
其中，在去除图案化的第一硬掩模层之后，还包括：在第一栅极的侧表面上形成侧墙。
为了解决上述问题，本申请还提供了一种半导体器件，该半导体器件包括：衬底，衬底包括第一有源区以及位于第一有源区周边的隔离区，第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区；位于在隔离区与第一沟道区之间的第一凹槽，第一凹槽部分位于隔离区中，且不贯穿隔离区；覆盖第一凹槽和第一沟道区的第一栅极绝缘层；位于第一栅极绝缘层上的第一栅极，第一栅极覆盖第一沟道区，且填充第一凹槽。
其中，衬底还包括第二有源区，第一有源区和第二有源区由隔离区分隔开，且第二有源区包括依次连接的第二源极区、第二沟道区和第二漏极区，半导体器件还包括：位于隔离区与第二沟道区之间的第二凹槽，第二凹槽部分位于隔离区中，且不贯穿隔离区；覆盖第二凹槽和第二沟道区的第二栅极绝缘层，第二栅极绝缘层的厚度与第一栅极绝缘层的厚度不同。
其中，半导体器件还包括第二栅极，第二栅极覆盖第二沟道区，且填充第二凹槽。
其中，第二凹槽在垂直于衬底的纵向上的深度小于第一凹槽在纵向上的深度。
为了解决上述问题，本申请还提供了一种NAND存储器件，该NAND存储器件包括电连接的存储阵列和外围器件，存储阵列包括多个存储单元串，外围器件包括：衬底，衬底包括第一有源区以及位于第一有源区周边的隔离区，第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区；位于在隔离区与第一沟道区之间的第一凹槽，第一凹槽部分位于隔离区中，且不贯穿隔离区；覆盖第一凹槽和第一沟道区的第一栅极绝缘层；位于第 一栅极绝缘层上的第一栅极，第一栅极覆盖第一沟道区，且填充第一凹槽。
其中，衬底还包括第二有源区，第一有源区和第二有源区由所述隔离区分隔开，且第二有源区包括依次连接的第二源极区、第二沟道区和第二漏极区，外围器件还包括：位于隔离区与第二沟道区之间的第二凹槽，第二凹槽部分位于隔离区中，且不贯穿隔离区；覆盖第二凹槽和第二沟道区的第二栅极绝缘层，第二栅极绝缘层的厚度与第一栅极绝缘层的厚度不同。
其中，外围器件还包括第二栅极，第二栅极覆盖第二沟道区，且填充第二凹槽。
其中，第二凹槽在垂直于衬底的纵向上的深度小于第一凹槽在纵向上的深度。
其中，存储阵列还包括：位于外围器件上的叠层结构，其中，每个存储单元串包括贯穿叠层结构的沟道层和存储功能层，且存储功能层位于沟道层和叠层结构之间。
其中，设于堆叠结构朝向外围器件的一侧上的互连层，其中，存储单元串与互连层电连接，且互连层电连接至第一源极区中的衬底、第一漏极区中的衬底和/或第一栅极。
有益效果
本申请的有益效果是：区别于现有技术，本申请提供的半导体器件及其制作方法、NAND存储器件，能够增大栅极有效长度，以改进栅极对晶体管沟道的控制，进而在晶体管器件尺寸缩小的同时，能够改善晶体管器件的饱和电流、漏电电流等电特性参数，提高晶体管器件的性能，并且无需通过刻蚀栅极材料层形成栅极，避免了由于晶体管器件尺寸缩小而导致通过刻蚀栅极材料层形成栅极的工艺难度增大，进而导致生产成本增高的问题，降低了生产成本。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面 描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的半导体器件的制作方法的流程示意图；
图2是本申请实施例提供的衬底的俯视结构示意图；
图3是沿图2中的线O-O’截取的截面结构示意图；
图4是沿图2中的线P-P’截取的截面结构示意图；
图5是本申请实施例提供的步骤S1223完成后的俯视结构示意图；
图6是沿图5中的线O-O’截取的截面结构示意图；
图7是沿图5中的线R-R’截取的截面结构示意图；
图8是本申请实施例提供的步骤S13完成后的俯视结构示意图；
图9是沿图8中的线O-O’截取的截面结构示意图；
图10是沿图8中的线R-R’截取的截面结构示意图；
图11是本申请实施例提供的步骤S13完成后的另一俯视结构示意图；
图12是沿图11中的线O-O’截取的截面结构示意图；
图13是沿图11中的线R-R’截取的截面结构示意图；
图14是本申请实施例提供的步骤S132完成后的另一俯视结构示意图；
图15是沿图14中的线O-O’截取的截面结构示意图；
图16是沿图14中的线R-R’截取的截面结构示意图；
图17是本申请实施例提供的步骤S14完成后的俯视结构示意图；
图18是沿图17中的线O-O’截取的截面结构示意图；
图19是沿图17中的线R-R’截取的截面结构示意图；
图20是本申请实施例提供的半导体器件的制作方法的另一流程示意图；
图21是本申请实施例提供的步骤S151完成后的俯视结构示 意图；
图22是沿图21中的线O-O’截取的截面结构示意图；
图23是沿图21中的线R-R’截取的截面结构示意图；
图24是本申请实施例提供的步骤S152完成后的俯视结构示意图；
图25是沿图24中的线O-O’截取的截面结构示意图；
图26是沿图24中的线R-R’截取的截面结构示意图；
图27是本申请实施例提供的步骤S16完成后的俯视结构示意图；
图28是沿图27中的线O-O’截取的截面结构示意图；
图29是沿图27中的线R-R’截取的截面结构示意图；
图30是本申请实施例提供的步骤S16完成后的另一俯视结构示意图；
图31是沿图30中的线O-O’截取的截面结构示意图；
图32是沿图30中的线R-R’截取的截面结构示意图；
图33是本申请实施例提供的步骤S23完成后的另一俯视结构示意图；
图34是沿图33中的线O-O’截取的截面结构示意图；
图35是沿图33中的线R-R’截取的截面结构示意图；
图36是本申请实施例提供的NAND存储器件的剖面结构示意图。
本申请的实施方式
下面结合附图和实施例，对本申请作进一步的详细描述。特别指出的是，以下实施例仅用于说明本申请，但不对本申请的范围进行限定。同样的，以下实施例仅为本申请的部分实施例而非全部实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
另外，本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制 本申请。在各个附图中，结构相似的单元采用相同的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，附图中可能未示出某些公知的部分。
本申请可以各种形式呈现，以下将描述其中一些示例。
请参阅图1，图1是本申请实施例提供的半导体器件的制作方法的流程示意图，该半导体器件的制作方法具体流程可以如下：
步骤S11：形成衬底，衬底包括第一有源区以及位于第一有源区周边的隔离区，第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区。
在本实施例中，上述半导体器件可以具体为具有至少一个晶体管的半导体器件，其中，晶体管可以具体为金属氧化物半导体场效应晶体管(MetalOxide Semiconductor Field-Effect Transistor，MOSFET)。具体地，上述第一有源区的数量可以为一个或多个，且每一第一有源区可以对应为上述半导体器件中一个晶体管的有源区。相应地，在每一第一有源区中，第一源极区中的衬底、第一沟道区中的衬底和第一漏极区中的衬底可以分别对应为上述半导体器件中一个晶体管的源极、沟道和漏极。
具体地，如图2、图3和图4所示，上述第一有源区212可以位于衬底21的顶部，且在该第一有源区212中，上述第一源极区2121和上述第一漏极区2123可以分别位于第一有源区212的相对两端(比如，顶部相对两端)，对应上述第一沟道区2122可以为上述第一有源区212中位于第一源极区2121和第一漏极区2123之间的区域。
并且，具体实施时，可以通过对初始衬底的初始有源区进行P型掺杂，以形成中间有源区，然后对该中间有源区的相对两端进行N型掺杂，以形成上述第一有源区212。在其他实施例中，还可以通过对初始衬底的初始有源区进行N型掺杂，以形成中间有源区，然后对该中间有源区的相对两端进行P型掺杂，以形成上述第一有源区212。其中，上述初始衬底为形成第一有源区212之前的衬底21，且该初始衬底可以具体为半导体衬底，例如可以为硅(Si)衬底、锗(Ge)衬底、SiGe衬底、绝缘体上硅(Silicon  On Insulator，SOI)衬底或绝缘体上锗(Germanium On Insulator，GOI)衬底等。
在本实施例中，如图2、图3和图4所示，上述隔离区211用于将第一有源区212与位于该第一有源区212周边的其他结构(比如，其他有源区)电隔离开，以便于后续对基于该第一有源区212所形成的晶体管进行独立控制。并且，当上述第一有源区212的数量为多个时，该多个第一有源区212可以间隔设置，并被上述隔离区211分隔开，以确保上述半导体器件中不同晶体管的有源区之间的电隔离。
具体地，上述隔离区211和上述第一有源区212可以均位于上述衬底21的顶部，且上述隔离区211在垂直于衬底21的纵向Z上的深度不小于上述第一有源区212在纵向Z上的深度。在一些实施例中，如图3和图4所示，上述第一有源区212的截面宽度由上至下可以逐渐增大，具体地，该第一有源区212的截面形状可以为正梯形。
步骤S12：在衬底上形成图案化的第一硬掩模层，图案化的第一硬掩模层包括第一开口，第一开口用于露出第一沟道区、以及部分隔离区。
其中，上述步骤S12可以具体包括：
步骤S1221：在衬底上依次形成第一硬掩膜层和光刻胶层。
步骤S1222：进行曝光显影，以图案化光刻胶层。
步骤S1223：根据图案化的光刻胶层刻蚀第一硬掩膜层，得到图案化的硬掩膜层。
其中，步骤S1223完成后的结构示意图如图5、图6和图7所示。
上述图案化的第一硬掩膜层24上所开设的第一开口24A用于定义上述半导体器件中至少部分晶体管的栅极形成位置。当上述半导体器件中集成有多个晶体管时，上述第一开口24A的数量也可以为多个，且该多个第一开口24A可以与上述半导体器件中的多个晶体管一一对应，也即，每一第一开口24A用于定义上述半导体器件中其对应的一个晶体管的栅极形成位置。其中，上述 第一硬掩膜层24的材质可以但不限于为氮化硅，上述第一开口24A的形状可以为矩形或“工”字形等形状。
可以理解的是，上述第一开口24A可以用于露出上述第一有源区212的部分第一沟道区2122，或者用于露出上述第一有源区212的全部第一沟道区2122。同理，上述第一开口24A可以用于露出上述第一沟道区2122与上述隔离区211连接的全部交界区CC，或者用于露出上述第一沟道区2122与上述隔离区211连接的部分交界区CC。例如，上述第一开口24A可以露出上述第一有源区212的部分第一沟道区2122以及上述第一有源区212的第一沟道区2122与上述隔离区211连接的全部交界区CC。并且，在刻蚀完上述第一硬掩膜层24之后，可以去除该第一硬掩膜层24上剩余的光刻胶层25，以得到上述图案化的第一硬掩膜层24。
步骤S13：通过第一开口在隔离区与第一沟道区之间形成第一凹槽，第一凹槽部分位于隔离区中，且不贯穿隔离区。
其中，上述步骤S13完成后的结构示意图如图8、图9和图10所示。
上述第一凹槽22在垂直于衬底21的纵向Z上的深度可以不大于上述第一沟道区2122在纵向Z上的深度，以避免位于该第一沟道区2122下方的衬底21通过上述第一凹槽22暴露出来，进而减少影响后续步骤中基于上述第一有源区212所形成的晶体管的性能。
在一个具体实施例中，在上述步骤S13之前，还可以包括：
步骤A：在隔离区的浅沟槽中形成浅沟槽隔离结构。
相应地，上述步骤S13可以具体为：通过第一开口在浅沟槽隔离结构与第一沟道区之间形成第一凹槽，第一凹槽在垂直于衬底的纵向上的深度小于浅沟槽隔离结构在纵向上的深度。
具体地，上述步骤S13完成后的结构示意图如图11、图12和图13所示。上述衬底21可以包括形成于隔离区211且位于第一有源区212周边的浅沟槽213。该浅沟槽213用于将第一有源区212与位于第一有源区212周边的其他结构隔离开，以便于后续对基于该第一有源区212所形成的晶体管进行独立控制。
并且，具体实施时，可以通过刻蚀上述隔离区211中的部分衬底21，形成上述浅沟槽213，然后在该浅沟槽213中填充绝缘材料(比如，氧化硅)，以得到上述沟槽隔离结构23。
在一些实施例中，上述浅沟槽213可以位于上述衬底21的顶部，且上述浅沟槽213在垂直于衬底21的纵向Z上的深度不小于上述第一有源区212在纵向Z上的深度。
在一些具体实施例中，如图11、图12和图13所示，上述浅沟槽213的侧壁可以为斜面，且该浅沟槽213的顶部尺寸可以大于其底部尺寸小。相应地，上述浅沟槽隔离结构23的侧壁也会为斜面，且该浅沟槽隔离结构23的顶部尺寸也会大于其底部尺寸小。
在一个具体实施例中，为了形成上述第一凹槽22，上述步骤S13可以具体包括：
步骤S131：在图案化的第一硬掩模层上形成图案化的第二硬掩模层，图案化的第二硬掩模层包括第二开口，第二开口与第一开口相连通，且部分浅沟槽隔离结构通过第一开口和第二开口暴露出来。
步骤S132：选择性地去除第一开口和第二开口暴露出来的部分浅沟槽隔离结构，以得到位于浅沟槽隔离结构与第一沟道区之间的第一凹槽，且其中，图案化的第二硬掩模层用于在选择性地去除第一开口和第二开口暴露出来的部分浅沟槽隔离结构的过程中，保护剩余浅沟槽隔离结构不被去除。
其中，步骤S132完成后的结构示意图如图14、图15和图16所示。
图案化的第二硬掩模层30上的第二开口30A与上述图案化的第一硬掩模层24上的第一开口24A相连通，且上述浅沟槽隔离结构23与上述第一沟道区2122连接的交界区CC可以通过上述第一开口24A和第二开口30A暴露出来。上述第一凹槽22位于浅沟槽隔离结构23与上述第一沟道区2122连接的交界区CC。其中，上述图案化的第二硬掩模层用于在选择性地去除上述第一开口24A和第二开口暴露出来的浅沟槽隔离结构23的过程中， 保护剩余的浅沟槽隔离结构23不被去除。其中，该剩余的浅沟槽隔离结构23可以包括上述图案化的第一硬掩模层24上其他开口暴露出来的浅沟槽隔离结构23。
步骤S14：形成覆盖第一凹槽和第一沟道区的第一栅极绝缘层。
其中，步骤S14完成后的结构示意图如图17、图18和图19所示。
上述第一栅极绝缘层26用于将基于上述第一有源区212所形成的晶体管中栅极和沟道电隔离。具体地，可以采用物理气相沉积法、化学气相淀积法、原子层沉积法、激光辅助淀积法等方法，在上述衬底21上沉积形成至少覆盖上述第一凹槽22和上述第一沟道区2122的第一栅极绝缘层26(比如，氧化硅层)。
并且，具体实施时，上述第一栅极绝缘层26除了覆盖上述第一凹槽22的内壁面以及上述第一沟道区2122，还可以覆盖上述图案化的第一硬掩模层24。
步骤S15：在第一栅极绝缘层上于第一开口和第一凹槽中形成第一栅极。
其中，如图20所示，上述步骤S15可以具体包括：
步骤S151：在第一栅极绝缘层上于第一开口和第一凹槽中沉积栅极材料。
其中，上述步骤S151完成后的结构示意图如图21、图22和图23所示。
在上述栅极材料27(比如，多晶硅)的沉积过程中，上述第一开口24A会被该栅极材料27填充，与此同时，上述第一凹槽22中的剩余空间会被该栅极材料27填充。
步骤S152：通过化学机械抛光去除位于第一开口外部的栅极材料，以得到第一栅极。
其中，上述步骤S152完成后的结构示意图如图24、图25和图26所示。
具体地，可以通过化学机械抛光方法去除溢出上述第一开口24A的牺牲材料，以得到具有第一栅极281的栅极层28，并使得 上述第一栅极281能够具有平整的顶表面，以便于后续步骤中在该第一栅极281上所形成的结构的稳定性。
在一些具体实施例中，在通过化学机械抛光方法去除位于上述第一开口24A外部的牺牲材料的过程中，位于上述图案化的第一硬掩模层24上的第一栅极绝缘层26也会被去除，以露出上述图案化的第一硬掩模层24的顶表面。
在本实施例中，利用图案化的硬掩模层来定义栅极的形成位置，也即，限定栅极的形成位置位于图案化的硬掩模层上对应的开口内，实现了栅极的自对准。之后，利用沉积、化学机械抛光等简单易实现的方法来形成栅极。相比于利用刻蚀方法来形成栅极，本申请实施例的技术方案能够减少由于晶体管器件尺寸缩小而导致刻蚀形成栅极的工艺难度增大的情况。因而，降低了生产成本。
步骤S16：去除图案化的第一硬掩模层。
其中，上述步骤S16完成后的结构示意图如图27、图28和图29所示。
具体地，可以通过刻蚀方法(比如，湿法刻蚀方法)去除上述图案化的第一硬掩模层24。在一些具体实施例中，在通过刻蚀方法去除位于上述图案化的第一硬掩模层24的过程中，位于上述栅极层28周边的第一栅极绝缘层26也可以被去除。
在本实施例中，上述第一栅极281覆盖上述第一有源区212的第一沟道区2122，且填充位于该第一沟道区2122与上述隔离区211之间的第一凹槽22。如此，后续基于该第一栅极281和该第一有源区212，所形成的晶体管中栅极能够在沟道的相对两侧面以及顶表面上包裹沟道，也即，相当于增大了晶体管中栅极或沟道的有效长度，有利于改善晶体管的饱和电流和漏电电流等参数表现。
并且，具体实施时，上述第一有源区212中的第一源极区2121、第一沟道区2122和第一漏极区2123可以在平行于衬底21的第一横向Y上呈线性分布，且上述第一栅极281在平行于衬底21且垂直于第一横向Y的第二横向X上的两个侧端部可以延伸 到上述第一沟道区2122两侧的部分隔离区211(比如，部分浅沟槽隔离结构23)上。
在上述实施例中，上述半导体器件中所包含的晶体管的数量可以为多个，且该多个晶体管可以根据工作电压(也即，栅极导通电压)被划分为至少一个晶体管类型(比如，高压晶体管类型、低压晶体管类型和超低压晶体管类型等)，其中，高压晶体管类型的晶体管的栅极导通电压高于低压晶体管类型的晶体管的栅极导通电压，低压晶体管类型的晶体管的栅极导通电压高于超低压晶体管类型的晶体管的栅极导通电压。
具体地，上述第一有源区212可以用于形成其中一种晶体管类型的晶体管(比如，高压晶体管类型的晶体管)，也即，当上述第一有源区212的数量为多个时，基于该多个第一有源区212所形成的多个晶体管属于同一晶体管类型。并且，具体实施时，同一晶体管类型的多个晶体管可以通过上述步骤S11～步骤S16同时制作得到，也可以将上述同一晶体管类型的多个晶体管逐个或分多次通过上述步骤S11～步骤S16制作得到。
在一个具体实施例中，如图30、图31和图32所示，上述衬底21还可以包括第二有源区214，该第二有源区214和上述第一有源区212由上述隔离区211分隔开，且该第二有源区214可以包括依次连接的第二源极区、第二沟道区和第二漏极区。可以理解的是，与上述第一有源区212类似，上述第二有源区214也可以对应为上述半导体器件中一个晶体管的有源区，且上述第一有源区212和上述第二有源区214的区别在于：在上述半导体器件中，基于第一有源区212所形成的晶体管与基于第二有源区214所形成的晶体管属于不同的晶体管类型，例如，基于第一有源区212所形成的晶体管可以属于高压晶体管类型，而基于第二有源区214所形成的晶体管则可以属于低压晶体管类型。
相应地，上述图案化的第一硬掩模层24还可以包括第三开口，第三开口用于露出上述第二有源区214的第二沟道区、以及部分上述隔离区211。
具体地，为了基于上述第二有源区214形成对应的晶体管， 如图20所示，在上述步骤S15之前，还可以包括：
步骤S17.通过第三开口在隔离区与第二沟道区之间形成第二凹槽，第二凹槽部分位于隔离区中，且不贯穿隔离区。
其中，上述步骤S17的具体实施方式可以参考上述步骤S13的具体实施方式，并且仅需将上述步骤S13的具体实施方式中的第一开口、第一沟道区和第一凹槽分别替换为第三开口、第二沟道区和第二凹槽，即可得到上述步骤S17的具体实施方式，故此处不再赘述。
步骤S18.形成覆盖第二凹槽和第二沟道区的第二栅极绝缘层。
其中，上述步骤S18的具体实施方式可以参考上述步骤S14的具体实施方式，并且仅需将上述步骤S14的具体实施方式中的第一凹槽、第一沟道区和第一栅极绝缘层分别替换为第二凹槽、第二沟道区和第二栅极绝缘层，即可得到上述步骤S18的具体实施方式，故此处不再赘述。
在另一个具体实施例中，如图30、图31和图32所示，上述衬底21还可以包括第三有源区215，该第三有源区215、上述第一有源区212和上述第二有源区214由上述隔离区211分隔开，且该第三有源区215可以包括依次连接的第三源极区、第三沟道区和第三漏极区。可以理解的是，与上述第一有源区212和上述第二有源区214类似，上述第三有源区215也可以对应为上述半导体器件中一个晶体管的有源区，并且，与上述第一有源区212和上述第二有源区214的区别在于：在上述半导体器件中，基于第三有源区215所形成的晶体管、基于第一有源区212所形成的晶体管和基于第二有源区214所形成的晶体管属于不同的晶体管类型，例如，基于第一有源区212所形成的晶体管可以属于高压晶体管类型，基于第二有源区214所形成的晶体管可以属于低压晶体管类型，而基于第三有源区215所形成的晶体管则可以属于超低压晶体管类型。
相应地，上述图案化的第一硬掩模层24还可以包括第四开口，该第四开口用于露出上述第三有源区215的第三沟道区、以 及上述隔离区211与该第三沟道区连接的交界区。
具体地，为了基于上述第三有源区215形成对应的晶体管，如图20所示，在上述步骤S15之前，还可以包括：
步骤S19：通过第四开口在隔离区与第三沟道区之间形成第三凹槽，第三凹槽部分位于隔离区中，且不贯穿隔离区。
其中，上述步骤S19的具体实施方式可以参考上述步骤S13的具体实施方式，并且仅需将上述步骤S13的具体实施方式中的第一开口、第一沟道区和第一凹槽分别替换为第四开口、第三沟道区和第三凹槽，即可得到上述步骤S19的具体实施方式，故此处不再赘述。
步骤S20：形成覆盖第三凹槽和第三沟道区的第三栅极绝缘层。
其中，上述步骤S20的具体实施方式可以参考上述步骤S14的具体实施方式，并且仅需将上述步骤S14的具体实施方式中的第一凹槽、第一沟道区和第一栅极绝缘层分别替换为第三凹槽、第三沟道区和第三栅极绝缘层，即可得到上述步骤S20的具体实施方式，故此处不再赘述。
在一个具体实施例中，为了形成上述第二凹槽31，上述步骤S17可以具体包括：在图案化的第一硬掩模层24上形成图案化的第三硬掩模层，该图案化的第三硬掩模层包括第五开口，该第五开口与上述图案化的第一硬掩模层24上的第三开口相连通，且上述浅沟槽隔离结构23与上述第二有源区214的第二沟道区连接的交界区可以通过上述第三开口和第五开口暴露出来；选择性地去除上述第三开口和第五开口暴露出来的浅沟槽隔离结构23，以得到位于该浅沟槽隔离结构23与上述第二沟道区连接的交界区的上述第二凹槽31。其中，上述图案化的第三硬掩模层用于在选择性地去除上述第三开口和第五开口暴露出来的浅沟槽隔离结构23的过程中，保护剩余的浅沟槽隔离结构23不被去除。其中，该剩余的浅沟槽隔离结构23可以包括上述图案化的第一硬掩模层24上其他开口(比如，上述第一开口24A和上述第四开口)暴露出来的浅沟槽隔离结构23。
在一个具体实施例中，为了形成上述第三凹槽32，上述步骤S19可以具体包括：在图案化的第一硬掩模层24上形成图案化的第四硬掩模层，该图案化的第四硬掩模层包括第六开口，该第六开口与上述图案化的第一硬掩模层24上的第四开口相连通，且上述浅沟槽隔离结构23与上述第三有源区215的第三沟道区连接的交界区可以通过上述第四开口和第六开口暴露出来；选择性地去除上述第四开口和第六开口暴露出来的浅沟槽隔离结构23，以得到位于该浅沟槽隔离结构23与上述第三沟道区连接的交界区的上述第三凹槽32。其中，上述图案化的第四硬掩模层用于在选择性地去除上述第四开口和第六开口暴露出来的浅沟槽隔离结构23的过程中，保护剩余的浅沟槽隔离结构23不被去除。其中，该剩余的浅沟槽隔离结构23可以包括上述图案化的第一硬掩模层24上其他开口(比如，上述第一开口24A和上述第三开口)暴露出来的浅沟槽隔离结构23。
在上述实施例中，为了确保基于上述第一有源区212所形成的晶体管与基于上述第二有源区214所形成的晶体管属于不同的晶体管类型，可以设置：上述第二凹槽31在垂直于衬底21的纵向Z上的深度H2不同于上述第一凹槽22在纵向Z上的深度H1；和/或，上述第二栅极绝缘层33的厚度不同于上述第一栅极绝缘层26的厚度。
具体举例，当基于上述第一有源区212所形成的晶体管的栅极导通电压大于基于上述第二有源区214所形成的晶体管的栅极导通电压，比如，基于上述第一有源区212所形成的晶体管属于高压晶体管类型，而基于上述第二有源区214所形成的晶体管属于低压晶体管类型时，可以设置：上述第二凹槽31在垂直于衬底21的纵向Z上的深度H2小于第一凹槽22在所述纵向Z上的深度H1；和/或，上述第二栅极绝缘层33的厚度小于第一栅极绝缘层26的厚度。
依次类推，为了确保基于上述第三有源区215所形成的晶体管与基于上述第一有源区212所形成的晶体管属于不同的晶体管类型，可以设置：上述第三凹槽32在垂直于衬底21的纵向Z上 的深度H3不同于上述第一凹槽22在纵向Z上的深度H1；和/或，上述第三栅极绝缘层34的厚度不同于上述第一栅极绝缘层的厚度。在其他实施例中，为了确保基于上述第三有源区215所形成的晶体管与基于上述第二有源区214所形成的晶体管属于不同的晶体管类型，可以设置：上述第三凹槽32在垂直于衬底21的纵向Z上的深度H3不同于上述第二凹槽31在纵向Z上的深度H2；和/或，上述第三栅极绝缘层34的厚度不同于上述第二栅极绝缘层33的厚度。
在一个可能的实施例中，基于上述第一有源区212所形成的晶体管的栅极导通电压可以大于基于上述第二有源区214所形成的晶体管的栅极导通电压，基于上述第二有源区214所形成的晶体管的栅极导通电压可以大于基于上述第三有源区215所形成的晶体管的栅极导通电压。例如，基于上述第一有源区212所形成的晶体管可以属于高压晶体管类型，基于上述第二有源区214所形成的晶体管可以属于低压晶体管类型，基于上述第三有源区215所形成的晶体管可以属于超低压晶体管类型。
相应地，上述第三凹槽32在垂直于衬底21的纵向Z上的深度H3可以小于第二凹槽32在纵向Z上的深度H2，上述第二凹槽31在垂直于衬底21的纵向Z上的深度H2可以小于第一凹槽22在纵向Z上的深度H1。并且，在一些实施例中，上述第三栅极绝缘层34的厚度可以小于第二栅极绝缘层33的厚度，上述第二栅极绝缘层33的厚度可以小于第一栅极绝缘层26的厚度。
需要说明的是，对于工作电压(也即，栅极导通电压)越高的晶体管，其栅极绝缘层越厚，越有利于改善晶体管器件的饱和电流、漏电电流等电特性参数，进而提高该晶体管的性能。并且，在上述实施例中，对于工作电压高的晶体管，其沟道与上述隔离区211之间的凹槽(也即，上述第一凹槽22、第二凹槽31或第三凹槽32)越深，越有利于改善栅极对晶体管沟道的控制能力，进而提高该晶体管的性能。
在一种可能的实施方式中，第一凹槽22、第二凹槽31和第三凹槽32在垂直于衬底21的纵向Z上深度可以相同，并且该第 一凹槽22、第二凹槽31和第三凹槽32可以通过同一道工艺(比如，一次刻蚀工艺)形成。也即，上述步骤S13、步骤S17和步骤S19可以是同一刻蚀工艺步骤，从而通过一步刻蚀即可形成上述第一凹槽22、第二凹槽31和第三凹槽32。
依次类推，在另一种可能的实施方式中，第一栅极绝缘层26、第二栅极绝缘层33和第三栅极绝缘层34具体相同的厚度，则该第一栅极绝缘层26、第二栅极绝缘层33和第三栅极绝缘层34还可以通过同一道工艺(比如，一次沉积工艺)形成。也即，上述步骤S14、步骤S18和步骤S20可以是同一沉积工艺步骤，从而通过一步沉积即可形成上述第一栅极绝缘层26、第二栅极绝缘层33和第三栅极绝缘层34。
在其他实施例中，当上述第一栅极绝缘层26、第二栅极绝缘层33和第三栅极绝缘层34具体不同的厚度时，可以按照厚度逐渐减小的顺序逐步形成该第一栅极绝缘层26、第二栅极绝缘层33和第三栅极绝缘层34。在上述实施例中，当上述第一凹槽22、第二凹槽31和第三凹槽32具体不同的深度时，可以按照深度逐渐减小的顺序逐步形成该第一凹槽22、第二凹槽31和第三凹槽32。
具体举例，当上述第一凹槽22、第二凹槽31和第三凹槽32的深度逐渐减小时，可以通过依次执行上述步骤S12、步骤S13、步骤S15、步骤S16、步骤S17和步骤S18，逐步形成上述第一凹槽22、第一栅极绝缘层26、第二凹槽31、第二栅极绝缘层33、第三凹槽32和第三栅极绝缘层34。
在上述实施例中，在上述步骤S18之后，还可以包括：
S21：在第二栅极绝缘层上于第三开口和第二凹槽中形成第二栅极。
其中，上述步骤S21的具体实施方式可以参考上述步骤S15的具体实施方式，并且仅需将上述步骤S15的具体实施方式中的第一栅极绝缘层、第一开口、第一凹槽和第一栅极分别对应替换为第二栅极绝缘层、第三开口、第二凹槽和第二栅极，即可得到上述步骤S21的具体实施方式，故此处不再赘述。
在一些实施例中，在上述步骤S20之后，还可以包括：
S22：在第三栅极绝缘层上于第四开口和第三凹槽中形成第三栅极。
其中，上述步骤S22的具体实施方式可以参考上述步骤S15的具体实施方式，并且仅需将上述步骤S15的具体实施方式中的第一栅极绝缘层、第一开口、第一凹槽和第一栅极分别对应替换为第三栅极绝缘层、第四开口、第三凹槽和第三栅极，即可得到上述步骤S22的具体实施方式，故此处不再赘述。
具体地，上述步骤S22完成后的结构示意图可以如图30、图31和图32所示，第一栅极281、第二栅极282和第三栅极283间隔绝缘设置。第二栅极282覆盖上述第二沟道区，且填充位于隔离区211与第二沟道区之间的第二凹槽31。第三栅极283覆盖上述第三沟道区，且填充位于隔离区211与第三沟道区之间的第三凹槽32。
并且，具体实施时，上述半导体器件中不同晶体管的栅极(比如，第一栅极281、第二栅极282和第三栅极283)可以通过同一道工艺形成，也可以通过多道工艺形成。
具体举例，当上述半导体器件中不同晶体管的栅极通过同一道工艺形成时，上述第一栅极281、第二栅极282和第三栅极283可以通过同一道工艺形成。也即，上述步骤S15、步骤S21和步骤S22可以是同一工艺步骤，从而通过一个工艺步骤即可形成包括第一栅极281、第二栅极282和第三栅极283的上述栅极层28。
如此，采用本实施例中的半导体器件的制作方法，能够制作得到具有不同厚度栅极绝缘层的晶体管、以及沟道与上述隔离区211之间的凹槽(比如，上述第一凹槽22、第二凹槽31和第三凹槽32)具有不同深度的晶体管，进而能够满足半导体器件中工作电压不同的晶体管对栅极绝缘层厚度以及对于栅极与沟道侧面的接触面积的多样化要求。
在上述实施例中，上述半导体器件可以具体为存储器(比如，3D NAND存储器)的外围电路芯片，该外围电路芯片中可以集成有多个晶体管，且该多个晶体管可以属于不同的晶体管类型。
上述实施例中，如图20所示，在上述步骤S16之后，也即， 在形成上述栅极层28之后，上述半导体器件的制作方法还可以包括：
步骤S23：在第一栅极的侧表面上形成侧墙。
其中，步骤S23完成后的结构示意图如图33、图34和图35所示。
具体地，可以在上述栅极层28的各个栅极(比如，上述第一栅极281、上述第二栅极281和上述第三栅极281)的侧表面(比如，前后左右四个侧表面)上，依次采用沉积工艺和刻蚀工艺形成上述侧墙35。其中，该侧墙的材质可以为氧化硅等绝缘材料，并且，该侧墙35用于保护上述栅极，并能够减少热载流子注入(Hot Carrier Injection,HCI)效应。
在一个具体实施例中，上述半导体器件可以同时包括高压晶体管类型的晶体管、低压晶体管类型的晶体管以及超低压晶体管类型的晶体管，并且形成该半导体器件的具体流程可以如下：
步骤S1-1：形成衬底，衬底包括第一有源区、第二有源区、第三有源区以及隔离区，隔离区将第一有源区、第二有源区和第三有源区分隔开，且第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区，第二有源区包括依次连接的第二源极区、第二沟道区和第二漏极区，第三有源区包括依次连接的第三源极区、第三沟道区和第三漏极区。
步骤S1-2：在衬底上形成图案化的第一硬掩模层，图案化的第一硬掩模层包括第一开口、第三开口和第四开口，第一开口用于露出第一沟道区以及部分隔离区，第三开口用于露出第二沟道区以及部分隔离区，第四开口用于露出第三沟道区以及部分隔离区。
步骤S1-3：通过第一开口在隔离区与第一沟道区之间形成第一凹槽，第一凹槽部分位于隔离区中，且不贯穿隔离区。
步骤S1-4：形成覆盖第一凹槽和第一沟道区的第一栅极绝缘层。
步骤S1-5：通过第三开口在隔离区与第二沟道区之间形成第二凹槽，第二凹槽部分位于隔离区中，且不贯穿隔离区。
步骤S1-6：形成覆盖第二凹槽和第二沟道区的第二栅极绝缘层。
步骤S1-7：通过第四开口在隔离区与第三沟道区之间形成第三凹槽，第三凹槽部分位于隔离区中，且不贯穿隔离区。
步骤S1-8：形成覆盖第三凹槽和第三沟道区的第三栅极绝缘层。
步骤S1-9：在第一栅极绝缘层上于第一开口和第一凹槽中形成第一栅极、在第二栅极绝缘层上于第三开口和第二凹槽中形成第二栅极、以及在第三栅极绝缘层上于第四开口和第三凹槽中形成第三栅极。
步骤S1-10：去除图案化的第一硬掩模层。
步骤S1-11：在第一栅极的侧表面、第二栅极的侧表面以及第三栅极的侧表面上形成侧墙。
其中，第一有源区、第二有源区和第三有源区可以具有不同的尺寸，比如，第一有源区的横截面面积、第二有源区的横截面面积和第三有源区的横截面面积可以依次减小。
其中，第一凹槽、第二凹槽和第三凹槽可以具有不同的深度，比如，第一凹槽的深度、第二凹槽的深度和第三凹槽的深度可以依次减小。
其中，第一栅极绝缘层、第二栅极绝缘层和第三栅极绝缘层可以具有不同的厚度，比如，第一栅极绝缘层的厚度、第二栅极绝缘层的厚度和第三栅极绝缘层的厚度可以依次减小。
可以理解的是，上述步骤S1-1的具体实施方式可以参考上述步骤S11的具体实施方式，上述步骤S1-2的具体实施方式可以参考上述步骤S12的具体实施方式，上述步骤S1-3的具体实施方式可以参考上述步骤S13的具体实施方式，上述步骤S1-4的具体实施方式可以参考上述步骤S14的具体实施方式，上述步骤S1-5的具体实施方式可以参考上述步骤S17的具体实施方式，上述步骤S1-6的具体实施方式可以参考上述步骤S18的具体实施方式，上述步骤S1-7的具体实施方式可以参考上述步骤S19的具体实施方式，上述步骤S1-8的具体实施方式可以参考上述步骤S20的具 体实施方式，上述步骤S1-9的具体实施方式可以参考上述步骤S15、步骤S21和步骤S22的具体实施方式，上述步骤S1-10的具体实施方式可以参考上述步骤S16的具体实施方式，上述步骤S1-11的具体实施方式可以参考上述步骤S23的具体实施方式，故在此不再赘述。
区别于现有技术，本实施例中的半导体器件的制作方法，通过形成衬底，衬底包括第一有源区以及位于第一有源区周边的隔离区，第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区，并在衬底上形成图案化的第一硬掩模层，图案化的第一硬掩模层包括第一开口，第一开口用于露出第一沟道区、以及部分隔离区，然后通过第一开口在隔离区与第一沟道区之间形成第一凹槽，第一凹槽部分位于隔离区中，且不贯穿隔离区，之后形成覆盖第一凹槽和第一沟道区的第一栅极绝缘层，并在第一栅极绝缘层上于第一开口和第一凹槽中形成第一栅极；接着去除图案化的第一硬掩模层，从而能够增大栅极有效长度，以改进栅极对晶体管沟道的控制，进而在晶体管器件尺寸缩小的同时，能够改善晶体管器件的饱和电流、漏电电流等电特性参数，提高晶体管器件的性能，并且无需通过刻蚀栅极材料层形成栅极，避免了由于晶体管器件尺寸缩小而导致通过刻蚀栅极材料层形成栅极的工艺难度增大，进而导致生产成本增高的问题，降低了生产成本。
根据本申请上述方法实施例制作而成的半导体器件如图27、图28和图29所示，该半导体器件包括：衬底21，衬底21包括第一有源区212以及位于第一有源区212周边的隔离区211，第一有源区212包括依次连接的第一源极区2121、第一沟道区2122和第一漏极区2123；位于隔离区211与第一沟道区2122之间的第一凹槽22，第一凹槽22部分位于隔离区211中，且不贯穿隔离区211；覆盖第一凹槽22和第一沟道区2122的第一栅极绝缘层26；位于第一栅极绝缘层26上的第一栅极281，第一栅极281覆盖第一沟道区2122，且填充上述第一凹槽22。
在一个具体实施例中，如图30、图31和图32所示，上述衬底21还可以包括第二有源区214，第一有源区212和第二有源区 214由上述隔离区211分隔开，且第二有源区214包括依次连接的第二源极区、第二沟道区和第二漏极区。
具体地，上述半导体器件还可以包括位于上述隔离区211与上述第二沟道区之间的第二凹槽31，第二凹槽31部分位于上述隔离区211中，且不贯穿隔离区211。进一步地，上述半导体器件还会包括覆盖上述第二凹槽31和上述第二沟道区的第二栅极绝缘层33。其中，第二栅极绝缘层33的厚度与第一栅极绝缘层26的厚度不同，例如，上述第二栅极绝缘层33的厚度可以小于上述第一栅极绝缘层26的厚度。
在一个具体实施例中，上述半导体器件还可以包括第二栅极282，该第二栅极282覆盖上述第二沟道区，且上述第二凹槽31。
其中，上述第二凹槽31在垂直于衬底21的纵向Z上的深度小于上述第一凹槽22在纵向Z上的深度。
在一些实施例中，上述衬底21还可以包括设置于隔离区211中且位于第一有源区212周边的浅沟槽。上述外围器件200还可以包括位于浅沟槽中的浅沟槽隔离结构23。上述第一凹槽22可以具体位于浅沟槽隔离结构23与第一沟道区之间，且该第一凹槽22在垂直于衬底21的纵向Z上的深度可以小于浅沟槽隔离结构23在纵向Z上的深度。
在一些实施例中，上述半导体器件还可以包括设置于第一栅极281的侧表面上的侧墙。
需要说明的是，本实施例中半导体器件的各个结构可以参考上述方法实施例中所描述的具体实施方式，故此处不再赘述。
区别于现有技术，本实施例提供的半导体器件，通过增大栅极有效长度，改进了栅极对晶体管沟道的控制，从而在晶体管器件尺寸缩小的同时，能够改善晶体管器件的饱和电流、漏电电流等电特性参数，提高晶体管器件的性能，并且无需通过刻蚀栅极材料层形成栅极，避免了由于晶体管器件尺寸缩小而导致通过刻蚀栅极材料层形成栅极的工艺难度增大，进而导致生产成本增高的问题，降低了生产成本。
请参阅图36，图36是本申请实施例提供的NAND存储器件 的结构示意图。如图36所示，该NAND存储器件可以包括电连接的存储阵列100和外围器件200，其中，存储阵列100可以包括多个存储单元串101，外围器件200可以包括上述任一实施例中的半导体器件。
具体地，上述外围器件200可以包括：衬底21，衬底21包括第一有源区212以及位于第一有源区212周边的隔离区211，第一有源区212包括依次连接的第一源极区、第一沟道区和第一漏极区；位于隔离区211与第一沟道区之间的第一凹槽22，第一凹槽22部分位于隔离区211中，且不贯穿隔离区211；覆盖第一凹槽22和第一沟道区2122的第一栅极绝缘层26；位于第一栅极绝缘层26上的第一栅极281，第一栅极281覆盖第一沟道区2122，且填充第一凹槽22。
在一个具体实施例中，上述第一凹槽22可以位于隔离区211与第一有源区212之间，且环绕第一有源区212。
在一个具体实施例中，上述衬底21还可以包括第二有源区214，第一有源区212和第二有源区214由上述隔离区211分隔开，且第二有源区214包括依次连接的第二源极区、第二沟道区和第二漏极区。
具体地，上述外围器件200还可以包括位于上述隔离区211与上述第二沟道区之间的第二凹槽31，第二凹槽31部分位于上述隔离区211中，且不贯穿隔离区211。进一步地，上述外围器件200还会包括覆盖上述第二凹槽31和上述第二沟道区的第二栅极绝缘层33。其中，第二栅极绝缘层33的厚度与第一栅极绝缘层26的厚度不同，例如，第二栅极绝缘层33的厚度可以小于第一栅极绝缘层26的厚度。
在一个具体实施例中，上述外围器件200还可以包括第二栅极282，该第二栅极282覆盖上述第二沟道区，且填充位于上述隔离区211与上述第二沟道区之间的第二凹槽31。
其中，上述第二凹槽31在垂直于衬底21的纵向Z上的深度小于上述第一凹槽22在纵向Z上的深度。
在一些实施例中，上述衬底21还可以包括设置于隔离区211 中且位于第一有源区212周边的浅沟槽。上述外围器件200还可以包括位于浅沟槽中的浅沟槽隔离结构23。上述第一凹槽22可以具体位于浅沟槽隔离结构23与第一沟道区之间，且该第一凹槽22在垂直于衬底21的纵向Z上的深度可以小于浅沟槽隔离结构23在纵向Z上的深度。
在一些实施例中，上述外围器件200还可以包括设置于第一栅极281的侧表面上的侧墙35。
需要说明的是，本实施例中外围器件200的各个结构可以参考上述半导体器件实施例中所描述的具体实施方式，故此处不再赘述。
在上述实施例中，上述存储阵列100还可以包括：位于外围器件200上的叠层结构102，其中，每个存储单元串101包括贯穿叠层结构102的沟道层和存储功能层，且存储功能层位于沟道层和叠层结构之间。其中，上述叠层结构102可以包括在纵向Z上多层交替层叠设置的若干层栅极层1021和栅绝缘层1022。
在一些具体实施例中，上述存储阵列100还可以包括设于堆叠结构102朝向外围器件200的一侧上的互连层104，其中，存储单元串101与互连层104电连接，且互连层104可以电连接至上述外围器件200的第一源极区中的衬底21、第一漏极区中的衬底21和/或第一栅极281。
具体地，上述存储阵列100还可以包括设于堆叠结构102和互连层104之间的层间介质层、以及形成于层间介质层中的多个导电触点103。其中，该多个导电触点103可以包括位线触点，位线触点可以在纵向Z上延伸，且一端与存储单元串101电连接，另一端与互连层104电连接。
可以理解的是，本实施例中存储阵列100的具体实施方式可以参考现有技术中存储阵列的具体实施方式，故此处不再赘述。
并且，本实施例中所例举的NAND存储器件虽以外围器件和存储阵列相键合的晶圆键合(Wafer bonding)架构作为示例，但在其他实施例中，上述NAND存储器件还可以是其他可能的NAND架构，比如，外围电路器件在阵列之下(periphery under core  array，PUC)架构、外围电路器件在阵列旁边(periphery near core array，PNC)架构等，本申请实施例对此不做具体限定。
区别于现有技术，本实施例提供的NAND存储器件，通过增大栅极有效长度，改进了栅极对晶体管沟道的控制，从而在晶体管器件尺寸缩小的同时，能够改善晶体管器件的饱和电流、漏电电流等电特性参数，提高晶体管器件的性能，并且无需通过刻蚀栅极材料层形成栅极，避免了由于晶体管器件尺寸缩小而导致通过刻蚀栅极材料层形成栅极的工艺难度增大，进而导致生产成本增高的问题，降低了生产成本。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (18)

  1. 一种半导体器件的制作方法，其包括：
    形成衬底，所述衬底包括第一有源区以及位于所述第一有源区周边的隔离区，所述第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区；
    在所述衬底上形成图案化的第一硬掩模层，所述图案化的第一硬掩模层包括第一开口，所述第一开口用于露出所述第一沟道区、以及部分所述隔离区；
    通过所述第一开口在所述隔离区与所述第一沟道区之间形成第一凹槽，所述第一凹槽部分位于所述隔离区中，且不贯穿所述隔离区；
    形成覆盖所述第一凹槽和所述第一沟道区的第一栅极绝缘层；
    在所述第一栅极绝缘层上于所述第一开口和所述第一凹槽中形成第一栅极；
    去除所述图案化的第一硬掩模层。
  2. 根据权利要求1所述的半导体器件的制作方法，其中，所述在所述第一栅极绝缘层上于所述第一开口和所述第一凹槽中形成第一栅极，具体包括：
    在所述第一栅极绝缘层上于所述第一开口和所述第一凹槽中沉积栅极材料；
    通过化学机械抛光去除位于所述第一开口外部的栅极材料，以得到第一栅极。
  3. 根据权利要求1所述的半导体器件的制作方法，其中，所述衬底还包括形成于所述隔离区且位于所述第一有源区周边的浅沟槽，在所述衬底上形成图案化的第一硬掩模层之前，还包括：
    在所述隔离区的所述浅沟槽中形成浅沟槽隔离结构；
    所述通过所述第一开口在所述隔离区与所述第一沟道区之间形成第一凹槽，具体包括：
    通过所述第一开口在所述浅沟槽隔离结构与所述第一沟道区之间形成第一凹槽，所述第一凹槽在垂直于所述衬底的纵向上的 深度小于所述浅沟槽隔离结构在所述纵向上的深度。
  4. 根据权利要求3所述的半导体器件的制作方法，其中，所述通过所述第一开口在所述浅沟槽隔离结构与所述第一沟道区之间形成第一凹槽，具体包括：
    在所述图案化的第一硬掩模层上形成图案化的第二硬掩模层，所述图案化的第二硬掩模层包括第二开口，所述第二开口与所述第一开口相连通，且部分所述浅沟槽隔离结构通过所述第一开口和所述第二开口暴露出来；
    选择性地去除所述第一开口和所述第二开口暴露出来的部分所述浅沟槽隔离结构，以得到位于所述浅沟槽隔离结构与所述第一沟道区之间的第一凹槽，且其中，所述图案化的第二硬掩模层用于在选择性地去除所述第一开口和所述第二开口暴露出来的部分所述浅沟槽隔离结构的过程中，保护剩余所述浅沟槽隔离结构不被去除。
  5. 根据权利要求1所述的半导体器件的制作方法，其中，所述衬底还包括第二有源区，所述第一有源区和所述第二有源区由所述隔离区分隔开，且所述第二有源区包括依次连接的第二源极区、第二沟道区和第二漏极区，所述图案化的第一硬掩模层还包括第三开口，所述第三开口用于露出所述第二沟道区、以及部分所述隔离区，所述在所述第一栅极绝缘层上于所述第一开口和所述第一凹槽中形成第一栅极之前，还包括：
    通过所述第三开口在所述隔离区与所述第二沟道区之间形成第二凹槽，所述第二凹槽部分位于所述隔离区中，且不贯穿所述隔离区；
    形成覆盖所述第二凹槽和所述第二沟道区的第二栅极绝缘层，所述第二栅极绝缘层的厚度与所述第一栅极绝缘层的厚度不同。
  6. 根据权利要求5所述的半导体器件的制作方法，其中，在所述形成覆盖所述第二凹槽和所述第二沟道区的第二栅极绝缘层之后，还包括：
    在所述第二栅极绝缘层上于所述第三开口和所述第二凹槽中 形成第二栅极。
  7. 根据权利要求5所述的半导体器件的制作方法，其中，所述第二凹槽在垂直于所述衬底的纵向上的深度小于所述第一凹槽在所述纵向上的深度。
  8. 根据权利要求1所述的半导体器件的制作方法，其中，在所述去除所述图案化的第一硬掩模层之后，还包括：
    在所述第一栅极的侧表面上形成侧墙。
  9. 一种半导体器件，其包括：
    衬底，所述衬底包括第一有源区以及位于所述第一有源区周边的隔离区，所述第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区；
    位于在所述隔离区与所述第一沟道区之间的第一凹槽，所述第一凹槽部分位于所述隔离区中，且不贯穿所述隔离区；
    覆盖所述第一凹槽和所述第一沟道区的第一栅极绝缘层；
    位于所述第一栅极绝缘层上的第一栅极，所述第一栅极覆盖所述第一沟道区，且填充所述第一凹槽。
  10. 根据权利要求9所述的半导体器件，其中，所述衬底还包括第二有源区，所述第一有源区和所述第二有源区由所述隔离区分隔开，且所述第二有源区包括依次连接的第二源极区、第二沟道区和第二漏极区，所述半导体器件还包括：
    位于所述隔离区与所述第二沟道区之间的第二凹槽，所述第二凹槽部分位于所述隔离区中，且不贯穿所述隔离区；
    覆盖所述第二凹槽和所述第二沟道区的第二栅极绝缘层，所述第二栅极绝缘层的厚度与所述第一栅极绝缘层的厚度不同。
  11. 根据权利要求10所述的半导体器件，其中，所述半导体器件还包括第二栅极，所述第二栅极覆盖所述第二沟道区，且填充所述第二凹槽。
  12. 根据权利要求10所述的半导体器件，其中，所述第二凹槽在垂直于所述衬底的纵向上的深度小于所述第一凹槽在所述纵向上的深度。
  13. 一种NAND存储器件，其包括电连接的存储阵列和外围 器件，所述存储阵列包括多个存储单元串，所述外围器件包括：
    衬底，所述衬底包括第一有源区以及位于所述第一有源区周边的隔离区，所述第一有源区包括依次连接的第一源极区、第一沟道区和第一漏极区；
    位于在所述隔离区与所述第一沟道区之间的第一凹槽，所述第一凹槽部分位于所述隔离区中，且不贯穿所述隔离区；
    覆盖所述第一凹槽和所述第一沟道区的第一栅极绝缘层；
    位于所述第一栅极绝缘层上的第一栅极，所述第一栅极覆盖所述第一沟道区，且填充所述第一凹槽。
  14. 根据权利要求13所述的NAND存储器件，其中，所述衬底还包括第二有源区，所述第一有源区和所述第二有源区由所述隔离区分隔开，且所述第二有源区包括依次连接的第二源极区、第二沟道区和第二漏极区，所述外围器件还包括：
    位于所述隔离区与所述第二沟道区之间的第二凹槽，所述第二凹槽部分位于所述隔离区中，且不贯穿所述隔离区；
    覆盖所述第二凹槽和所述第二沟道区的第二栅极绝缘层，所述第二栅极绝缘层的厚度与所述第一栅极绝缘层的厚度不同。
  15. 根据权利要求14所述的NAND存储器件，其中，所述外围器件还包括第二栅极，所述第二栅极覆盖所述第二沟道区，且填充所述第二凹槽。
  16. 根据权利要求14所述的NAND存储器件，其中，所述第二凹槽在垂直于所述衬底的纵向上的深度小于所述第一凹槽在所述纵向上的深度。
  17. 根据权利要求13所述的NAND存储器件，其中，所述存储阵列还包括：
    位于所述外围器件上的叠层结构，其中，每个所述存储单元串包括贯穿所述叠层结构的沟道层和存储功能层，且所述存储功能层位于所述沟道层和所述叠层结构之间。
  18. 根据权利要求17所述的NAND存储器件，其中，所述存储阵列还包括：
    设于所述堆叠结构朝向所述外围器件的一侧上的互连层，其 中，所述存储单元串与所述互连层电连接，且所述互连层电连接至所述第一源极区中的所述衬底、所述第一漏极区中的所述衬底和/或所述第一栅极。
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