WO2022188620A1 - Nor型存储器件及其制造方法及包括存储器件的电子设备 - Google Patents

Nor型存储器件及其制造方法及包括存储器件的电子设备 Download PDF

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WO2022188620A1
WO2022188620A1 PCT/CN2022/077238 CN2022077238W WO2022188620A1 WO 2022188620 A1 WO2022188620 A1 WO 2022188620A1 CN 2022077238 W CN2022077238 W CN 2022077238W WO 2022188620 A1 WO2022188620 A1 WO 2022188620A1
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layer
source
drain
semiconductor
region
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PCT/CN2022/077238
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French (fr)
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朱慧珑
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中国科学院微电子研究所
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular, to a NOR-type memory device, a method of manufacturing the same, and an electronic device including such a memory device.
  • a horizontal type device such as a metal oxide semiconductor field effect transistor (MOSFET)
  • MOSFET metal oxide semiconductor field effect transistor
  • the source, gate and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the horizontal type device cannot easily be further reduced.
  • the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical type devices are easier to shrink than horizontal type devices.
  • the integration density can be increased by stacking with each other. However, this may result in poor performance. Because in order to facilitate stacking a plurality of devices, polysilicon is generally used as the channel material, resulting in increased resistance compared with the channel material of single crystal silicon. In addition, it is also desirable to be able to individually adjust the doping levels in the source/drain regions and the channel.
  • NOR-type memory device with improved performance, a method of manufacturing the same, and an electronic device including such a memory device.
  • a vertical memory device comprising: a gate stack extending vertically on a substrate, the gate stack including a gate conductor layer and a memory function layer; and surrounding a periphery of the gate stack, along the gate
  • the sidewalls of the stack extend a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer being respectively at different heights with respect to the substrate.
  • the storage function layer is interposed between the first semiconductor layer and the gate conductor layer and between the second semiconductor layer and the gate conductor layer.
  • Each of the first semiconductor layer and the second semiconductor layer includes a first source/drain region, a channel region and a second source/drain region which are sequentially arranged in a vertical direction.
  • Memory cells are defined where the gate stack intersects the first semiconductor layer and where the gate stack intersects the second semiconductor layer, respectively.
  • a method of fabricating a vertical memory device comprising: disposing a plurality of device layers on a substrate, each device layer including a first source/drain defining layer, a first channel A stack of defining layers and a second source/drain defining layer; forming processing channels extending vertically relative to the substrate to pass through the stacks in the respective device layers; A semiconductor layer is epitaxially grown on the sidewall; and a gate stack is formed in the processing channel, the gate stack includes a gate conductor layer and a memory function layer disposed between the gate conductor layer and the semiconductor layer, and a memory function is defined at the intersection of the gate stack and the semiconductor layer unit.
  • an electronic device including the above-mentioned NOR type memory device.
  • three-dimensional (3D) NOR-type memory devices may be created using stacks of single crystal materials as building blocks. Therefore, when a plurality of memory cells are stacked on each other, an increase in resistance can be suppressed.
  • the semiconductor layer can be in the form of nanosheets, which is particularly beneficial to control the short-channel effect of the device, and is also beneficial to reduce the height of the device, increase the number of device layers, and improve the integration density.
  • FIGS. 1 to 18(c) are schematic diagrams showing some stages in the process of manufacturing a NOR memory device according to an embodiment of the present disclosure
  • 19(a) and 19(b) are schematic diagrams showing some stages in a process of manufacturing a NOR memory device according to another embodiment of the present disclosure.
  • 20(a) and 20(b) illustrate schematic diagrams of some stages in a process for manufacturing a NOR memory device according to another embodiment of the present disclosure
  • FIG. 21 schematically shows an equivalent circuit diagram of a NOR type memory device according to an embodiment of the present disclosure
  • FIG. 2(a), 12(a), 14(a), 18(a), and 19(a) are top views, and FIG. 2(a) shows the positions of AA' and BB' lines,
  • Figures 1, 2(b), 3 to 11, 12(b), 13, 14(b), 15(a), 16(a), 17(a), 18(b), 19(b), 20 (a) is a cross-sectional view along line AA',
  • 14(c), 15(b), 16(b), 17(b), 18(c), and 20(b) are cross-sectional views along line BB'.
  • a layer/element when referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element.
  • a layer/element when a layer/element is “on” another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under” the other layer/element.
  • the memory device is based on a vertical type device.
  • the vertical device may include an active region provided on the substrate in a vertical direction (a direction substantially perpendicular to the surface of the substrate), including source/drain regions provided at the upper and lower ends and a trench located between the source/drain regions Road area.
  • a conductive channel may be formed between the source/drain regions through the channel region.
  • the source/drain region and the channel region can be defined, for example, by doping concentration.
  • the active region may be defined by a vertically extending semiconductor layer.
  • the source/drain regions may be formed at opposite ends of the semiconductor layer, respectively, and the channel region may be formed in the middle of the semiconductor layer.
  • the gate stack may extend through the semiconductor layer such that the active region may surround the perimeter of the gate stack.
  • the semiconductor layer may take the form of annular nanosheets surrounding the gate stack.
  • the gate stack may include a storage function layer such as at least one of a charge trapping material or a ferroelectric material, so as to realize the storage function. In this way, the gate stack cooperates with the opposite active region to define the memory cell.
  • the storage unit may be a flash memory (flash) unit.
  • the gate stack may extend vertically through the plurality of semiconductor layers.
  • the plurality of semiconductor layers may be substantially coplanar in a vertical direction, eg, extending along sidewalls of the gate stack. In this way, for a single gate stack, a plurality of vertically stacked memory cells are defined by intersecting the plurality of vertically stacked semiconductor layers.
  • each gate stack may similarly pass through multiple semiconductor layers to define multiple memory cells where the multiple gate stacks intersect the semiconductor layers.
  • the memory cells may be vertically arranged in multiple levels, with the memory cells in each level arranged in an array (eg, typically a two-dimensional array arranged in rows and columns) corresponding to the multiple gate stacks. Thus, a three-dimensional (3D) array of memory cells can be obtained.
  • the memory cells (or semiconductor layers) within each level may be substantially coplanar.
  • each memory cell may be connected to a common source line.
  • every two adjacent memory cells can share the same source line connection in the vertical direction.
  • the above-mentioned semiconductor layer may include (first) source/drain region-(first) channel region-(second) source/drain region-(second) channel region-(third) source/drain region configuration.
  • the first source/drain region, the first channel region and the second source/drain region can cooperate with the gate stack as described above to define the first memory cell, and in addition the second source/drain region and the second channel region and the third source/drain regions can also cooperate with the gate stack to define the second memory cell.
  • the first memory cell and the second memory cell are stacked on each other and share the same second source/drain region, which may be electrically connected to the source line.
  • interconnect layers may be provided in contact with the source/drain regions.
  • respective source/drain regions of memory cells in each level may be electrically connected to bit lines or source lines through the same interconnect layer.
  • the interconnection layers may be formed to surround the respective source/drain regions in the corresponding levels, so that the entirety may exhibit a plate shape through which the respective semiconductor layers pass through the plate-shaped interconnection layers.
  • the interconnection layer can extend from the device region where the memory cells are located to the region where the contact is to be formed, so that the contact portion to the interconnection layer can be made later.
  • the source/drain regions may be defined by respective interconnect layers.
  • the source/drain regions may be formed by laterally driving dopants in the interconnect layer into the semiconductor layer. Accordingly, the interconnect layers and the corresponding source/drain regions may be substantially coplanar in the lateral direction.
  • Such a vertical type memory device can be manufactured as follows, for example. Specifically, a plurality of device layers may be provided on the substrate, each device layer including a first source/drain defining layer, a first channel defining layer and a second source/drain defining layer (and optionally, a second channel defining layer) A stack of channel defining layers and third source/drain defining layers). For example, these layers may be provided by epitaxial growth and may be of single crystal semiconductor material. During epitaxial growth, the thicknesses of the grown layers, especially the channel defining layers, can be controlled. In addition, during epitaxial growth, the layers in the stack, especially the source/drain defining layers, can be doped in situ to achieve the desired doping polarity and doping concentration. Here, there may be etch selectivity between the channel layer and the source/drain defining layer.
  • a sacrificial layer may be formed between at least some or even all of the adjacent device layers. This sacrificial layer can then be replaced with an isolation layer to electrically isolate adjacent bit lines. The sacrificial layer may have etch selectivity with respect to the device layer.
  • Process vias can be formed that extend vertically relative to the substrate to pass through the stacks in the various device layers.
  • the sidewalls of the sacrificial layer can be exposed so that they can be replaced by spacers.
  • the semiconductor layers may be epitaxially grown on the sidewalls of the individual device layers exposed in the processing channels through the processing channels.
  • the active region, in particular the channel region, of the memory cell can be defined by this semiconductor layer. Therefore, the memory cell can be a nanosheet device, which helps to control the short-channel effect.
  • the above-mentioned semiconductor layer may be formed by epitaxial growth, and may be a single crystal semiconductor material. It is easier to form a single crystal active region than a conventional process of forming a plurality of gate stacks on top of each other and then forming a vertical active region through the gate stacks.
  • the source/drain regions may be formed in the semiconductor layer by laterally diffusing dopants in the source/drain defining layer into the semiconductor layer through an annealing process.
  • the location of the source/drain regions relative to the substrate may correspond to the location of the corresponding source/drain defining layers relative to the substrate.
  • the channel defining layer also contains dopants
  • the channel region in the semiconductor layer may also be doped to improve device performance such as improving short channel effects, adjusting threshold voltage, and the like.
  • the sidewalls of the device layer exposed in the processing channel may be recessed laterally to a certain depth via the processing channel prior to growing the semiconductor layer.
  • the grown semiconductor layers can be located in such recesses and can be substantially coplanar in the vertical direction so that the gate stacks subsequently formed in the processing channels can have relatively flat surfaces.
  • gate stacks can be formed.
  • etch selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a certain material layer is etched, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then such etching Can be selective, and the material layer can have etch selectivity relative to other layers exposed to the same etch recipe.
  • FIGS. 1 to 18(c) show schematic diagrams of some stages in the process of fabricating a NOR-type memory device according to an embodiment of the present disclosure.
  • the substrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • SiGe substrates SiGe substrates
  • a bulk Si substrate such as a Si wafer is used as an example for description.
  • a memory device such as a NOR type flash, may be formed as described below.
  • a cell in a memory device may be an n-type device or a p-type device.
  • an n-type memory cell is taken as an example for description, and for this purpose, a p-type well may be formed in the substrate 1001 . Accordingly, the following description, particularly with regard to doping types, is directed to the formation of n-type devices. However, the present disclosure is not limited thereto.
  • a sacrificial layer 1003 1 for defining an isolation layer, a first source/drain defining layer 1005 1 for defining a source/drain region, a first source/drain defining layer 1005 1 for defining a channel region may be formed by, for example, epitaxial growth.
  • a channel defining layer 1007 1 , a second source/drain defining layer 1009 1 for defining source/drain regions, a second channel defining layer 1011 1 for defining source/drain regions, and a second channel defining layer 1011 1 for defining source/drain regions The third source/drain defining layer 1013 1 .
  • the first source/drain defining layer 1005 1 , the first channel defining layer 1007 1 , the second source/drain defining layer 1009 1 , the second channel defining layer 1011 1 and the third source/drain defining layer 1013 1 will subsequently define
  • the positions of the active regions of the device which may be referred to as “device layers", are labeled L1 in the figure.
  • Each layer grown on the substrate 1001 may be a single crystal semiconductor layer. Since these layers are grown or doped separately, they may have crystal interfaces or doping concentration interfaces with each other.
  • the sacrificial layer 10031 may then be replaced with an isolation layer for isolating the device from the substrate, the thickness of which may correspond to the thickness of the isolation layer desired to be formed, eg, about 10 nm-50 nm. According to circuit design, the sacrificial layer 1003 1 may not be provided.
  • the first source/drain defining layer 1005 1 , the second source/drain defining layer 1009 1 and the third source/drain defining layer 1013 1 may be doped (eg, in situ during growth) to define the source/drain regions , whose thickness may be, for example, about 20 nm-50 nm.
  • the first channel defining layer 1007 1 and the second channel defining layer 1011 1 may define a gate length, and the thickness may correspond to the desired gate length, eg, about 15 nm-100 nm.
  • These semiconductor layers may include various suitable semiconductor materials, such as elemental semiconductor materials such as Si or Ge, compound semiconductor materials such as SiGe, and the like. In consideration of the following process, there may be etching selectivity between adjacent ones of these semiconductor layers.
  • the sacrificial layer 1003 1 , the first channel defining layer 1007 1 and the second channel defining layer 1011 1 may include SiGe (the atomic percentage of Ge is, for example, about 15-30%), the first source/drain defining layer 1005 1.
  • the second source/drain defining layer 1009 1 and the third source/drain defining layer 1013 1 may include Si.
  • first source/drain defining layer 1005 1 the second source/drain defining layer 1009 1 and the third source/drain defining layer 1013 1 , they may be doped in-situ for subsequent use in forming the source/drain Area.
  • n -type doping can be performed, and the doping concentration can be, for example, about 1E19-1E21 cm- 3 .
  • the device layer L2 can be provided on the device layer L1 by epitaxial growth, and the device layers are spaced apart by a sacrificial layer 1003 2 for defining an isolation layer.
  • a sacrificial layer 1003 2 for defining an isolation layer.
  • an isolation layer may not be provided between some device layers.
  • the device layer L2 may have a first source/drain defining layer 1005 2 , a first channel defining layer 1007 2 , a second source/drain defining layer 1009 2 , a second channel defining layer 1011 2 and a third source/drain defining layer 1009 2 . Drain defining layer 1013 2 .
  • Corresponding layers in each device layer may have the same or similar thicknesses and/or materials, or may have different thicknesses and/or materials.
  • a hard mask layer 1015 may be provided to facilitate patterning.
  • the hard mask layer 1015 may include nitride (eg, silicon nitride) with a thickness of about 50nm-200nm.
  • a sacrificial layer 1003 3 for defining an isolation layer may also be provided.
  • the sacrificial layers 1003 2 and 1003 3 reference may be made to the above description of the sacrificial layer 1003 1 .
  • the thicknesses of the sacrificial layers 1003 1 , 1003 2 and 1003 3 may be different from, eg, smaller than, the thicknesses of the channel defining layers 1007 1 , 1011 1 , 1007 2 and 1011 2 in consideration of the following processes.
  • the gate region may be defined using the machined vias.
  • a photoresist 1017 can be formed on the hard mask layer 1015 and patterned by photolithography to have a series of openings that can define the processing channels Location.
  • the openings can be of various suitable shapes, such as circular, rectangular, square, polygonal, etc., and of suitable size, such as a diameter or side length of about 20 nm to 500 nm.
  • the size of the opening may be larger than the thicknesses of the sacrificial layers 1003 1 , 1003 2 and 1003 3 and the thicknesses of the channel defining layers 1007 1 , 1011 1 , 1007 2 and 1011 2 .
  • the openings (especially in the device region) can be arranged in an array, for example a two-dimensional array along the horizontal and vertical directions in the sheet of Figure 2(a).
  • the array can then define an array of memory cells.
  • the openings are shown in FIG. 2(a) as being formed in substantially uniform size, substantially uniform density over the substrate (including the device regions where the memory cells will be later made and the contact regions where the contacts will later be made),
  • the present disclosure is not limited thereto.
  • the size and/or density of the openings can be varied, eg, the density of openings in the contact region can be less than the density of openings in the device region to reduce resistance in the contact region.
  • the photoresist 1017 thus patterned can be used as an etching mask to etch various layers on the substrate 1001 by anisotropic etching such as reactive ion etching (RIE), so as to form processing channels T.
  • RIE reactive ion etching
  • RIE may be performed in a generally vertical direction (eg, a direction perpendicular to the substrate surface) and may be performed into the substrate 1001 .
  • a series of vertical processing channels T are left on the substrate 1001 .
  • the processing channel T in the device region also defines the gate area. Afterwards, the photoresist 1017 can be removed.
  • the sidewalls of the sacrificial layer are exposed in the processing channel T.
  • the sacrificial layer can be replaced by an isolation layer via the exposed sidewalls.
  • the support layer may be formed in consideration of the support function for the device layers L1 and L2 during replacement.
  • a layer of support material may be formed on the substrate 1001 by, for example, deposition such as chemical vapor deposition (CVD) or the like.
  • the layer of support material may be formed in a substantially conformal manner.
  • the support material layer may comprise, for example, SiC.
  • the supporting material layer in part of the processing channels T can be removed, while the supporting material layers in the remaining processing channels T can be retained.
  • the remaining layer of support material forms the support layer 1019 .
  • the sacrificial layer can be replaced on the one hand by the processing channel in which the supporting layer 1019 is not formed, and on the other hand the device layers L1, L2 can be supported by the supporting layer 1019 in the other processing channel.
  • the photoresist 1021 may be removed.
  • the arrangement of the processing channels in which the support layer 1019 is formed and the processing channels in which the support layer 1019 is not formed can be achieved by patterning of the photoresist 1021, and they can be approximately uniformly distributed for process consistency and uniformity. As shown in FIG. 4 , the processing channels in which the supporting layers 1019 are formed and the processing channels in which the supporting layers 1019 are not formed may be alternately arranged.
  • the sacrificial layer can be replaced via the processing channel while the device layer is supported by the support layer 1019 .
  • both the sacrificial layer and the channel defining layer include SiGe.
  • the operation of replacing the isolation layer may affect the channel defining layer.
  • the protective plug can be formed self-aligned to the channel defining layer to avoid the channel defining layer being affected by the operation of replacing the isolation layer. It should be noted that, in the case where the sacrificial layer and the channel defining layer have etch selectivity with each other, the operation of forming the protective plug may be omitted.
  • the channel defining layers 1007 1 , 1011 1 , 1007 2 and 1011 2 can be relatively recessed laterally (relative to the upper and lower source/drain defining layers) by selective etching.
  • atomic layer etching ALE
  • ALE atomic layer etching
  • a guard gap that is self-aligned to the channel defining layer is formed.
  • protective plugs may be formed in the protective gaps.
  • the sacrificial layers 1003 1 to 1003 3 are relatively recessed to form isolation gaps.
  • a position maintaining plug may be formed in the isolation gap.
  • the layer 1002 of the position maintaining material may be formed by deposition.
  • the deposited thickness of the position maintaining material layer 1002 may be greater than half the thickness of the isolation gap (ie, the thickness of the sacrificial layer), but less than half the thickness of the guard gap (ie, the channel defining layer).
  • the layer of position maintaining material 1002 may not fill the processing channel.
  • atomic layer deposition ALD
  • the position maintaining material layer 1002 may include, for example, oxide.
  • the position retaining material layer 1002 may be removed to a certain thickness by selective etching.
  • the removed thickness may be substantially equal to or slightly greater than the deposited thickness of the layer 1002 of position maintaining material.
  • the layer of position maintaining material 1002 can be removed from the guard gap and left in the isolation gap to form position maintaining plugs 1002'.
  • ALE can be used for fine control of removal thickness.
  • protection plugs 1006 may be formed in the protection gap, as shown in FIG. 7 .
  • the protective plug 1006 may be formed by deposition followed by RIE in the vertical direction.
  • protective plug 1006 may comprise, for example, SiC (which may be removed in a subsequent process along with support layer 1019, which is also SiC; of course
  • the protective plug 1006 may also comprise a different material than the support layer 1019, in which case it may be removed by a separate etching in a subsequent step).
  • the support layer 1019 may be covered with a photoresist 1004 to prevent the support layer 1019 from being removed. Afterwards, the photoresist 1004 can be removed.
  • the position retaining plug 1002 ′ may be removed by selective etching through the processing channel T to expose the sacrificial layers 1003 1 , 1003 2 and 1003 3 , and the exposed sacrificial layers may be removed by selective etching 1003 1 , 1003 2 and 1003 3 .
  • the device layers L1, L2 Due to the presence of the support layer 1019, the device layers L1, L2 can be kept from collapsing.
  • a dielectric material can be filled by a process such as deposition (preferably ALD for better control of film thickness) followed by etch back (eg vertical RIE) to The isolation layers 1023 1 , 1023 2 and 1023 3 are formed.
  • Suitable dielectric materials such as oxides, nitrides, SiC, or combinations thereof, can be selected for various purposes such as optimizing isolation reliability, leakage current or capacitance, and the like.
  • the isolation layers 1023 1 , 1023 2 and 1023 3 may include oxide (eg, silicon oxide).
  • the position maintaining plug 1002' is formed first.
  • the thickness of the channel defining layer may be made smaller than the thickness of the sacrificial layer.
  • the protection plugs can be formed in the protection gaps self-aligned to the channel defining layers in a manner of forming the position retaining plugs 1002', and the space of the isolation gaps can be reserved. The sacrificial layer can be exposed through the isolation gap and thus can be replaced.
  • the source / The drain limiting layer is also recessed to some extent in the lateral direction.
  • the lateral concavity of the source/drain defining layers may be substantially the same as the lateral concavity of the channel defining layers such that they may have substantially coplanar sidewalls. Subsequently, a semiconductor layer can be grown on such substantially flat sidewalls.
  • the support layer 1019 may be removed by selective etching.
  • the protective plug 1006 may also be removed.
  • the sidewalls of the current device layer are laterally recessed to some extent relative to the sidewalls of the openings in the hardmask layer 1015 due to the above-described processes.
  • the sidewalls of the current device layer are consistent with the sidewalls of the openings in the hard mask layer 1015 .
  • the sidewalls of the device layers may also recessed to some extent laterally in the processing channel where the support layer 1019 was previously formed.
  • the lateral concavity of the sidewalls of the device layer in each processing channel may be substantially uniform. For example, as shown in FIG.
  • a photoresist 1008 may be formed and patterned to cover the processing channels where the support layer 1019 was not previously formed, while exposing the processing channels where the support layer 1019 was previously formed.
  • the device layers can be relatively recessed by selective etching.
  • the selective etching of the channel defining layer and the selective etching of the source/drain defining layer in the device layer may be performed separately, and their etching depths may be substantially the same. Afterwards, the photoresist 1008 can be removed.
  • semiconductor layers 1010 may be formed on the sidewalls of the respective device layers L1 and L2 by, for example, selective epitaxial growth.
  • the semiconductor layer 1010 may be formed as annular nanosheets around the processing channel, and may include various suitable semiconductor materials such as Si.
  • the material and/or thickness of semiconductor layer 1010 can be selected to improve device performance.
  • the semiconductor layer 1010 may include Ge, a group IV-IV compound semiconductor such as SiGe, a group III-V compound semiconductor, etc., to improve carrier mobility or reduce leakage current.
  • Vertically adjacent semiconductor layers 1010 may be isolated from each other by an isolation layer.
  • An annealing process may be performed to drive dopants in the source/drain defining layers into the semiconductor layer 1010 to form source/drain regions in portions of the semiconductor layer 1010 corresponding in height to the source/drain defining layers.
  • the doping distribution in the semiconductor layer 1010 can be mainly affected by the lateral diffusion from the device layer by controlling the process parameters such as the annealing time, and is not substantially affected by the vertical diffusion Influence or little effect of vertical diffusion.
  • the channel defining layer can also be in-situ doped during growth, so that during the annealing process, a certain doping profile can be formed in the portion of the semiconductor layer 1010 corresponding to the channel defining layer in height to define the channel region. doping properties.
  • the semiconductor layer 1010 may be in-situ doped during growth to define the doping characteristics of the channel region. Doping of the channel region can facilitate improving device performance such as improving short channel effects, adjusting threshold voltage (Vt), and the like.
  • Gate stacks may be formed in the processing vias, particularly in the device regions.
  • a memory function may be implemented by a gate stack.
  • a storage structure such as a charge trapping material or a ferroelectric material, may be included in the gate stack.
  • the memory function layer 1025 and the gate conductor layer 1027 may be sequentially formed, for example, by deposition.
  • the memory functional layer 1025 may be formed in a substantially conformal manner, and the gate conductor layer 1027 may fill the void remaining after the memory functional layer 1025 is formed in the processing channel T.
  • the formed gate conductor layer 1027 and the memory function layer 1025 can be planarized such as chemical mechanical polishing (CMP, for example, can stop at the hard mask layer 1015), so that the gate conductor layer 1027 and the memory function layer 1025 can be left in the processing channel In T, a gate stack is formed.
  • CMP chemical mechanical polishing
  • the storage functional layer 1025 may be based on dielectric charge trapping, ferroelectric material effects, or bandgap engineered charge storage (SONOS), among others.
  • the memory functional layer 1025 may include a dielectric tunneling layer (eg, an oxide with a thickness of about 1 nm-5 nm, which can be formed by oxidation or ALD), a band-shifting layer (eg, a nitride with a thickness of about 2 nm-10 nm, which may be formed) Formed by CVD or ALD) - spacer layer (eg oxide with a thickness of about 2 nm-6 nm, which can be formed by oxidation, CVD or ALD).
  • a dielectric tunneling layer eg, an oxide with a thickness of about 1 nm-5 nm, which can be formed by oxidation or ALD
  • a band-shifting layer eg, a nitride with a thickness of about 2 nm-10 nm, which may be
  • the memory functional layer 1025 may include a layer of a ferroelectric material, such as HfZrO 2 with a thickness of about 2 nm-20 nm.
  • the gate conductor layer 1027 may comprise eg (doped, eg p-doped in the case of n-type devices) polysilicon or metal gate material.
  • the channel defining layer can be removed so that the channel region can be completely formed in the semiconductor layer 1010 .
  • a nanosheet device can be obtained.
  • a mask layer 1012 such as an oxide, can be formed over the hard mask layer 1015 and patterned to expose areas where processing vias need to be formed. Process vias may be formed where gate stacks are not provided.
  • every several memory cells in the example of FIG. 12 ( a ) may be provided along the first direction (the vertical direction in the paper plane in FIG. 12 ( a )).
  • a processing channel extending in a second direction (horizontal direction in the paper plane in FIG. 12(a) ) intersecting (eg, perpendicular) to the first direction is provided.
  • the photoresist 1012 as an etching mask, the underlying layers are etched by anisotropic etching such as RIE in the vertical direction. Etching may proceed into the substrate 1001, thereby defining processing channels in which the respective channel defining layers are exposed. Each channel defining layer may be removed by selective etching through the processing channel.
  • a dielectric 1014 such as oxide
  • a dielectric 1014 can be filled in the voids (and machined vias) left by the removal of the channel-defining layer by deposition for structural support and electrical isolation.
  • the deposited dielectric 1014 may be subjected to a planarization process such as CMP.
  • Mask layer 1012 is shown integrally with dielectric 1014 since it also includes oxide.
  • the gate stack ( 1025 / 1027 ) with the memory functional layer is surrounded by the semiconductor layer 1010 .
  • the gate stack cooperates with the semiconductor layer 1010 to define memory cells, as shown by the dashed circles in FIG. 13 .
  • the source/drain regions are formed in the upper and lower ends of the semiconductor layer 1010 corresponding to the source/drain defining layers, and the channel regions are formed in the middle portion corresponding to the channel defining layers.
  • the channel region may connect the source/drain regions at opposite ends, and the channel region may be controlled by the gate stack.
  • the gate stack extends in a column shape in a vertical direction and overlaps a plurality of semiconductor layers, thereby defining a plurality of memory cells that are stacked on each other in a vertical direction.
  • Memory cells associated with a single gate stack pillar may form memory cell strings.
  • a plurality of such strings of memory cells are arranged on the substrate, thereby forming a three-dimensional (3D) array of memory cells.
  • a single gate stack pillar may define two memory cells in a single device layer, as shown by the two dotted circles in the device layer L1 in FIG. 13 .
  • the two memory cells may share the same source/drain region (a portion in the semiconductor layer 1010 corresponding in height to the middle second source/drain defining layer 1009 1 or 1009 2 ), and The source line may be electrically connected through the second source/drain defining layer 1009 1 or 1009 2 .
  • the other source/drain regions of the two memory cells may be electrically connected to different bit lines through corresponding source/drain defining layers, respectively. That is, the source/drain defining layer may serve as an interconnect structure for electrically connecting the source/drain regions of the memory cells to bit lines or source lines.
  • the channel region is formed in the semiconductor layer 1010 in the form of annular nanosheets, so the device can be a nanosheet or nanowire device, which can achieve good short channel effect control and power consumption reduction.
  • a stepped structure may be formed in the contact regions.
  • the stepped structure may be formed as follows, for example.
  • a photoresist 1031 may be formed on the dielectric 1014 (including the mask layer 1012) and patterned to mask the device regions by photolithography. Expose the contact area. Using the photoresist 1031 as an etch mask, the dielectric 1014, the hard mask layer 1015, the isolation layer 1023 , and the gate stack are etched by selective etching such as RIE to expose the device layers. By controlling the etching depth, the surface exposed by the photoresist 1031 in the contact area after etching can be made substantially flat.
  • the dielectric 1014 over the hard mask layer 1015 may be etched first to expose the gate stack; then the gate conductor layer 1027 may be etched, and the etching of the gate conductor layer 1027 may be stopped near the top surface of the device layer L2; then, the gate conductor layer 1027 may be etched
  • the hard mask layer 1015 and the isolation layer 1023 3 are sequentially etched; after such etching, the top of the memory functional layer 1025 may protrude above the top surface of the device layer L2 and may be removed by RIE. In this way, a step is formed between the contact area and the device area. Afterwards, the photoresist 1031 may be removed.
  • the spacer 1033 may be formed at the step between the contact region and the device region through a spacer forming process.
  • lateral extensions of the deposited dielectric can be removed by depositing a layer of dielectric such as oxide in a substantially conformal manner, followed by anisotropic etching such as vertical RIE of the deposited dielectric, The vertically extending portion thereof is left, thereby forming the side wall 1033 .
  • the etch depth of the RIE can be controlled to be substantially equal to or slightly larger than the deposition thickness of the dielectric to avoid completely removing the dielectric 1014 above the hard mask layer 1015 .
  • the width of the spacers 1033 (in the horizontal direction in the figure) may be substantially equal to the deposition thickness of the dielectric.
  • the width of the sidewall spacers 1033 defines the size of the landing pads that follow the contacts to the third source/drain defining layer 10132 in the device layer L2.
  • the exposed third source/drain defining layer 1013 2 , the dielectric 1014 and the gate stack can be etched by selective etching such as RIE to expose the exposed third source/drain defining layer 1013 2 , the dielectric 1014 and the gate stack.
  • the second source/drain defining layer 1009 2 By controlling the etching depth, the surface exposed by the sidewall spacers 1033 in the contact region after etching can be made substantially flat.
  • the gate conductor layer 1027 may be etched first (in the case where the gate conductor layer 1027 includes polysilicon, the third source/drain defining layer 1013 2 of Si here may also be at least partially etched), and the etching may be stopped at the first Near the top surface of the second source/drain defining layer 10092; the third source/drain defining layer 10132 can then be etched (eg, not fully etched before; or the gate conductor layer 1027 includes a metal gate, thus using a (selective etching recipe), the etching can stop at the dielectric 1014; then the dielectric 1014 is etched, and the etching can stop at the second source/drain defining layer 1009 2 ; after such etching, the top of the memory functional layer 1025 can be Protrudes over the top surface of the second source/drain defining layer 1009 2 and can be removed by RIE. In this way, a further step is formed between the third source/drain defining layer 1013 2 and the surface exposed
  • a plurality of steps can be formed in the contact area by forming sidewall spacers and performing etching using the sidewall spacers as an etching mask according to the process described above in conjunction with FIGS. 15(a) and 15(b), as shown in FIG. 16(a). ) and 16(b). These steps form a stepped structure such that for each layer in each device layer that needs to be electrically connected, such as the source/drain defining layer described above, its ends protrude relatively with respect to the upper layer to define the contact portion to the layer. landing pads. 1035 in Figures 16(a) and 16(b) represents the remaining portion of the sidewalls formed each time after processing.
  • the contacts can be made.
  • the interlayer dielectric layer 1037 may be formed by depositing oxide and planarizing such as CMP.
  • oxide and planarizing such as CMP.
  • other oxide components such as the spacers 1035 are shown as one body with the interlayer dielectric layer 1037 .
  • contacts 1039 , 1041 may be formed in the interlayer dielectric layer 1037 .
  • a contact portion 1039 is formed in the device region and is electrically connected to the gate conductor layer 1027 in the gate stack;
  • a contact portion 1041 is formed in the contact region and is electrically connected to each source/drain defining layer.
  • the contact portion 1041 in the contact region may avoid the gate stack remaining in the contact region.
  • These contacts may be formed by etching holes in the interlayer dielectric layer 1037 and filling them with a conductive material such as metal.
  • the contact portion 1039 may be electrically connected to the word line.
  • the gate control signal can be applied to the gate conductor layer 1027 via the contact portion 1039 through the word line.
  • the source/drain defining layers in the middle ie the second source/drain defining layers 1009 1 , 1009 2
  • contacts 1041 is electrically connected to the source line;
  • the source/drain defining layers at the upper and lower ends namely the first source/drain defining layers 1005 1 , 1005 2 and the third source/drain defining layers 1013 1 , 1013 2
  • the present disclosure is not limited thereto.
  • only a single memory cell may be formed in one device layer.
  • only the first source/drain defining layer, the first channel defining layer, and the second source/drain defining layer may be arranged in the device layer, and the second channel defining layer and the third source/drain defining layer need not be arranged Floor.
  • FIG. 21 schematically shows an equivalent circuit diagram of a NOR type memory device according to an embodiment of the present disclosure.
  • bit lines WL1 , WL2 , WL3 and eight bit lines BL1 , BL2 , BL3 , BL4 , BL5 , BL6 , BL7 , BL8 are schematically shown.
  • a memory cell MC is provided where the bit line and the word line intersect.
  • Also shown in FIG. 21 are four source lines SL1, SL2, SL3, SL4. As described above, every two layers of adjacent memory cells in the vertical direction may share the same source line connection.
  • the respective source lines may be connected to each other, so that the respective memory cells MC may be connected to a common source line.
  • a two-dimensional array of memory cells MC is shown.
  • a plurality of such two-dimensional arrays may be arranged in a direction intersecting this two-dimensional array (eg, a direction perpendicular to the paper in the figure), thereby obtaining a three-dimensional array.
  • the extending direction of the word lines WL1 to WL3 in FIG. 21 may correspond to the extending direction of the gate stack, that is, the vertical direction relative to the substrate in the foregoing embodiments. In this direction, adjacent bit lines are isolated from each other. This is also the reason why an isolation layer is provided between vertically adjacent device layers in the above embodiments.
  • the contact portion 1041 in the contact region needs to avoid the gate stack remaining in the contact region.
  • isolation such as a dielectric material, may be formed on top of the remaining gate stacks in the contact regions, so that these remaining gate stacks do not need to be deliberately avoided.
  • the spacers 1035 are removed to expose the top of each gate stack (in the device and contact regions).
  • the gate stack in the device region may be masked by a masking layer such as photoresist, while the gate stack in the contact region may be exposed.
  • the gate conductor layer can be recessed by, for example, about 50 nm-150 nm by selective etching such as RIE. After that, the masking layer can be removed.
  • the voids in the contact regions formed by the recess of the gate conductor layer may be filled with a dielectric material such as SiC, for example, by deposition and then etch back, to form isolation plugs 1016 .
  • an interlayer dielectric layer may be formed and the contacts 1039, 1041' formed therein according to the above-described embodiments.
  • the contact portion 1041 ′ in the contact region may extend into the isolation plug 1016 . Therefore, the contact portion 1041' may not be limited to the form of the above-described plug, but may be formed in a strip shape to reduce contact resistance.
  • the strip-shaped contacts 1041' may extend along the landing pads (ie, steps in the stepped structure) of the corresponding layers.
  • the contact portions are in direct contact with the corresponding landing pads.
  • silicide may be formed at the landing pad to reduce contact resistance. More specifically, at each step of the contact region, the lateral surfaces of the step serve as landing pads on which silicide can be formed. On the other hand, on the vertical surfaces of the steps, silicide may not be formed to avoid shorting between the respective landing pads of adjacent steps.
  • Dielectric spacers 1047 such as nitride, may be formed on the vertical surfaces of each step through a spacer forming process to shield these vertical surfaces from subsequent silicidation reactions. The exposed lateral surfaces of each step may then be silicided.
  • a metal such as NiPt can be deposited and annealed to cause silicidation of the deposited metal with the semiconductor material (eg, Si) at the lateral surfaces of the steps, resulting in a conductive metal suicide 1049 such as NiPtSi. Afterwards, unreacted metals can be removed.
  • the semiconductor material eg, Si
  • the gate conductor layer 1027 is, for example, polysilicon, so the top of the gate conductor layer 1027 can also undergo silicidation reaction and be covered by silicide.
  • a protective layer eg, nitride
  • the gate conductor layer 1027 can be prevented from being damaged by etching when the metal is removed in the silicidation process.
  • an interlayer dielectric layer may be formed as described above, and the contacts 1039, 1041 may be formed therein.
  • Silicide 1049 can be used as an etch stop when etching the holes for the contacts. Therefore, the etching depth of the holes can be better controlled.
  • the memory device may be applied to various electronic devices.
  • a storage device may store various programs, applications, and data required for the operation of an electronic device.
  • the electronic device may also include a processor in cooperation with the memory device.
  • a processor may operate an electronic device by running a program stored in a storage device.
  • Such electronic devices are, for example, smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, or power banks.

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Abstract

一种NOR型存储器件及其制造方法及包括该NOR型存储器件的电子设备。根据实施例，该NOR型存储器件可以包括：在衬底上竖直延伸的栅堆叠，栅堆叠包括栅导体层和存储功能层；以及围绕栅堆叠的外周、沿栅堆叠的侧壁延伸的第一半导体层和第二半导体层，第一半导体层和第二半导体层相对于衬底分别处于不同的高度处。存储功能层介于第一半导体层与栅导体层以及第二半导体层与栅导体层之间。第一半导体层和第二半导体层中的每一个包括在竖直方向上依次设置的第一源/漏区、沟道区和第二源/漏区。在栅堆叠与第一半导体层相交之处以及在栅堆叠与第二半导体层相交之处分别限定存储单元。

Description

NOR型存储器件及其制造方法及包括存储器件的电子设备
相关申请的引用
本申请要求于2021年3月8日递交的题为“NOR型存储器件及其制造方法及包括存储器件的电子设备”的中国专利申请202110252871.2的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，具体地，涉及NOR型存储器件及其制造方法以及包括这种存储器件的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，水平型器件不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件更容易缩小。
对于竖直型器件，可以通过彼此叠置来增加集成密度。但是，这可能会导致性能变差。因为为了方便叠置多个器件，通常使用多晶硅来作为沟道材料，导致与单晶硅的沟道材料相比电阻变大。另外，也期望能够单独调节源/漏区与沟道中的掺杂水平。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有改进性能的NOR型存储器件及其制造方法以及包括这种存储器件的电子设备。
根据本公开的一个方面，提供了一种竖直型存储器件，包括：在衬底上竖直延伸的栅堆叠，栅堆叠包括栅导体层和存储功能层；以及围绕栅堆叠的外周、沿栅堆叠的侧壁延伸的第一半导体层和第二半导体层，第一半导体层和第二半导体层相对于衬底分别处于不同的高度处。存储功能层介于第一半导体层与栅导体层以及第二半导体层与栅导体层与之间。第一半导体层和第二半导体层中 的每一个包括在竖直方向上依次设置的第一源/漏区、沟道区和第二源/漏区。在栅堆叠与第一半导体层相交之处以及在栅堆叠与第二半导体层相交之处分别限定存储单元。
根据本公开的另一方面，提供了一种制造竖直型存储器件的方法，包括：在衬底上设置多个器件层，每个器件层包括第一源/漏限定层、第一沟道限定层和第二源/漏限定层的叠层；形成相对于衬底竖直延伸以穿过各个器件层中的叠层的加工通道；通过加工通道，在各个器件层在加工通道中露出的侧壁上外延生长半导体层；以及在加工通道中形成栅堆叠，栅堆叠包括栅导体层和设置在栅导体层与半导体层之间的存储功能层，在栅堆叠与半导体层相交之处限定存储单元。
根据本公开的另一方面，提供了一种电子设备，包括上述NOR型存储器件。
根据本公开的实施例，可以使用单晶材料的叠层作为构建模块，来建立三维(3D)NOR型存储器件。因此，在彼此叠置多个存储单元时，可以抑制电阻的增大。另外，半导体层可以是纳米片的形式，这特别有利于控制器件的短沟道效应，而且还利于降低器件的高度和增加器件层的层数，提高集成密度。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至18(c)示出了根据本公开实施例的制造NOR型存储器件的流程中部分阶段的示意图；
图19(a)和19(b)示出了根据本公开另一实施例的制造NOR型存储器件的流程中部分阶段的示意图；
图20(a)和20(b)示出了根据本公开另一实施例的制造NOR型存储器件的流程中部分阶段的示意图；
图21示意性示出了根据本公开实施例的NOR型存储器件的等效电路图，
其中，图2(a)、12(a)、14(a)、18(a)、19(a)是俯视图，图2(a)中示出了AA′线、BB′线的位置，
图1、2(b)、3至11、12(b)、13、14(b)、15(a)、16(a)、17(a)、18(b)、19(b)、20(a)是沿AA′线的截面图，
图14(c)、15(b)、16(b)、17(b)、18(c)、20(b)是沿BB′线的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开实施例的存储器件基于竖直型器件。竖直型器件可以包括在衬底上沿竖直方向(大致垂直于衬底表面的方向)设置的有源区，包括设于上下两端的源/漏区以及位于源/漏区之间的沟道区。源/漏区之间可以通过沟道区形成导电通道。在有源区中，源/漏区和沟道区例如可以通过掺杂浓度来限定。
根据本公开的实施例，有源区可以由竖直延伸的半导体层来限定。源/漏区可以分别形成在半导体层的相对两端，沟道区可以形成在半导体层的中部。栅堆叠可以延伸穿过该半导体层，从而有源区可以围绕栅堆叠的外周。于是，半导体层可以呈现围绕栅堆叠的环形纳米片的形式。在此，栅堆叠可以包括存储功能层如电荷捕获材料或铁电材料中至少之一，以便实现存储功能。这样，栅堆叠同与之相对的有源区相配合而限定存储单元。在此，存储单元可以是闪 存(flash)单元。
由于竖直型器件易于叠置的特性，可以在竖直方向上设置多个这样的半导体层。栅堆叠可以竖直延伸，从而穿过这多个半导体层。这多个半导体层可以在竖直方向上实质上共面，例如沿着栅堆叠的侧壁延伸。这样，对于单个栅堆叠而言，与竖直方向上叠置的这多个半导体层相交而限定在竖直方向上叠置的多个存储单元。
可以设置多个这样的栅堆叠，每个栅堆叠可以类似地穿过多个半导体层，从而在这多个栅堆叠与这些半导体层相交之处限定多个存储单元。这些存储单元可以在竖直方向上排列成多个层级，各层级内的存储单元排列成与该多个栅堆叠相对应的阵列(例如，通常是按行和列排列的二维阵列)。于是，可以得到存储单元的三维(3D)阵列。每一层级内的存储单元(或者说，半导体层)可以实质上共面。
在NOR(“或非”)型存储器件中，各存储单元可以连接到公共的源极线。鉴于这种配置，为节省布线，在竖直方向上，每两个相邻的存储单元可以共用相同的源极线连接。例如，上述半导体层可以包括(第一)源/漏区-(第一)沟道区-(第二)源/漏区-(第二)沟道区-(第三)源/漏区的配置。这样，第一源/漏区、第一沟道区和第二源/漏区可以如上所述与栅堆叠相配合而限定第一存储单元，另外第二源/漏区、第二沟道区和第三源/漏区同样可以与栅堆叠相配合而限定第二存储单元。第一存储单元和第二存储单元彼此叠置，且共用相同的第二源/漏区，该第二源/漏区可以电连接到源极线。
为实现到源/漏区的电连接，可以设置与源/漏区相接触的互连层。根据本公开的实施例，每一层级中的存储单元的相应源/漏区可以通过相同的互连层而电连接到位线或源极线。于是，互连层可以形成为围绕相应层级内的各源/漏区，从而整体上可以呈现板状，各半导体层穿过该板状的互连层。互连层可以从存储单元所在的器件区延伸到要形成接触区，以便之后制作到互连层的接触部。
源/漏区可以由相应的互连层来限定。例如，可以通过将互连层中的掺杂剂在横向上驱入到半导体层中来形成源/漏区。因此，互连层与相应的源/漏区可以在横向上实质上共面。
这种竖直型存储器件例如可以如下制造。具体地，可以在衬底上设置多个器件层，每个器件层包括第一源/漏限定层、第一沟道限定层和第二源/漏限定层(以及可选地，第二沟道限定层和第三源/漏限定层)的叠层。例如，这些层可以通过外延生长来提供，并可以是单晶半导体材料。在外延生长时，可以控制所生长的各层特别是沟道限定层的厚度。另外，在外延生长时，可以对叠层中的各层特别是源/漏限定层进行原位掺杂，以实现所需的掺杂极性和掺杂浓度。在此，沟道层与源/漏限定层之间可以具有刻蚀选择性。
在至少一部分乃至全部相邻的器件层之间，可以形成牺牲层。这种牺牲层随后可以被替换为隔离层，以电隔离相邻的位线。牺牲层可以相对于器件层具有刻蚀选择性。
可以形成相对于衬底竖直延伸以穿过各个器件层中的叠层的加工通道。在加工通道中，可以露出牺牲层的侧壁，从而可以将之替换为隔离层。可以通过加工通道，在各个器件层在加工通道中露出的侧壁上外延生长半导体层。随后，可以由该半导体层来限定存储单元的有源区，特别是沟道区。因此，存储单元可以是纳米片器件，这有助于控制短沟道效应。上述半导体层可以通过外延生长而形成，并可以为单晶半导体材料。与形成彼此叠置的多个栅堆叠，再形成穿过这些栅堆叠的竖直有源区的常规工艺相比，更容易形成单晶的有源区。
可以通过退火处理，使源/漏限定层中的掺杂剂在横向上扩散到半导体层中，以便在半导体层中形成源/漏区。源/漏区相对于衬底的位置可以对应于相应的源/漏限定层相对于衬底的位置。在沟道限定层也包含掺杂剂的情况下，半导体层中的沟道区也可以被掺杂，以改进器件性能如改善短沟道效应、调节阈值电压等。通过源/漏限定层和沟道限定层的掺杂特性，可以相对容易地分别调节源/漏区和沟道区的掺杂特性。
在生长半导体层之前，可以经由加工通道，使器件层在加工通道中露出的侧壁在横向上凹进一定深度。生长的半导体层可以位于这种凹进中，并可以在竖直方向上实质上共面，以便随后在加工通道中形成的栅堆叠可以具有相对平整的表面。
在加工通道中，可以形成栅堆叠。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中， 涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离，导电材料用于形成电极、互连结构等)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至18(c)示出了根据本公开实施例的制造NOR型存储器件的流程中部分阶段的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底如Si晶片为例进行描述。
在衬底1001上，可以如下所述形成存储器件，例如NOR型闪存(flash)。存储器件中的存储单元(cell)可以是n型器件或p型器件。在此，以n型存储单元为例进行描述，为此衬底1001中可以形成有p型阱。因此，以下的描述，特别是关于掺杂类型的描述，针对n型器件的形成。但是，本公开不限于此。
在衬底1001上，可以通过例如外延生长，形成用于限定隔离层的牺牲层1003 1、用于限定源/漏区的第一源/漏限定层1005 1、用于限定沟道区的第一沟道限定层1007 1、用于限定源/漏区的第二源/漏限定层1009 1、用于限定沟道区的第二沟道限定层1011 1以及用于限定源/漏区的第三源/漏限定层1013 1。第一源/漏限定层1005 1、第一沟道限定层1007 1、第二源/漏限定层1009 1、第二沟道限定层1011 1和第三源/漏限定层1013 1随后将限定器件的有源区位置，可以将它们称作“器件层”，图中标示为L1。
衬底1001上所生长的各层可以是单晶的半导体层。这些层由于分别生长或者掺杂，从而彼此之间可以具有晶体界面或掺杂浓度界面。
牺牲层1003 1随后可以被替换为用于将器件与衬底隔离的隔离层，其厚度可以对应于希望形成的隔离层的厚度，例如为约10nm-50nm。根据电路设计， 也可以不设置牺牲层1003 1。第一源/漏限定层1005 1、第二源/漏限定层1009 1和第三源/漏限定层1013 1可以被掺杂(例如，在生长时原位掺杂)来限定源/漏区，其厚度例如可以为约20nm-50nm。第一沟道限定层1007 1和第二沟道限定层1011 1可以限定栅长，其厚度可以对应于希望形成的栅长，例如为约15nm-100nm。
这些半导体层可以包括各种合适的半导体材料，例如元素半导体材料如Si或Ge、化合物半导体材料如SiGe等。考虑到以下工艺，这些半导体层中相邻的半导体层之间可以具有刻蚀选择性。例如，牺牲层1003 1、第一沟道限定层1007 1和第二沟道限定层1011 1可以包括SiGe(Ge的原子百分比例如为约15％-30％)，第一源/漏限定层1005 1、第二源/漏限定层1009 1和第三源/漏限定层1013 1可以包括Si。
在生长第一源/漏限定层1005 1、第二源/漏限定层1009 1和第三源/漏限定层1013 1时，可以对它们进行原位掺杂，以便随后用来形成源/漏区。例如，对于 n型器件，可以进行 n型掺杂，掺杂浓度可以为例如约1E19-1E21cm- 3。
为增加集成密度，可以设置多个器件层。例如，可以通过外延生长，在器件层L1上设置器件层L2，器件层之间通过用于限定隔离层的牺牲层1003 2间隔开。尽管图1中仅示出了两个器件层，但是本公开不限于此。根据电路设计，某些器件层之间也可以不设置隔离层。类似地，器件层L2可以具有第一源/漏限定层1005 2、第一沟道限定层1007 2、第二源/漏限定层1009 2、第二沟道限定层1011 2以及第三源/漏限定层1013 2。各器件层中相应的层可以具有相同或相似的厚度和/或材料，也可以具有不同的厚度和/或材料。在此，仅为方便描述起见，假设各器件层L1和L2具有相同的配置。
在衬底1001上形成的这些层上，可以设置硬掩模层1015，以方便构图。例如，硬掩模层1015可以包括氮化物(例如，氮化硅)，厚度为约50nm-200nm。
在硬掩模层1015与器件层L2之间，也可以设置用于限定隔离层的牺牲层1003 3。关于牺牲层1003 2和1003 3，可以参见以上关于牺牲层1003 1的描述。考虑到以下工艺，牺牲层1003 1、1003 2和1003 3的厚度可以不同于，例如小于，沟道限定层1007 1、1011 1、1007 2和1011 2的厚度。
以下，一方面，需要能到达牺牲层的加工通道，以便将牺牲层替换为隔离 层；另一方面，需要限定用于形成栅的区域。根据本公开的实施例，这两者可以结合进行。具体地，可以利用加工通道来限定栅区域。
例如，如图2(a)和2(b)所示，可以在硬掩模层1015上形成光刻胶1017，并通过光刻将其构图为具有一系列开口，这些开口可以限定加工通道的位置。开口可以是各种合适的形状，例如圆形、矩形、方形、多边形等，并具有合适的大小，例如直径或边长为约20nm-500nm。考虑到以下工艺，开口的尺寸可以大于牺牲层1003 1、1003 2和1003 3的厚度以及沟道限定层1007 1、1011 1、1007 2和1011 2的厚度。在此，这些开口(特别是在器件区中)可以排列成阵列形式，例如沿图2(a)中纸面内水平方向和竖直方向的二维阵列。该阵列随后可以限定存储单元的阵列。尽管在图2(a)中将开口示出为以基本上一致的大小、大致均匀的密度形成在衬底(包括随后将制作存储单元的器件区以及随后将制作接触部的接触区)上，但是本公开不限于此。开口的大小和/或密度可以改变，例如接触区中开口的密度可以小于器件区中开口的密度，以降低接触区中的电阻。
如图3所示，可以如此构图的光刻胶1017作为刻蚀掩模，通过各向异性刻蚀如反应离子刻蚀(RIE)，来刻蚀衬底1001上的各层，以便形成加工通道T。RIE可以沿大致竖直的方向(例如，垂直于衬底表面的方向)进行，并可以进行到衬底1001中。于是，在衬底1001上留下了一系列竖直的加工通道T。器件区中的加工通道T还限定了栅区域。之后，可以去除光刻胶1017。
当前，牺牲层的侧壁在加工通道T中露出。于是，可以经由露出的侧壁，将牺牲层替换为隔离层。考虑到替换时对器件层L1、L2的支撑功能，可以形成支撑层。
例如，如图4所示，可以通过例如淀积如化学气相淀积(CVD)等，在衬底1001上形成支撑材料层。支撑材料层可以大致共形的方式形成。考虑到刻蚀选择性，特别是相对于硬掩模层1015(在该示例中为氮化物)以及随后形成的隔离层(在该示例中为氧化物)，支撑材料层可以包括例如SiC。可以例如通过形成光刻胶1021，并配合光刻胶1021进行选择性刻蚀如RIE，去除部分加工通道T中的支撑材料层，而保留其余加工通道T中的支撑材料层。留下的支撑材料层形成支撑层1019。这样，一方面可以通过其中没有形成支 撑层1019的加工通道来替换牺牲层，另一方面可以通过其他加工通道中的支撑层1019来支撑器件层L1、L2。之后，可以去除光刻胶1021。
其中形成有支撑层1019的加工通道与其中没有形成支撑层1019的加工通道的排布可以通过光刻胶1021的构图来实现，并且为了工艺的一致性和均匀性，它们可以大致均匀地分布。如图4中所示，其中形成有支撑层1019的加工通道与其中没有形成支撑层1019的加工通道可以交替排列。
于是，可以在由支撑层1019支撑器件层的同时经由加工通道来替换牺牲层。但是，在本示例中，牺牲层与沟道限定层均包括SiGe。这种情况下，替换隔离层的操作可能影响到沟道限定层。可以形成自对准于沟道限定层的保护插塞，来避免沟道限定层受到替换隔离层的操作的影响。需要指出的是，在牺牲层与沟道限定层彼此之间具有刻蚀选择性的情况下，可以省略形成保护插塞的操作。
例如，如图5所示，可以通过选择性刻蚀，使沟道限定层1007 1、1011 1、1007 2和1011 2在横向上(相对于上下的源/漏限定层)相对凹入。为很好地控制刻蚀深度，可以采用原子层刻蚀(ALE)。于是，形成了自对准于沟道限定层的保护间隙。之后，可以在保护间隙中形成保护插塞。在此，同样地牺牲层1003 1至1003 3会相对凹入，从而形成隔离间隙。
为避免保护插塞也形成在隔离间隙中从而妨碍替换牺牲层，可以在隔离间隙中形成位置保持插塞。例如，可以通过淀积，形成位置保持材料层1002。位置保持材料层1002的淀积厚度可以大于隔离间隙的厚度(即，牺牲层的厚度)的一半，但小于保护间隙的厚度(即，沟道限定层)的一半。另外，由于加工通道的尺寸相对较大，位置保持材料层1002可以并未填满加工通道。为很好地控制淀积厚度，可以采用原子层淀积(ALD)。考虑到刻蚀选择性，位置保持材料层1002可以包括例如氧化物。
之后，如图6所示，可以通过选择性刻蚀，去除一定厚度的位置保持材料层1002。例如，去除厚度可以基本等于或略大于位置保持材料层1002的淀积厚度。于是，位置保持材料层1002可以从保护间隙中去除，而留于隔离间隙中，形成位置保持插塞1002′。为很好地控制去除厚度，可以采用ALE。
接下来，可以在保护间隙中形成保护插塞1006，如图7所示。例如，可 以通过淀积然后沿竖直方向进行RIE来形成保护插塞1006。考虑到刻蚀选择性(相对于位置保持插塞1002′、硬掩模层1015)，保护插塞1006可以包括例如SiC(在后继工艺中可以与同样为SiC的支撑层1019被一同去除；当然保护插塞1006也可以包括不同于支撑层1019的材料，这种情况下其在后继步骤中可以通过单独的刻蚀来去除)。在为形成保护插塞1006而进行刻蚀时，可以利用光刻胶1004来覆盖支撑层1019，以避免支撑层1019被去除。之后，可以去除光刻胶1004。
然后，如图8所示，可以经由加工通道T，通过选择性刻蚀去除位置保持插塞1002′以露出牺牲层1003 1、1003 2和1003 3，并通过选择性刻蚀去除露出的牺牲层1003 1、1003 2和1003 3。由于支撑层1019的存在，可以保持器件层L1、L2不会坍塌。在由于牺牲层的去除而留下的空隙中，可以通过例如淀积(优选为ALD，以更好地控制膜厚)然后回蚀(例如，竖直方向的RIE)的工艺，填充电介质材料以形成隔离层1023 1、1023 2和1023 3。可以出于各种目的例如优化隔离的可靠性、漏电流或电容等，选择合适的电介质材料，例如氧化物、氮化物、SiC或其组合。在此，考虑到刻蚀选择性，隔离层1023 1、1023 2和1023 3可以包括氧化物(例如，氧化硅)。
在以上示例中，为形成保护插塞1006，先形成了位置保持插塞1002′。但是，本公开不限于此。例如，可以使沟道限定层的厚度小于牺牲层的厚度。这种情况下，可以按照形成位置保持插塞1002′的方式，在自对准于沟道限定层的保护间隙中形成保护插塞，而可以保留隔离间隙的空间。牺牲层可以通过隔离间隙露出，并因此可以被替换。
由于之前为了形成自对准的保护插塞1006而使沟道限定层相对凹进，考虑到后继的半导体层生长工艺以及生长的半导体层之间的隔离，可以通过选择性刻蚀，使源/漏限定层也在横向上凹进一定程度。源/漏限定层的横向凹进程度可以与沟道限定层的横向凹进程度基本上相同，从而它们可以具有基本共面的侧壁。随后，可以在这样实质上平坦的侧壁上生长半导体层。
之后，可以通过选择性刻蚀，去除支撑层1019。在去除支撑层1019的同时，保护插塞1006也可以被去除。
在之前并未形成有支撑层1019的加工通道中，当前器件层的侧壁由于上 述处理而相对于硬掩模层1015中的开口的侧壁在横向上凹进一定程度。而在之前形成有支撑层1019的加工通道中，当前器件层的侧壁与硬掩模层1015中的开口的侧壁保持一致。考虑随后生长的半导体层之间的隔离，同样可以使器件层的侧壁在之前形成有支撑层1019的加工通道中也在横向上凹进一定程度。器件层的侧壁在各加工通道中的横向凹进程度可以基本上一致。例如，如图9所示，可以形成光刻胶1008，并将其构图为覆盖之前并未形成有支撑层1019的加工通道，而露出之前形成有支撑层1019的加工通道。通过露出的这些加工通道，可以通过选择性刻蚀，使器件层相对凹进。对器件层中沟道限定层的选择性刻蚀和源/漏限定层的选择性刻蚀可以分别进行，它们的刻蚀深度可以基本相同。之后，可以去除光刻胶1008。
然后，如图10所示，可以通过例如选择性外延生长，在各器件层L1、L2的侧壁上分别形成半导体层1010。半导体层1010可以形成为绕加工通道的环形纳米片，并可以包括各种合适的半导体材料如Si。可以选择半导体层1010的材料和/或厚度，以改进器件性能。例如，半导体层1010可以包括Ge、IV-IV族化合物半导体如SiGe、III-V族化合物半导体等，以改进载流子迁移率或者降低漏电流。竖直方向上相邻的半导体层1010之间可以通过隔离层彼此隔离。
可以进行退火处理，以将源/漏限定层中的掺杂剂驱入半导体层1010中，从而在半导体层1010在高度上与源/漏限定层相对应的部分中形成源/漏区。在此，由于半导体层1010相对较薄，可以通过控制工艺参数如退火时间，使得半导体层1010中的掺杂分布主要受源自器件层的横向扩散影响，而基本不受竖直方向上的扩散影响或者受竖直方向上的扩散影响很小。沟道限定层在生长时也可以被原位掺杂，从而在退火处理时半导体层1010在高度上与沟道限定层相对应的部分中可以形成一定的掺杂分布，以限定沟道区的掺杂特性。或者，半导体层1010在生长时可以被原位掺杂，以限定沟道区的掺杂特性。沟道区的掺杂可以便于改进器件性能如改善短沟道效应、调节阈值电压(Vt)等。
在加工通道，特别是器件区的加工通道中，可以形成栅堆叠。在此，要形成存储器件，可以通过栅堆叠来实现存储功能。例如，栅堆叠中可以包括存储结构，如电荷捕获材料或铁电材料等。
如图11所示，可以例如通过淀积，依次形成存储功能层1025和栅导体层 1027。存储功能层1025可以大致共形的方式形成，栅导体层1027可以填充加工通道T中形成存储功能层1025之后剩余的空隙。可以对形成的栅导体层1027和存储功能层1025进行平坦化处理如化学机械抛光(CMP，例如可以停止于硬掩模层1015)，从而栅导体层1027和存储功能层1025可以留于加工通道T中，形成栅堆叠。
存储功能层1025可以基于介电电荷捕获、铁电材料效应或带隙工程电荷存储(SONOS)等。例如，存储功能层1025可以包括电介质隧穿层(例如厚度为约1nm-5nm的氧化物，可通过氧化或ALD形成)-能带偏移层(例如厚度为约2nm-10nm的氮化物，可通过CVD或ALD形成)-隔离层(例如厚度为约2nm-6nm的氧化物，可通过氧化、CVD或ALD形成)。这种三层结构可导致捕获电子或空穴的能带结构。或者，存储功能层1025可以包括铁电材料层，例如厚度为约2nm-20nm的HfZrO 2。
栅导体层1027可以包括例如(掺杂的，例如在n型器件的情况下p型掺杂)多晶硅或金属栅材料。
可以将沟道限定层去除，这样沟道区可以完全形成于半导体层1010中。于是，可以得到纳米片器件。
为去除沟道限定层，需要形成到各沟道限定层的(另外的)加工通道(之前的加工通道已被栅堆叠占据)。例如，如图12(a)和12(b)所示，可以在硬掩模层1015上形成掩模层1012如氧化物，并将其构图为露出需要形成加工通道的区域。加工通道可以形成在未设置栅堆叠之处。在图12(a)和12(b)的示例中，可以沿第一方向(图12(a)中纸面内的竖直方向)每隔若干个存储单元(图12(a)的示例中，三个)设置一个沿与第一方向交叉(例如，垂直)的第二方向(图12(a)中纸面内的水平方向)延伸的加工通道。可以光刻胶1012作为刻蚀掩模，通过各向异性刻蚀如竖直方向上的RIE，刻蚀之下的各层。刻蚀可以进行到衬底1001中，从而限定了加工通道，各沟道限定层在加工通道中露出。可以经由加工通道，通过选择性刻蚀，去除各沟道限定层。
如图13所示，可以通过淀积，在由于沟道限定层的去除而留下的空隙(以及加工通道)中填充电介质1014如氧化物，以实现结构支撑以及电隔离。可以对淀积的电介质1014进行平坦化处理如CMP。掩模层1012由于也包括氧 化物，从而与电介质1014一体示出。
如图13所示，具有存储功能层的栅堆叠(1025/1027)被半导体层1010围绕。栅堆叠与半导体层1010相配合，限定存储单元，如图13中的虚线圈所示。如上所述，半导体层1010在上下两端与源/漏限定层相对应的部分中形成源/漏区，而在中部与沟道限定层相对应的部分中形成沟道区。沟道区可以连接相对两端的源/漏区，沟道区可以受栅堆叠的控制。
栅堆叠在竖直方向上呈柱状延伸，与多个半导体层相交迭，从而可以限定在竖直方向上彼此叠置的多个存储单元。与单个栅堆叠柱相关联的存储单元可以形成存储单元串。与栅堆叠柱的布局(对应于上述加工通道T的布局，例如二维阵列)相对应，在衬底上布置有多个这样的存储单元串，从而形成存储单元的三维(3D)阵列。
在本实施例中，单个栅堆叠柱在单个器件层中可以限定两个存储单元，如图13中器件层L1中的两个虚线圈所示。在NOR型存储器件中，这两个存储单元可以共用相同的源/漏区(半导体层1010中在高度上与中间的第二源/漏限定层1009 1或1009 2相对应的部分)，并可以通过第二源/漏限定层1009 1或1009 2电连接到源极线。另外，这两个存储单元的另外的源/漏区(半导体层1010中在高度上与第一源/漏限定层1005 1或1005 2以及第三源/漏限定层1013 1或1013 2相对应的部分)可以分别通过相应源/漏限定层电连接到不同的位线。也即，源/漏限定层可以用作将存储单元的源/漏区电连接到位线或源极线的互连结构。沟道区形成于呈环形纳米片形式的半导体层1010中，因此该器件可以成为纳米片或纳米线器件，于是可以实现良好的短沟道效应控制和功耗降低。
这样，就完成了(器件区中)存储单元的制作。然后，可以(在接触区中)制作各种电接触部以实现所需的电连接。
为实现到各器件层的电连接，在接触区中可以形成阶梯结构。本领域存在多种方式来形成这样的阶梯结构。根据本公开的实施例，阶梯结构例如可以如下形成。
如图14(a)、14(b)和14(c)所示，可以在电介质1014(包括掩模层1012)上，形成光刻胶1031，并将其通过光刻构图为遮蔽器件区而露出接触区。可以光刻胶1031作为刻蚀掩模，通过选择性刻蚀如RIE，刻蚀电介质1014、硬 掩模层1015、隔离层1023 3和栅堆叠，以露出器件层。可以通过控制刻蚀深度，使得刻蚀后接触区中被光刻胶1031露出的表面大致平坦。例如，可以先刻蚀硬掩模层1015上方的电介质1014，以露出栅堆叠；然后刻蚀栅导体层1027，对栅导体层1027的刻蚀可以停止在器件层L2的顶面附近；然后，可以依次刻蚀硬掩模层1015和隔离层1023 3；如此刻蚀之后，存储功能层1025的顶端可以突出于器件层L2的顶面上方，并可以通过RIE去除。这样，在接触区与器件区之间形成了一个台阶。之后，可以去除光刻胶1031。
如图15(a)和15(b)所示，可以通过侧墙(spacer)形成工艺，在接触区与器件区之间的台阶处形成侧墙1033。例如，可以通过以大致共形的方式淀积一层电介质如氧化物，然后对淀积的电介质进行各向异性刻蚀如竖直方向上的RIE，以去除所淀积电介质的横向延伸部分，而留下其竖直延伸部分，从而形成侧墙1033。在此，考虑到电介质1014也包括氧化物，可以控制RIE的刻蚀深度实质上等于或稍大于电介质的淀积厚度，以避免完全去除硬掩模层1015上方的电介质1014。侧墙1033的宽度(在图中水平方向上)可以基本等于电介质的淀积厚度。侧墙1033的宽度限定了随后到器件层L2中的第三源/漏限定层1013 2的接触部的着落垫(1anding pad)的大小。
以如此形成的侧墙1033作为刻蚀掩模，可以通过选择性刻蚀如RIE，来刻蚀露出的第三源/漏限定层1013 2、电介质1014以及栅堆叠，以露出器件层L2中的第二源/漏限定层1009 2。可以通过控制刻蚀深度，使得刻蚀后接触区中被侧墙1033露出的表面大致平坦。例如，可以先刻蚀栅导体层1027(在栅导体层1027包括多晶硅的情况下，在此为Si的第三源/漏限定层1013 2也可以至少部分地刻蚀)，刻蚀可以停止于第二源/漏限定层1009 2的顶面附近；然后可以刻蚀第三源/漏限定层1013 2(例如，之前未被完全刻蚀；或者栅导体层1027包括金属栅，从而使用了具有刻蚀选择性的刻蚀配方)，刻蚀可以停止于电介质1014；然后刻蚀电介质1014，刻蚀可以停止于第二源/漏限定层1009 2；如此刻蚀之后，存储功能层1025的顶端可以突出于第二源/漏限定层1009 2的顶面上方，并可以通过RIE去除。这样，在接触区中在第三源/漏限定层1013 2与被侧墙1033露出的表面之间形成了又一台阶。
可以按照以上结合图15(a)和15(b)描述的工艺，通过形成侧墙，以侧墙为 刻蚀掩模进行刻蚀，来在接触区中形成多个台阶，如图16(a)和16(b)所示。这些台阶形成这样的阶梯结构，使得对于各器件层中需要电连接的各层，例如上述源/漏限定层，其相对于上方的层，端部相对突出，以限定到该层的接触部的着落焊盘。图16(a)和16(b)中的1035表示各次形成的侧墙在处理之后的留下部分。
之后，可以制作接触部。
例如，如图17(a)和17(b)所示，可以通过淀积氧化物并平坦化如CMP，来形成层间电介质层1037。在此，由于均为氧化物，将之前的侧墙1035等其他氧化物部件均示出为与层间电介质层1037一体。然后，如图18(a)、18(b)和18(c)所示，可以在层间电介质层1037中形成接触部1039、1041。具体地，接触部1039形成在器件区中，电连接到栅堆叠中的栅导体层1027；接触部1041形成在接触区中，电连接到各源/漏限定层。接触区中的接触部1041可以避开接触区中残留的栅堆叠。这些接触部可以通过在层间电介质层1037中刻蚀孔洞，并在其中填充导电材料如金属来形成。
在此，接触部1039可以电连接到字线。通过字线，经由接触部1039，可以向栅导体层1027施加栅控制信号。对于同一器件层中彼此叠置的两个存储单元，位于中间的源/漏限定层，即第二源/漏限定层1009 1、1009 2，由这两个存储单元共享，并可以经由接触部1041而电连接到源极线；位于上下两端的源/漏限定层，即第一源/漏限定层1005 1、1005 2和第三源/漏限定层1013 1、1013 2，可以经由接触部1041而分别电连接到不同的位线。这样，可以得到NOR型配置。
在此，在一个器件层中形成两个存储单元，可以减少布线数量。但是，本公开不限于此。例如，在一个器件层中可以仅形成单个存储单元。这种情况下，器件层中可以仅设置第一源/漏限定层、第一沟道限定层和第二源/漏限定层，而无需设置第二沟道限定层和第三源/漏限定层。
图21示意性示出了根据本公开实施例的NOR型存储器件的等效电路图。
在图21的示例中，示意性示出了三条字线WL1、WL2、WL3以及八条位线BL1、BL2、BL3、BL4、BL5、BL6、BL7、BL8。但是，位线和字线的具体数目不限于此。在位线与字线交叉之处，设置有存储单元MC。图21中 还示出了四条源极线SL1、SL2、SL3、SL4。如上所述，竖直方向上每两层相邻的存储单元可以共用相同的源极线连接。另外，各条源极线可以彼此连接，从而各存储单元MC可以连接到公共的源极线。
在此，仅为图示方便起见，示出了存储单元MC的二维阵列。可以在与此二维阵列相交的方向上(例如，图中垂直于纸面的方向)，设置多个这样的二维阵列，从而得到三维阵列。
图21中字线WL1至WL3的延伸方向可以对应于栅堆叠的延伸方向，即，前述实施例中相对于衬底的竖直方向。在该方向上，相邻的位线之间彼此隔离。这也是在上述实施例中，在竖直方向上相邻的器件层之间设置隔离层的原因。
在上述实施例中，接触区中的接触部1041需要避开接触区中残留的栅堆叠。根据本公开的另一实施例，可以在接触区中残留的栅堆叠顶端形成隔离如电介质材料，从而无需刻意避开这些残留的栅堆叠。
例如，如图19(a)和19(b)所示，在如以上结合图14(a)至16(b)所述在接触区中形成阶梯结构之后，可以通过选择性刻蚀如RIE，去除侧墙1035，以(在器件区以及接触区中)露出各栅堆叠的顶端。可以通过遮蔽层例如光刻胶，遮蔽器件区中的栅堆叠，而露出接触区中的栅堆叠。对接触区中露出的栅堆叠，可以通过选择性刻蚀如RIE，使得栅导体层凹进例如约50nm-150nm。之后，可以去除遮蔽层。在接触区中由于栅导体层的凹进而形成的空隙中，可以通过例如淀积然后回蚀，填充电介质材料如SiC，以形成隔离插塞1016。
然后，可以按照上述实施例形成层间电介质层并在其中形成接触部1039、1041′。在该示例中，接触区中的接触部1041′可以延伸到隔离插塞1016中。因此，接触部1041′可以不限于上述插塞的形式，而是可以形成为条形，以降低接触电阻。条形接触部1041′可以沿着相应层的着落垫(即，阶梯结构中的台阶)延伸。
在上述实施例中，接触部与相应的着落垫直接接触。根据本公开的其他实施例，可以在着落垫处形成硅化物，以降低接触电阻。更具体地，在接触区的各台阶处，台阶的横向表面用作着落垫，可以在其上形成硅化物。另一方面，在台阶的竖直表面上，可以不形成硅化物，以免使相邻台阶各自的着落垫之间短路。
例如，如图20(a)和20(b)所示，在如以上结合图14(a)至16(b)所述在接触区中形成阶梯结构之后，可以通过选择性刻蚀如RIE，去除侧墙1035，以在接触区中露出各台阶的表面。可以通过侧墙形成工艺，在各台阶的竖直表面上形成电介质侧墙1047如氮化物，以将这些竖直表面遮蔽以免随后发生硅化反应。然后，可以对各台阶露出的横向表面进行硅化处理。例如，可以淀积金属如NiPt，并进行退火，使得淀积的金属与各台阶的横向表面处的半导体材料(例如，Si)发生硅化反应，从而生成导电的金属硅化物1049如NiPtSi。之后，可以去除未反应的金属。
在所示出的示例中，栅导体层1027例如是多晶硅，因此其顶端也可以发生硅化反应从而被硅化物覆盖。在栅导体层1027是金属栅的情况下，可以先在器件区上形成保护层(例如，氮化物)以覆盖栅堆叠再进行硅化处理。于是，可以避免栅导体层1027在硅化处理工艺中去除金属时被刻蚀损坏。
之后，可以如上所述形成层间电介质层，并在其中形成接触部1039、1041。在刻蚀用于接触部的孔洞时，可以硅化物1049作为刻蚀停止层。因此，可以更好地控制孔洞的刻蚀深度。
根据本公开实施例的存储器件可以应用于各种电子设备。例如，存储器件可以存储电子设备操作所需的各种程序、应用和数据。电子设备还可以包括与存储器件相配合的处理器。例如，处理器可以通过运行存储器件中存储的程序来操作电子设备。这种电子设备例如智能电话、个人计算机(PC)、平板电脑、人工智能设备、可穿戴设备或移动电源等。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (39)

  1. 一种NOR型存储器件，包括：
    在衬底上竖直延伸的栅堆叠，所述栅堆叠包括栅导体层和存储功能层；以及
    围绕所述栅堆叠的外周、沿所述栅堆叠的侧壁延伸的第一半导体层和第二半导体层，所述第一半导体层和所述第二半导体层相对于所述衬底分别处于不同的高度处，
    其中，所述存储功能层介于所述第一半导体层与所述栅导体层以及所述第二半导体层与所述栅导体层与之间，
    其中，所述第一半导体层和所述第二半导体层中的每一个包括在竖直方向上依次设置的第一源/漏区、沟道区和第二源/漏区，以及
    其中，在所述栅堆叠与所述第一半导体层相交之处以及在所述栅堆叠与所述第二半导体层相交之处分别限定存储单元。
  2. 根据权利要求1所述的NOR型存储器件，所述第一半导体层和所述第二半导体层中的每一个还包括在竖直方向上依次设置的第二沟道区和第三源/漏区使得所述第二沟道区在竖直方向上处于所述第二源/漏区与所述第三源/漏区之间，在所述栅堆叠与所述第一半导体层相交之处以及在所述栅堆叠与所述第二半导体层相交之处分别限定彼此叠置的两个存储单元。
  3. 根据权利要求1或2所述的NOR型存储器件，其中，所述存储功能层包括电荷捕获材料或铁电材料中至少之一。
  4. 根据权利要求1或2所述的NOR型存储器件，其中，所述半导体层包括单晶半导体材料。
  5. 根据权利要求1或2所述的NOR型存储器件，其中，所述存储功能层形成在所述栅导体层的底面和侧壁上。
  6. 根据权利要求1或2所述的NOR型存储器件，其中，所述第一半导体层和所述第二半导体层在竖直方向上实质上共面。
  7. 根据权利要求2所述的NOR型存储器件，其中，所述第一半导体层与所述第二半导体层之间设置有隔离层。
  8. 根据权利要求7所述的NOR型存储器件，其中，所述第一半导体层与所述第二半导体层中位于所述隔离层上方的半导体层的与所述隔离层相邻的源/漏区以及位于所述隔离层下方的半导体层的与所述隔离层相邻的源/漏区分别电连接到不同的位线。
  9. 根据权利要求2所述的NOR型存储器件，包括布置成阵列的多个所述栅堆叠以及分别围绕各个所述栅堆叠的第一半导体层和第二半导体层，
    其中，各个所述栅堆叠外周的所述第一半导体层在横向上实质上共面，各个所述栅堆叠外周的所述第二半导体层在横向上实质上共面，
    其中，各个所述第一半导体层中的所述第一源/漏区、所述第一沟道区、所述第二源/漏区、所述第二沟道区和所述第三源/漏区分别在横向上实质上共面，各个所述第二半导体层中的所述第一源/漏区、所述第一沟道区、所述第二源/漏区、所述第二沟道区和所述第三源/漏区分别在横向上实质上共面。
  10. 根据权利要求9所述的NOR型存储器件，其中，所述衬底包括器件区以及与器件区相邻的接触区，所述存储单元形成在所述器件区上，
    所述NOR型存储器件还包括：
    彼此不同的第一位线和第二位线；
    源极线；
    横向延伸的第一互连层，所述第一互连层围绕各个所述栅堆叠外周的各个所述第一半导体层中的所述第一源/漏区，并延伸到所述接触区；
    横向延伸的第二互连层，所述第二互连层围绕各个所述栅堆叠外周的各个所述第一半导体层中的所述第二源/漏区，并延伸到所述接触区；以及
    横向延伸的第三互连层，所述第三互连层围绕各个所述栅堆叠外周的各个所述第一半导体层中的所述第三源/漏区，并延伸到所述接触区，
    其中，所述第一互连层和所述第三互连层分别电连接到所述第一位线和所述第二位线，所述第二互连层电连接到所述源极线。
  11. 根据权利要求10所述的NOR型存储器件，其中，所述第一互连层、所述第二互连层和所述第三互连层包括掺杂的单晶半导体材料。
  12. 根据权利要求10所述的NOR型存储器件，其中，
    所述第一互连层与各个所述第一半导体层中的所述第一源/漏区在横向上 实质上共面，
    所述第二互连层与各个所述第一半导体层中的所述第二源/漏区在横向上实质上共面，
    所述第三互连层与各个所述第一半导体层中的所述第三源/漏区在横向上实质上共面。
  13. 根据权利要求10所述的NOR型存储器件，其中，所述第一互连层与所述第二互连层之间以及所述第二互连层与所述第三互连层之间设置有电介质材料。
  14. 根据权利要求10所述的NOR型存储器件，还包括：
    所述接触区中到所述第一互连层的第一接触部；
    所述接触区中到所述第二互连层的第二接触部；以及
    所述接触区中到所述第三互连层的第三接触部，
    其中，所述第一互连层经由所述第一接触部电连接到所述第一位线，所述第三互连层经由所述第三接触部电连接到所述第二位线，且所述第二互连层经由所述第二接触部电连接到所述源极线。
  15. 根据权利要求14所述的NOR型存储器件，其中，所述第一接触部、所述第二接触部和所述第三接触部形成为彼此实质上平行延伸的条状。
  16. 根据权利要求10所述的NOR型存储器件，其中，所述第一互连层、所述第二互连层和所述第三互连层在接触区中形成阶梯结构。
  17. 根据权利要求16所述的NOR型存储器件，其中，所述阶梯结构包括具有横向表面以及竖直表面的台阶，所述NOR型存储器件还包括：
    所述台阶的所述横向表面上的硅化物；以及
    所述台阶的所述竖直表面上的电介质侧墙。
  18. 根据权利要求1或2所述的NOR型器件，还包括：
    字线；以及
    到所述栅导体层的第四接触部，所述第四接触部电连接到所述字线。
  19. 根据权利要求1或2所述的NOR型器件，其中，所述第一半导体层和所述第二半导体层均为横截面呈环形、竖直延伸的纳米片。
  20. 一种制造NOR型存储器件的方法，包括：
    在衬底上设置多个器件层，每个所述器件层包括第一源/漏限定层、第一沟道限定层和第二源/漏限定层的叠层；
    形成相对于所述衬底竖直延伸以穿过各个所述器件层中的所述叠层的加工通道；
    通过所述加工通道，在各个所述器件层在所述加工通道中露出的侧壁上外延生长半导体层；以及
    在所述加工通道中形成栅堆叠，所述栅堆叠包括栅导体层和设置在所述栅导体层与所述半导体层之间的存储功能层，在所述栅堆叠与所述半导体层相交之处限定存储单元。
  21. 根据权利要求20所述的方法，其中，所述多个器件层中至少一部分器件层的所述叠层还包括第二沟道限定层和第三源/漏限定层。
  22. 根据权利要求20或21所述的方法，其中，所述叠层通过外延生长形成。
  23. 根据权利要求22所述的方法，其中，所述叠层中的至少各源/漏限定层在外延生长时原位掺杂。
  24. 根据权利要求23所述的方法，还包括：
    进行退火处理，使所述叠层中的掺杂剂在横向上扩散到所述半导体层中。
  25. 根据权利要求20或21所述的方法，还包括：
    通过经由所述加工通道进行刻蚀，使所述器件层在所述加工通道中露出的所述侧壁在横向上凹进一定深度。
  26. 根据权利要求25所述的方法，其中，所述多个器件层各自的所述侧壁在凹进之后在竖直方向上实质上共面。
  27. 根据权利要求20或21所述的方法，还包括：
    在至少一部分相邻的器件层之间形成牺牲层，
    其中，在设置所述多个器件层之后，该方法还包括将所述牺牲层替换为隔离层。
  28. 根据权利要求27所述的方法，其中，将所述牺牲层替换为隔离层包括：
    在一部分加工通道中形成支撑层，而所述牺牲层在其余加工通道中露出；
    经由所述其余加工通道，将所述牺牲层替换为所述隔离层；以及
    去除所述支撑层。
  29. 根据权利要求28所述的方法，其中，将所述牺牲层替换为所述隔离层包括：
    经由所述其余加工通道，通过选择性刻蚀，使所述沟道限定层和所述牺牲层在横向上凹进第一深度；
    在由于所述牺牲层的凹进而形成的第一间隙中形成位置保持插塞，其中所述牺牲层的厚度小于所述沟道限定层的厚度，从而位置保持插塞不形成在由于所述沟道限定层的凹进而形成的第二间隙中；
    在所述第二间隙中形成保护插塞；
    通过选择性刻蚀，去除所述位置保持插塞，以露出所述牺牲层。
  30. 根据权利要求29所述的方法，其中，外延生长所述半导体层包括：
    经由所述其余加工通道，通过选择性刻蚀，使所述源/漏限定层在横向上凹进第二深度，所述第二深度实质上等于所述第一深度；
    通过选择性刻蚀，去除所述保护插塞和所述支撑层；
    利用遮蔽层遮蔽所述其余加工通道，并露出所述一部分加工通道；
    经由所述一部分加工通道，通过选择性刻蚀，使所述器件层在所述一部分加工通道中露出的侧壁在横向上凹进第三深度，所述第三深度实质上等于所述第一深度；
    去除所述遮蔽层；以及
    在所述器件层在各个所述加工通道中露出的侧壁上外延生长所述半导体层。
  31. 根据权利要求20或21所述的方法，其中，形成所述栅堆叠包括：
    以实质上共形的方式在所述加工通道的底面和侧壁上形成所述存储功能层；以及
    在形成有所述存储功能层的所述加工通道中填充所述栅导体层。
  32. 根据权利要求20或21所述的方法，其中，形成布置成阵列的多个所述加工通道。
  33. 根据权利要求20或21所述的方法，还包括：
    通过选择性刻蚀，去除所述器件层中的各沟道限定层；以及
    在由于沟道限定层的去除而留下的间隙中填充电介质。
  34. 根据权利要求21所述的方法，其中，所述衬底包括器件区以及与器件区相邻的接触区，所述存储单元形成在所述器件区上，
    所述方法还包括：
    在所述接触区上形成到所述第一源/漏限定层的第一接触部、到所述第二源/漏限定层的第二接触部以及到所述第三源/漏限定层的第三接触部。
  35. 根据权利要求30所述的方法，其中，将所述第一接触部至所述第三接触部形成为彼此实质上平行延伸的条状。
  36. 根据权利要求34所述的方法，还包括：
    将各个所述器件层中的所述第一源/漏限定层、所述第二源/漏限定层和所述第三源/漏限定层在所述接触区中构图为阶梯结构。
  37. 根据权利要求36所述的方法，其中，所述阶梯结构包括具有横向表面以及竖直表面的台阶，所述方法还包括：
    在所述台阶的所述竖直表面上形成电介质侧墙；以及
    对所述台阶的所述横向表面进行硅化处理。
  38. 一种电子设备，包括如权利要求1至19中任一项所述的NOR型存储器件。
  39. 根据权利要求38所述的电子设备，其中，所述电子设备包括智能电话、个人计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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