WO2023028740A1 - 一种氮化镓器件及其制造方法、电子设备 - Google Patents

一种氮化镓器件及其制造方法、电子设备 Download PDF

Info

Publication number
WO2023028740A1
WO2023028740A1 PCT/CN2021/115270 CN2021115270W WO2023028740A1 WO 2023028740 A1 WO2023028740 A1 WO 2023028740A1 CN 2021115270 W CN2021115270 W CN 2021115270W WO 2023028740 A1 WO2023028740 A1 WO 2023028740A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gallium nitride
gate
gate region
barrier layer
Prior art date
Application number
PCT/CN2021/115270
Other languages
English (en)
French (fr)
Inventor
唐高飞
上田大助
孙辉
包琦龙
王汉星
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/115270 priority Critical patent/WO2023028740A1/zh
Priority to CN202180005517.8A priority patent/CN116235301A/zh
Priority to EP21955322.9A priority patent/EP4336562A1/en
Publication of WO2023028740A1 publication Critical patent/WO2023028740A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular to a gallium nitride device, a manufacturing method thereof, and electronic equipment.
  • GaN devices such as power switches based on wide bandgap semiconductor material GaN have attracted more and more attention.
  • gallium nitride devices mainly include devices based on aluminum gallium nitride (AlGaN)/GaN heterostructures, such as high electron mobility transistors (high electron mobility transistors, HEMTs), and AlGaN/GaN heterostructures can A high-mobility two-dimensional electron gas (2-DEG) channel is naturally formed, so devices based on this heterostructure behave as normally-on switching devices.
  • AlGaN aluminum gallium nitride
  • GaN heterostructures such as high electron mobility transistors (high electron mobility transistors, HEMTs)
  • 2-DEG high-mobility two-dimensional electron gas
  • normally-off GaN devices have the advantages of being compatible with Si device driving schemes and simple driving methods, and have more market value.
  • a p-type GaN (p-GaN) layer can be grown on the surface of the AlGaN/GaN heterojunction in the gate region, and the p-GaN layer is doped by epitaxial growth.
  • Doping magnesium (Mg) to deplete the two-dimensional electron gas channel, and the non-gate region outside the gate region does not form p-GaN, so that the gate region has no channel, and the non-gate region has a channel.
  • Mg magnesium
  • the current normally-off GaN devices based on p-GaN have reliability problems such as serious dynamic resistance degradation and resistance degradation after high temperature operating life (HTOL).
  • the embodiment of the present application provides a gallium nitride device and its manufacturing method, and electronic equipment, which realizes channel depletion by forming a new structure in the gate region, thereby reducing the risk of dynamic resistance and resistance degradation after HTOL .
  • the first aspect of the embodiments of the present application provides a gallium nitride device, including a gallium nitride layer, a barrier layer on one side of the gallium nitride layer, and a gate on the side of the barrier layer away from the gallium nitride layer , the gallium nitride layer has a gate region and a non-gate region around the gate region, the elements of the composition material of the barrier layer include aluminum (Al), gallium (Ga) and nitrogen (N), and the barrier layer is located in the gate region and the non-gate region, in the direction vertical to the surface of the gallium nitride layer, the size of the barrier layer in the gate region is larger than the size of the barrier layer in the non-gate region, and the barrier layer in the gate region faces
  • the aluminum concentration on one side of the gallium nitride layer is higher than the aluminum concentration on the side facing the gate, so that the aluminum concentration in the barrier layer decreases gradually in the direction away from the gate region from the gall
  • the barrier layer can naturally be equivalent to p-type doping without Mg doping, so that the electrons at the AlGaN/GaN interface in the gate region can be naturally depleted, and the two-dimensional electron gas channel in the non-gate region is not depleted As much as possible, and while forming a normally-off GaN device, no defect state will be formed in the barrier layer of the non-gate region due to Mg doping, thus reducing the risk of dynamic resistance degradation of the device and resistance degradation after HTOL, It is beneficial to obtain gallium nitride devices with excellent performance.
  • the barrier layer includes a first portion facing the gallium nitride layer and a second portion facing the gate, and the aluminum concentration of the first portion is higher than that of the second portion.
  • Aluminum concentration, the first part is located in the gate region and the non-gate region, and the projection of the second part on the surface of the gallium nitride layer is located in the gate region.
  • the barrier layer may include a first part and a second part, the aluminum concentration of the first part is higher than that of the second part, and the second part is located on the first part of the gate region, and the second part of the gate region.
  • the part and the second part can be equivalent to p-type doping naturally without Mg doping, which is beneficial to the channel depletion of the gate region.
  • the first part is a first film layer
  • the second part includes stacked multi-layer sub-film layers
  • the aluminum concentration of the sub-film layers facing the gate is lower than that facing the second film layer. Al concentration of a portion of the sublayers.
  • the first part is the first film layer
  • the second part includes multiple sub-film layers of the stacked layer, so that the barrier layer can form a multi-layer structure, and the concentration decreases sequentially, enhancing the barrier layer in the gate region.
  • the polarization effect is beneficial to the control of aluminum concentration and the depletion of the channel in the gate region.
  • the aluminum concentration in the second portion shows a decreasing trend from a side facing the first portion to a side facing away from the first portion.
  • the second part may be an integral structure, the integral structure has no obvious boundary, and the aluminum concentration in the interior shows a downward trend from the side facing the first part to the side away from the first part, so that the aluminum concentration Gradient setting enhances the polarization effect in the barrier layer of the gate region, which is beneficial to the control of aluminum concentration and the depletion of the channel in the gate region.
  • the size of the barrier layer located in the non-gate region in a direction perpendicular to the surface of the gallium nitride layer is less than or equal to 30 nm.
  • the thickness of the barrier layer in the non-gate region is small, so that the thickness of the barrier layer capable of generating two-dimensional electron gas in the gate region is also small, which is beneficial to the depletion of the channel in the gate region.
  • the molar ratio of aluminum to gallium in the barrier layer located in the non-gate region is greater than or equal to 3/7.
  • the molar ratio of aluminum and gallium in the barrier layer in the non-gate region is greater than or equal to a preset value, so that the barrier layer in the non-gate region has a relatively large aluminum concentration, which is beneficial to the barrier layer and Sufficient two-dimensional electron gas is generated between the AlGaN layers, which is conducive to the formation of channels in non-gate regions.
  • the gallium nitride device further includes:
  • a source electrode and a drain electrode are located on a side of the barrier layer of the non-gate region away from the gallium nitride layer.
  • the gallium nitride device further includes a source and a drain, respectively located on both sides of the gate, for applying source signals and drain signals.
  • the material of at least one of the source, drain and gate is: nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride and copper at least one.
  • the materials of the source electrode, the drain electrode and the gate electrode are materials with better conductivity, which is beneficial to improve device performance.
  • the gallium nitride device further includes:
  • a passivation layer covering the barrier layer located in the non-gate region.
  • the gallium nitride device further includes a passivation layer, which is used to provide stress for the barrier layer, to promote the regeneration of the two-dimensional electron gas channel in the non-gate region, and to obtain a channel with a high charge transfer rate.
  • a passivation layer which is used to provide stress for the barrier layer, to promote the regeneration of the two-dimensional electron gas channel in the non-gate region, and to obtain a channel with a high charge transfer rate.
  • the passivation layer also covers the barrier layer located in the gate region;
  • the gate includes a first gate structure and a second gate structure electrically connected, and the first The gate structure penetrates the passivation layer, and the second gate structure is formed on a side of the first gate structure away from the gallium nitride layer and covers part of the surface of the passivation layer.
  • the gate may include two parts to form a "T"-shaped structure, which facilitates the extraction of the gate.
  • the material of the passivation layer is at least one of silicon nitride and aluminum carbide.
  • the passivation layer is a material capable of providing stress to the barrier layer, which is beneficial to channel regeneration in the non-gate region.
  • the gallium nitride device further includes:
  • a gate dielectric layer located between the barrier layer and the gate.
  • the gallium nitride device further includes:
  • a substrate located on a side of the gallium nitride layer away from the barrier layer.
  • the gallium nitride layer may be disposed on the substrate, and the substrate is used to provide support for the gallium nitride layer.
  • the gallium nitride device further includes:
  • a buffer layer between the substrate and the gallium nitride layer.
  • a buffer layer is formed between the gallium nitride layer and the substrate, which facilitates the formation of a gallium nitride layer with better quality.
  • a method for manufacturing a gallium nitride device including:
  • a gallium nitride layer having a gate region and a non-gate region surrounding the gate region;
  • a barrier layer is formed on one surface of the gallium nitride layer, and a gate located on the side of the barrier layer in the gate region away from the gallium nitride layer is formed, and the composition material of the barrier layer is
  • the elements include aluminum, gallium and nitrogen; the barrier layer is located in the gate region and the non-gate region, and in the direction perpendicular to the surface of the gallium nitride layer, the size of the barrier layer in the gate region is greater than the size of the barrier layer located in the non-gate region, and the aluminum concentration on the side of the barrier layer located in the gate region facing the gallium nitride layer is higher than the aluminum concentration on the side facing the gate concentration.
  • the barrier layer includes a first portion facing the gallium nitride layer and a second portion facing the gate, and the aluminum concentration of the first portion is higher than that of the second portion.
  • Aluminum concentration, the first part is located in the gate region and the non-gate region, and the projection of the second part on the surface of the gallium nitride layer is located in the gate region.
  • the first part is a first film layer
  • the second part includes stacked multi-layer sub-film layers
  • the aluminum concentration of the sub-film layers facing the gate is lower than that facing the second film layer. Al concentration of a portion of the sublayers.
  • the aluminum concentration in the second portion shows a decreasing trend from a side facing the first portion to a side facing away from the first portion.
  • the size of the barrier layer located in the non-gate region in a direction perpendicular to the surface of the gallium nitride layer is less than or equal to 30 nm.
  • the molar ratio of aluminum to gallium in the barrier layer located in the non-gate region is greater than or equal to 3/7.
  • the method also includes:
  • a source and a drain are formed on a side of the barrier layer in the non-gate region away from the gallium nitride layer.
  • the material of at least one of the source, drain and gate is: nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride and copper at least one.
  • the barrier layer is formed on one side of the gallium nitride layer, and the gate located on the side of the barrier layer in the gate region away from the gallium nitride layer is poles, including:
  • An aluminum gallium nitride material layer is formed on one side surface of the gallium nitride layer, and the elements of the composition material of the aluminum gallium nitride material layer include aluminum, gallium and nitrogen; the aluminum gallium nitride material layer faces the gallium nitride material layer the aluminum concentration on the side of the layer is higher than the aluminum concentration on the side facing away from the gallium nitride layer;
  • a gate is formed on a side of the barrier layer located in the gate region away from the gallium nitride layer.
  • forming the gate on the side of the barrier layer located in the gate region away from the gallium nitride layer includes:
  • the gate includes a first gate structure and a second gate structure electrically connected, the first gate structure is located in the gate hole, and the second gate structure It is formed on the side of the first gate structure away from the gallium nitride layer and covers part of the surface of the passivation layer.
  • the method before forming the gate, the method further includes:
  • a gate dielectric layer is formed between the barrier layer and the gate.
  • the barrier layer is formed on one side of the gallium nitride layer, and the gate located on the side of the barrier layer in the gate region away from the gallium nitride layer is poles, including:
  • An aluminum gallium nitride material layer is formed on one side surface of the gallium nitride layer, and a gate material layer located on a side of the aluminum gallium nitride material layer away from the gallium nitride layer; the aluminum gallium nitride material layer
  • the elements of the constituent materials of the layer include aluminum, gallium and nitrogen; the aluminum concentration of the aluminum gallium nitride material layer facing the gallium nitride layer is higher than the aluminum concentration on the side away from the gallium nitride layer;
  • the method also includes:
  • the gate dielectric material layer on the side away from the gallium nitride layer of the aluminum gallium nitride material layer in the non-gate region is also etched, so as to obtain the The gate dielectric layer between the gates.
  • the method further includes:
  • a passivation layer is formed covering the barrier layer.
  • the material of the passivation layer is at least one of silicon nitride and aluminum carbide.
  • a substrate is provided on a side of the gallium nitride layer away from the barrier layer.
  • a buffer layer is disposed between the gallium nitride layer and the substrate.
  • the third aspect of the embodiment of the present application provides an electronic device, including a circuit board, and a gallium nitride device as provided in the first aspect of the present application connected to the circuit board.
  • Embodiments of the present application provide a gallium nitride device and its manufacturing method, and electronic equipment.
  • the gallium nitride device may include a gallium nitride layer, a barrier layer on one side of the gallium nitride layer, and a barrier layer away from the gallium nitride layer.
  • the gate on one side of the layer, the gallium nitride layer has a gate region and a non-gate region around the gate region, the elements of the composition material of the barrier layer include aluminum (Al), gallium (Ga) and nitrogen (N), and the potential
  • the barrier layer is located in the gate area and the non-gate area, and in the direction along the surface of the gallium nitride layer, the size of the barrier layer located in the gate area is larger than the size of the barrier layer located in the non-gate area, and the size of the barrier layer located in the gate area is
  • the aluminum concentration on the side of the barrier layer facing the gallium nitride layer is higher than the aluminum concentration on the side facing the gate, so that the aluminum concentration in the barrier layer decreases gradually in the direction away from the gallium nitride layer in the gate region, Based on the polarization effect, the barrier layer can be naturally equivalent to p-type doping without Mg doping, so that the electrons at the AlGaN/GaN interface in the
  • the gas channel is not depleted, and while forming a normally-off GaN device, no defect state will be formed in the barrier layer of the non-gate region due to Mg doping, thus reducing the dynamic resistance degradation and HTOL of the device
  • the risk of post-resistance degradation is beneficial to obtain gallium nitride devices with excellent performance.
  • FIG. 1 is a schematic diagram of the epitaxial growth of a p-GaN layer in an embodiment of the present application
  • FIG. 2 is a schematic diagram of forming a p-GaN layer in the gate region in an embodiment of the present application
  • 3 is a schematic diagram of the relationship between the dynamic resistance of the device and the Mg doping concentration in the embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of a gallium nitride device provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a second part provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of the concentration distribution of the first part and the second part in the embodiment of the present application.
  • FIG. 7 is a schematic diagram of the barrier height of a gallium nitride layer and a barrier layer in the gate region provided by an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of another gallium nitride device provided in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another gallium nitride device provided in the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another gallium nitride device provided in the embodiment of the present application.
  • FIG. 11 is a flowchart of a method for manufacturing a gallium nitride device provided in an embodiment of the present application.
  • FIGS. 12-21 are schematic structural diagrams of the gallium nitride device in the manufacturing process in the embodiment of the present application.
  • Embodiments of the present application provide a gallium nitride device, a manufacturing method thereof, and an electronic device.
  • Channel depletion is achieved by forming a new structure in the gate region, thereby reducing the risk of dynamic resistance and resistance degradation after HTOL.
  • normally-on GaN devices require a stable conduction current to keep them turned on, and must Only when a reverse voltage is applied to the pole, the device can be turned off. This characteristic is not conducive to the design of the driving circuit, and the power consumption of the device is high.
  • normally-off GaN devices have the advantages of being compatible with Si device driving schemes and simple driving methods, and have more market value.
  • a p-GaN layer can be formed on the surface of the AlGaN/GaN heterojunction in the gate region, which is depleted by doping Mg during the epitaxial growth process
  • the two-dimensional electron gas channel, and the non-gate region does not form p-GaN, so that the gate region has no channel, and the non-gate region has a channel.
  • the AlGaN/GaN heterojunction will be formed in the gate region and the non-gate region at the same time, that is, both the gate region and the non-gate region have two-dimensional electron gas channels.
  • a p-GaN material layer can be epitaxially formed on the surface of the AlGaN/GaN heterojunction in the gate region and the non-gate region, as shown in Figure 1, which is the p-GaN layer in the embodiment of this application
  • Figure 1 is the p-GaN layer in the embodiment of this application
  • FIG. 2 which is a schematic diagram of forming a p-GaN layer in the gate region in the embodiment of the present application; then a gate 141 can be formed on the p-GaN layer 131, A source 142 and a drain 143 are formed in the non-gate region.
  • the Mg atoms used to form p-GaN will also diffuse (out-diffuse) into the AlGaN barrier layer (ie, the AlGaN layer 120), introducing defect levels for the AlGaN layer 120, Referring to Figure 1 and Figure 2, this will cause electrons to be trapped by these defect levels during the high-voltage switching process of the device, causing reliability problems such as dynamic resistance degradation of the device and resistance degradation after HTOL.
  • the dynamic resistance degradation of the device is strongly related to the Mg doping concentration.
  • the degradation of dynamic resistance can be reduced by reducing the Mg concentration, but the threshold voltage of the device will also decrease accordingly, which is not conducive to switching application scenarios. Therefore, how to realize the depletion of the two-dimensional electron gas channel in the gate region without affecting the dynamic resistance of the device is an urgent problem to be solved in this field.
  • the gallium nitride device may include a gallium nitride layer, a barrier layer on one side of the gallium nitride layer, and a barrier layer
  • the aluminum concentration on the side of the barrier layer facing the GaN layer is higher than that on the side facing the gate, so that the aluminum concentration in the barrier
  • FIG. 4 it is a schematic structural diagram of a gallium nitride device provided by an embodiment of the present application, including a gallium nitride layer 220, barrier layers 231 & 232, and a gate 251, and the barrier layers 231 & 232 are located on the gallium nitride layer 220.
  • One side surface, and the element of the composition material of barrier layer 231&232 includes aluminum, gallium and nitrogen, and its composition material can be expressed as aluminum gallium nitrogen (Al x Ga 1-x N), and gallium nitride layer 220 and material are aluminum gallium
  • the nitrogen barrier layers 231 & 232 form a heterostructure of AlGaN/GaN, thereby generating a two-dimensional electron gas, and GaN devices formed based on this can use the two-dimensional electron gas generated by the heterostructure to work.
  • the GaN device may be, for example, a GaN-based high-electron-mobility transistor (HEMT) device.
  • HEMT high-electron-mobility transistor
  • the thickness of the gallium nitride layer 220 can be relatively large, so the gallium nitride layer 220 can be a substrate made of gallium nitride, which provides support for the film layer on it, and at the same time acts as an AlGaN substrate. /GaN heterostructure components.
  • the thickness of the gallium nitride layer 220 can be relatively thin, so the gallium nitride layer 220 can be formed on the substrate 200, and the substrate 200 is arranged on the side of the gallium nitride layer away from the barrier layers 231 & 232,
  • the substrate 200 provides support for the film layer on it, and the gallium nitride layer 220 serves as a component of the heterostructure of AlGaN/GaN, wherein the material of the substrate 200 can be aluminum nitride (AlN), silicon (Si), silicon carbide One or more of (SiC), sapphire.
  • a buffer layer 210 may also be provided between the substrate 200 and the gallium nitride layer 220.
  • the material of the buffer layer 210 may be aluminum nitride, or gallium nitride grown at a low temperature.
  • the buffer layer 210 is When GaN is grown at a low temperature, the GaN layer 220 can be a GaN layer grown at a high temperature, so that the low-temperature GaN layer serves as a buffer layer 210 between the high-temperature GaN layer and the substrate 200, thereby improving the high-temperature GaN layer. Layer epitaxial quality.
  • the gallium nitride layer 220 may have a gate region 1001 and a non-gate region 1002 around the gate region 1001, the gate region 1001 and the non-gate region 1002 are regions on the surface of the gallium nitride layer 220, including the surface of the gallium nitride layer 220 As well as the space defined by countless straight lines perpendicular to the surface of the GaN layer 220 , for ease of description, the direction parallel to the surface of the GaN layer 220 is taken as the horizontal direction, and the direction perpendicular to the surface of the GaN layer 220 is taken as the vertical direction.
  • the gate region 1001 is used to form the gate 251, and can be the central region between the regions where the source 252 and the drain 253 are located.
  • the gate region 1001 can be larger than the region where the gate 251 is located, or can be equal to the area where the gate 251 is located.
  • the dotted line box in the middle indicates the gate region 1001
  • the dotted line boxes on both sides of the gate region 1001 indicate the non-gate region 1002.
  • the subsequent structural schematic diagrams adopt the same representation method. Since FIG. 4 is a cross-sectional view, in fact the non-gate region 1002 may be located on both sides of the gate region 1001 , and may form a ring-shaped region surrounding the gate region 1001 , such as a circular ring region or a polygonal region.
  • the barrier layers 231 & 232 are located in the gate region 1001 and the non-gate region 1002, and the size of the barrier layer in the gate region 1001 is The size of the barrier layer in the non-gate region 1002 is larger than that of the barrier layer in the non-gate region 1002 , and the aluminum concentration on the side of the barrier layer facing the GaN layer 220 in the gate region 1001 is higher than that on the side facing the gate 251 .
  • the concentration of aluminum on the side of the barrier layer of the gate region 1001 facing the gallium nitride layer 220 is higher than the concentration of aluminum on the side facing the gate 251.
  • the barrier layer of the gate region 1001 faces the gallium nitride layer.
  • the concentration of gallium on the side of layer 220 is higher than the concentration of gallium on the side facing gate 251, since this arrangement is located in gate region 1001, in gate region 1001 from the side facing gallium nitride layer 220 to Towards the side of the gate 251, the reduction of the aluminum composition is realized, and the part with the lower aluminum composition has a lower barrier height, so the barrier height between the part with the lower aluminum composition and the gallium nitride layer 220 is lower.
  • the hole concentration is strongly related to the activation of Mg, so the activation temperature and doping concentration of p-GaN need to be precisely controlled.
  • the holes in the examples of this application are generated by the polarization effect.
  • the number of holes is basically equal to the number of electrons in the two-dimensional electron gas channel 222 of the gate region 1001, and many problems such as the need to accurately control the activation of holes in the Mg doping technology do not exist; at the same time, because there is no p-GaN layer, Therefore, there is no problem of defect states caused by Mg diffusion; at the same time, the threshold voltage of the device is determined by the structure of the gate region 1001, the process window is large, and there is no problem that the threshold voltage is sensitive to Mg doping concentration and p-GaN activation conditions.
  • the barrier layers 231 & 232 may include a first portion 231 facing the gallium nitride layer 220 and a second portion 232 facing the gate 251, wherein the first portion 231 is formed in the gate region 1001 and the non-gate region 1002, and the second portion
  • the projection of 232 on the surface of the gallium nitride layer 220 is located in the gate region, that is, the second part 232 is formed on the first part 231 of the gate region 1001. It can be considered that the second part 232 is formed on the gate region 1001.
  • a boundary is set between the first part 231 and the second part 232, and the boundary is the plane where the upper surface of the first part 231 is located. In the cross-sectional view of FIG.
  • a straight line is represented by a horizontal dotted line, that is, the first part 231 and the second part 232 are separated by a horizontal dotted line, and the same representation method is used in subsequent structural schematic diagrams. That is to say, the barrier layer can be divided into a first portion 231 and a second portion 232 vertically, and the second portion 232 covers the first portion 231 located in the gate region 1001 .
  • the first part 231 and the second part 232 are defined for the convenience of description, and there is not necessarily a clear dividing line.
  • the first part 231 and the second part 232 will be used to represent different parts of the barrier layer, and the surface of the first part 231 and The surface of the second portion 232 represents the surface of the barrier layer, wherein the second portion 232 covers the surface of the first portion 231 located in the gate region 1001 .
  • the concentration of aluminum in the first part 231 is higher than the concentration of aluminum in the second part 232, correspondingly, the concentration of gallium in the first part 231 is higher than the concentration of gallium in the second part 232, because the second part 232 is formed in the gate Pole region 1001, in this way, from the first part 231 to the second part 232 in the gate region 1001, the reduction of aluminum composition is realized, and the part with lower aluminum composition has a lower barrier height, so the aluminum composition is lower There is a lower potential barrier between the part of the GaN layer and the GaN layer 220.
  • the first part 231 and the second part 232 Holes are generated in the gate region 1001, so the barrier layers 231 & 232 of the gate region 1001 can be equivalent to p-type doping without Mg doping, and the number of holes is basically equal to the two-dimensional electron gas channel of the gate region 1001
  • the number of electrons in the 222, the electrons in the two-dimensional electron gas channel 222 can be naturally depleted.
  • the concentration of aluminum in the first part 231 is higher than the concentration of aluminum in the second part 232, which can be reflected in that the average concentration of aluminum in the first part 231 is higher than the average concentration of aluminum in the second part 232, and the second The concentration of aluminum in portion 232 may be uniform or non-uniform.
  • the second part 232 may include stacked multi-layer sub-film layers, and the multiple sub-film layers are stacked vertically, wherein the aluminum concentration of the multi-layer sub-film layers may not be completely the same, and the aluminum concentration of the sub-film layers facing the gate 251
  • the concentration is less than the aluminum concentration of the sub-film layer towards the first part, that is, the aluminum concentration of the upper sub-film layer can be lower than the aluminum concentration of the lower sub-film layer, so that the aluminum concentration is from the side towards the first part 231 to the side away from the first part
  • One side of 231 decreases in turn, and the aluminum concentration of each sub-film layer presents a downward trend, achieving a stepwise decrease in aluminum concentration and enhancing the polarization effect in the barrier layers 231 & 232 of the gate region 1001 .
  • the second part 232 may include stacked n-1 sub-layers, and the first part 231 may be the first The film layer (not shown in FIG. 5 ).
  • FIG. 6 it is a schematic diagram of the concentration distribution of the first part and the second part in the embodiment of the present application, wherein the abscissa represents the height of the film layer, with the interface between the first part 231 and the gallium nitride layer 220 as the height zero point, from the direction toward the second part.
  • the height of the film layer gradually increases, and the ordinate indicates the content of the Al component, wherein, as shown in Figure 6A, the aluminum group at different film heights inside each sub-film layer
  • the content of the Al component is the same, from the side facing the first part 231 to the side away from the first part 231, the content of the Al component presents a stepwise decrease, expressed as x1, x2, x3, x4, . . . , xn presents a stepwise decrease.
  • the aluminum concentration in the multi-layer sub-film layer may not strictly decrease sequentially, and the aluminum concentration in the small number of sub-film layers may also increase slightly. , that is, the aluminum concentration of part of the upper sub-film layer may be greater than the aluminum concentration of the lower sub-film layer.
  • the barrier height of the second portion 232 gradually decreases from the side facing the first portion 231 to the side away from the first portion 231, and the second portion 232 includes
  • the barrier height of the second part 232 also decreases stepwise, as shown in FIG.
  • a schematic diagram of the barrier height of a gallium nitride layer and a barrier layer in the gate region, where n is 6 for example, and x6 0, and from right to left are gallium nitride layers (GaN) 220 , the first part (Al x1 Ga 1-x1 N) 231, the second part (Al x2 Ga 1-x2 N, Al x3 Ga 1-x3 N, Al x4 Ga 1-x4 N, Al x5 Ga 1-x5 N, GaN)232, where Al x1 Ga 1-x1 N, Al x2 Ga 1-x2 N, Al x3 Ga 1-x3 N, Al x4 Ga 1-x4 N, Al x5 Ga 1-x5 N are collectively represented as AlGaN, from In the direction from right to left, the barrier height of the second part 232 decreases successively, so that the number of holes generated on the side of the first part 231 away from the gallium nitride layer 220 is expressed as ⁇ p1 ,
  • the second part 232 can also be an integrated structure without obvious boundaries, that is, there may be no obvious sudden change in the aluminum content in the second part 232, and the aluminum concentration of the second part 232 changes from the side facing the first part 231 to the side away from the first part 231.
  • One side of a part of 231 shows a downward trend, and this downward trend can be continuous or non-uniform downward.
  • the aluminum concentration at different film layer heights inside the first part 231 is the same, and the aluminum concentration in the second part 232 decreases at a constant speed from the side facing the first part 231 to the side away from the first part 231 .
  • the aluminum concentration of the second portion 232 may increase to a small degree in a small amount from the side facing the first portion 231 to the side away from the first portion 231 .
  • the first part 231 and the second part 232 can also be an integral structure without obvious boundaries, and the aluminum in the first part 231 is evenly distributed.
  • the molar ratio of aluminum and gallium in the barrier layer located in the non-gate region is greater than or equal to 3/7, that is, the molar ratio of aluminum and gallium in the first part 231 is greater than or equal to 3/7, that is, the aforementioned x1 ⁇ 30%, so the first part 231 has a higher potential barrier height and can effectively generate two-dimensional electron gas.
  • the two-dimensional electron gas channel 222 generated between the relatively low-thickness AlGaN layer and the GaN layer 220 is easily depleted, so the first part 231 can be set to have a smaller thickness, specifically
  • the size of the first portion 231 (ie, the barrier layer of the non-gate region 1002 ) along the direction perpendicular to the surface of the GaN layer 220 (ie, the vertical size) may be less than or equal to 30 nm, for example, 5 nm.
  • a passivation layer 240 can also be formed on the surface of the first part 231 (ie, the surface of the barrier layer of the non-gate region 1001) to generate stress, so that the two-dimensional electron gas in the first part 231 can channel 222 regeneration, which is beneficial to realize a channel with a high charge transfer rate, as shown in FIG. 4 .
  • the passivation layer 240 covers the barrier layer (ie, the first part 231) located in the non-gate region 1002, and may also cover the barrier layer (ie, the second part 232) of the gate region 1001, for example, the second part 232 covers the gate region 1001
  • the first part 231 covers the sidewall of the second part 232
  • the passivation layer 240 can also cover part of the upper surface of the second part 232 .
  • the material of the passivation layer 240 may be at least one of silicon nitride and aluminum carbide.
  • the gate 251 is formed on the side of the barrier layers 231 & 232 of the gate region 1001 away from the GaN layer 220 , that is, formed on the second portion 232 .
  • part of the upper surface of the second portion 232 is covered with a passivation layer 240 , and the gate 251 may penetrate through the passivation layer 240 covering the second portion 232 , as shown in FIG. 4 .
  • the gate 251 may include a first gate structure and a second gate structure electrically connected, the first gate structure penetrates the passivation layer 240, and the second gate structure is formed on the first gate structure.
  • the structure is away from the side of the substrate 200 and covers part of the surface of the passivation layer 240, that is, the gate 251 can form a "T"-shaped structure. Referring to FIG. 4, the gate 251 can cover part of the upper surface of the second part 232, and Covering part of the upper surface of the passivation layer 240 facilitates the extraction of the gate 251 .
  • the gate 251 may also cover the entire upper surface of the second part 232 to form a planar structure, and the side walls of the gate 251 and the second part 232 may be flush, as shown in FIG. 8 .
  • a schematic structural diagram of another gallium nitride device provided in the embodiment of the present application, the passivation layer may cover the sidewall of the gate 251 .
  • the gate 251 and the second part 232 can be in direct contact to form a Schottky gate device structure. Referring to FIG. 4 and FIG. 8 , compared to using the gate 251 to contact the first part 231, The scheme that the gate 251 is in contact with the second portion 232 reduces the forward leakage of the device.
  • a gate dielectric layer 260 may also be formed between the gate 251 and the second part 232 of the barrier layer to form an insulated gate device structure.
  • the gate dielectric layer 260 is directly in contact with the first part 231 with a higher aluminum concentration, the solution that the gate 251 is in contact with the gate dielectric layer 260 and the gate dielectric layer 260 is in contact with the second part 232 reduces interface defects, Improve the threshold stability of the device.
  • FIG. 9 is a schematic structural diagram of another gallium nitride device provided in the embodiment of the present application. This figure shows that a gate dielectric is added on the basis of the gallium nitride structure in FIG.
  • the gallium nitride structure behind the layer 260 is schematically shown, wherein the gate 251 includes a first gate structure and a second gate structure electrically connected, and the gate dielectric layer 260 is formed between the gate 251 and the second part 232, thereby covering the first Part of the upper surface of the two parts 232, the gate dielectric layer 260 can also be formed between the gate 251 and the passivation layer 240, thereby covering the sidewall of the passivation layer 240 facing the gate 251, of course, the gate dielectric layer 260 can also be Covering the sidewall of the passivation layer 240 away from the gate 251 , and covering the surface of the part of the first portion 231 .
  • FIG. 10 is a schematic structural diagram of another gallium nitride device provided in the embodiment of the application.
  • This figure shows that a gate dielectric is added on the basis of the gallium nitride structure in FIG. 8
  • the gallium nitride structure behind the layer 260 is schematically shown, wherein the gate dielectric layer 260 covers the entire upper surface of the second part 232, the gate 251 covers the entire upper surface of the gate dielectric layer 260, and the passivation layer 240 may cover the entire upper surface of the gate dielectric layer 260.
  • the sidewall can also cover the sidewall of the gate 251
  • the gallium nitride device may further include a source 252 and a drain 253, and the source 252 and the drain 253 are located on the side of the barrier layer of the non-gate region 1002 away from the gallium nitride layer 220, that is Located on the first portion 231 , the source 252 and the drain 253 are respectively located on two sides of the gate 251 .
  • the source electrode 252, the drain electrode 253, and the grid electrode 251 are all made of materials with better conductivity.
  • the material of at least one of the source electrode 252, the drain electrode 253, and the grid electrode 251 is: nickel, titanium, aluminum, palladium, platinum, At least one of gold, titanium nitride, tantalum nitride and copper.
  • the gallium nitride device may include a gallium nitride layer, a barrier layer on the surface of the gallium nitride layer, and a gate on the side of the barrier layer away from the gallium nitride layer.
  • the gallium layer has a gate region and a non-gate region on the periphery of the gate region.
  • Elements of the composition material of the barrier layer include aluminum, gallium and nitrogen.
  • the barrier layer is located in the gate region and the non-gate region.
  • the size of the barrier layer located in the gate region is larger than the size of the barrier layer located in the non-gate region, and the aluminum concentration of the barrier layer located in the gate region facing the gallium nitride layer is higher than The aluminum concentration on the side facing the gate, so that the aluminum concentration in the barrier layer decreases gradually in the direction away from the gallium nitride layer in the gate region.
  • the barrier layer can naturally be equivalent to p-type doping.
  • the embodiment of the present application also provides a method for manufacturing a gallium nitride device.
  • FIG. 11 it is a gallium nitride device provided in the embodiment of the present application
  • the flow chart of the manufacturing method, Figure 12- Figure 21 is a schematic structural diagram of the gallium nitride device in the manufacturing process provided in the embodiment of the present application, the manufacturing method may include:
  • the thickness of the gallium nitride layer 220 can be relatively large, so the gallium nitride layer 220 can be a substrate made of gallium nitride, which provides support for the film layer on it, and at the same time acts as an AlGaN substrate. /GaN heterostructure components.
  • the thickness of the gallium nitride layer 220 can be relatively thin.
  • the gallium nitride layer 220 can be formed on the substrate 200, and the substrate 200 provides support for the film layer , the gallium nitride layer 220 is a component of the AlGaN/GaN heterostructure, wherein the material of the substrate 200 can be one or more of aluminum nitride (AlN), silicon (Si), silicon carbide (SiC), and sapphire kind.
  • a buffer layer 210 may also be provided between the substrate 200 and the gallium nitride layer 220, and the material of the buffer layer 210 may be aluminum nitride, or gallium nitride grown at a low temperature.
  • the buffer layer 210 may be formed on the surface of the substrate 200 first, and then the gallium nitride layer 220 is formed on the buffer layer 210 .
  • the gallium nitride layer 220 may be formed by metal organic chemical vapor deposition (Metal organic chemical vapor deposition, MOCVD).
  • the gallium nitride layer 220 may have a gate region 1001 and a non-gate region 1002 around the gate region 1001 , and the gate region 1001 and the non-gate region 1002 are regions on the surface of the gallium nitride layer 220 .
  • the gate region 1001 is used to form the gate 251, which can be the central region between the regions where the source 252 and the drain 253 are located.
  • the gate region 1001 can be larger than the region where the gate 251 is located, or can be equal to the area where the gate 251 is located. Refer to As shown in FIG. 12 , the dashed-line frame in the middle represents the gate region 1001 , and the dashed-line frames on both sides of the gate region 1001 represent the non-gate region 1002 .
  • barrier layers 231 & 232 on one side of the gallium nitride layer 220, and the gate 251 located on the side of the barrier layers 231 & 232 in the gate region 1001 away from the gallium nitride layer 220, refer to FIGS. 13-21 .
  • the barrier layers 231 & 232 can be formed on the surface of the gallium nitride layer 220, the barrier layers 231 & 232 are located on one side surface of the gallium nitride layer 220, and the constituent materials of the barrier layers 231 & 232 include aluminum, gallium and Nitrogen, its constituent material can be expressed as aluminum gallium nitride (Al x Ga 1-x N), the material of the gallium nitride layer 220 is the barrier layers 231 & 232 of aluminum gallium nitride to form a heterostructure of AlGaN/GaN, thereby producing a two-dimensional GaN devices formed based on this electron gas can work with the two-dimensional electron gas generated by the heterostructure.
  • the barrier layers 231 & 232 are disposed on the side of the GaN layer 220 away from the substrate 200 .
  • the barrier layers 231 & 232 are located in the gate region 1001 and the non-gate region 1002, and the size of the barrier layer in the gate region 1001 is The size of the barrier layer in the non-gate region 1002 is larger than that of the barrier layer in the non-gate region 1002 , and the aluminum concentration on the side of the barrier layer facing the GaN layer 220 in the gate region 1001 is higher than that on the side facing the gate 251 .
  • the concentration of aluminum on the side of the barrier layer of the gate region 1001 facing the gallium nitride layer 220 is higher than the concentration of aluminum on the side facing the gate 251.
  • the barrier layer of the gate region 1001 faces the gallium nitride layer.
  • the concentration of gallium on the side of layer 220 is higher than the concentration of gallium on the side facing gate 251, since this arrangement is located in gate region 1001, in gate region 1001 from the side facing gallium nitride layer 220 to Towards the side of the gate 251, the reduction of the aluminum composition is realized, and the part with the lower aluminum composition has a lower barrier height, so the barrier height between the part with the lower aluminum composition and the gallium nitride layer 220 is lower.
  • the hole concentration is strongly related to the activation of Mg, so the activation temperature and doping concentration of p-GaN need to be precisely controlled.
  • the holes in the examples of this application are generated by the polarization effect.
  • the number of holes is basically equal to the number of electrons in the two-dimensional electron gas channel 222 of the gate region 1001, and many problems such as the need to accurately control the activation of holes in the Mg doping technology do not exist; at the same time, because there is no p-GaN layer, Therefore, there is no problem of defect states caused by Mg diffusion; at the same time, the threshold voltage of the device is determined by the structure of the gate region 1001, the process window is large, and there is no problem that the threshold voltage is sensitive to Mg doping concentration and p-GaN activation conditions.
  • the barrier layer may include a first portion 231 facing the gallium nitride layer 220 and a second portion 232 facing the gate 251, wherein the first portion 231 is formed in the gate region 1001 and the non-gate region 1002, and the second portion 232
  • the projection on the surface of the gallium nitride layer 220 is located in the gate region, that is, the second part 232 is formed on the first part 231 of the gate region 1001.
  • the second part 232 is formed on the gate region 1001, and the aluminum in the first part 231 concentration is higher than the concentration of aluminum in the second part 232, correspondingly, the concentration of gallium in the first part 231 is higher than the concentration of gallium in the second part 232, since the second part 232 is formed in the gate region 1001, so in From the first part 231 to the second part 232 in the gate region 1001, the reduction of aluminum composition is realized, and the part with lower aluminum composition has a lower barrier height, so the part with lower aluminum composition and gallium nitride There is a lower potential barrier between the layers 220.
  • the barrier layers 231 & 232 of the gate region 1001 are naturally equivalent to p-type doping without Mg doping, and the number of holes is basically equal to the number of electrons in the two-dimensional electron gas channel 222 of the gate region 1001, The electrons in the two-dimensional electron gas channel 222 can be naturally depleted.
  • the molar ratio of aluminum and gallium in the barrier layer located in the non-gate region is greater than or equal to 3/7, that is, the molar ratio of aluminum and gallium in the first part 231 is greater than or equal to 3/7, that is, the aforementioned x1 ⁇ 30%, so the first part 231 has a higher potential barrier height and can effectively generate two-dimensional electron gas.
  • the size of the first part 231 (that is, the barrier layer of the non-gate region 1002) along the direction perpendicular to the surface of the gallium nitride layer 220 (that is, the longitudinal dimension) may be less than or equal to 30 nm, for example, it may be 5 nm, and the aluminum gallium nitride layer is within this size range.
  • the two-dimensional electron gas channel in the gate region 1001 is easily depleted.
  • the AlGaN material layer 230 can be formed on one side surface of the GaN layer 220 first, as shown in FIG.
  • the gallium nitride material layer 230 is etched so as to be thinned to obtain a barrier layer.
  • the barrier layer may include a first part 231 and a second part 232.
  • the first part 231 is located in the gate region 1001 and the non-gate region 1002, and the second part 232 is located in Gate region 1001, as shown in FIG. 14, and then form gate 251 on the side of the barrier layer located in gate region 1001 away from the gallium nitride layer 220, refer to FIGS. 15-17, FIG. 4, and 9.
  • the elements of the constituent materials of the AlGaN material layer 230 include aluminum, gallium and nitrogen, and the concentration of aluminum on the side of the AlGaN material layer 230 facing the GaN layer 220 is higher than that on the side away from the GaN layer 220.
  • Aluminum concentration is higher than that on the side away from the GaN layer 220.
  • the AlGaN material layer 230 has a higher aluminum concentration on the side facing the GaN layer 220, and a lower Al content on the side facing away from the GaN layer 220, and the entire AlGaN material layer 230 may have no obvious
  • the integral structure of the boundary can also include multiple sub-layers. Specifically, when the AlGaN material layer 230 has an integrated structure, it can be obtained through the same deposition process.
  • the aluminum concentration at different thicknesses can be adjusted by adjusting the deposition rates of aluminum and gallium respectively, and the non-gate region 1002 Etching the AlGaN material layer 230 is equivalent to thinning part of the AlGaN material layer 230, and the part that still covers the gate region 1001 and the non-gate region 1002 after thinning is regarded as the first part 231, which is located at the gate
  • the part of the area 1001 is regarded as the second part 232.
  • an interface is set for the first part 231 and the second part 232.
  • the interface is the plane where the upper surface of the first part 231 is located, which is represented by the horizontal dotted line in FIG. 14 , the same expression is used in the subsequent structural diagrams.
  • the formed barrier layers 231&232 have a larger thickness in the gate region 1001, and have a smaller thickness in the non-gate region 1002, and the thickness of the barrier layers 231&232 in the non-gate region 1002 is equal to the thickness of the first part 231, and in the gate region
  • the thickness of the region 1001 is equal to the sum of the thickness of the first portion 231 and the thickness of the second portion 232 , as shown in FIG. 14 .
  • the AlGaN material layer 230 can be formed by MOCVD
  • the AlGaN material layer 230 can be etched by a photolithography process
  • the etching method can be anisotropic dry etching
  • the etched thickness can be Controlled by etch rate and etch time.
  • a passivation layer 240 may also be formed on the surface of the barrier layer in the non-gate region 1002 to generate stress to regenerate the two-dimensional electron gas channel 222 in the first part 231 , which is conducive to the realization of a channel with high charge transfer rate.
  • the material of the passivation layer 240 may be at least one of silicon nitride and aluminum carbide.
  • the gate 251 is formed on the side of the barrier layer in the gate region 1001 away from the gallium nitride layer 220, which may be specifically formed as a passivation layer 240 covering the barrier layer, as shown in FIG.
  • the formed passivation layer 240 covers the first part 231 and the second part 232 , eg covers the sidewall of the second part 232 , and may also cover part of the upper surface of the second part 232 , as shown in FIG. 4 .
  • the gate 251 may include a first gate structure and a second gate structure electrically connected, the first gate structure is located in the gate hole and penetrates the passivation layer 240, and the second gate structure is formed on the first gate
  • the structure is away from the side of the substrate 200 and covers a part of the surface of the passivation layer 240 , that is, the gate 251 can form a “T”-shaped structure, which improves the extraction reliability of the gate 251 .
  • the first gate structure and the second gate structure can be formed by deposition and etching. Specifically, a conductor material can be deposited so that the conductor material fills the gate hole 270 and covers the gate hole 270.
  • the conductor material It may be at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride and copper. Then the conductive material outside the gate region 1001 can be removed to form a gate located in the gate region 1001 .
  • the gate 251 may also only include the first gate structure penetrating the passivation layer 240 .
  • the gate 251 and the second part 232 can be in direct contact to form a Schottky gate device structure, as shown in FIG. , reducing the forward leakage of the device; a gate dielectric layer 260 may also be formed between the gate 251 and the second part 232 in the barrier layer to form an insulated gate device structure. Referring to FIG.
  • the gate dielectric layer 260 and The second part 232 is in contact with the gate dielectric layer 260 in contact with the first part 231 with a higher aluminum concentration, and the gate dielectric layer 260 is directly in contact with the first part 231 with a higher aluminum concentration, and the gate 251 is in contact with the gate dielectric layer 260
  • the solution that the gate dielectric layer 260 is in contact with the second portion 232 reduces interface defects and improves the threshold stability of the device.
  • a gate dielectric layer 260 may be formed between the second portion 232 and the gate 251 .
  • the gate dielectric material layer 262 can be formed on the AlGaN material layer 230, and when the AlGaN material layer 230 located in the non-gate region 1002 is etched, the AlGaN material layer 262 located in the non-gate region 1002 is also etched.
  • gate dielectric material layer 262 on the layer 230 is etched to form the gate dielectric layer 260 located in the gate region 1001, the gate dielectric layer 260 is located between the gate 251 and the barrier layer, and the passivation layer 240 is formed on the gate dielectric layer Above 260 , gate hole 270 obtained by etching passivation layer 240 exposes gate dielectric layer 260 .
  • the gate dielectric layer 260 may be deposited and formed, the gate dielectric layer 260 covers the passivation layer 240, and covers the sidewall and bottom of the gate hole 270, as shown in FIG.
  • a gate 251 is formed in the gate hole 270 , as shown in FIG. 9 .
  • an aluminum gallium nitride material layer 230 can be formed on one side surface of the gallium nitride layer 220, and the aluminum gallium nitride material layer 230 is located away from the gallium nitride material layer.
  • the gate material layer 253 on one side of the layer 220 as shown in FIG.
  • the first part 231 of 1002 is shown with reference to FIGS.
  • the constituent elements of the AlGaN material layer 230 include aluminum, gallium, and nitrogen; the concentration of aluminum on the side of the AlGaN material layer 230 facing the GaN layer 220 is higher than that on the side away from the GaN layer 220
  • the concentration of aluminum, the material of the gate material layer 253 can be at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride and copper.
  • the part of the AlGaN material layer 230 facing the GaN layer 220 has a higher aluminum concentration, while the part facing away from the GaN layer 220 has a lower Al content.
  • the entire AlGaN material layer 230 may have an integral structure, or Multiple film layers may be included. Specifically, when the AlGaN material layer 230 has an integrated structure, it can be obtained through the same deposition process.
  • the aluminum concentration at different thicknesses can be adjusted by adjusting the deposition rates of aluminum and gallium respectively, and the non-gate region 1002 Etching the AlGaN material layer 230 is equivalent to thinning part of the AlGaN material layer 230, and the part that still covers the gate region 1001 and the non-gate region 1002 after thinning is regarded as the first part 231, which is located at the gate
  • the part of the area 1001 is regarded as the second part 232.
  • an interface is set for the first part 231 and the second part 232.
  • the interface is the plane where the upper surface of the first part 231 is located, which is represented by the horizontal dotted line in FIG. 19 .
  • the formed barrier layers 231&232 have a larger thickness in the gate region 1001, and have a smaller thickness in the non-gate region 1002.
  • the thickness of the barrier layers 231&232 in the non-gate region 1002 is equal to the thickness of the first part 231, and in the gate region
  • the thickness of the region 1001 is equal to the sum of the thickness of the first portion 231 and the thickness of the second portion 232 , as shown in FIG. 19 .
  • the gate 251 and the second part 232 can be in direct contact to form a Schottky gate device structure. As shown in FIG. The scheme reduces the forward leakage of the device; a gate dielectric layer 260 may also be formed between the gate 251 and the second part 232 to form an insulated gate device structure, as shown in FIG. 10 , compared with the gate dielectric layer 260 and The first part 231 with higher aluminum concentration is in contact, and the gate dielectric layer 260 is directly in contact with the first part 231 with higher aluminum concentration, the gate 251 is in contact with the gate dielectric layer 260 and the gate dielectric layer 260 is in contact with the second part 232
  • the scheme reduces the interface defects and improves the threshold stability of the device.
  • the gate dielectric material layer 262 between the AlGaN material layer 230 and the gate material layer 253 can also be formed, as shown in FIG.
  • the non-gate region 1002 can be simultaneously The gate dielectric material layer 262 on the side of the aluminum gallium nitride material layer away from the gallium nitride layer is etched to obtain the gate dielectric layer 260 located in the gate region 1001, and the gate dielectric layer 260 is located between the barrier layers 231&232 and between the gates 251, as shown in FIG. 21 .
  • a passivation layer 240 may also be formed on the surface of the barrier layer of the non-gate region 1002 (that is, the surface of the first part 231) to generate stress, so that the two in the first part 231
  • the regeneration of the dimensional electron gas channel 222 is conducive to realizing a channel with a high charge transfer rate.
  • the material of the passivation layer 240 may be at least one of silicon nitride and aluminum carbide.
  • the concentration of aluminum in the first part 231 is higher than the concentration of aluminum in the second part 232, which can be reflected in that the average concentration of aluminum in the first part 231 is higher than the average concentration of aluminum in the second part 232, while the second The concentration of aluminum in the second portion 232 can be uniform or non-uniform.
  • the second part 232 may include stacked multi-layer sub-film layers, and the multiple sub-film layers are stacked vertically, wherein the aluminum concentration of the multi-layer sub-film layers may not be completely the same, and the aluminum concentration of the sub-film layers facing the gate 251
  • the concentration is less than the aluminum concentration of the sub-film layer towards the first part 231, that is, the aluminum concentration of the upper sub-film layer can be lower than the aluminum concentration of the lower sub-film layer, so that the aluminum concentration is from the side towards the first part 231 to the side away from the first part 231.
  • One side of part 231 is lowered sequentially, and the aluminum concentration of each sub-film layer shows a downward trend, so as to realize the stepwise decrease of aluminum concentration and enhance the polarization effect in the barrier layers 231 & 232 of the gate region 1001; specifically, the second part 232
  • It can also be an integral structure without obvious boundaries, that is, there may be no obvious sudden change in the aluminum content in the second part 232, and the aluminum concentration in the second part 232 decreases from the side facing the first part 231 to the side away from the first part 231
  • This downward trend can be a continuous uniform decline or a non-uniform decline.
  • the aluminum concentration at different film layer heights inside the first part 231 is the same, and the aluminum concentration in the second part 232 decreases at a constant speed from the side facing the first part 231 to the side away from the first part 231 .
  • the source electrode 252 and the drain electrode 253 can also be formed on the barrier layer of the non-gate region 1002, that is, the source electrode 252 and the drain electrode 253 are formed on the first part 231, respectively located on both sides of the gate electrode 251
  • the source electrode 252 and the drain electrode 253 may be formed on the surface of the first portion 231 , or may be formed in a through hole obtained by etching the first portion 231 .
  • the material of the source electrode 252 and/or the drain electrode 253 is at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride and copper.
  • An embodiment of the present application provides a method for manufacturing a gallium nitride device.
  • a gallium nitride layer is obtained.
  • the gallium nitride layer has a gate region and a non-gate region around the gate region, and a potential is formed on one side of the gallium nitride layer.
  • the aluminum concentration on one side of the layer is higher than the aluminum concentration on the side facing the gate, so that the aluminum concentration in the barrier layer in the direction away from the gate region away from the GaN layer decreases gradually, based on the polarization effect, the barrier layer can naturally It is equivalent to p-type doping without Mg doping, so that the electrons at the AlGaN/GaN interface in the gate region can be naturally depleted, and the two-dimensional electron gas channel in the non-gate region is not de
  • the embodiment of the present application also provides an electronic device, the electronic device includes a circuit board, and a gallium nitride device connected to the circuit board, and the gallium nitride device can be Any of the gallium nitride devices provided above.
  • the circuit board may be a printed circuit board (printed circuit board, PCB), and of course the circuit board may also be a flexible circuit board (FPC), etc., and this embodiment does not limit the circuit board.
  • the electronic device is different types of user equipment or terminal equipment such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices; the electronic device may also be network equipment such as base stations.
  • the electronic device further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB through solder balls, and the gallium nitride device is fixed on the packaging substrate through solder balls.
  • a non-transitory computer-readable storage medium for use with a computer having software for creating a gallium nitride device, the computer-readable storage medium having stored thereon one or A plurality of computer readable data structures, one or more computer readable data structures having photomask data for fabricating the gallium nitride device provided in any one of the illustrations provided above.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本申请实施例公开了一种氮化镓器件及其制造方法、电子设备，氮化镓器件可以包括氮化镓层、氮化镓层一侧表面的势垒层以及势垒层的背离氮化镓层一侧的栅极，氮化镓层具有栅极区域和栅极区域外围的非栅区域，势垒层的组成材料的元素包括铝(Al)、镓(Ga)和氮(N)，势垒层位于栅极区域和非栅区域，在沿垂直氮化镓层的表面的方向上，位于栅极区域的势垒层的尺寸大于位于非栅区域的势垒层的尺寸，且位于栅极区域的势垒层朝向氮化镓层的一侧的铝浓度高于朝向栅极的一侧的铝浓度，这样在栅极区域背离氮化镓层的方向上势垒层中的铝浓度递减，基于极化效应使势垒层天然可以等效为p型掺杂而无需Mg掺杂，从而使栅极区域的AlGaN/GaN界面的电子可以被天然的耗尽，而非栅区域的二维电子气沟道不被耗尽，且在构成常关型氮化镓器件的同时，不会由于Mg掺杂而在非栅区域的势垒层中形成缺陷态，因此降低器件的动态电阻退化和HTOL后电阻退化的风险，利于得到性能优异的氮化镓器件。

Description

一种氮化镓器件及其制造方法、电子设备 技术领域
本申请涉及半导体制造技术领域，尤其涉及一种氮化镓器件及其制造方法、电子设备。
背景技术
随着电源类产品朝着高效率和小型化的趋势发展，以宽禁带半导体材料氮化镓(GaN)为基础制备的功率开关等氮化镓器件越来越受到关注。
目前，氮化镓器件主要包含基于铝镓氮(AlGaN)/GaN的异质结构的器件，例如高电子迁移率晶体管(high electron mobility transistor，HEMT)，AlGaN/GaN的异质结构能够在其界面天然形成高迁移率的二维电子气(two-dimensional electron gas，2-DEG)沟道，因此基于该异质结构制备的器件表现为常开型开关型器件。但是在开关电源应用领域，常关型氮化镓器件具有兼容Si器件驱动方案、驱动方式简单等优点，更具有市场价值。
在常关型氮化镓器件的制备过程中，可以在栅极区域的AlGaN/GaN异质结表面生长一层p型GaN(p-GaN)层，该p-GaN层通过外延生长过程中掺杂镁(Mg)来耗尽二维电子气沟道，而栅极区域之外的非栅区域不形成p-GaN，从而使栅极区域无沟道，非栅区域有沟道。然而目前的基于p-GaN的常关型氮化镓器件存在动态电阻退化严重以及高温工作寿命实验(high temperature operating life，HTOL)后电阻退化等可靠性问题。
发明内容
有鉴于此，本申请实施例提供了一种氮化镓器件及其制造方法、电子设备，通过栅极区域形成新的结构来实现沟道耗尽，从而降低动态电阻和HTOL后电阻退化的风险。
本申请实施例的第一方面，提供了一种氮化镓器件，包括氮化镓层、氮化镓层一侧表面的势垒层以及势垒层的背离氮化镓层一侧的栅极，氮化镓层具有栅极区域和栅极区域外围的非栅区域，势垒层的组成材料的元素包括铝(Al)、镓(Ga)和氮(N)，势垒层位于栅极区域和非栅区域，在沿垂直氮化镓层的表面的方向上，位于栅极区域的势垒层的尺寸大于位于非栅区域的势垒层的尺寸，且位于栅极区域的势垒层朝向氮化镓层的一侧的铝浓度高于朝向栅极的一侧的铝浓度，这样在栅极区域背离氮化镓层的方向上势垒层中的铝浓度递减，基于极化效应使势垒层天然可以等效为p型掺杂而无需Mg掺杂，从而使栅极区域的AlGaN/GaN界面的电子可以被天然的耗尽，而非栅区域的二维电子气沟道不被耗尽，且在构成常关型氮化镓器件的同时，不会由于Mg掺杂而在非栅区域的势垒层中形成缺陷态，因此降低器件的动态电阻退化和HTOL后电阻退化的风险，利于得到性能优异的氮化镓器件。
在一些可能的实施方式中，所述势垒层包括朝向所述氮化镓层的第一部分和朝向所述栅极的第二部分，所述第一部分的铝浓度高于所述第二部分的铝浓度，所述第一部分位于所述栅极区域和所述非栅区域，所述第二部分在氮化镓层表面的投影位于所述栅极区域。
本申请实施例中，势垒层可以包括第一部分和第二部分，第一部分的铝浓度高于第二部分的铝浓度，且第二部分位于栅极区域的第一部分上，栅极区域的第一部分和第二部分 天然可以等效为p型掺杂而无需Mg掺杂，利于栅极区域的沟道耗尽。
在一些可能的实施方式中，所述第一部分为第一膜层，所述第二部分包括堆叠的多层子膜层，且朝向所述栅极的子膜层的铝浓度小于朝向所述第一部分的子膜层的铝浓度。
本申请实施例中，第一部分为第一膜层，第二部分包括堆叠层的多个子膜层，使势垒层能够构成多层结构，且浓度依次下降，增强栅极区域的势垒层中的极化效应，利于铝浓度的控制和栅极区域沟道的耗尽。
在一些可能的实施方式中，所述第二部分的铝浓度从朝向所述第一部分的一侧至背离所述第一部分的一侧呈下降趋势。
本申请实施例中，第二部分可以为一体结构，该一体结构不具有明显的分界线，且内部的铝浓度从朝向第一部分的一侧至背离第一部分的一侧呈下降趋势，使铝浓度渐变设置，增强栅极区域的势垒层中的极化效应，利于铝浓度的控制和栅极区域沟道的耗尽。
在一些可能的实施方式中，位于所述非栅区域的势垒层在垂直所述氮化镓层的表面的方向上的尺寸小于或等于30nm。
本申请实施例中，非栅区域的势垒层的厚度较小，使栅极区域的能够产生二维电子气的势垒层的厚度也较小，利于栅极区域沟道的耗尽。
在一些可能的实施方式中，位于所述非栅区域的势垒层中铝和镓的摩尔比大于或等于3/7。
本申请实施例中，位于非栅区域的势垒层中的铝和镓的摩尔比大于或等于一个预设值，使非栅区域的势垒层具有较大的铝浓度，利于势垒层和铝镓氮层之间产生足够的二维电子气，利于形成非栅区域的沟道。
在一些可能的实施方式中，所述氮化镓器件还包括：
源极和漏极，所述源极和漏极位于所述非栅区域的势垒层的背离所述氮化镓层的一侧上。
本申请实施例中，氮化镓器件还包括源极和漏极，分别位于栅极两侧，用于施加源极信号和漏极信号。
在一些可能的实施方式中，所述源极、漏极、栅极中的至少一种的材料为：镍、钛、铝、钯、铂、金、氮化钛、氮化钽以及铜中的至少一种。
本申请实施例中，源极、漏极和栅极的材料为导电性较好的材料，利于提高器件性能。
在一些可能的实施方式中，所述氮化镓器件还包括：
钝化层，所述钝化层覆盖位于所述非栅区域的势垒层。
本申请实施例中，氮化镓器件还包括钝化层，用于为势垒层提供应力，促进非栅区域的二维电子气沟道再生，利于得到高电荷传输率的沟道。
在一些可能的实施方式中，所述钝化层还覆盖位于所述栅极区域的势垒层；所述栅极包括电连接的第一栅极结构和第二栅极结构，所述第一栅极结构贯穿所述钝化层，所述第二栅极结构形成于所述第一栅极结构背离所述氮化镓层的一侧且覆盖所述钝化层的部分表面。
本申请实施例中，栅极可以包括两部分，构成“T”形结构，利于栅极的引出。
在一些可能的实施方式中，所述钝化层的材料为氮化硅、碳化铝中的至少一种。
本申请实施例中，钝化层为能够为势垒层提供应力的材料，利于非栅区域的沟道再生。
在一些可能的实施方式中，所述氮化镓器件还包括：
位于所述势垒层和所述栅极之间的栅介质层。
本申请实施例中，势垒层和栅极之间可以具有栅介质层，相比于栅极和势垒层直接接触，减少了界面缺陷，提高器件的阈值稳定性。
在一些可能的实施方式中，所述氮化镓器件还包括：
基底，位于所述氮化镓层背离所述势垒层的一侧。
本申请实施例中，氮化镓层可以设置在基底上，利用基底为氮化镓层提供支撑。
在一些可能的实施方式中，所述氮化镓器件还包括：
位于所述基底和所述氮化镓层之间的缓冲层。
本申请实施例中，氮化镓层和基底之间形成有缓冲层，利于形成质量较好的氮化镓层。
本申请实施例第二方面，提供了一种氮化镓器件的制造方法，包括：
获取氮化镓层，所述氮化镓层具有栅极区域和所述栅极区域外围的非栅区域；
在所述氮化镓层的一侧表面形成势垒层，以及位于所述栅极区域的势垒层的背离所述氮化镓层的一侧的栅极，所述势垒层的组成材料的元素包括铝、镓和氮；所述势垒层位于栅极区域和非栅区域，在沿垂直所述氮化镓层的表面的方向上，位于所述栅极区域的势垒层的尺寸大于位于所述非栅区域的势垒层的尺寸，且位于所述栅极区域的势垒层朝向所述氮化镓层的一侧的铝浓度高于朝向所述栅极的一侧的铝浓度。
在一些可能的实施方式中，所述势垒层包括朝向所述氮化镓层的第一部分和朝向所述栅极的第二部分，所述第一部分的铝浓度高于所述第二部分的铝浓度，所述第一部分位于所述栅极区域和所述非栅区域，所述第二部分在氮化镓层表面的投影位于所述栅极区域。
在一些可能的实施方式中，所述第一部分为第一膜层，所述第二部分包括堆叠的多层子膜层，且朝向所述栅极的子膜层的铝浓度小于朝向所述第一部分的子膜层的铝浓度。
在一些可能的实施方式中，所述第二部分的铝浓度从朝向所述第一部分的一侧至背离所述第一部分的一侧呈下降趋势。
在一些可能的实施方式中，位于所述非栅区域的势垒层在垂直所述氮化镓层的表面的方向上的尺寸小于或等于30nm。
在一些可能的实施方式中，位于所述非栅区域的势垒层中铝和镓的摩尔比大于或等于3/7。
在一些可能的实施方式中，所述方法还包括：
在所述非栅区域的势垒层的背离所述氮化镓层的一侧形成源极和漏极。
在一些可能的实施方式中，所述源极、漏极、栅极中的至少一种的材料为：镍、钛、铝、钯、铂、金、氮化钛、氮化钽以及铜中的至少一种。
在一些可能的实施方式中，所述在所述氮化镓层的一侧表面形成势垒层，以及位于所述栅极区域的势垒层的背离所述氮化镓层的一侧的栅极，包括：
在所述氮化镓层的一侧表面形成铝镓氮材料层，所述铝镓氮材料层的组成材料的元素 包括铝、镓和氮；所述铝镓氮材料层朝向所述氮化镓层一侧的铝浓度高于背离所述氮化镓层一侧的铝浓度；
对位于所述非栅区域的铝镓氮材料层进行减薄，得到势垒层；
在位于所述栅极区域的势垒层的背离所述氮化镓层的一侧形成栅极。
在一些可能的实施方式中，所述在位于所述栅极区域的势垒层的背离所述氮化镓层的一侧形成栅极，包括：
形成覆盖所述势垒层的钝化层；
对覆盖所述栅极区域的势垒层的钝化层进行刻蚀，形成贯穿所述钝化层的栅极孔，并在所述栅极孔内形成栅极。
在一些可能的实施方式中，所述栅极包括电连接的第一栅极结构和第二栅极结构，所述第一栅极结构位于所述栅极孔内，所述第二栅极结构形成于所述第一栅极结构背离所述氮化镓层的一侧且覆盖所述钝化层的部分表面。
在一些可能的实施方式中，形成所述栅极之前，所述方法还包括：
在所述势垒层和所述栅极之间形成栅介质层。
在一些可能的实施方式中，所述在所述氮化镓层的一侧表面形成势垒层，以及位于所述栅极区域的势垒层的背离所述氮化镓层的一侧的栅极，包括：
在所述氮化镓层的一侧表面形成铝镓氮材料层，以及位于所述铝镓氮材料层的背离所述氮化镓层的一侧的栅极材料层；所述铝镓氮材料层的组成材料的元素包括铝、镓和氮；所述铝镓氮材料层朝向所述氮化镓层一侧的铝浓度高于背离所述氮化镓层一侧的铝浓度；
对位于所述非栅区域的铝镓氮材料层的背离所述氮化镓层的一侧的栅极材料层进行刻蚀，并对位于所述非栅区域的铝镓氮材料层进行减薄，得到势垒层和位于所述栅极区域的势垒层的背离所述氮化镓层的一侧的栅极。
在一些可能的实施方式中，所述方法还包括：
形成所述铝镓氮材料层和所述栅极材料层之间的栅介质材料层；
所述对位于所述非栅区域的铝镓氮材料层的背离所述氮化镓层的一侧的栅极材料层进行刻蚀，并对位于所述非栅区域的所述铝镓氮材料层进行减薄时，还对位于所述非栅区域的铝镓氮材料层的背离所述氮化镓层的一侧的栅介质材料层进行刻蚀，以得到位于所述势垒层和所述栅极之间的栅介质层。
在一些可能的实施方式中，在形成所述势垒层后，所述方法还包括：
形成覆盖所述势垒层的钝化层。
在一些可能的实施方式中，所述钝化层的材料为氮化硅、碳化铝中的至少一种。
在一些可能的实施方式中，所述氮化镓层背离所述势垒层的一侧设置有基底。
在一些可能的实施方式中，所述氮化镓层和所述基底之间设置有缓冲层。
本申请实施例第三方面，提供了一种电子设备，包括电路板，以及与电路板连接的、如本申请第一方面提供的氮化镓器件。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请实施例提供一种氮化镓器件及其制造方法、电子设备，氮化镓器件可以包括氮化镓层、氮化镓层一侧表面的势垒层以及势垒层的背离氮化镓层一侧的栅极，氮化镓层具有栅极区域和栅极区域外围的非栅区域，势垒层的组成材料的元素包括铝(Al)、镓(Ga)和氮(N)，势垒层位于栅极区域和非栅区域，在沿垂直氮化镓层的表面的方向上，位于栅极区域的势垒层的尺寸大于位于非栅区域的势垒层的尺寸，且位于栅极区域的势垒层朝向氮化镓层的一侧的铝浓度高于朝向栅极的一侧的铝浓度，这样在栅极区域背离氮化镓层的方向上势垒层中的铝浓度递减，基于极化效应使势垒层天然可以等效为p型掺杂而无需Mg掺杂，从而使栅极区域的AlGaN/GaN界面的电子可以被天然的耗尽，而非栅区域的二维电子气沟道不被耗尽，且在构成常关型氮化镓器件的同时，不会由于Mg掺杂而在非栅区域的势垒层中形成缺陷态，因此降低器件的动态电阻退化和HTOL后电阻退化的风险，利于得到性能优异的氮化镓器件。
附图说明
为了清楚地理解本申请的具体实施方式，下面将描述本申请具体实施方式时用到的附图做一简要说明。显而易见地，这些附图仅是本申请的部分实施例。
图1为本申请实施例中p-GaN层外延生长的示意图；
图2为本申请实施例中在栅极区域形成p-GaN层的示意图；
图3为本申请实施例中器件的动态电阻和Mg掺杂浓度的相关关系示意图；
图4为本申请实施例提供的一种氮化镓器件的结构示意图；
图5为本申请实施例提供的一种第二部分的结构示意图；
图6为本申请实施例中第一部分和第二部分的浓度分布示意图；
图7为本申请实施例提供的一种氮化镓层和栅极区域中的势垒层的势垒高度示意图；
图8为本申请实施例提供的另一种氮化镓器件的结构示意图；
图9为本申请实施例提供的又一种氮化镓器件的结构示意图；
图10为本申请实施例提供的再一种氮化镓器件的结构示意图；
图11为本申请实施例提供的一种氮化镓器件的制造方法的流程图；
图12-21为本申请实施例中氮化镓器件在制造过程中的结构示意图。
具体实施方式
本申请实施例提供了一种氮化镓器件及其制造方法、电子设备，通过栅极区域形成新的结构来实现沟道耗尽，从而降低动态电阻和HTOL后电阻退化的风险。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、 方法、产品或设备固有的其它步骤或单元。
本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
目前，基于AlGaN/GaN异质结制备的器件常表现为常开型开关型器件，然而常开型的氮化镓器件需要一个稳定的导通电流来保持它的导通，并且必须要在栅极加上一个反向电压，才能使器件关断，这种特性不利于驱动电路的设计，并且器件功耗较高。实际上，在开关电源应用领域，常关型氮化镓器件具有兼容Si器件驱动方案、驱动方式简单等优点，更具有市场价值。
在常关型氮化镓器件的制备过程中，可以在栅极区域的AlGaN/GaN异质结表面形成一层p-GaN层，该p-GaN层通过外延生长过程中掺杂Mg来耗尽二维电子气沟道，而非栅区域不形成p-GaN，从而使栅极区域无沟道，非栅区域有沟道。
实际操作中，AlGaN/GaN异质结会同时形成于栅极区域和非栅区域，即栅极区域和非栅区域均有二维电子气沟道，为了在栅极区域的AlGaN/GaN异质结表面形成p-GaN层，可以先在栅极区域和非栅区域的AlGaN/GaN异质结表面外延形成p-GaN材料层，参考图1所示，为本申请实施例中p-GaN层外延生长的示意图，其中氮化镓层110上形成有铝镓氮层120，氮化镓层110和铝镓氮层120之间形成有二维电子气(图未示出)，在铝镓氮层120上外延形成p-GaN材料层130，p-GaN材料层130中掺杂有Mg；而后刻蚀去除非栅区域的p-GaN材料层来恢复非栅区域的二维电子气沟道，形成位于栅极区域的p-GaN层131，参考图2所示，为本申请实施例中在栅极区域形成p-GaN层的示意图；之后可以在p-GaN层131上形成栅极141，在非栅区域形成源极142和漏极143。然而在外延生长过程中，用于形成p-GaN的Mg原子也会扩散(out-diffuse)到AlGaN势垒层(即铝镓氮层120)中，为铝镓氮层120引入缺陷能级，参考图1和图2所示，这将造成器件在高压开关过程中，电子被这些缺陷能级俘获，造成器件的动态电阻退化以及HTOL后电阻退化等可靠性问题。
器件动态电阻退化与Mg掺杂浓度强相关，p-GaN中的Mg掺杂浓度越高，器件的动态电阻退化越严重，如图3所示，为本申请实施例中器件的动态电阻和Mg掺杂浓度的相关关系示意图，其中横坐标为Mg掺杂浓度，纵坐标为器件的动态电阻，从图中可以看出，Mg掺杂浓度越高，器件动态电阻退化越严重。通过降低Mg浓度可以降低动态电阻的退化，但是器件的阈值电压也会相应的下降，不利于开关应用场景。因此，如何在不影响器件动态电阻的情况下实现栅极区域的二维电子气沟道耗尽，是本领域亟待解决的问题。
基于以上技术问题，本申请实施例提供了一种氮化镓器件及其制造方法、电子设备，氮化镓器件可以包括氮化镓层、氮化镓层一侧表面的势垒层以及势垒层的背离氮化镓层一侧的栅极，氮化镓层具有栅极区域和栅极区域外围的非栅区域，势垒层的组成材料的元素包括铝、镓和氮，势垒层位于栅极区域和非栅区域，在沿垂直氮化镓层的表面的方向上，位于栅极区域的势垒层的尺寸大于位于非栅区域的势垒层的尺寸，且位于栅极区域的势垒层朝向氮化镓层的一侧的铝浓度高于朝向栅极的一侧的铝浓度，这样在栅极区域背离氮化镓层的方向上势垒层中的铝浓度递减，基于极化效应使势垒层天然可以等效为p型掺杂而 无需Mg掺杂，从而使栅极区域的AlGaN/GaN界面的电子可以被天然的耗尽，而非栅区域的二维电子气沟道不被耗尽，且在构成常关型氮化镓器件的同时，不会由于Mg掺杂而在非栅区域的势垒层中形成缺陷态，因此降低器件的动态电阻退化和HTOL后电阻退化的风险，利于得到性能优异的氮化镓器件。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。
参考图4所示，为本申请实施例提供的一种氮化镓器件的结构示意图，包括氮化镓层220、势垒层231&232和栅极251，势垒层231&232位于氮化镓层220的一侧表面，且势垒层231&232的组成材料的元素包括铝、镓和氮，其组成材料可以表示为铝镓氮(Al xGa 1-xN)，氮化镓层220和材料为铝镓氮的势垒层231&232形成AlGaN/GaN的异质结构，从而产生二维电子气，基于此形成的氮化镓器件可以利用该异质结构产生的二维电子气工作。氮化镓器件例如可以为基于氮化镓的高电子迁移率晶体管(high-electron-mobility transistor，HEMT)器件。
作为一种可能的实现方式，氮化镓层220的厚度可以较大，则氮化镓层220可以为材料为氮化镓的基底，该基底为其上的膜层提供支撑作用，同时作为AlGaN/GaN的异质结构的组成部分。
作为另一种可能的实现方式，氮化镓层220的厚度可以较薄，则氮化镓层220可以形成于基底200上，基底200设置于氮化镓层背离势垒层231&232的一侧，基底200为其上的膜层提供支撑作用，氮化镓层220作为AlGaN/GaN的异质结构的组成部分，其中基底200的材料可以为氮化铝(AlN)、硅(Si)、碳化硅(SiC)、蓝宝石中的一种或多种。可选的，在基底200和氮化镓层220之间，还可以设置有缓冲层210，缓冲层210的材料可以为氮化铝，也可以为低温生长的氮化镓，在缓冲层210为低温生长的氮化镓时，氮化镓层220可以为高温生长的氮化镓层，这样低温氮化镓层作为高温氮化镓层和基底200之间的缓冲层210，提高高温氮化镓层的外延质量。
氮化镓层220可以具有栅极区域1001和栅极区域1001外围的非栅区域1002，栅极区域1001和非栅区域1002为氮化镓层220表面上的区域，包括氮化镓层220表面以及垂直氮化镓层220表面的无数条直线界定出的空间，为了便于描述，这里将平行氮化镓层220表面的方向作为横向，将垂直氮化镓层220表面的方向作为纵向。栅极区域1001用于形成栅极251，可以为源极252和漏极253所在区域之间的中心区域，栅极区域1001可以大于栅极251所在区域，也可以等于栅极251所在区域，在图4中，中间的虚线框表示栅极区域1001，栅极区域1001两侧的虚线框表示非栅区域1002，后续结构示意图采用相同的表示方式，由于图4为剖视图，因此实际上非栅区域1002可以位于栅极区域1001的两侧，可以形成包围栅极区域1001的环状区域，例如圆环区域或多边形区域。
本申请实施例中，势垒层231&232位于栅极区域1001和非栅区域1002，在沿垂直氮化镓层220的表面的方向(即纵向)上，位于栅极区域1001的势垒层的尺寸大于位于非栅区域1002的势垒层的尺寸，且栅极区域1001的势垒层朝向氮化镓层220的一侧的铝浓度 高于朝向栅极251的一侧的铝浓度。
栅极区域1001的势垒层朝向氮化镓层220的一侧的铝的浓度高于朝向栅极251的一侧的铝的浓度，相应的，栅极区域1001的势垒层朝向氮化镓层220的一侧的镓的浓度高于朝向栅极251的一侧的镓的浓度，由于这种设置位于栅极区域1001，在栅极区域1001内从朝向氮化镓层220的一侧到朝向栅极251的一侧，实现了铝组分的减少，铝组分较低的部分具有较低的势垒高度，因此铝组分较低的部分和氮化镓层220之间具有较低的势垒，这种从朝向氮化镓层220的一侧到朝向栅极251的一侧铝组分减少的结构中，由于极化效应会在势垒层231&232中产生空穴，因此栅极区域1001的势垒层231&232天然的可以等效为p型掺杂而无需Mg的掺杂，且空穴的数量基本等于栅极区域1001的二维电子气沟道222中的电子数量，二维电子气沟道222中的电子可以被天然耗尽。
此外，相比于p-GaN方案中空穴浓度与Mg的激活强相关所以需要精准控制p-GaN的激活温度和掺杂浓度等参数，本申请实施例中的空穴是由极化效应产生的，空穴的数量基本等于栅极区域1001的二维电子气沟道222中的电子数量，不存在需要精准控制Mg掺杂技术中空穴的激活等诸多问题；同时由于不存在p-GaN层，因此不存在Mg扩散导致的缺陷态的问题；同时器件的阈值电压由栅极区域1001的结构决定，工艺窗口大，不存在阈值电压对Mg掺杂浓度与p-GaN激活条件敏感的问题。
具体的，势垒层231&232可以包括朝向氮化镓层220的第一部分231和朝向栅极251的第二部分232，其中第一部分231形成于栅极区域1001和非栅区域1002中，第二部分232在氮化镓层220表面的投影位于栅极区域，即第二部分232形成于栅极区域1001的第一部分231上，可以认为第二部分232形成于栅极区域1001，为了便于说明，在第一部分231和第二部分232之间设置分界面，分界面为第一部分231的上表面所在平面，在图4的剖视图中，分界面体现为分界线，该分界线为第一部分231上表面所在直线，用水平虚线表示，即第一部分231和第二部分232利用水平虚线分隔开，后续的结构示意图中采用同样的表示方式。也就是说，势垒层从纵向上可以分为第一部分231和第二部分232，第二部分232覆盖位于栅极区域1001的第一部分231。第一部分231和第二部分232是为了方便描述所界定的，不一定有明确的分界线，后续将以第一部分231和第二部分232表示势垒层的不同部分，以第一部分231的表面和第二部分232的表面表示势垒层的表面，其中第二部分232覆盖位于栅极区域1001的第一部分231的表面。
第一部分231中的铝的浓度高于第二部分232中铝的浓度，相应的，第一部分231中的镓的浓度高于第二部分232中的镓的浓度，由于第二部分232形成于栅极区域1001，这样在栅极区域1001内从第一部分231到第二部分232，实现了铝组分的减少，铝组分较低的部分具有较低的势垒高度，因此铝组分较低的部分和氮化镓层220之间具有较低的势垒，这种从第一部分231到第二部分232铝组分减少的结构中，由于极化效应会在第一部分231和第二部分232中产生空穴，因此栅极区域1001的势垒层231&232天然的可以等效为p型掺杂而无需Mg的掺杂，且空穴的数量基本等于栅极区域1001的二维电子气沟道222中的电子数量，二维电子气沟道222中的电子可以被天然耗尽。
本申请实施例中，第一部分231中的铝的浓度高于第二部分232中铝的浓度，可以体 现为第一部分231中铝的平均浓度高于第二部分232中铝的平均浓度，第二部分232中铝的浓度可以是均匀的，也可以是不均匀的。
具体的，第二部分232可以包括堆叠的多层子膜层，多个子膜层在纵向堆叠，其中，多层子膜层的铝浓度可以不完全相同，朝向栅极251的子膜层的铝浓度小于朝向第一部分的子膜层的铝浓度，即位于上层的子膜层的铝浓度可以小于位于下层的子膜层的铝浓度，这样铝浓度从朝向第一部分231的一侧至背离第一部分231的一侧依次降低，各个子膜层的铝浓度呈现下降趋势，实现铝浓度的阶梯式下降，增强栅极区域1001的势垒层231&232中的极化效应。举例来说，参考图5所示，为本申请实施例提供的一种第二部分的结构示意图，第二部分232可以包括堆叠的n-1层子膜层，此外第一部分231可以为第一膜层(图5未示出)，即栅极区域1001的势垒层231&232共包括n层膜层，其中n≥2，第一部分231的成分表示为Al x1Ga 1-x1N，从朝向第一部分231的一侧至背离第一部分231的一侧，子膜层的成分依次表示为Al x2Ga 1-x2N、Al x3Ga 1-x3N、Al x4Ga 1-x4N、…、Al xnGa 1-xnN，其中1≥x1>x2≥x3…≥xn≥0，其中当x1＝1时，对应的第一部分231的材料为AlN；当xn＝0时，对应的子膜层的材料为GaN。
参考图6所示，为本申请实施例中第一部分和第二部分的浓度分布示意图，其中横坐标表示膜层高度，以第一部分231和氮化镓层220的界面为高度零点，从朝向第一部分231的一侧至背离第一部分231的一侧，膜层高度逐渐上升，纵坐标表示Al组分的含量，其中，参考图6A所示，每个子膜层内部不同膜层高度处的铝组分含量相同，从朝向第一部分231的一侧至背离第一部分231的一侧，Al组分的含量呈现阶梯式下降，表示为x1、x2、x3、x4、…、xn呈现阶梯式下降。当然，从朝向第一部分231的一侧至背离第一部分231的一侧，多层子膜层中的铝浓度也可以不是严格的依次下降，其中少量子膜层中的铝浓度也可以略有提高，即可以存在部分上层的子膜层的铝浓度大于位于下层的子膜层的铝浓度。
由于在铝组分较低的部分具有较低的势垒高度，因此第二部分232从朝向第一部分231的一侧至背离第一部分231的一侧势垒高度逐渐降低，在第二部分232包括纵向堆叠的多层子膜层，且多层子膜层的铝浓度呈阶梯式下降时，第二部分232的势垒高度也呈阶梯式下降，参考图7所示，为本申请实施例提供的一种氮化镓层和栅极区域中的势垒层的势垒高度示意图，其中以n为6进行举例说明，且x6＝0，从右向左依次为氮化镓层(GaN)220、第一部分(Al x1Ga 1-x1N)231、第二部分(Al x2Ga 1-x2N、Al x3Ga 1-x3N、Al x4Ga 1-x4N、Al x5Ga 1-x5N、GaN)232，其中Al x1Ga 1-x1N、Al x2Ga 1-x2N、Al x3Ga 1-x3N、Al x4Ga 1-x4N、Al x5Ga 1-x5N共同表示为AlGaN，从右向左的方向上，第二部分232的势垒高度依次下降，这样第一部分231背离氮化镓层220的一侧产生的空穴数量表示为σ p1，第二部分232产生的空穴的数量依次表示为σ p2、σ p3、σ p4、σ p5、σ p6，且σ p1、σ p2、σ p3、σ p4、σ p5、σ p6依次增大，在栅极区域1001的势垒层231&232中产生的空穴数量σ n为σ p1、σ p2、σ p3、σ p4、σ p5、σ p6之和，与第一部分(Al x1Ga 1-x1N)231和氮化镓层(GaN)220之间产生的位于栅极区域1001的二维电子气沟道222中的电子数量基本相同。
具体的，第二部分232也可以为没有明显界限的一体结构，即第二部分232内可以没有明显的铝含量骤变，第二部分232的铝浓度从朝向第一部分231的一侧至背离第一部分 231的一侧呈下降趋势，这种下降趋势可以是连续的匀速下降，也可以是非匀速下降。参考图6B所示，第一部分231内部不同膜层高度处的铝浓度含量相同，第二部分232的铝浓度从朝向第一部分231的一侧至背离第一部分231的一侧匀速下降。当然，第二部分232的铝浓度从朝向第一部分231的一侧至背离第一部分231的一侧还可以存在少量位置呈现较小程度的上升。此外，第一部分231和第二部分232也可以为没有明显界限的一体结构，第一部分231中的铝均匀分布。
本申请实施例中，位于非栅区域的势垒层中铝和镓的摩尔比大于或等于3/7，即第一部分231中的铝和镓的摩尔比大于或等于3/7，即前述的x1≥30％，因此第一部分231具有较高的势垒高度，能够有效产生二维电子气。
本申请实施例中，较低厚度的铝镓氮层与氮化镓层220之间产生的二维电子气沟道222容易被耗尽，因此可以设置第一部分231具有较小的厚度，具体的，第一部分231(即非栅区域1002的势垒层)沿垂直氮化镓层220表面的方向的尺寸(即纵向尺寸)可以小于或等于30nm，例如可以为5nm。在第一部分231的纵向尺寸较小时，还可以在第一部分231表面(即非栅区域1001的势垒层表面)形成钝化层240以产生应力，使第一部分231中的二维电子气沟道222再生，有利于实现电荷传输率高的沟道，参考图4所示。钝化层240覆盖位于非栅区域1002的势垒层(即第一部分231)，还可以覆盖栅极区域1001的势垒层(即第二部分232)，例如第二部分232覆盖栅极区域1001的第一部分231，覆盖第二部分232的侧壁，钝化层240还可以覆盖第二部分232的部分上表面。钝化层240的材料可以为氮化硅、碳化铝中的至少一种。
本申请实施例中，栅极251形成于栅极区域1001的势垒层231&232背离氮化镓层220的一侧，即形成于第二部分232上。
在一些可能的实施方式中，第二部分232的部分上表面覆盖有钝化层240，栅极251可以贯穿覆盖第二部分232的钝化层240，参考图4所示。在一些可能的实施方式中，栅极251可以包括电连接的第一栅极结构和第二栅极结构，第一栅极结构贯穿钝化层240，第二栅极结构形成于第一栅极结构背离基底200的一侧且覆盖钝化层240的部分表面，即栅极251可以构成“T”形结构，参考图4所示，栅极251可以覆盖第二部分232的部分上表面，以及覆盖钝化层240的部分上表面，利于栅极251的引出。
在另一些可能的实施方式中，栅极251也可以覆盖第二部分232的整个上表面，构成面状结构，栅极251和第二部分232的侧壁可以齐平，参考图8所示，为本申请实施例提供的另一种氮化镓器件的结构示意图，钝化层可以覆盖栅极251的侧壁。
本申请实施例中，栅极251和第二部分232可以直接接触，构成肖特基栅器件结构，参考图4和图8所示，相比于利用栅极251与第一部分231接触而言，栅极251与第二部分232接触的方案，减少了器件的正向漏电。
本申请实施例中，栅极251和势垒层中的第二部分232之间也可以形成有栅介质层260，构成绝缘栅器件结构，相比于栅极251与铝浓度较高的第一部分231接触，以及栅介质层260直接与铝浓度较高的第一部分231接触而言，栅极251与栅介质层260接触而栅介质层260与第二部分232接触的方案，减少了界面缺陷，提高器件的阈值稳定性。
在一些可能的实施方式中，参考图9所示，为本申请实施例提供的又一种氮化镓器件的结构示意图，该图为在图4中的氮化镓结构的基础上增设栅介质层260后的氮化镓结构示意，其中栅极251包括电连接的第一栅极结构和第二栅极结构，栅介质层260形成于栅极251和第二部分232之间，从而覆盖第二部分232的部分上表面，栅介质层260还可以形成于栅极251和钝化层240之间，从而覆盖钝化层240的朝向栅极251的侧壁，当然，栅介质层260还可以覆盖钝化层240的远离栅极251的侧壁，以及覆盖第一部分231的部分的表面。
在另一些可能的实施方式中，参考图10所示，为申请实施例提供的再一种氮化镓器件的结构示意图，该图为在图8中的氮化镓结构的基础上增设栅介质层260后的氮化镓结构示意，其中，栅介质层260覆盖第二部分232的全部上表面，栅极251覆盖栅介质层260的全部上表面，钝化层240可以覆盖栅介质层260的侧壁，还可以覆盖栅极251的侧壁
在本申请实施例中，氮化镓器件还可以包括源极252和漏极253，源极252和漏极253位于非栅区域1002的势垒层的背离氮化镓层220的一侧，即位于第一部分231上，源极252和漏极253分别位于栅极251的两侧。源极252、漏极253、栅极251均采用导电性较好的材料，源极252、漏极253、栅极251中的至少一种的材料为：镍、钛、铝、钯、铂、金、氮化钛、氮化钽以及铜中的至少一种。
本申请实施例提供一种氮化镓器件，氮化镓器件可以包括氮化镓层、氮化镓层表面的势垒层以及势垒层的背离氮化镓层一侧的栅极，氮化镓层具有栅极区域和栅极区域外围的非栅区域，势垒层的组成材料的元素包括铝、镓和氮，势垒层位于栅极区域和非栅区域，在沿垂直氮化镓层的表面的方向上，位于栅极区域的势垒层的尺寸大于位于非栅区域的势垒层的尺寸，且位于栅极区域的势垒层朝向氮化镓层的一侧的铝浓度高于朝向栅极的一侧的铝浓度，这样在栅极区域背离氮化镓层的方向上势垒层中的铝浓度递减，基于极化效应使势垒层天然可以等效为p型掺杂而无需Mg掺杂，从而使栅极区域的AlGaN/GaN界面的电子可以被天然的耗尽，而非栅区域的二维电子气沟道不被耗尽，在构成常关型氮化镓器件的同时，不会由于Mg掺杂而在非栅区域的势垒层中形成缺陷态，因此降低器件的动态电阻退化和HTOL后电阻退化的风险，利于得到性能优异的氮化镓器件。
基于本申请实施例提供的一种氮化镓器件，本申请实施例还提供了一种氮化镓器件的制造方法，参考图11所示，为本申请实施例提供的一种氮化镓器件的制造方法的流程图，图12-图21为本申请实施例提供中在该制造过程中氮化镓器件的结构示意图，该制造方法可以包括：
S101，获取氮化镓层220，参考图12所示。
作为一种可能的实现方式，氮化镓层220的厚度可以较大，则氮化镓层220可以为材料为氮化镓的基底，该基底为其上的膜层提供支撑作用，同时作为AlGaN/GaN的异质结构的组成部分。
作为另一种可能的实现方式，氮化镓层220的厚度可以较薄，参考图12所示，则氮化镓层220可以形成于基底200上，基底200为其上的膜层提供支撑作用，氮化镓层220作 为AlGaN/GaN的异质结构的组成部分，其中基底200的材料可以为氮化铝(AlN)、硅(Si)、碳化硅(SiC)、蓝宝石中的一种或多种。可选的，在基底200和氮化镓层220之间，还可以设置有缓冲层210，缓冲层210的材料可以为氮化铝，也可以为低温生长的氮化镓。
具体实施时，可以先在基底200表面形成缓冲层210，而后在缓冲层210上形成氮化镓层220。氮化镓层220的形成方式可以为有机金属化学气相沉积(Metal organic chemical vapor deposition，MOCVD)。
氮化镓层220可以具有栅极区域1001和栅极区域1001外围的非栅区域1002，栅极区域1001和非栅区域1002为氮化镓层220表面上的区域。栅极区域1001用于形成栅极251，可以为源极252和漏极253所在区域之间的中心区域，栅极区域1001可以大于栅极251所在区域，也可以等于栅极251所在区域，参考图12所示，中间的虚线框表示栅极区域1001，栅极区域1001两侧的虚线框表示非栅区域1002。
S102，在氮化镓层220的一侧表面形成势垒层231&232，以及位于栅极区域1001的势垒层231&232的背离氮化镓层220的一侧的栅极251，参考图13-图21。
本申请实施例中，可以在氮化镓层220表面形成势垒层231&232，势垒层231&232位于氮化镓层220的一侧表面，且势垒层231&232的组成材料的元素包括铝、镓和氮，其组成材料可以表示为铝镓氮(Al xGa 1-xN)，氮化镓层220的材料为铝镓氮的势垒层231&232形成AlGaN/GaN的异质结构，从而产生二维电子气，基于此形成的氮化镓器件可以利用该异质结构产生的二维电子气工作。在氮化镓层220设置在基底200上时，势垒层231&232设置于氮化镓层220背离基底200的一侧。
本申请实施例中，势垒层231&232位于栅极区域1001和非栅区域1002，在沿垂直氮化镓层220的表面的方向(即纵向)上，位于栅极区域1001的势垒层的尺寸大于位于非栅区域1002的势垒层的尺寸，且栅极区域1001的势垒层朝向氮化镓层220的一侧的铝浓度高于朝向栅极251的一侧的铝浓度。
栅极区域1001的势垒层朝向氮化镓层220的一侧的铝的浓度高于朝向栅极251的一侧的铝的浓度，相应的，栅极区域1001的势垒层朝向氮化镓层220的一侧的镓的浓度高于朝向栅极251的一侧的镓的浓度，由于这种设置位于栅极区域1001，在栅极区域1001内从朝向氮化镓层220的一侧到朝向栅极251的一侧，实现了铝组分的减少，铝组分较低的部分具有较低的势垒高度，因此铝组分较低的部分和氮化镓层220之间具有较低的势垒，这种从朝向氮化镓层220的一侧到朝向栅极251的一侧铝组分减少的结构中，由于极化效应会在势垒层231&232中产生空穴，因此栅极区域1001的势垒层231&232天然的可以等效为p型掺杂而无需Mg的掺杂，且空穴的数量基本等于栅极区域1001的二维电子气沟道222中的电子数量，二维电子气沟道222中的电子可以被天然耗尽。
此外，相比于p-GaN方案中空穴浓度与Mg的激活强相关所以需要精准控制p-GaN的激活温度和掺杂浓度等参数，本申请实施例中的空穴是由极化效应产生的，空穴的数量基本等于栅极区域1001的二维电子气沟道222中的电子数量，不存在需要精准控制Mg掺杂技术中空穴的激活等诸多问题；同时由于不存在p-GaN层，因此不存在Mg扩散导致的缺陷态的问题；同时器件的阈值电压由栅极区域1001的结构决定，工艺窗口大，不存在阈值 电压对Mg掺杂浓度与p-GaN激活条件敏感的问题。
具体的，势垒层可以包括朝向氮化镓层220的第一部分231和朝向栅极251的第二部分232，其中第一部分231形成于栅极区域1001和非栅区域1002中，第二部分232在氮化镓层220表面的投影位于栅极区域，即第二部分232形成于栅极区域1001的第一部分231上，可以认为第二部分232形成于栅极区域1001，第一部分231中的铝的浓度高于第二部分232中铝的浓度，相应的，第一部分231中的镓的浓度高于第二部分232中的镓的浓度，由于第二部分232形成于栅极区域1001，这样在栅极区域1001内从第一部分231到第二部分232，实现了铝组分的减少，铝组分较低的部分具有较低的势垒高度，因此铝组分较低的部分和氮化镓层220之间具有较低的势垒，这种从第一部分231到第二部分232铝组分减少的结构中，由于极化效应会在第一部分231和第二部分232中产生空穴，因此栅极区域1001的势垒层231&232天然的可以等效为p型掺杂而无需Mg的掺杂，且空穴的数量基本等于栅极区域1001的二维电子气沟道222中的电子数量，二维电子气沟道222中的电子可以被天然耗尽。
本申请实施例中，位于非栅区域的势垒层中铝和镓的摩尔比大于或等于3/7，即第一部分231中的铝和镓的摩尔比大于或等于3/7，即前述的x1≥30％，因此第一部分231具有较高的势垒高度，能够有效产生二维电子气。第一部分231(即非栅区域1002的势垒层)沿垂直氮化镓层220表面的方向的尺寸(即纵向尺寸)可以小于或等于30nm，例如可以为5nm，铝镓氮层在该尺寸范围内时在栅极区域1001的二维电子气沟道容易被耗尽。
作为一种形成势垒层231&232和栅极的实现方式，可以先在氮化镓层220的一侧表面形成铝镓氮材料层230，参考图13所示，而后对位于非栅区域1002的铝镓氮材料层230进行刻蚀从而减薄，得到势垒层，势垒层可以包括第一部分231和第二部分232，第一部分231位于栅极区域1001和非栅区域1002，第二部分232位于栅极区域1001，参考图14所示，而后在位于栅极区域1001的势垒层的背离所述氮化镓层220的一侧形成栅极251，参考图15-图17、图4、图9所示。其中铝镓氮材料层230的组成材料的元素包括铝、镓和氮，铝镓氮材料层230朝向氮化镓层220的一侧的铝的浓度高于背离氮化镓层220的一侧的铝的浓度。
具体的，铝镓氮材料层230朝向氮化镓层220的一侧铝浓度较高，而背离氮化镓层220的一侧的铝含量较低，整个铝镓氮材料层230可以为没有明显界限的一体结构，也可以包括多个子膜层。具体的，铝镓氮材料层230为一体结构时，可以通过同一沉积工艺得到，在沉积过程中通过分别调控铝和镓的沉积速率可以调控不同厚度处的铝浓度，则对非栅区域1002的铝镓氮材料层230进行刻蚀，相当于对铝镓氮材料层230进行部分区域的减薄，减薄后仍旧覆盖栅极区域1001和非栅区域1002的部分作为第一部分231，位于栅极区域1001的部分作为第二部分232，为了便于描述，为第一部分231和第二部分232设定分界面，该分界面为第一部分231的上表面所在的平面，体现为图14中的水平虚线，后续的结构示意图中采用同样的表达方式。
形成的势垒层231&232在栅极区域1001具有较大的厚度，而在非栅区域1002具有较小的厚度，势垒层231&232在非栅区域1002的厚度等于第一部分231的厚度，在栅极区 域1001的厚度等于第一部分231的厚度与第二部分232的厚度之和，参考图14所示。其中，铝镓氮材料层230的形成方式可以为MOCVD，对铝镓氮材料层230的刻蚀可以通过光刻工艺，刻蚀方式可以为各向异性的干法刻蚀，刻蚀的厚度可以通过刻蚀速率和蚀刻时长来控制。
在一些可能的实施方式中，形成势垒层231&232后，还可以在非栅区域1002的势垒层表面形成钝化层240以产生应力，使第一部分231中的二维电子气沟道222再生，有利于实现电荷传输率高的沟道。钝化层240的材料可以为氮化硅、碳化铝中的至少一种。此时，在位于栅极区域1001的势垒层的背离所述氮化镓层220的一侧形成栅极251，可以具体为，形成覆盖势垒层的钝化层240，参考图15所示，对覆盖栅极区域1001的势垒层的钝化层240进行刻蚀，形成贯穿钝化层240的栅极孔270，参考图16所示，并在栅极孔270内形成栅极251，形成的钝化层240覆盖第一部分231以及第二部分232，例如覆盖第二部分232的侧壁，还可以覆盖第二部分232的部分上表面，参考图4所示。
其中，栅极251可以包括电连接的第一栅极结构和第二栅极结构，第一栅极结构位于栅极孔内，贯穿钝化层240，第二栅极结构形成于第一栅极结构背离基底200的一侧且覆盖钝化层240的部分表面，即栅极251可以构成“T”形结构，提高栅极251的引出可靠性。第一栅极结构和第二栅极结构可以通过沉积和刻蚀的方式形成，具体的，可以沉积导体材料，以使导体材料填充栅极孔270，以及覆盖在栅极孔270上方，导体材料可以为镍、钛、铝、钯、铂、金、氮化钛、氮化钽以及铜中的至少一种。而后可以去除栅极区域1001之外的导体材料，以形成位于栅极区域1001的栅极。当然，栅极251也可以仅包括贯穿钝化层240的第一栅极结构。
栅极251和第二部分232可以直接接触，构成肖特基栅器件结构，参考图4所示，相比于利用栅极251与第一部分231接触，栅极251与第二部分232接触的方案，减少了器件的正向漏电；栅极251和势垒层中的第二部分232之间也可以形成有栅介质层260，构成绝缘栅器件结构，参考图9所示，栅介质层260与第二部分232接触，相比于栅介质层260与铝浓度较高的第一部分231接触，以及栅介质层260直接与铝浓度较高的第一部分231接触，栅极251与栅介质层260接触而栅介质层260与第二部分232接触的方案，减少了界面缺陷，提高器件的阈值稳定性。
在绝缘栅器件的制造过程中，形成栅极251之前，可以在第二部分232和栅极251之间形成栅介质层260。具体的，可以在铝镓氮材料层230上形成栅介质材料层262，在对位于非栅区域1002的铝镓氮材料层230进行刻蚀时，一并对位于非栅区域1002铝镓氮材料层230上的栅介质材料层262进行刻蚀，以形成位于栅极区域1001的栅介质层260，栅介质层260位于栅极251和势垒层之间，钝化层240形成于栅介质层260之上，对钝化层240进行刻蚀得到的栅极孔270暴露栅介质层260。具体的，也可以在形成栅极孔270之后，沉积形成栅介质层260，栅介质层260覆盖钝化层240，并覆盖栅极孔270的侧壁和底部，参考图17所示，而后在栅极孔270中形成栅极251，参考图9所示。
作为另一种形成势垒层231&232和栅极的实现方式，可以在氮化镓层220的一侧表面形成铝镓氮材料层230，以及位于铝镓氮材料层230的背离所述氮化镓层220的一侧的栅 极材料层253，参考图18所示，对位于非栅区域1002铝镓氮材料层230的背离氮化镓层的一侧的的栅极材料层253进行刻蚀，并对位于非栅区域的铝镓氮材料层230进行刻蚀从而减薄，即在非栅区域1002对栅极材料层253和铝镓氮材料层230进行刻蚀，得到势垒层231&232和位于栅极区域1001的势垒层的背离所述氮化镓层220的一侧的栅极251，势垒层包括位于栅极区域1001的第二部分232，以及位于栅极区域1001和非栅区域1002的第一部分231，参考图19-21、图8、图10所示。其中，铝镓氮材料层230的组成材料的元素包括铝、镓和氮；铝镓氮材料层230朝向氮化镓层220的一侧的铝的浓度高于背离氮化镓层220的一侧的铝的浓度，栅极材料层253的材料可以为镍、钛、铝、钯、铂、金、氮化钛、氮化钽以及铜中的至少一种。
具体的，铝镓氮材料层230朝向氮化镓层220的部分铝浓度较高，而背离氮化镓层220的部分的铝含量较低，整个铝镓氮材料层230可以为一体结构，也可以包括多个膜层。具体的，铝镓氮材料层230为一体结构时，可以通过同一沉积工艺得到，在沉积过程中通过分别调控铝和镓的沉积速率可以调控不同厚度处的铝浓度，则对非栅区域1002的铝镓氮材料层230进行刻蚀，相当于对铝镓氮材料层230进行部分区域的减薄，减薄后仍旧覆盖栅极区域1001和非栅区域1002的部分作为第一部分231，位于栅极区域1001的部分作为第二部分232，为了便于描述，为第一部分231和第二部分232设定分界面，该分界面为第一部分231的上表面所在的平面，体现为图19中的水平虚线。形成的势垒层231&232在栅极区域1001具有较大的厚度，而在非栅区域1002具有较小的厚度，势垒层231&232在非栅区域1002的厚度等于第一部分231的厚度，在栅极区域1001的厚度等于第一部分231的厚度与第二部分232的厚度之和，参考图19所示。
栅极251和第二部分232可以直接接触，构成肖特基栅器件结构，参考图8所示，相比于利用栅极251与第一部分231接触而言，栅极251与第二部分232接触的方案，减少了器件的正向漏电；栅极251和第二部分232之间也可以形成有栅介质层260，构成绝缘栅器件结构，参考图10所示，相比于栅介质层260与铝浓度较高的第一部分231接触，以及栅介质层260直接与铝浓度较高的第一部分231接触而言，栅极251与栅介质层260接触而栅介质层260与第二部分232接触的方案，减少了界面缺陷，提高器件的阈值稳定性。
在绝缘栅器件的制造过程中，还可以形成铝镓氮材料层230和栅极材料层253之间的栅介质材料层262，参考图20所示，则在对位于非栅区域1002的铝镓氮材料层的背离所述氮化镓层的一侧的栅极材料层253进行刻蚀，以及对位于非栅区域的铝镓氮材料层230进行减薄时，可以同时对位于非栅区域1002的铝镓氮材料层的背离所述氮化镓层的一侧的栅介质材料层262进行刻蚀，以得到位于栅极区域1001的栅介质层260，栅介质层260位于势垒层231&232和栅极251之间，参考图21所示。
在一些可能的实施方式中，形成势垒层231&232后，还可以在非栅区域1002的势垒层表面(即第一部分231表面)形成钝化层240以产生应力，使第一部分231中的二维电子气沟道222再生，有利于实现电荷传输率高的沟道。钝化层240的材料可以为氮化硅、碳化铝中的至少一种。则在形成栅极251后，可以形成覆盖势垒层231&232的钝化层240，参考图8和图10，钝化层240覆盖第二部分232的侧壁，以及第一部分231的上表面。
本申请实施例中，第一部分231中的铝的浓度高于第二部分232中铝的浓度，可以体现为第一部分231中铝的平均浓度高于第二部分232中铝的平均浓度，而第二部分232中铝的浓度可以是均匀的，也可以是不均匀的。具体的，第二部分232可以包括堆叠的多层子膜层，多个子膜层在纵向堆叠，其中，多层子膜层的铝浓度可以不完全相同，朝向栅极251的子膜层的铝浓度小于朝向第一部分231的子膜层的铝浓度，即位于上层的子膜层的铝浓度可以小于位于下层的子膜层的铝浓度，这样铝浓度从朝向第一部分231的一侧至背离第一部分231的一侧依次降低，各个子膜层的铝浓度呈现下降趋势，实现铝浓度的阶梯式下降，增强栅极区域1001的势垒层231&232中的极化效应；具体的，第二部分232也可以为没有明显界限的一体结构，即第二部分232内可以没有明显的铝含量骤变，第二部分232的铝浓度从朝向第一部分231的一侧至背离第一部分231的一侧呈下降趋势，这种下降趋势可以是连续的匀速下降，也可以是非匀速下降。参考图6B所示，第一部分231内部不同膜层高度处的铝浓度含量相同，第二部分232的铝浓度从朝向第一部分231的一侧至背离第一部分231的一侧匀速下降。
本申请实施例中，还可以在非栅区域1002的势垒层上形成源极252和漏极253，即在第一部分231上形成源极252和漏极253，分别位于栅极251的两侧，源极252和漏极253可以形成于第一部分231的表面，也可以形成于对第一部分231进行刻蚀得到的通孔中。源极252和/或漏极253的材料为镍、钛、铝、钯、铂、金、氮化钛、氮化钽以及铜中的至少一种。
本申请实施例提供一种氮化镓器件的制造方法，获取氮化镓层，氮化镓层具有栅极区域和栅极区域外围的非栅区域，在氮化镓层的一侧表面形成势垒层，以及位于栅极区域的势垒层的背离氮化镓层的一侧的栅极，势垒层的组成材料的元素包括铝、镓和氮，势垒层位于栅极区域和非栅区域，在沿垂直氮化镓层的表面的方向上，位于栅极区域的势垒层的尺寸大于位于非栅区域的势垒层的尺寸，且位于栅极区域的势垒层朝向氮化镓层的一侧的铝浓度高于朝向栅极的一侧的铝浓度，这样栅极区域背离氮化镓层的方向上势垒层中的铝浓度递减，基于极化效应使势垒层天然可以等效为p型掺杂而无需Mg掺杂，从而使栅极区域的AlGaN/GaN界面的电子可以被天然的耗尽，而非栅区域的二维电子气沟道不被耗尽，在构成常关型氮化镓器件的同时，不会由于Mg掺杂而在非栅区域的势垒层中形成缺陷态，因此降低器件的动态电阻退化和HTOL后电阻退化的风险，利于得到性能优异的氮化镓器件。
基于本申请实施例提供的一种氮化镓器件，本申请实施例还提供一种电子设备，该电子设备包括电路板、以及与电路板连接的氮化镓器件，该氮化镓器件可以为上文所提供的任一种氮化镓器件。其中，该电路板可以为印制电路板(printed circuit board，PCB)，当然电路板还可以为柔性电路板(FPC)等，本实施例对电路板不作限制。可选的，该电子设备为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。
可选的，该电子设备还包括封装基板，该封装基板通过焊球固定于印刷电路板PCB上， 该氮化镓器件通过焊球固定于封装基板上。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于创建氮化镓器件的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构具有用于制造上文所提供的任意一个图示所提供的氮化镓器件的光掩膜数据。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。
以上为本申请的具体实现方式。应当理解，以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (33)

  1. 一种氮化镓器件，其特征在于，包括：
    氮化镓层，所述氮化镓层具有栅极区域和所述栅极区域外围的非栅区域；
    势垒层，所述势垒层位于所述氮化镓层的一侧表面上，所述势垒层的组成材料的元素包括铝、镓和氮；
    栅极，所述栅极位于所述栅极区域的势垒层的背离所述氮化镓层的一侧；
    所述势垒层位于栅极区域和非栅区域；在沿垂直所述氮化镓层的表面的方向上，位于所述栅极区域的势垒层的尺寸大于位于所述非栅区域的势垒层的尺寸，且位于所述栅极区域的势垒层朝向所述氮化镓层的一侧的铝浓度高于朝向所述栅极的一侧的铝浓度。
  2. 根据权利要求1所述的氮化镓器件，其特征在于，所述势垒层包括朝向所述氮化镓层的第一部分和朝向所述栅极的第二部分，所述第一部分的铝浓度高于所述第二部分的铝浓度，所述第一部分位于所述栅极区域和所述非栅区域，所述第二部分在氮化镓层表面的投影位于所述栅极区域。
  3. 根据权利要求2所述的氮化镓器件，其特征在于，所述第一部分为第一膜层，所述第二部分包括堆叠的多层子膜层，且朝向所述栅极的子膜层的铝浓度小于朝向所述第一部分的子膜层的铝浓度。
  4. 根据权利要求2所述的氮化镓器件，其特征在于，所述第二部分的铝浓度从朝向所述第一部分的一侧至背离所述第一部分的一侧呈下降趋势。
  5. 根据权利要求1-4任意一项所述的氮化镓器件，其特征在于，位于所述非栅区域的势垒层在垂直所述氮化镓层的表面的方向上的尺寸小于或等于30nm。
  6. 根据权利要求2-5任意一项所述的氮化镓器件，其特征在于，位于所述非栅区域的势垒层中铝和镓的摩尔比大于或等于3/7。
  7. 根据权利要求1-6任意一项所述的氮化镓器件，其特征在于，还包括：
    源极和漏极，所述源极和漏极位于所述非栅区域的势垒层的背离所述氮化镓层的一侧上。
  8. 根据权利要求7所述的氮化镓器件，其特征在于，所述源极、漏极、栅极中的至少一种的材料为：镍、钛、铝、钯、铂、金、氮化钛、氮化钽以及铜中的至少一种。
  9. 根据权利要求1-8任意一项所述的氮化镓器件，其特征在于，还包括：
    钝化层，所述钝化层覆盖位于所述非栅区域的势垒层。
  10. 根据权利要求9所述的氮化镓器件，其特征在于，所述钝化层还覆盖位于所述栅极区域的势垒层；所述栅极包括电连接的第一栅极结构和第二栅极结构，所述第一栅极结构贯穿所述钝化层，所述第二栅极结构形成于所述第一栅极结构背离所述氮化镓层的一侧且覆盖所述钝化层的部分表面。
  11. 根据权利要求9或10所述的氮化镓器件，其特征在于，所述钝化层的材料为氮化硅、碳化铝中的至少一种。
  12. 根据权利要求1-11任意一项所述的氮化镓器件，其特征在于，还包括：
    位于所述势垒层和所述栅极之间的栅介质层。
  13. 根据权利要求1-12任意一项所述的氮化镓器件，其特征在于，还包括：
    基底，位于所述氮化镓层背离所述势垒层的一侧。
  14. 根据权利要求13所述的氮化镓器件，其特征在于，还包括：
    位于所述基底和所述氮化镓层之间的缓冲层。
  15. 一种氮化镓器件的制造方法，其特征在于，包括：
    获取氮化镓层，所述氮化镓层具有栅极区域和所述栅极区域外围的非栅区域；
    在所述氮化镓层的一侧表面形成势垒层，以及位于所述栅极区域的势垒层的背离所述氮化镓层的一侧的栅极，所述势垒层的组成材料的元素包括铝、镓和氮；所述势垒层位于栅极区域和非栅区域，在沿垂直所述氮化镓层的表面的方向上，位于所述栅极区域的势垒层的尺寸大于位于所述非栅区域的势垒层的尺寸，且位于所述栅极区域的势垒层朝向所述氮化镓层的一侧的铝浓度高于朝向所述栅极的一侧的铝浓度。
  16. 根据权利要求15所述的方法，其特征在于，所述势垒层包括朝向所述氮化镓层的第一部分和朝向所述栅极的第二部分，所述第一部分的铝浓度高于所述第二部分的铝浓度，所述第一部分位于所述栅极区域和所述非栅区域，所述第二部分在氮化镓层表面的投影位于所述栅极区域。
  17. 根据权利要求16所述的方法，其特征在于，所述第一部分为第一膜层，所述第二部分包括堆叠的多层子膜层，且朝向所述栅极的子膜层的铝浓度小于朝向所述第一部分的子膜层的铝浓度。
  18. 根据权利要求16所述的方法，其特征在于，所述第二部分的铝浓度从朝向所述第一部分的一侧至背离所述第一部分的一侧呈下降趋势。
  19. 根据权利要求15-18任意一项所述的方法，其特征在于，位于所述非栅区域的势垒层在垂直所述氮化镓层的表面的方向上的尺寸小于或等于30nm。
  20. 根据权利要求15-19任意一项所述的方法，其特征在于，位于所述非栅区域的势垒层中铝和镓的摩尔比大于或等于3/7。
  21. 根据权利要求15-20任意一项所述的方法，其特征在于，还包括：
    在所述非栅区域的势垒层的背离所述氮化镓层的一侧形成源极和漏极。
  22. 根据权利要求21所述的方法，其特征在于，所述源极、漏极、栅极中的至少一种的材料为：镍、钛、铝、钯、铂、金、氮化钛、氮化钽以及铜中的至少一种。
  23. 根据权利要求15-22任意一项所述的方法，其特征在于，所述在所述氮化镓层的一侧表面形成势垒层，以及位于所述栅极区域的势垒层的背离所述氮化镓层的一侧的栅极，包括：
    在所述氮化镓层的一侧表面形成铝镓氮材料层，所述铝镓氮材料层的组成材料的元素包括铝、镓和氮；所述铝镓氮材料层朝向所述氮化镓层一侧的铝浓度高于背离所述氮化镓层一侧的铝浓度；
    对位于所述非栅区域的铝镓氮材料层进行减薄，得到势垒层；
    在位于所述栅极区域的势垒层的背离所述氮化镓层的一侧形成栅极。
  24. 根据权利要求23所述的方法，其特征在于，所述在位于所述栅极区域的势垒层的 背离所述氮化镓层的一侧形成栅极，包括：
    形成覆盖所述势垒层的钝化层；
    对覆盖所述栅极区域的势垒层的钝化层进行刻蚀，形成贯穿所述钝化层的栅极孔，并在所述栅极孔内形成栅极。
  25. 根据权利要求24所述的方法，其特征在于，所述栅极包括电连接的第一栅极结构和第二栅极结构，所述第一栅极结构位于所述栅极孔内，所述第二栅极结构形成于所述第一栅极结构背离所述氮化镓层的一侧且覆盖所述钝化层的部分表面。
  26. 根据权利要求23-25任意一项所述的方法，其特征在于，形成所述栅极之前，还包括：
    在所述势垒层和所述栅极之间形成栅介质层。
  27. 根据权利要求15-22任意一项所述的方法，其特征在于，所述在所述氮化镓层的一侧表面形成势垒层，以及位于所述栅极区域的势垒层的背离所述氮化镓层的一侧的栅极，包括：
    在所述氮化镓层的一侧表面形成铝镓氮材料层，以及位于所述铝镓氮材料层的背离所述氮化镓层的一侧的栅极材料层；所述铝镓氮材料层的组成材料的元素包括铝、镓和氮；所述铝镓氮材料层朝向所述氮化镓层一侧的铝浓度高于背离所述氮化镓层一侧的铝浓度；
    对位于所述非栅区域的铝镓氮材料层的背离所述氮化镓层的一侧的栅极材料层进行刻蚀，并对位于所述非栅区域的铝镓氮材料层进行减薄，得到势垒层和位于所述栅极区域的势垒层的背离所述氮化镓层的一侧的栅极。
  28. 根据权利要求27所述的方法，其特征在于，还包括：
    形成所述铝镓氮材料层和所述栅极材料层之间的栅介质材料层；
    所述对位于所述非栅区域的铝镓氮材料层的背离所述氮化镓层的一侧的栅极材料层进行刻蚀，并对位于所述非栅区域的所述铝镓氮材料层进行减薄时，还对位于所述非栅区域的铝镓氮材料层的背离所述氮化镓层的一侧的栅介质材料层进行刻蚀，以得到位于所述势垒层和所述栅极之间的栅介质层。
  29. 根据权利要求27或28所述的方法，其特征在于，在形成所述势垒层后，还包括：
    形成覆盖所述势垒层的钝化层。
  30. 根据权利要求24、25、29中任意一项所述的方法，其特征在于，所述钝化层的材料为氮化硅、碳化铝中的至少一种。
  31. 根据权利要求15-30任意一项所述的方法，其特征在于，所述氮化镓层背离所述势垒层的一侧设置有基底。
  32. 根据权利要求31所述的方法，其特征在于，所述氮化镓层和所述基底之间设置有缓冲层。
  33. 一种电子设备，其特征在于，包括电路板，以及与所述电路板连接的、如权利要求1-14任意一项所述的氮化镓器件。
PCT/CN2021/115270 2021-08-30 2021-08-30 一种氮化镓器件及其制造方法、电子设备 WO2023028740A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2021/115270 WO2023028740A1 (zh) 2021-08-30 2021-08-30 一种氮化镓器件及其制造方法、电子设备
CN202180005517.8A CN116235301A (zh) 2021-08-30 2021-08-30 一种氮化镓器件及其制造方法、电子设备
EP21955322.9A EP4336562A1 (en) 2021-08-30 2021-08-30 Gallium nitride device and manufacturing method therefor, and electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/115270 WO2023028740A1 (zh) 2021-08-30 2021-08-30 一种氮化镓器件及其制造方法、电子设备

Publications (1)

Publication Number Publication Date
WO2023028740A1 true WO2023028740A1 (zh) 2023-03-09

Family

ID=85411734

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/115270 WO2023028740A1 (zh) 2021-08-30 2021-08-30 一种氮化镓器件及其制造方法、电子设备

Country Status (3)

Country Link
EP (1) EP4336562A1 (zh)
CN (1) CN116235301A (zh)
WO (1) WO2023028740A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110210377A1 (en) * 2010-02-26 2011-09-01 Infineon Technologies Austria Ag Nitride semiconductor device
JP2012227456A (ja) * 2011-04-22 2012-11-15 Panasonic Corp 半導体装置
CN103337516A (zh) * 2013-06-07 2013-10-02 苏州晶湛半导体有限公司 增强型开关器件及其制造方法
CN110875381A (zh) * 2018-08-29 2020-03-10 苏州能讯高能半导体有限公司 一种半导体器件及其制造方法
CN112382661A (zh) * 2020-10-22 2021-02-19 西南交通大学 一种耐高击穿电压的GaN HEMT器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110210377A1 (en) * 2010-02-26 2011-09-01 Infineon Technologies Austria Ag Nitride semiconductor device
JP2012227456A (ja) * 2011-04-22 2012-11-15 Panasonic Corp 半導体装置
CN103337516A (zh) * 2013-06-07 2013-10-02 苏州晶湛半导体有限公司 增强型开关器件及其制造方法
CN110875381A (zh) * 2018-08-29 2020-03-10 苏州能讯高能半导体有限公司 一种半导体器件及其制造方法
CN112382661A (zh) * 2020-10-22 2021-02-19 西南交通大学 一种耐高击穿电压的GaN HEMT器件

Also Published As

Publication number Publication date
EP4336562A1 (en) 2024-03-13
CN116235301A (zh) 2023-06-06

Similar Documents

Publication Publication Date Title
JP5909531B2 (ja) 窒化物系トランジスタおよびその製造方法
US20130292690A1 (en) Semiconductor device and method of manufacturing the same
US9502544B2 (en) Method and system for planar regrowth in GaN electronic devices
KR101955337B1 (ko) 문턱전압 변동을 줄인 고 전자 이동도 트랜지스터 및 그 제조방법
KR20140011791A (ko) 고전자이동도 트랜지스터 및 그 제조방법
JP2007142243A (ja) 窒化物半導体電界効果トランジスタ及びその製造方法
CN114127951B (zh) 氮化物基半导体装置以及制造其的方法
US20240030335A1 (en) Semiconductor device and method for manufacturing the same
CN112185959B (zh) 一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法
JP2006210725A (ja) 半導体装置
US20240038852A1 (en) Semiconductor device and method for manufacturing the same
US20210305404A1 (en) Method and system for regrown source contacts for vertical gallium nitride based fets
US20230268381A2 (en) Fin-Shaped Semiconductor Device, Fabrication Method, and Application Thereof
CN111863957B (zh) 一种常闭型高电子迁移率晶体管及其制造方法
CN111933709A (zh) 一种具有高可靠性的氮化物器件及其制备方法
TW202109739A (zh) 半導體裝置及其製造方法
WO2023028740A1 (zh) 一种氮化镓器件及其制造方法、电子设备
US20240030327A1 (en) Semiconductor device and method for manufacturing the same
JP2015008244A (ja) ヘテロ接合電界効果型トランジスタおよびその製造方法
CN114026699A (zh) 半导体装置和其制造方法
CN111384167B (zh) 半导体器件及制作方法
CN110875379B (zh) 一种半导体器件及其制造方法
CN114600253A (zh) 半导体结构及其制作方法
CN117316767B (zh) 一种半导体器件及其制备方法
US20240154012A1 (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21955322

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2021955322

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2021955322

Country of ref document: EP

Effective date: 20231207

NENP Non-entry into the national phase

Ref country code: DE