WO2023024149A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023024149A1
WO2023024149A1 PCT/CN2021/116421 CN2021116421W WO2023024149A1 WO 2023024149 A1 WO2023024149 A1 WO 2023024149A1 CN 2021116421 W CN2021116421 W CN 2021116421W WO 2023024149 A1 WO2023024149 A1 WO 2023024149A1
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WIPO (PCT)
Prior art keywords
groove
pixel electrode
data line
slot
layer
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PCT/CN2021/116421
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English (en)
French (fr)
Inventor
刘毅
Original Assignee
Tcl华星光电技术有限公司
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Priority to US17/605,251 priority Critical patent/US11662639B2/en
Publication of WO2023024149A1 publication Critical patent/WO2023024149A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133615—Edge-illuminating devices, i.e. illuminating from the side
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • the pixel structure of a display panel is defined by interlacing scan lines and data lines to define pixel units.
  • the structure of doubling the data lines in a single pixel unit can double the pixel charging, thereby improving the pixel charging rate.
  • the data lines will greatly occupy the layout space of the pixels, thereby reducing the aperture ratio of the pixels.
  • two data lines pass under the pixel opening area and are located on the left and right sides of the pixel opening, and the two data items are positive and negative.
  • the current pixel structure has a horizontal trunk pixel electrode and a vertical trunk pixel electrode in a cross configuration, and the potential of the pixel electrode is controlled through the data line.
  • a cross-shaped dark stripe will be formed in the trunk area of the pixel electrode. That is to say, the dark cross pattern and the two data lines in the opening area respectively occupy different ranges of the pixel opening area, and together cause pixel penetration loss and reduce the area of the pixel opening.
  • the present application provides a display panel and a display device to solve the technical problem of reducing pixel opening area due to pixel penetration loss caused by double data lines and cross lines occupying different areas of pixel openings in existing display panels.
  • An embodiment of the present application provides a display panel, including a first substrate and a second substrate oppositely arranged, a display layer, and a plurality of pixel units distributed between the first substrate and the second substrate.
  • the display panel includes a pixel electrode layer at a part corresponding to each of the pixel units, which is arranged between the first substrate and the display layer, and includes pixel electrodes, isolation grooves and shielding electrodes, wherein the isolation grooves are set between the pixel electrode and the shielding electrode, and surrounding the pixel electrode; a first metal layer, disposed on the first substrate, and located between the pixel electrode layer and the first substrate;
  • the second metal layer is arranged between the first substrate and the pixel electrode layer, and includes a data line group having a first data line and a second data line, and the data line group is electrically connected to the pixel electrode layer;
  • a common electrode layer which is arranged between the second substrate and the display layer, and includes a common electrode and a trunk groove, a first groove, and a
  • the main groove includes a first end and a second end oppositely arranged and an intermediate shaft defined between the first end and the second end, wherein the first slot and the second slot respectively located on opposite sides of the middle axis, the horizontal distance between the first data line and the middle axis is smaller than the horizontal distance between the first data line and the first end, and the first The horizontal distance between the second data line and the middle axis is smaller than the horizontal distance between the second data line and the second end.
  • the orthographic projection of the main groove on the pixel electrode layer is located at the central position of the pixel electrode or close to the central position, and the first end and the second end of the main groove extend to the pixel electrode respectively. two opposite sides of the electrode, or beyond the two opposite sides of the pixel electrode.
  • first data line and the second data line respectively include a top line segment, a bottom line segment and a vertical line segment between the top line segment and the bottom line segment, wherein the top line segment and the bottom line segment respectively inclined towards the middle axis of the main groove, the vertical line segment of the first data line corresponds to the position of the first slot, and the vertical line segment of the second data line corresponds to the second slot s position.
  • the pixel electrode of the pixel electrode layer is a rectangular electrode block
  • the shielding electrode is arranged around the isolation groove, and is electrically connected to the second metal layer.
  • the orthographic projection of the end of the first groove away from the trunk groove on the pixel electrode layer is beyond the top side of the pixel electrode, and the end of the second groove away from the trunk groove is at The orthographic projection of the pixel electrode layer is beyond the bottom side of the pixel electrode.
  • the trunk groove has a first width
  • the first groove and the second groove have a second width respectively, wherein the first width and the second width are respectively less than or equal to 30 microns, And greater than or equal to 3 microns.
  • the trunk groove is horizontal and arranged on the common electrode in a horizontal direction, and the first slot and the second slot are vertical and respectively perpendicular to the trunk groove , wherein the width of the first data line is greater than or equal to the width of the first slot or the second slot, and the width of the second data line is greater than or equal to the width of the second slot or the The width of the second slot.
  • the display panel further includes a grid insulating layer, a buffer layer disposed on the second metal layer, a color filter layer and a flat layer disposed between the buffer layer and the second substrate.
  • the embodiment of the present application also provides a display device, including a backlight module and any one of the display panels, the backlight module is used to provide a light source required by the display panel.
  • the common electrode layer includes a trunk groove and a first groove and a second groove arranged on opposite sides of the trunk groove at intervals, and the pixel electrode layer includes a rectangular block The pixel electrode structure of the pixel electrode, the isolation groove and the shielding electrode.
  • the first groove and the second groove present a non-cross-shaped dark area, and the resulting
  • the above-mentioned dark area can be shielded by the first data line and the second data line, and will not occupy different parts of the pixel opening, thereby reducing the loss of the pixel opening, improving the charging rate of the pixel, and increasing the performance of the display panel at a high refresh rate display effect.
  • the display panel and the display device of the present application effectively solve the problem of reducing the area of the pixel opening due to the pixel penetration loss caused by the traditional display panel because the cross lines and the data lines in the opening area respectively occupy different ranges of the pixel opening area. question.
  • FIG. 1 is a schematic diagram of a three-dimensional exploded structure of a display panel according to an embodiment of the present application.
  • FIG. 2 is a partial structural schematic diagram of a pixel electrode layer according to an embodiment of the present application.
  • FIG. 3 is a partial structural schematic diagram of a common electrode layer according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of the mutual alignment of the pixel electrode layer and the common electrode layer.
  • FIG. 5 is a schematic diagram of an optical simulation of a pixel unit according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a pixel electrode layer according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a common electrode layer according to an embodiment of the present application.
  • FIG. 8 is a schematic plan view of the combined structure of the display panel in FIG. 1 .
  • FIG. 9 is a simulated diagram of pixel dark fringe distribution of a pixel unit according to an embodiment of the present application.
  • FIG. 10 is a diagram of potential field distribution and liquid crystal inversion distribution of a pixel of a pixel unit according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • the embodiment of the present application provides a display panel, in particular, a liquid crystal display panel having a thin film transistor array.
  • the display panel is provided with several gate scanning lines and several data lines, and the several gate scanning lines and several data lines define a plurality of pixel units, and each pixel unit is provided with a thin film transistor and a pixel electrode.
  • the embodiment of the present application adopts a structure in which the number of gate lines in a single pixel unit is halved and the number of data lines is doubled to drive the display unit. That is, each pixel unit is driven by a combination of two data lines and one scan line.
  • FIG. 1 is a perspective exploded structural diagram of a display panel 1 according to an embodiment of the present application.
  • the display panel 1 of the embodiment of the present application has a stacked structure, including a first substrate 10 and a first metal layer 11 arranged from bottom to top (that is, from right to left as shown in FIG. 1 ).
  • gate insulating layer 12, second metal layer 13, passivation layer 15, color filter layer 16, flat layer 17, pixel electrode layer 18, display layer 30, common electrode layer 21, black matrix layer 201 and second substrate 20 .
  • the display layer 30 of this embodiment is a liquid crystal display layer including a plurality of liquid crystal molecules (not shown).
  • the first metal layer 11 includes gates 111 and scan lines 112
  • the second metal layer 13 includes a data line group 130 and active components 14, wherein the data line group 130 is composed of the first data line 131 and the second data line 132, and the active component 14 and the gate 111 together form a thin film transistor. That is, the first substrate 10 of the present application is an array substrate, that is, the display panel 1 of the present application is a thin film transistor liquid crystal display panel.
  • the materials of the gate insulating layer 12 , the passivation layer 15 and the planar layer 17 may be nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide) or other insulating materials.
  • the color filter layer 16 of the embodiment of the present application is integrated with the first substrate 10 to form a color filter on array substrate (color filter on array, COA for short) structure.
  • the use of the COA structure can avoid the problems that the deviation of the first substrate 10 and the second substrate 20 when they are aligned with the cell affects the aperture ratio of the display device and the problems of light leakage.
  • the display panel 1 of the present application is not limited by the COA structure. That is, the color filter layer 16 can also be disposed on one side of the second substrate 20 (not shown), so as to form a non-COA color filter substrate.
  • FIG. 2 is a partial structural diagram of the pixel electrode layer 18 according to the embodiment of the present application.
  • the material of the pixel electrode layer 18 in the embodiment of the present application is indium tin oxide (indium tin oxide, ITO), and include a pixel electrode structure composed of a pixel electrode 181, a shielding electrode 182 and an isolation groove 183, wherein the isolation groove 183 is arranged between the pixel electrode 181 and the shielding electrode 182, and surrounds the pixel electrode 181, and the width of the isolation groove 183 greater than or equal to 2 microns.
  • ITO indium tin oxide
  • the pixel electrode 181 of the present application is a whole rectangular electrode block, that is, there is no slit in the rectangular electrode block.
  • FIG. 3 is a partial structural diagram of the common electrode layer 21 according to the embodiment of the present application.
  • the common electrode layer 21 is disposed between the second substrate 20 and the display layer 30 (as shown in FIG. 1 ).
  • the material of the common electrode layer 21 is ITO, and includes a common electrode 211 and a groove structure formed in the common electrode 211 and penetrating through the common electrode 211 .
  • the groove structure includes a trunk groove 212 , a first groove 213 and a second groove 214 , wherein the common electrode 211 is set corresponding to the rectangular block-shaped pixel electrode 181 .
  • the first slot 213 and the second slot 214 are located at different longitudinal positions, and the first slot 213 is vertical and connected to one side of the trunk slot 212, and the second slot 214 is vertical and connected to The other side of the trunk groove 212 .
  • the trunk groove 212 includes a first end 212a and a second end 212b opposite to each other and an intermediate shaft 210 defined between the first end 212a and the second end 212b, wherein the first slot 213 and the second slot 214 They are respectively located on two opposite sides of the intermediate shaft 210 .
  • the trunk groove 212 has a first width D1
  • the first groove 213 and the second groove 214 have a second width D2 respectively, wherein the first width D1 and the second width D2 are respectively less than or equal to 30 microns, And greater than or equal to 3 microns.
  • the first width D1 and the second width D2 cannot be too large.
  • first slot 213 and the main slot 212 together form an approximately inverted T configuration, while the second slot 214 and the main slot 212 jointly form a T configuration.
  • first slot 213 , the second slot 214 and the main slot 212 jointly form an approximately zigzag configuration in a side view.
  • FIG. 4 is a schematic structural diagram of the mutual alignment of the pixel electrode layer 18 and the common electrode layer 21
  • FIG. 5 is a schematic diagram of an optical simulation of the pixel unit of the embodiment of the present application.
  • the end of the first groove 213 away from the main groove 212 extends beyond the top side of the pixel electrode 181 and enters the pixel electrode layer 18.
  • the isolation groove 183 and the end of the second opening 214 away from the trunk groove 212 extend beyond the bottom side of the pixel electrode 181 and enter the isolation groove 183 .
  • FIG. 4 is a schematic structural diagram of the mutual alignment of the pixel electrode layer 18 and the common electrode layer 21
  • FIG. 5 is a schematic diagram of an optical simulation of the pixel unit of the embodiment of the present application.
  • the main groove 212 is located at the central position of the corresponding pixel electrode 181 or close to the central position, and the first end 212a and the second end 212b of the main groove 212 respectively extend to two opposite ends of the pixel electrode 181. side, or two opposite sides beyond the pixel electrode 181 .
  • the pixel unit of the present application utilizes the trunk groove 212, the first groove 213, and the second groove 214 of the common electrode layer 21 in combination with the lower rectangular block-shaped pixel electrode 181 and isolation groove 183.
  • the optical simulation diagram under the control of the data signal of the data line group 130 perfectly presents the dark fringe shape of the trunk groove 212 , the first groove 213 and the second groove 214 , that is, there is no dark fringe abnormality.
  • the gap electric field formed by the rectangular isolation groove 183 is used to induce the liquid crystal in the pixel unit to tilt correctly. It should be noted that the length of the first groove 213 beyond the pixel electrode 181 must be greater than or equal to 1 micron, and the length of the second groove 214 beyond the pixel electrode 181 must be greater than or equal to 1 micron.
  • the display status of the application is shown in Figure 5, with no dark streak abnormalities.
  • the pixel unit of this application adopts a structure in which the number of gate lines is halved and the number of data lines is multiplied (that is, half gate and two data, HG2D) to improve the charging rate of the pixel, thereby enhancing the display with a high refresh rate Effect.
  • the first data line 131 and the second data line 132 in the embodiment of the present application together form a data line group 130 , which is arranged under the pixel electrode layer 18 .
  • FIG. 6 is a schematic structural diagram of the pixel electrode layer 18 according to the embodiment of the present application. As shown in FIG.
  • the shielding electrode 182 is disposed around the isolation groove 183 , and a connection line 184 extends from one side of the shielding electrode 182 for electrically connecting to the second metal layer 13 .
  • the shielding electrode 182 forms a data line without black matrix (data line black matrix) less, DBS), but not limited thereto.
  • FIG. 7 is a schematic structural diagram of the common electrode layer 21 of the embodiment of the present application.
  • the common electrode layer 21 shown in FIG. 7 is a reverse view of the common electrode layer 21 shown in FIG. 3 .
  • the common electrode layer 21 includes a common electrode 211 and a groove structure formed in the common electrode 211 and penetrating through the common electrode 211 .
  • the slot structure includes a trunk slot 212 , a first slot 213 and a second slot 214 , and their mutual structural relationship has been described in detail above, and will not be repeated here.
  • a black matrix layer 201 may be disposed between the top of the common electrode layer 21 and the second substrate 20 to shield components below.
  • FIG. 8 is a schematic plan view of the combined structure of the display panel 1 in FIG. 1 , which is mainly used to show the corresponding relationship among the common electrode layer 21 , the pixel electrode layer 18 and the second metal layer 13 .
  • the active component 14 of the second metal layer 13 includes a source 141 , a drain 142 and a channel layer 143 , and the active component 14 is correspondingly located between the connecting line 184 of the shielding electrode 182 and the pixel electrode 181 area.
  • the horizontal distance between the first data line 131 and the middle axis 210 of the trunk groove 212 is smaller than the horizontal distance between the first data line 131 and the first end 212a of the trunk groove 212, and the first The horizontal distance between the second data line 132 and the middle axis 210 is smaller than the horizontal distance between the second data line 132 and the second end 212b.
  • the first data line 131 and the second data line 132 respectively include a top line segment 133, a bottom line segment 134, and a vertical line segment 135 between the top line segment 133 and the bottom line segment 134, wherein the top line segment 133 and the bottom line segment 134
  • the bottom line segments 134 are respectively inclined toward the middle axis 210, so that the vertical line segments 135 approach the middle axis 210, so that the vertical line segments 135 of the first data line 131 correspond to the position of the first slot 213, and the position of the second data line 132
  • the vertical line segment 135 corresponds to the position of the second slot 214 .
  • the first slot 213 overlaps with the first data line 131 relative to the pixel electrode layer 18
  • the second slot 214 overlaps with the second data line 132 relative to the pixel electrode layer 18 .
  • the width of the first data line 131 and the width of the second data line 132 are respectively greater than or equal to the width of the first slot 213 or the width of the second slot 214, so that the first data line 131 and the second data line 132
  • the first slot 213 and the second slot 214 can be covered respectively.
  • the first data line 131 and the second data line 132 respectively extend towards the middle of the common electrode layer 21 and cooperate with the first slot 213 and the second slot 214 It is set so that the dark area presented by the first slot 213 and the second slot 214 can be shielded by the first data line 131 and the second data line 132, so as not to occupy different parts of the pixel opening and reduce the loss of the pixel opening.
  • FIG. 9 is a simulated diagram of pixel dark fringe distribution of a pixel unit according to an embodiment of the present application.
  • the voltage difference between the dark lines of the liquid crystal on the second substrate 20 (ie, the upper plate) and the ITO electrodes of the first substrate 10 (ie, the lower plate) is stable, and the liquid crystal is dark.
  • the pattern distribution is consistent, wherein the first data line 131 and the second data line 132 coincide with the dark lines of the first slot 213 and the second slot 214 on the left and right respectively, which reduces the loss of the pixel opening.
  • FIG. 10 is a diagram of the potential field distribution and liquid crystal inversion distribution of the pixel unit in FIG. 9 .
  • a pixel electrode structure including a rectangular block-shaped pixel electrode 181, a shielding electrode 182, and an isolation groove 183, in conjunction with a groove structure including a trunk groove 212, a first groove 213, and a second groove 214, in the data
  • the potential in the first slot 213 and the second slot 214 is the highest, and the liquid crystal distributed on the pixel unit is reversed, respectively along 45°, 135°, and -45° in the four domains.
  • the direction distribution of -135° can achieve the same direction of liquid crystal as the slit design of the traditional pixel electrode.
  • FIG. 11 is a schematic structural diagram of a display device 100 provided in an embodiment of the present application.
  • the embodiment of the present application further provides a display device 100 including a backlight module 4 and the display panel 1 of the above-mentioned embodiment.
  • the backlight module 4 in the embodiment of the present application takes an edge-lit backlight as an example, and is used to provide the light source required by the display panel 1 .
  • the backlight module 4 includes optical elements such as a light emitting element 41 , a reflector 42 , and a diffusion plate 43 .
  • the detailed structure of the backlight module 4 can be the same as that of the existing backlight module of the liquid crystal display device, and will not be repeated here.
  • the common electrode layer includes a trunk groove and a groove structure of the first groove and the second groove arranged at intervals on opposite sides of the trunk groove, and the pixel
  • the electrode layer includes a pixel electrode structure of a rectangular block pixel electrode, an isolation groove and a shielding electrode.
  • the first groove and the second groove present a non-cross-shaped dark area, and the resulting
  • the above-mentioned dark area can be shielded by the first data line and the second data line, and will not occupy different parts of the pixel opening, thereby reducing the loss of the pixel opening, improving the charging rate of the pixel, and increasing the performance of the display panel at a high refresh rate display effect.
  • the display panel and the display device of the embodiment of the present application effectively solve the problem of reducing the area of the pixel opening caused by the pixel penetration loss caused by the traditional display panel because the cross lines and the data lines in the opening area respectively occupy different parts of the pixel opening. The problem.

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Abstract

一种显示面板(1)及显示装置(100)。显示面板(1)在对应每一像素单元的部分包括像素电极层(18)、第一金属层(11)、第二金属层(13)及公共电极层(21)。第二金属层(13)包括第一数据线(131)及第二数据线(132)。公共电极层(21)包括公共电极(211)与设在公共电极(211)的主干槽(212)及分别位于不同纵向位置的第一开槽(213)与第二开槽(214)。第一开槽(213)相对像素电极层(18)与第一数据线(131)重叠，第二开槽(214)相对像素电极层(18)与第二数据线(132)重叠。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
一般显示面板的像素结构是由扫描线与数据线交错定义出像素单元。对于超高清面板或高刷新频率的像素设计而言，在单一像素单元增加一倍数据线的架构，可增加一倍像素充电，进而改善像素的充电率。但是对于上述像素单元架构而言，因增加一倍数据线(data line)数量，数据线会大量挤占像素的布局空间，从而降低像素的开口率。以开口损失比较小的一种像素架构来说，对每个像素而言，两根数据线从像素开口区下面穿过，并且位于像素开口的左、右两侧，两根数据项正负极性不同，其对像素电极的耦合效应可以正负抵消。目前的像素结构具有交叉构型的横向主干像素电极及纵向主干像素电极，通过数据线控制像素电极的电位。然而，在目前利用两根数据线构成的像素结构的光学特征中发现，在像素亮态时，会在像素电极的主干区形成十字构型的暗纹。亦即，该十字暗纹和在开口区的两根数据线分别占据了像素开口区不同的范围，并一起造成像素穿透损失，减少像素开口的面积。
 技术问题
本申请提供一种显示面板及显示装置，以解决现有的显示面板因为双数据线及十字暗纹分别占据了像素开口不同的区域，造成像素穿透损失，减少像素开口面积的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，包括相对设置的第一基板及第二基板、显示层及分布在所述第一基板及所述第二基板之间的多个像素单元。所述显示面板在对应每一所述像素单元的部分包括像素电极层，设置在所述第一基板与所述显示层之间，包括像素电极、隔离槽及屏蔽电极，其中所述隔离槽设置在所述像素电极及所述屏蔽电极之间，并围绕所述像素电极；第一金属层，设置在所述第一基板上，并位于所述像素电极层及所述第一基板之间；第二金属层，设置在所述第一基板及所述像素电极层之间，并包括具有第一数据线及第二数据线的数据线组，所述数据线组电连接于所述像素电极层；公共电极层，设置在所述第二基板与所述显示层之间，并包括公共电极及设在所述公共电极的主干槽、第一开槽及第二开槽，其中所述公共电极对应所述像素电极设置，所述第一开槽与所述第二开槽分别位于不同的纵向位置，所述第一开槽垂直并连接于所述主干槽的一侧，所述第二开槽垂直并连接于所述主干槽的另一侧，且所述第一开槽相对所述像素电极层与所述第一数据线重叠，所述第二开槽相对所述像素电极层与所述第二数据线重叠。
进一步地，所述主干槽包括相对设置的第一端及第二端及定义在所述第一端及第二端之间的中间轴，其中所述第一开槽及所述第二开槽分别位于所述中间轴的相对二侧，所述第一数据线与所述中间轴之间的水平距离小于所述第一数据线与所述第一端之间的水平距离，且所述第二数据线与所述中间轴之间的水平距离小于所述第二数据线与所述第二端之间的水平距离。
进一步地，所述主干槽在所述像素电极层的正投影位于所述像素电极的中央位置或靠近所述中央位置，且所述主干槽的第一端及第二端分别延伸至所述像素电极的相对二边，或超出所述像素电极的相对二边。
进一步地，所述第一数据线及所述第二数据线分别包括顶线段、底线段及位于所述顶线段及所述底线段之间的垂直线段，其中所述顶线段及所述底线段分别朝所述主干槽的中间轴方向倾斜，所述第一数据线的垂直线段对应于所述第一开槽的位置，且所述第二数据线的垂直线段对应于所述第二开槽的位置。
进一步地，所述像素电极层的像素电极为矩形电极块，所述遮蔽电极包围所述隔离槽设置，并电连接于所述第二金属层。
进一步地，所述第一开槽远离所述主干槽的一端在所述像素电极层的正投影是超过所述像素电极的顶侧，及所述第二开槽远离所述主干槽的一端在所述像素电极层的正投影是超过所述像素电极的底侧。
进一步地，所述主干槽具有第一宽度，所述第一开槽及所述第二开槽分别具有第二宽度，其中所述第一宽度及所述第二宽度分别小于或等于30微米，且大于或等于3微米。
进一步地，所述主干槽为水平状，并以一水平方向设置在所述公共电极，所述第一开槽及所述第二开槽分别为竖直状，并分别垂直于所述主干槽，其中所述第一数据线的宽度大于或等于所述第一开槽或所述第二开槽的宽度，及所述第二数据线的宽度大于或等于所述第二开槽或所述第二开槽的宽度。
进一步地，所述显示面板还包括栅极绝缘层、设在所述第二金属层上的缓冲层、设在所述缓冲层及所述像第二基板之间的彩膜层及平坦层。
本申请实施例还提供一种显示装置，包括背光模块及任一所述的显示面板，所述背光模块用于提供所述显示面板所需的光源。
 有益效果
在本申请提供的显示面板及显示装置中，公共电极层包括主干槽及相互间隔设置在主干槽相对二侧的第一开槽及第二开槽的开槽结构，及像素电极层包括矩形块状像素电极、隔离槽及屏蔽电极的像素电极结构。利用朝内延伸设置的第一数据线和第二数据线、所述开槽结构及所述像素电极结构的配合，使第一开槽及第二开槽呈现非十字形的暗区，并且所述暗区可以被第一数据线及第二数据线遮蔽，不会占据相素开口的不同部位，从而减少像素开口的损失，同时可改善像素的充电率，提升显示面板的在高刷新频率的显示效果。据此，本申请的显示面板及显示装置有效解决传统显示面板因为十字暗纹和在开口区的数据线分别占据了像素开口区不同的范围，进而造成像素穿透损失，减少像素开口的面积的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例的显示面板的立体分解结构示意图。
图2为本申请实施例的像素电极层的部分结构示意图。
图3为本申请实施例的公共电极层的部分结构示意图。
图4为所述像素电极层及所述公共电极层相互对准的结构示意图。
图5为本申请实施例的像素单元的光学模拟示意图。
图6为本申请实施例的像素电极层的结构示意图。
图7为本申请实施例的公共电极层的结构示意图。
图8为图1的显示面板部分的平面组合结构示意图。
图9为本申请实施例的像素单元的像素暗纹分布仿真图。
图10为本申请实施例的像素单元的像素的电势场分布和液晶倒向分布图。
图11为本申请实施例的显示装置的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
本申请实施例提供一种显示面板，尤其是指一种具有薄膜晶体管阵列的液晶显示面板。所述显示面板设置有数条栅极扫描线和数条数据线，所述数条栅极扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极。具体的，本申请实施例采用单一像素单元中的栅极线的数量减半、数据线的数量倍增的架构驱动显示单元。亦即，每一像素单元是利用两条数据线及一条扫描线的搭配驱动所述像素单元。
请参阅图1，图1为本申请实施例的显示面板1的立体分解结构示意图。如图1所示，本申请实施例的显示面板1具有一层叠架构，包括由下往上(即图1所示的由右朝左的方向)设置的第一基板10、第一金属层11、栅极绝缘层12、第二金属层13、钝化层15、彩膜层16、平坦层17、像素电极层18、显示层30、公共电极层21、黑矩阵层201及第二基板20。特别注意的是，图1是以一个像素单元具有四畴(domain)的像素设计作为本申请显示面板1的说明，其中第一基板10及第二基板20可为玻璃基板、石英基板或塑料基板，在此并不限定。第一基板10及第二基板20之间以阵列方式排布有多个所述像素单元。本实施例的显示层30为一液晶显示层，包括有多个液晶分子(未图示)。此外，第一金属层11包括栅极111及扫描线112，而第二金属层13包括一个数据线组130及有源组件14，其中数据线组130由第一数据线131及第二数据线132构成，且有源组件14及栅极111共同构成一个薄膜晶体管。亦即，本申请的第一基板10为阵列基板，即本申请的显示面板1为一种薄膜晶体管液晶显示面板。
如图1所示，栅极绝缘层12、钝化层15及平坦层17的材料可分别为氮化物(氮化硅等)、氧化物(氧化硅、二氧化硅)或者其他绝缘材料。此外，本申请实施例的彩膜层16与第一基板10集成在一起而形成一种彩膜在阵列基板(color filter on array，简称C0A)的结构。利用COA结构可以避免第一基板10和第二基板20对盒时的偏差影响显示器件开口率和出现漏光的问题。然而，本申请的显示面板1并不以COA结构为限制。亦即，彩膜层16也可以设在第二基板20的一侧(未图示)，从而形成一种非COA结构的彩膜基板。
请参阅图2，其为本申请实施例的像素电极层18的部分结构示意图。如图2所示，本申请实施例的像素电极层18的材料为氧化铟锡( indium tin oxide, ITO) ，并包括像素电极181、屏蔽电极182及隔离槽183构成的像素电极结构，其中隔离槽183设置在像素电极181及屏蔽电极182之间，并围绕像素电极181，且隔离槽183的宽度大于或等于2微米。特别注意的是，有别于传统像素单元的结构，本申请的像素电极181为整片的矩形电极块，亦即，矩形电极块内并不具有狭缝。
请参阅图3并配合图1，图3为本申请实施例的公共电极层21的部分结构示意图。公共电极层21设置在第二基板20与显示层30之间(如图1所示)。如图3所示，公共电极层21的材料为氧化铟锡，并包括公共电极211及形成在公共电极211内并且穿透公共电极211的开槽结构。所述开槽结构包括主干槽212、第一开槽213及第二开槽214，其中公共电极211是对应矩型块状的像素电极181设置。在本实施例中，第一开槽213与第二开槽214分别位于不同的纵向位置，且第一开槽213垂直并连接于主干槽212的一侧，第二开槽214垂直并连接于主干槽212的另一侧。具体地，主干槽212包括相对设置的第一端212a及第二端212b及定义在第一端212a及第二端212b之间的中间轴210，其中第一开槽213及第二开槽214分别位于中间轴210的相对二侧。在本实施例中，主干槽212具有第一宽度D1，第一开槽213及第二开槽214分别具有第二宽度D2，其中第一宽度D1及第二宽度D2分别小于或等于30微米，且大于或等于3微米。特别注意的是，第一宽度D1不能太小，否则ITO缝隙诱发的偏转电场不会很强，对应所述开槽结构的暗纹可能不会按照预期形成。此外，考虑到对像素穿透率的损失，第一宽度D1及第二宽度D2亦不能过大。换句话说，越大的开槽的宽度所损失开口率越大，即像素有效发光面积越小，故在实现所需功能的前提下，以小于或等于30微米的范围为佳。
此外，如图3所示，第一开槽213与主干槽212共同构成近似倒转T的构型，而第二开槽214与主干槽212共同构成一个T构型。具体地，第一开槽213、第二开槽214及主干槽212在侧向视角下共同构成一近似Z字形的构型。
请参阅图4及图5。图4为像素电极层18及公共电极层21相互对准的结构示意图，图5为本申请实施例的像素单元的光学模拟示意图。如图4所示，在公共电极层21在像素电极层18的正投影的视角下，第一开槽213远离主干槽212的一端是延伸超过像素电极181的顶侧，并且进入像素电极层18的隔离槽183，及第二开槽214远离主干槽212的一端是延伸超过像素电极181的底侧，并且进入隔离槽183。此外，如图4所示，主干槽212位于对应的像素电极181的中央位置或靠近所述中央位置，且主干槽212的第一端212a及第二端212b分别延伸至像素电极181的相对二边，或超出像素电极181的相对二边。如图5所示，利用公共电极层21的主干槽212、第一开槽213及第二开槽214的开槽结构搭配下方矩形块状的像素电极181及隔离槽183，本申请的像素单元在数据线组130的数据信号控制下的光学模拟图完好呈现出主干槽212、第一开槽213及第二开槽214的暗纹形状，亦即，没有出现暗纹异常。此外，矩形隔离槽183形成的缝隙电场，用以诱导像素单元内液晶正确倾倒。特别注意的是，第一开槽213超过像素电极181的长度必须是大于或等于1微米，且第二开槽214超过像素电极181的长度必须是大于或等于1微米，通过上述结构才能使本申请的显示状态如图5所示的无暗纹异常。
如上所述，本申请像素单元采用栅极线的数量减半，且数据线的数量倍增的结构(即half gate and two data, HG2D)，以改善像素的充电率，从而提升高更新率的显示效果。如图1所示，本申请实施例的第一数据线131及第二数据线132共同构成一个数据线组130，设置在像素电极层18的下方。请参阅图6，图6为本申请实施例的像素电极层18的结构示意图。如图6所示，遮蔽电极182包围隔离槽183设置，且遮蔽电极182的一侧延伸出连接线184，用以电连接于第二金属层13。在本申请实施例中，遮蔽电极182形成一种数据线上方无黑色矩阵(data line black matrix less，DBS)的公共电极线，但并不以此为限。
请参阅图7，其为本申请实施例的公共电极层21的结构示意图。图7所述的公共电极层21为图3所示的公共电极层21的反向视图。如图7所示，公共电极层21包括公共电极211及形成在公共电极211内并且穿透公共电极211的开槽结构。所述开槽结构包括主干槽212、第一开槽213及第二开槽214，其相互结构关系已详述如上，于此不再赘述。特别注意的是，公共电极层21的顶部和第二基板20之间可设置黑矩阵层201，用以遮蔽下方部件。
请参阅图8并配合图1及图3。图8为图1的显示面板1部分的平面组合结构示意图，主要用以表示公共电极层21、像素电极层18及第二金属层13之间的对应关系。如图8所示，第二金属层13的有源组件14包括源极141、漏极142及通道层143，且有源组件14对应位于遮蔽电极182的连接线184及像素电极181 之间的区域。续请参阅图8及图3，第一数据线131与主干槽212的中间轴210之间的水平距离小于第一数据线131与主干槽212的第一端212a之间的水平距离，及第二数据线132与中间轴210之间的水平距离小于第二数据线132与第二端212b之间的水平距离。具体地，如图8所示，第一数据线131及第二数据线132分别包括顶线段133、底线段134及位于顶线段133及底线段134之间的垂直线段135，其中顶线段133及底线段134分别朝中间轴210方向倾斜，使垂直线段135朝中间轴210方向靠近，从而使第一数据线131的垂直线段135对应于第一开槽213的位置，及第二数据线132的垂直线段135对应于第二开槽214的位置。亦即，第一开槽213相对像素电极层18与第一数据线131重叠，第二开槽214相对像素电极层18与第二数据线132重叠。特别注意的是，第一数据线131的宽度及第二数据线132的宽度分别大于或等于第一开槽213或第二开槽214的宽度，使第一数据线131及第二数据线132可以分别覆盖第一开槽213及第二开槽214。
如上所述，在本申请显示面板1的像素单元中，第一数据线131及第二数据线132分别朝向公共电极层21的中间部位延伸，并配合第一开槽213及第二开槽214设置，使第一开槽213及第二开槽214呈现的暗区可以被第一数据线131及第二数据线132遮蔽，从而不会占据相素开口的不同部位，减少像素开口的损失。
图9为本申请实施例的像素单元的像素暗纹分布仿真图。如图9所示，在7伏特电压的状态下，液晶暗纹在第二基板20(即上板)和第一基板10(即下板)的ITO电极的压差稳定，且所述液晶暗纹分布一致，其中第一数据线131及第二数据线132分别和左侧及右侧的第一开槽213及第二开槽214的暗纹重合，减少了像素开口的损失。
图10为图9的像素单元的电势场分布和液晶倒向分布图。如图10所示，利用包括矩形块状像素电极181、屏蔽电极182及隔离槽183的像素电极结构，配合包括主干槽212第一开槽213及第二开槽214的开槽结构，在数据线的数据信号控制下，使在第一开槽213及第二开槽214的电势最高，并且像素单元上分布的液晶倒向，在四畴里面分别沿着45°，135°，-45°，-135°的方向分布，其可实现与传统像素电极的狭缝设计所要达到的液晶走向一致。
请参阅图11，其为本申请实施例提供的一种显示装置100的结构示意图。如图11所示，本申请实施例另外提供一种显示装置100，包括背光模块4及上述实施例的显示面板1。本申请实施例的背光模块4是以侧入式背光为例，用于提供显示面板1所需的光源。背光模块4包括发光元件41、反射片42及扩散板43等光学元件。背光模块4的细部结构可与现有的液晶显示装置的背光模块的结构相同，于此不再赘述。
综上所述，在本申请提供的显示面板及显示装置中，公共电极层包括主干槽及相互间隔设置在主干槽相对二侧的第一开槽及第二开槽的开槽结构，及像素电极层包括矩形块状像素电极、隔离槽及屏蔽电极的像素电极结构。利用朝内延伸设置的第一数据线和第二数据线、所述开槽结构及所述像素电极结构的配合，使第一开槽及第二开槽呈现非十字形的暗区，并且所述暗区可以被第一数据线及第二数据线遮蔽，不会占据相素开口的不同部位，从而减少像素开口的损失，同时可改善像素的充电率，提升显示面板的在高刷新频率的显示效果。据此，本申请实施例的显示面板及显示装置有效解决传统显示面板因为十字暗纹和在开口区的数据线分别占据了像素开口不同的部位，进而造成像素穿透损失，减少像素开口的面积的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，包括相对设置的第一基板及第二基板、显示层及分布在所述第一基板及所述第二基板之间的多个像素单元，所述显示面板在对应每一所述像素单元的部分包括：
    像素电极层，设置在所述第一基板与所述显示层之间，包括像素电极、隔离槽及屏蔽电极，其中所述隔离槽设置在所述像素电极及所述屏蔽电极之间，并围绕所述像素电极；
    第一金属层，设置在所述第一基板上，并位于所述像素电极层及所述第一基板之间；
    第二金属层，设置在所述第一基板及所述像素电极层之间，并包括具有第一数据线及第二数据线的数据线组，所述数据线组电连接于所述像素电极层；
    公共电极层，设置在所述第二基板与所述显示层之间，并包括公共电极及设在所述公共电极的主干槽、第一开槽及第二开槽，其中所述公共电极对应所述像素电极设置，所述第一开槽与所述第二开槽分别位于不同的纵向位置，所述第一开槽连接于所述主干槽的一侧，所述第二开槽连接于所述主干槽的另一侧，且所述第一开槽相对所述像素电极层与所述第一数据线重叠，所述第二开槽相对所述像素电极层与所述第二数据线重叠。
  2. 如权利要求1所述的显示面板，其中所述主干槽包括相对设置的第一端及第二端及定义在所述第一端及第二端之间的中间轴，其中所述第一开槽及所述第二开槽分别位于所述中间轴的相对二侧，所述第一数据线与所述中间轴之间的水平距离小于所述第一数据线与所述第一端之间的水平距离，且所述第二数据线与所述中间轴之间的水平距离小于所述第二数据线与所述第二端之间的水平距离。
  3. 如权利要求2所述的显示面板，其中所述主干槽在所述像素电极层的正投影位于所述像素电极的中央位置或靠近所述中央位置，且所述主干槽的第一端及第二端分别延伸至所述像素电极的相对二边，或超出所述像素电极的相对二边。
  4. 如权利要求2所述的显示面板，其中所述第一数据线及所述第二数据线分别包括顶线段、底线段及位于所述顶线段及所述底线段之间的垂直线段，其中所述顶线段及所述底线段分别朝所述主干槽的中间轴方向倾斜，所述第一数据线的垂直线段对应于所述第一开槽的位置，且所述第二数据线的垂直线段对应于所述第二开槽的位置。
  5. 如权利要求1所述的显示面板，其中所述像素电极层的像素电极为矩形电极块，所述遮蔽电极包围所述隔离槽设置，并电连接于所述第二金属层。
  6. 如权利要求5所述的显示面板，其中所述第一开槽远离所述主干槽的一端在所述像素电极层的正投影是超过所述像素电极的顶侧，及所述第二开槽远离所述主干槽的一端在所述像素电极层的正投影是超过所述像素电极的底侧。
  7. 如权利要求1所述的显示面板，其中所述主干槽具有第一宽度，所述第一开槽及所述第二开槽分别具有第二宽度，其中所述第一宽度及所述第二宽度分别小于或等于30微米，且大于或等于3微米。
  8. 如权利要求1所述的显示面板，其中所述主干槽为水平状，并以一水平方向设置在所述公共电极，所述第一开槽及所述第二开槽分别为竖直状，并分别垂直于所述主干槽，其中所述第一数据线的宽度大于或等于所述第一开槽或所述第二开槽的宽度，及所述第二数据线的宽度大于或等于所述第二开槽或所述第二开槽的宽度。
  9. 如权利要求1所述的显示面板，其中所述显示面板还包括栅极绝缘层、设在所述第二金属层上的钝化层、设在所述钝化层及所述像第二基板之间的彩膜层及平坦层。
  10. 一种显示装置，包括背光模块及显示面板，所述背光模块用于提供所述显示面板所需的光源，所述显示面板包括相对设置的第一基板及第二基板、显示层及分布在所述第一基板及所述第二基板之间的多个像素单元，其中所述显示面板在对应每一所述像素单元的部分包括：
    像素电极层，设置在所述第一基板与所述显示层之间，包括像素电极、隔离槽及屏蔽电极，其中所述隔离槽设置在所述像素电极及所述屏蔽电极之间，并围绕所述像素电极；
    第一金属层，设置在所述第一基板上，并位于所述像素电极层及所述第一基板之间；
    第二金属层，设置在所述第一基板及所述像素电极层之间，并包括具有第一数据线及第二数据线的数据线组，所述数据线组电连接于所述像素电极层；以及
    公共电极层，设置在所述第二基板与所述显示层之间，并包括公共电极及设在所述公共电极的主干槽、第一开槽及第二开槽，其中所述公共电极对应所述像素电极设置，所述第一开槽与所述第二开槽分别位于不同的纵向位置，所述第一开槽连接于所述主干槽的一侧，所述第二开槽连接于所述主干槽的另一侧，且所述第一开槽相对所述像素电极层与所述第一数据线重叠，所述第二开槽相对所述像素电极层与所述第二数据线重叠。
  11. 如权利要求10所述的显示装置，其中所述主干槽包括相对设置的第一端及第二端及定义在所述第一端及第二端之间的中间轴，其中所述第一开槽及所述第二开槽分别位于所述中间轴的相对二侧，所述第一数据线与所述中间轴之间的水平距离小于所述第一数据线与所述第一端之间的水平距离，且所述第二数据线与所述中间轴之间的水平距离小于所述第二数据线与所述第二端之间的水平距离。
  12. 如权利要求11所述的显示装置，其中所述主干槽在所述像素电极层的正投影位于所述像素电极的中央位置或靠近所述中央位置，且所述主干槽的第一端及第二端分别延伸至所述像素电极的相对二边，或超出所述像素电极的相对二边。
  13. 如权利要求11所述的显示装置，其中所述第一数据线及所述第二数据线分别包括顶线段、底线段及位于所述顶线段及所述底线段之间的垂直线段，其中所述顶线段及所述底线段分别朝所述主干槽的中间轴方向倾斜，所述第一数据线的垂直线段对应于所述第一开槽的位置，且所述第二数据线的垂直线段对应于所述第二开槽的位置。
  14. 如权利要求10所述的显示装置，其中所述像素电极层的像素电极为矩形电极块，所述遮蔽电极包围所述隔离槽设置，并电连接于所述第二金属层。
  15. 如权利要求14所述的显示装置，其中所述第一开槽远离所述主干槽的一端在所述像素电极层的正投影是超过所述像素电极的顶侧，及所述第二开槽远离所述主干槽的一端在所述像素电极层的正投影是超过所述像素电极的底侧。
  16. 如权利要求10所述的显示装置，其中所述主干槽为水平状，并以一水平方向设置在所述公共电极，所述第一开槽及所述第二开槽分别为竖直状，并分别垂直于所述主干槽，其中所述第一数据线的宽度大于或等于所述第一开槽或所述第二开槽的宽度，及所述第二数据线的宽度大于或等于所述第二开槽或所述第二开槽的宽度。
  17. 如权利要求10所述的显示装置，其中所述显示面板还包括栅极绝缘层、设在所述第二金属层上的钝化层、设在所述钝化层及所述像第二基板之间的彩膜层及平坦层。
  18. 如权利要求10所述的显示装置，其中所述主干槽具有第一宽度，所述第一开槽及所述第二开槽分别具有第二宽度，其中所述第一宽度及所述第二宽度分别小于或等于30微米，且大于或等于3微米。
  19. 如权利要求10所述的显示装置，其中所述主干槽、所述第一开槽及所述第二开槽分别穿透所述公共电极。
  20. 如权利要求10所述的显示装置，其中所述背光模块包括发光元件、反射片及扩散板。
PCT/CN2021/116421 2021-08-25 2021-09-03 显示面板及显示装置 WO2023024149A1 (zh)

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