WO2023024136A1 - 显示面板 - Google Patents

显示面板 Download PDF

Info

Publication number
WO2023024136A1
WO2023024136A1 PCT/CN2021/116072 CN2021116072W WO2023024136A1 WO 2023024136 A1 WO2023024136 A1 WO 2023024136A1 CN 2021116072 W CN2021116072 W CN 2021116072W WO 2023024136 A1 WO2023024136 A1 WO 2023024136A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
stack structure
compensation
conductive layer
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/116072
Other languages
English (en)
French (fr)
Inventor
肖翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/599,822 priority Critical patent/US20240049520A1/en
Publication of WO2023024136A1 publication Critical patent/WO2023024136A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness

Definitions

  • the present application relates to the field of display technology, in particular to a display panel.
  • Organic light emitting diodes (Organic Light Emitting Diode, OLED) have the characteristics of self-luminescence, fast response speed, wide viewing angle, etc., and have broad application prospects.
  • OLED Organic Light Emitting Diode
  • AMOLED evaporation active-matrix Organic Light Emitting Diode
  • IJP Ink Jet Printing
  • the maximum step difference of the entire pixel area be as small as possible.
  • the spreadability of the ink will be uneven, and the film thickness will be uneven after drying, which will eventually affect the luminous effect. Therefore, the flattening ability of the planarization layer of IJP-AMOLED has more stringent requirements.
  • the planarization layer is an organic photosensitive material, and the current solution is to thicken the planarization layer.
  • the one-time planarization ability of the planarization layer is limited, that is, when the base level difference reaches a certain level, the planarization layer has increased to a very thick level, but the flatness still cannot meet the requirements; 2.
  • the planarization layer is designed with openings. If the opening is too deep, it will affect the subsequent film deposition, such as climbing and breaking lines.
  • the embodiment of the present application provides a display panel, which can reduce the risk of uneven film thickness of the light-emitting layer.
  • An embodiment of the present application provides a display panel, the display panel includes a plurality of pixel regions, including:
  • a thin film transistor layer is arranged on the substrate, the thin film transistor layer includes a first stack structure and a second stack structure, and the first stack structure and the second stack structure are correspondingly arranged on the same
  • the first stacked structure includes a multi-layered conductive layer and a multi-layered insulating layer
  • the second stacked structure includes a compensation layer and a multi-layered insulating layer
  • the first stacked structure The number of layers of the conductive layer is greater than the number of layers of the conductive layer of the second stack structure; the height of the first stack structure is greater than or equal to the height of the second stack structure, and the compensation layer is used to increase the height of the second stack structure. the height of the stacked structure;
  • the flat layer covers the thin film transistor layer, and the surface of the flat layer away from the substrate is a flat surface;
  • the electrode layer is disposed on the planar layer
  • a pixel definition layer is arranged on the electrode layer, the pixel definition layer includes a plurality of openings, one of the openings is correspondingly arranged in one of the pixel regions, the first stack structure and the second The two stacked structures correspond to the same arrangement of the openings;
  • the light emitting layer is disposed in the opening.
  • a side of the first stack structure away from the substrate is flush with a side of the second stack structure away from the substrate.
  • a portion of the surface of the flat layer away from the substrate corresponding to the pixel region is a flat surface.
  • the thin film transistor layer further includes a multilayer stacked insulating layer disposed on the substrate, and the conductive layer is disposed between two adjacent insulating layers. ;
  • the compensation layer is disposed at any position on the substrate.
  • the multiple compensation layers are arranged in different layers from each other.
  • the second stack structure further includes at least one conductive layer.
  • the second stack structure includes a first compensation structure and a second compensation structure
  • the first compensation structure includes a first compensation layer and multiple layers of the insulating layer
  • the second compensation structure includes a second compensation layer and multiple layers of the insulating layer, and the number of layers of the conductive layer of the second compensation structure is smaller than the number of layers of the conductive layer of the first compensation structure;
  • the first compensation layer is arranged at any position on the substrate;
  • the second compensation layer is arranged at any position on the substrate.
  • the first compensation layer is connected to the second compensation layer.
  • the thickness of the first compensation layer is smaller than the thickness of the second compensation layer.
  • the thin film transistor layer further includes a third stack structure disposed corresponding to the opening, and in the area of the same opening, the third stack structure is located on the On one side of the second stack structure, the third stack structure includes the second compensation layer and at least one conductive layer, and the number of layers of the conductive layer of the second stack structure is greater than that of the third stack structure the number of layers;
  • the third compensation layer is disposed at any position on the substrate.
  • the side of the first stack structure away from the substrate, the side of the second stack structure away from the substrate, and the side of the third stack structure away from the substrate Set flush on one side.
  • the multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer
  • the plurality of insulating layers include a first insulating layer, a second insulating layer, and a second insulating layer. layer and a third insulating layer;
  • the first stack structure consists of a portion of the first conductive layer, the first insulating layer, a portion of the second conductive layer, the second insulating layer, a portion of the third conductive layer, and the A capacitor structure formed by stacking third insulating layers in sequence;
  • the second stack structure consists of the compensation layer, the first insulating layer, part of the second conductive layer, the second insulating layer and the third The insulating layer stack is formed.
  • the thickness of the compensation layer is equal to or smaller than the sum of the thicknesses of the first conductive layer and the third conductive layer.
  • the multi-layer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer
  • the multiple insulating layers include a first insulating layer. layer, a second insulating layer, a third insulating layer and a fourth insulating layer;
  • the first stack structure consists of a portion of the first conductive layer, the first insulating layer, a portion of the fourth conductive layer, the fourth insulating layer, a portion of the second conductive layer, the A thin film transistor structure formed by sequentially stacking the second insulating layer, part of the third conductive layer, and the third insulating layer;
  • the second stack structure consists of part of the first conductive layer, the first insulating layer, the The compensation layer, the part of the second conductive layer, the second insulating layer, the part of the third conductive layer and the third insulating layer are sequentially stacked to form a capacitive structure.
  • the multi-layer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer
  • the multiple insulating layers include a first insulating layer. layer, a second insulating layer, a third insulating layer and a fourth insulating layer;
  • the first stack structure consists of a portion of the first conductive layer, the first insulating layer, a portion of the fourth conductive layer, the fourth insulating layer, a portion of the second conductive layer, the A thin film transistor structure formed by sequentially stacking the second insulating layer, part of the third conductive layer, and the third insulating layer;
  • the second stack structure consists of part of the first conductive layer, the first insulating layer, the The compensation layer, the part of the second conductive layer, the second insulating layer, the part of the third conductive layer and the third insulating layer are sequentially stacked to form a capacitive structure;
  • the third stack structure consists of the The third compensation layer, the first insulating layer, part of the second conductive layer, the second insulating layer and the third insulating layer are stacked and formed.
  • the thickness of the third compensation layer is greater than or equal to the sum of the thicknesses of the fourth insulating layer and the fourth conductive layer.
  • the embodiment of the present application also relates to a display panel, including a plurality of pixel regions, wherein the display panel includes:
  • a thin film transistor layer the thin film transistor layer is arranged on the substrate, the thin film transistor layer includes a first stack structure and a second stack structure, the first stack structure includes a multi-layer conductive layer and a multi-layer An insulating layer, the second stack structure includes a compensation layer and multiple layers of the insulating layer, the number of conductive layers of the first stack structure is greater than the number of conductive layers of the second stack structure; the first The height of the stacked structure is greater than or equal to the height of the second stacked structure, and the compensation layer is used to increase the height of the second stacked structure;
  • the electrode layer is disposed on the planar layer
  • a pixel definition layer is arranged on the electrode layer, the pixel definition layer includes a plurality of openings, one of the openings is correspondingly arranged in one of the pixel regions, the first stack structure and the second The two stacked structures correspond to the same arrangement of the openings;
  • a light emitting layer disposed within the opening
  • a surface of the first stack structure away from the substrate is flush with a surface of the second stack structure away from the substrate; a portion of the surface of the flat layer away from the substrate corresponding to the pixel region is a flat surface.
  • the compensation layer is disposed at any position on the substrate.
  • the multiple compensation layers are arranged in different layers from each other.
  • the second stack structure further includes at least one conductive layer.
  • the display panel of the embodiment of the present application includes a substrate, a thin film transistor layer, a flat layer, an electrode layer, a pixel definition layer, and a light emitting layer arranged in sequence;
  • the thin film transistor layer includes a first stack structure and a second stack structure, and the first stack structure and
  • the second stacked structures are all correspondingly arranged in the same pixel area.
  • the first stacked structure includes a multi-layered conductive layer and an insulating layer arranged in different layers.
  • the second stacked structure includes a compensation layer and a multi-layered insulating layer.
  • the conductive layer of the first stacked structure The number of layers is greater than the number of conductive layers of the second stack structure; the compensation layer is used to increase the height of the second stack structure; the flat layer covers the thin film transistor layer.
  • a compensation layer is added to the second stack structure to reduce the height difference between the first stack structure and the second stack structure, so that the flat layer can planarize the first stack structure and the second stack structure, at least the light emitting layer.
  • FIG. 1 is a schematic top view of a display panel provided in the first embodiment of the present application
  • FIG. 2 is a first cross-sectional schematic diagram of the display panel provided by the first embodiment of the present application
  • FIG. 3 is a schematic diagram of a second view structure of the display panel provided by the first embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a third view of the display panel provided by the first embodiment of the present application.
  • FIG. 5 is a schematic diagram of a fourth view structure of the display panel provided by the first embodiment of the present application.
  • FIG. 6 is a schematic top view of the display panel provided by the second embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional structural view of a display panel provided in a second embodiment of the present application.
  • FIG. 8 is a schematic top view of the display panel provided by the third embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional structural view of a display panel provided by a third embodiment of the present application.
  • FIG. 10 is a schematic top view of the display panel provided by the fourth embodiment of the present application.
  • An embodiment of the present application provides a display panel, which will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • the embodiment of the present application provides a display panel 100 , and the display panel 100 includes a plurality of pixel regions px.
  • the display panel 100 includes a substrate 11 , a thin film transistor layer 12 , a flat layer 13 , an electrode layer 14 , a pixel definition layer 15 and a light emitting layer 16 .
  • the thin film transistor layer 12 is disposed on the substrate 11 .
  • the thin film transistor layer 12 includes a first stack structure de1 and a second stack structure de2, and both the first stack structure de1 and the second stack structure de2 are correspondingly disposed in the same pixel area px.
  • the first stacked structure de1 includes multiple conductive layers 12a and multiple insulating layers 12b arranged in different layers.
  • the second stack structure de2 includes a compensation layer 12c and a multi-layer insulating layer 12b.
  • the number of conductive layers 12a in the first stack structure de1 is greater than the number of conductive layers 12a in the second stack structure de2.
  • the height h1 of the first stack structure de1 is greater than or equal to the height h2 of the second stack structure de2.
  • the compensation layer 12c is used to increase the height of the second stack structure de2.
  • the flat layer 13 covers the TFT layer 12 .
  • the electrode layer 14 is provided on the flat layer 13 .
  • the pixel definition layer 15 is disposed on the electrode layer 14 .
  • the pixel definition layer 15 includes a plurality of openings 151, and one opening 151 is correspondingly disposed in a pixel area px.
  • the light emitting layer 16 is disposed within the opening 151 .
  • the first stack structure de1 and the second stack structure de2 are disposed corresponding to the same opening 151 .
  • the display panel 100 of this first embodiment reduces the height difference between the first stack structure and the second stack structure in the prior art by adding a compensation layer 12c to the second stack structure de2, so that the flat layer 13 can planarize the first stack structure de1 and the second stack structure de2 at least provide a relatively flat reference plane for the formation of the light emitting layer 16 , thereby reducing the risk of uneven film thickness of the light emitting layer 16 .
  • the portion of the surface of the flat layer 13 away from the substrate 11 corresponding to the pixel region px is a flat surface.
  • Such an arrangement provides a flat reference plane for the formation of the light-emitting layer 16 , further reducing the risk of non-uniform film thickness of the light-emitting layer 16 .
  • the substrate 11 may be a rigid substrate or a flexible substrate.
  • the material of the substrate 11 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.
  • the material of the compensation layer 12c may be a metal material or an inorganic or organic material, such as silicon oxide, silicon nitride, resin, copper or an alloy.
  • the material of the flat layer 13 may be an organic transparent film layer, such as transparent photoresist, epoxy resin, polyimide, polyvinyl alcohol, polymethyl methacrylate, polystyrene, and the like.
  • organic transparent film layer such as transparent photoresist, epoxy resin, polyimide, polyvinyl alcohol, polymethyl methacrylate, polystyrene, and the like.
  • the display panel 100 further includes another electrode layer, and the other electrode layer is disposed on the light emitting layer 16 .
  • the two electrode layers one is an anode and the other is a cathode.
  • the side a1 of the first stack structure de1 away from the substrate 11 is flush with the side a2 of the second stack structure de2 away from the substrate 11 .
  • Such an arrangement makes the first stack structure de1 and the second stack structure de2 have the same height, which facilitates the planarization process of the planar layer 13 .
  • the thin film transistor layer 12 further includes an insulating layer 12b stacked on the substrate 11, and the conductive layer 12a is arranged between two adjacent insulating layers 12b.
  • the compensation layer 12 c is disposed at any position on the substrate 11 .
  • the multi-layer conductive layer 12 a includes a first conductive layer 121 , a second conductive layer 122 and a third conductive layer 123 .
  • the plurality of insulating layers 12 b includes a first insulating layer 124 , a second insulating layer 125 and a third insulating layer 126 .
  • the second stack structure de2 further includes at least one conductive layer 12a.
  • the second stack structure de2 is formed by stacking the conductive layer 12a and the multi-layer insulating layer 12c.
  • the compensation layer 12c extends to the boundary of the second stack structure de2, so as to compensate the height of the area between the first stack structure de1 and the second stack structure de2.
  • the thickness of the compensation layer 12c is greater than the thickness of the first conductive layer 121 .
  • the first stack structure de1 is composed of a part of the first conductive layer 121 , a part of the first insulating layer 124 , a part of the second conductive layer 122 , a second insulating layer 125 , and a part of the third conductive layer 123 .
  • Parts and the third insulating layer 126 are sequentially stacked to form a capacitive structure.
  • the second stack structure is formed by stacking the compensation layer 12 c , the first insulating layer 124 , part of the second conductive layer 122 , the second insulating layer 125 and the third insulating layer 126 . That is to say, the compensation layer 12c and the first conductive layer 121 are disposed on the same layer.
  • the first conductive layer 121 is a light-shielding metal layer.
  • the material of the compensation layer 12c is the same as that of the first conductive layer 121, or it may be different.
  • the second conductive layer 122 includes first electrodes 1221 and wires 1222 .
  • the third conductive layer 123 includes a second electrode 1231 .
  • the first conductive layer 121 is connected to the second electrode 1231 .
  • the first conductive layer 121, the first electrode 1221 and the second electrode 1231 are in a first stacked structure de1.
  • the trace 1222 is in the second stack structure de2.
  • the thickness of the compensation layer 12c is equal to or slightly smaller than the sum of the thicknesses of the first conductive layer 121 and the third conductive layer.
  • part of the second conductive layer 122 of the second stack structure de2 may also be replaced with a part of the third conductive layer 123 , that is, the level position of the wiring 1222 is adjusted.
  • the first stacked structure de1 may also be formed by stacking two conductive layers 12a and two insulating layers 12b, while the second stacked structure de2 is formed by stacking one conductive layer 12a and two insulating layers 12b; for example When the thin film transistor layer is a bottom gate type thin film transistor layer.
  • the first stacked structure de1 consists of a part of the first conductive layer 121, a first insulating layer 124, a part of the second conductive layer 122, a second The second insulating layer 125 , part of the third conductive layer 123 and the third insulating layer 126 are sequentially stacked to form a capacitor structure.
  • the second stack structure de2 is formed by stacking the first insulating layer 124 , part of the second conductive layer 122 , the compensation layer 12 c , the second insulating layer 125 and the third insulating layer 126 . That is, the compensation layer 12c is disposed between the second conductive layer 122 and the second insulating layer 125 .
  • the compensation layer 12 c may also be disposed between the second insulating layer 125 and the third insulating layer 126 , or disposed on the third insulating layer 126 .
  • the multiple compensation layers 12c are arranged in different layers.
  • a compensation layer 12 c is disposed on the same layer as the first conductive layer 121 , and a compensation layer 12 c is disposed on the same layer as the third conductive layer 123 .
  • the arrangement of multiple compensation layers 12c can achieve the effect of gradually increasing the height, which is convenient for film formation in the subsequent process.
  • the second stack structure de2 may also be formed by stacking the compensation layer 12c and the multi-layer insulation layer 12b. That is, the second stack structure de2 does not have the conductive layer 12a.
  • the second stack structure de2 includes a first compensation structure d01 and a second compensation structure d02
  • the first compensation structure d01 includes a first compensation layer 12c1 and multiple insulating layers 12c.
  • the second compensation structure d02 includes a second compensation layer 12c2 and a multilayer insulating layer 12c.
  • the number of conductive layers 12 a of the second compensation structure d02 is smaller than the number of conductive layers 12 a of the first compensation structure d01 .
  • the first compensation layer 12c1 is disposed at any position on the substrate 11 .
  • the second compensation layer 12c2 is disposed at any position on the substrate 11 .
  • the first compensation structure d01 is formed by stacking the first insulating layer 124 , part of the second conductive layer 122 , the first compensation layer 12c1 , the second insulating layer 125 and the third insulating layer 126 . That is to say, the first compensation layer 12c1 and the first conductive layer 121 are disposed on the same layer.
  • the second compensation structure d02 is formed by stacking the second compensation layer 12c2 , the first insulating layer 124 , the second insulating layer 125 and the third insulating layer 126 .
  • the first compensation layer 12c1 and the second compensation layer 12c2 are connected and formed as an integral structure, or each may be an independent structure.
  • the integrally formed structure of the first compensation layer 12c1 and the second compensation layer 12c2 not only saves a photomask process, but also reduces the risk of a steep slope between the first compensation structure d01 and the second compensation structure d02.
  • the thickness of the first compensation layer 12c1 is smaller than the thickness of the second compensation layer 12c2, so as to reduce the height difference between the first compensation structure d01 and the second compensation structure d02.
  • the thickness of the first compensation layer 12c1 and the thickness of the second compensation layer 12c2 may also be equal.
  • the side of the first compensation structure d01 away from the substrate 11 is flush with the side of the second compensation structure d02 away from the substrate 11 .
  • Such an arrangement facilitates the formation of the flat layer 13 having a flat surface.
  • the difference between the display panel 200 of the second embodiment and the display panel 100 of the first embodiment is that the multilayer conductive layer 12a includes a first conductive layer 121, a second conductive layer 122, The third conductive layer 123 and the fourth conductive layer 127 , and the plurality of insulating layers 12 b include a first insulating layer 124 , a second insulating layer 125 , a third insulating layer 126 and a fourth insulating layer 128 .
  • the first stack structure de1 consists of a part of the first conductive layer 121, a first insulating layer 124, a part of the fourth conductive layer 127, a fourth insulating layer 128, a part of the second conductive layer 122, a second insulating layer 125, a third Parts of the conductive layer 123 and the third insulating layer 126 are sequentially stacked to form a thin film transistor structure.
  • the second stack structure de2 is composed of a part of the first conductive layer 121, a first insulating layer 124, a compensation layer 12c, a part of the second conductive layer 122, a second insulating layer 125, a part of the third conductive layer 123 and a third insulating layer. 126 are sequentially stacked to form a capacitive structure.
  • the material of the fourth conductive layer may be a semiconductor material.
  • the difference between the display panel 200 of the second embodiment and the display panel 100 of the first embodiment lies in the difference between the first stack structure de1 and the second stack structure de2.
  • the compensation layer 12c is along the boundary to the first stack structure de1 to compensate the height of the area between the first stack structure de1 and the second stack structure de2.
  • the display panel 200 of the second embodiment is described using the first cross-sectional structure of the display panel 100 of the first embodiment as a comparative example, but it is not limited thereto.
  • the three or fourth cross-sectional structures are comparative examples.
  • the display panel 200 of the second embodiment may be a top emission structure, that is, the electrode layer 14 has light reflection performance.
  • the difference between the display panel 300 of the third embodiment and the display panel 200 of the second embodiment is that:
  • the TFT layer 12 further includes a third stack structure de3 disposed corresponding to the opening 151 .
  • the third stack structure de3 is located on one side of the second stack structure de2.
  • the third stack structure de3 includes a third compensation layer 12c2 and at least one conductive layer 12a.
  • the number of conductive layers 12a in the first stack structure de1 is greater than the number of conductive layers 12a in the third stack structure de3.
  • the third compensation layer 12c3 is disposed at any position on the substrate 11 .
  • the compensation layer 12c is used to raise the second stacked structure de2
  • the third compensation layer 12c3 is used to raise the third stacked structure de3, thereby making up for the height difference between the two and the first stacked structure de1
  • the third compensation layer can also be defined as a pad layer, which is used to pad up the height of the third stack structure de3.
  • the compensation layer 12c and the third compensation layer 12c3 are arranged in the same layer. Such an arrangement compensates for the height difference between the second stack structure de2 and the third stack structure de3 and saves process steps.
  • the thickness of the third compensation layer 12c3 is greater than the thickness of the compensation layer 12c. Such setting is used to make up for the height difference between the second stack structure de2 and the third stack structure de3.
  • the thickness of the third compensation layer 12c3 is greater than or equal to the sum of the thicknesses of the fourth insulating layer 128 and the fourth conductive layer 127 .
  • the side a1 of the first stack structure de1 away from the substrate 11 , the side a2 of the second stack structure de2 away from the substrate, and the side a3 of the third stack structure de3 away from the substrate 11 are arranged flush. Such an arrangement is more convenient for the flat layer 13 to form a flat surface.
  • the first stack structure de1 is a thin film transistor structure
  • the second stack structure de2 is a capacitor structure
  • the third stack structure de3 is a single wire stack structure.
  • the third stack structure de3 consists of the first insulating layer 124, the third compensation layer 12c3, part of the second conductive layer 122, the second insulating layer 125 and the second Three insulating layers 126 are stacked.
  • the difference between the display panel 400 of the fourth embodiment and the display panel 300 of the third embodiment is that: on the basis of the display panel 300 of the third embodiment, the thin film transistor layer 12 includes at least two The third stack structure de3.
  • the display panel 400 of the fourth embodiment is described by taking two third stack structures de3 as an example, but it is not limited thereto.
  • the conductive layers 12a in the two third stacked structures de3 are arranged in different layers.
  • the conductive layer 12a of one third stacked structure de3 is the second conductive layer 122
  • the conductive layer 12a of the other third stacked structure de3 is the third conductive layer.
  • the first stack structure de1 and the second stack structure de2 in the fourth embodiment are the same or similar to the first stack structure de1 and the second stack structure de2 in the third embodiment.
  • the display panel of the embodiment of the present application includes a substrate, a thin film transistor layer, a flat layer, an electrode layer, a pixel definition layer, and a light emitting layer arranged in sequence;
  • the thin film transistor layer includes a first stack structure and a second stack structure, and the first stack structure and
  • the second stacked structures are all correspondingly arranged in the same pixel area,
  • the first stacked structure includes multiple conductive layers arranged in different layers,
  • the second stacked structure includes a compensation layer and at least one conductive layer, and the layers of the conductive layer in the first stacked structure
  • the number is greater than the number of conductive layers of the second stack structure;
  • the compensation layer is used to increase the height of the second stack structure;
  • the flat layer covers the thin film transistor layer, and the surface of the flat layer away from the substrate is a flat surface.
  • a compensation layer is added to the second stack structure to reduce the height difference between the first stack structure and the second stack structure, so that the flat layer can planarize the first stack structure and the second stack structure, which is the light emitting layer.
  • the formation provides a flat reference surface, thereby reducing the risk of uneven film thickness of the light-emitting layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板(100)，薄膜晶体管层(12)包括第一堆叠结构(de1)和第二堆叠结构(de2)，第一堆叠结构(de1)和第二堆叠结构(de2)对应于同一开口(151)设置，第一堆叠结构(de1)包括导电层(12a)和绝缘层(12b)，第二堆叠结构(de2)包括补偿层(12c)和绝缘层(12b)，第一堆叠结构(de1)的导电层(12a)的层数大于第二堆叠结构(de2)的导电层(12a)的层数；补偿层(12c)用于增高第二堆叠结构(de2)的高度；平坦层(13)覆盖薄膜晶体管层(12)。

Description

显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板。
 背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)具有自发光性、应答速度快、广视角等特点，应用前景广阔。对于蒸镀主动式有机发光二极体(Active-matrix Organic Light Emitting Diode，AMOLED)来讲，蒸镀材料到达像素区膜厚均匀性好，对像素区基底平坦度的要求相对较松，而喷墨印刷(Ink Jet Printing，IJP)工艺的AMOLED的墨水打印到像素区是流动的，墨水铺展性的主要影响因素之一是像素区基底的平坦度，要求整个像素区最大段差越小越好，超过该规格时墨水的铺展性不均，则烘干后膜厚不均，最终影响发光效果，因此IJP-AMOLED的平坦化层的平坦能力有了更苛刻的要求。
在对现有技术的研究和实践过程中，本申请的发明人发现，平坦化层是有机感光材料，目前的应对方案是平坦化层的加厚，段差越大需要越厚的平坦化层，所以存在的问题及可能的风险：1、平坦化层的一次平坦化能力是有限的，即当基底段差达到一定程度，平坦化层已经增加至很厚，但平坦度依然不能达到要求；2、平坦化层都有开孔设计，开孔过深对后续的薄膜沉积有影响，比如爬坡断线等不良。
综上所述，现有技术的喷墨打印制程中，平坦化层难以达到制备需求的平整度，整个像素区最大段差较大，墨水的铺展性不均匀，烘干后的发光层膜厚不均匀，进而影响OLED显示面板的显示效果。
 技术问题
本申请实施例提供一种显示面板，可以降低所述发光层膜厚不均匀的风险。
 技术解决方案
本申请实施例提供一种显示面板，所述显示面板包括多个像素区，其包括：
基板；
薄膜晶体管层，所述薄膜晶体管层设置在所述基板上，所述薄膜晶体管层包括第一堆叠结构和第二堆叠结构，所述第一堆叠结构和所述第二堆叠结构均对应设置于同一所述像素区，所述第一堆叠结构包括多层异层设置的导电层和多层绝缘层，所述第二堆叠结构包括补偿层和多层所述绝缘层，所述第一堆叠结构的导电层的层数大于所述第二堆叠结构的导电层的层数；所述第一堆叠结构的高度大于或等于所述第二堆叠结构的高度，所述补偿层用于增高所述第二堆叠结构的高度；
平坦层，所述平坦层覆盖所述薄膜晶体管层，所述平坦层远离所述基板的表面为平坦面；
电极层，所述电极层设置在所述平坦层上；
像素定义层，所述像素定义层设置在所述电极层上，所述像素定义层包括多个开口，一所述开口对应设置在一所述像素区，所述第一堆叠结构和所述第二堆叠结构对应同一所述开口设置；以及
发光层，所述发光层设置在所述开口内。
可选的，在本申请的一些实施例中，所述第一堆叠结构远离所述基板的一面与所述第二堆叠结构远离所述基板的一面齐平。
可选的，在本申请的一些实施例中，所述平坦层远离所述基板的表面对应于所述像素区的部分为平坦面。
可选的，在本申请的一些实施例中，所述薄膜晶体管层还包括多层堆叠设置在所述基板上的绝缘层，所述导电层设置在相邻的两层所述绝缘层之间；
在所述第二堆叠结构的堆叠的方向上，所述补偿层设置在所述基板上的任意位置。
可选的，在本申请的一些实施例中，所述补偿层具有多个，在所述第二堆叠结构的堆叠的方向上，多个所述补偿层相互异层设置。
可选的，在本申请的一些实施例中，所述第二堆叠结构还包括至少一所述导电层。
可选的，在本申请的一些实施例中，所述第二堆叠结构包括第一补偿结构和第二补偿结构，所述第一补偿结构包括第一补偿层和多层所述绝缘层；所述第二补偿结构包括第二补偿层和多层所述绝缘层，所述第二补偿结构的所述导电层的层数小于所述第一补偿结构的所述导电层的层数；
在所述第一补偿结构的堆叠的方向上，所述第一补偿层设置在所述基板上的任意位置；
在所述第二补偿结构的堆叠的方向上，所述第二补偿层设置在所述基板上的任意位置。
可选的，在本申请的一些实施例中，所述第一补偿层和所述第二补偿层相连。
可选的，在本申请的一些实施例中，所述第一补偿层的厚度小于第二补偿层的厚度。
可选的，在本申请的一些实施例中，所述薄膜晶体管层还包括对应所述开口设置于的第三堆叠结构，在同一所述开口的区域中，所述第三堆叠结构位于所述第二堆叠结构的一侧，所述第三堆叠结构包括所述第二补偿层和至少一所述导电层，所述第二堆叠结构的导电层的层数大于所述第三堆叠结构的导电层的层数；
在所述第三堆叠结构的堆叠的方向上，所述第三补偿层设置在所述基板上的任意位置。
可选的，在本申请的一些实施例中，所述第一堆叠结构远离所述基板的一面、所述第二堆叠结构远离所述基板的一面以及所述第三堆叠结构远离所述基板的一面齐平设置。
可选的，在本申请的一些实施例中，多层所述导电层包括第一导电层、第二导电层和第三导电层，多个所述绝缘层包括第一绝缘层、第二绝缘层和第三绝缘层；
所述第一堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述第二导电层的部分、所述第二绝缘层、所述第三导电层的部分和所述第三绝缘层依次堆叠形成的电容结构；所述第二堆叠结构由所述补偿层、所述第一绝缘层、所述第二导电层的部分、所述第二绝缘层和所述第三绝缘层堆叠形成。
可选的，在本申请的一些实施例中，所述补偿层的厚度等于或小于所述第一导电层和所述第三导电层的厚度之和。
可选的，在本申请的一些实施例中，多层所述导电层包括第一导电层、第二导电层、第三导电层和第四导电层，多个所述绝缘层包括第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
所述第一堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述第四导电层的部分、所述第四绝缘层、所述第二导电层的部分、所述第二绝缘层、第三导电层的部分和所述第三绝缘层依次堆叠形成的薄膜晶体管结构；所述第二堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述补偿层、所述第二导电层的部分、所述第二绝缘层、所述第三导电层的部分和所述第三绝缘层依次堆叠形成的电容结构。
可选的，在本申请的一些实施例中，多层所述导电层包括第一导电层、第二导电层、第三导电层和第四导电层，多个所述绝缘层包括第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
所述第一堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述第四导电层的部分、所述第四绝缘层、所述第二导电层的部分、所述第二绝缘层、第三导电层的部分和所述第三绝缘层依次堆叠形成的薄膜晶体管结构；所述第二堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述补偿层、所述第二导电层的部分、所述第二绝缘层、所述第三导电层的部分和所述第三绝缘层依次堆叠形成的电容结构；所述第三堆叠结构由所述第三补偿层、所述第一绝缘层、所述第二导电层的部分、所述第二绝缘层和所述第三绝缘层堆叠形成。
可选的，在本申请的一些实施例中，所述第三补偿层的厚度大于或等于所述第四绝缘层和所述第四导电层厚度之和。
相应的，本申请实施例还涉及一种显示面板，包括多个像素区，其中，所述显示面板包括：
基板；
薄膜晶体管层，所述薄膜晶体管层设置在所述基板上，所述薄膜晶体管层包括第一堆叠结构和第二堆叠结构，所述第一堆叠结构包括多层异层设置的导电层和多层绝缘层，所述第二堆叠结构包括补偿层和多层所述绝缘层，所述第一堆叠结构的导电层的层数大于所述第二堆叠结构的导电层的层数；所述第一堆叠结构的高度大于或等于所述第二堆叠结构的高度，所述补偿层用于增高所述第二堆叠结构的高度；
平坦层，所述平坦层覆盖所述薄膜晶体管层；
电极层，所述电极层设置在所述平坦层上；
像素定义层，所述像素定义层设置在所述电极层上，所述像素定义层包括多个开口，一所述开口对应设置在一所述像素区，所述第一堆叠结构和所述第二堆叠结构对应同一所述开口设置；以及
发光层，所述发光层设置在所述开口内；
所述第一堆叠结构远离所述基板的一面与所述第二堆叠结构远离所述基板的一面齐平；所述平坦层远离所述基板的表面对应于所述像素区的部分为平坦面。
可选的，在本申请的一些实施例中，在所述第二堆叠结构的堆叠的方向上，所述补偿层设置在所述基板上的任意位置。
可选的，在本申请的一些实施例中，所述补偿层具有多个，在所述第二堆叠结构的堆叠的方向上，多个所述补偿层相互异层设置。
可选的，在本申请的一些实施例中，所述第二堆叠结构还包括至少一所述导电层。
 有益效果
本申请实施例的显示面板，包括依次设置的基板、薄膜晶体管层、平坦层、电极层、像素定义层和发光层；薄膜晶体管层包括第一堆叠结构和第二堆叠结构，第一堆叠结构和所述第二堆叠结构均对应设置于同一像素区，第一堆叠结构包括多层异层设置的导电层和绝缘层，第二堆叠结构包括补偿层和多层绝缘层，第一堆叠结构的导电层的层数大于第二堆叠结构的导电层的层数；补偿层用于增高所述第二堆叠结构的高度；平坦层覆盖薄膜晶体管层。本实施例的显示面板通过在第二堆叠结构增设补偿层以降低第一堆叠结构和第二堆叠结构的高度差，使得平坦层能平坦化第一堆叠结构和第二堆叠结构，至少为发光层的形成提供一个相对平坦的基准面，进而降低发光层的膜厚不均匀的风险。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请第一实施例提供的显示面板的俯视结构示意图；
图2是本申请第一实施例提供的显示面板的第一种剖视结构示意图；
图3是本申请第一实施例提供的显示面板的第二种视结构示意图；
图4是本申请第一实施例提供的显示面板的第三种视结构示意图；
图5是本申请第一实施例提供的显示面板的第四种视结构示意图；
图6是本申请第二实施例提供的显示面板的俯视结构示意图；
图7是本申请第二实施例提供的显示面板的剖视结构示意图；
图8是本申请第三实施例提供的显示面板的俯视结构示意图；
图9是本申请第三实施例提供的显示面板的剖视结构示意图；
图10是本申请第四实施例提供的显示面板的俯视结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种显示面板，下文进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参照图1和图2，本申请实施例提供一种显示面板100，显示面板100包括多个像素区px。显示面板100包括基板11、薄膜晶体管层12、平坦层13、电极层14、像素定义层15和发光层16。
薄膜晶体管层12设置在基板11上。薄膜晶体管层12包括第一堆叠结构de1和第二堆叠结构de2，第一堆叠结构de1和第二堆叠结构de2均对应设置于同一像素区px。第一堆叠结构de1包括多层异层设置的导电层12a和多层绝缘层12b。第二堆叠结构de2包括补偿层12c和多层绝缘层12b。第一堆叠结构de1的导电层12a的层数大于第二堆叠结构de2的导电层12a的层数。第一堆叠结构de1的高度h1大于或等于第二堆叠结构de2的高度h2。补偿层12c用于增高第二堆叠结构de2的高度。
平坦层13覆盖薄膜晶体管层12。电极层14设置在平坦层13上。像素定义层15设置在电极层14上。像素定义层15包括多个开口151，一开口151对应设置在一像素区px。发光层16设置在开口151内。第一堆叠结构de1和第二堆叠结构de2对应同一开口151设置。
本第一实施例的显示面板100通过在第二堆叠结构de2增设补偿层12c以降低现有技术中第一堆叠结构和第二堆叠结构的高度差，使得平坦层13能平坦化第一堆叠结构de1和第二堆叠结构de2，至少为发光层16的形成提供一个相对平坦的基准面，进而降低发光层16的膜厚不均匀的风险。
可选的，平坦层13远离基板11的表面对应于像素区px的部分为平坦面。这样的设置为发光层16的形成提供一个平坦的基准面，进一步降低发光层16的膜厚不均匀的风险。
可选的，基板11可为硬性基板或者柔性衬底。基板11的材质包括玻璃、蓝宝石、硅、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种。
可选的，补偿层12c的材料可以是金属材料也可以是无机或有机材料，比如氧化硅、氮化硅、树脂、铜或合金等。
可选的，平坦层13的材料可以是有机透明膜层，比如透明光刻胶，环氧树脂、聚酰亚胺、聚乙烯醇、聚甲基丙烯酸甲酯、聚苯乙烯等。
可选的，显示面板100还包括另一电极层，另一电极层设置在发光层16上。其中，两个电极层中，一个为阳极，另一个为阴极。
请参照图2，可选的，第一堆叠结构de1远离基板11的一面a1与第二堆叠结构de2远离基板11的一面a2齐平。这样的设置使得第一堆叠结构de1和第二堆叠结构de2等高，便于平坦层13进行平坦化处理。
可选的，在一些实施例中，第一堆叠结构de1的面a1和第二堆叠结构de2的面a2也可以存在一定的高度差，只要平坦层13能够平坦第一堆叠结构de1和第二堆叠结构de2后，形成相对平坦的基准面即可。
可选的，薄膜晶体管层12还包括多层堆叠设置在基板11上的绝缘层12b，导电层12a设置在相邻的两层所述绝缘层12b之间。
在第二堆叠结构de2的堆叠的方向上，补偿层12c设置在基板11上的任意位置。
比如，可选的，多层导电层12a包括第一导电层121、第二导电层122和第三导电层123。多个绝缘层12b包括第一绝缘层124、第二绝缘层125和第三绝缘层126。
可选的，第二堆叠结构de2还包括至少一导电层12a。第二堆叠结构de2由导电层12a和多层绝缘层12c堆叠形成。
可选的，补偿层12c延伸至第二堆叠结构de2的边界处，以补偿第一堆叠结构de1和第二堆叠结构de2之间区域的高度。
可选的，补偿层12c的厚度大于第一导电层121的厚度。
如图2所示，可选的，第一堆叠结构de1由第一导电层121的部分、第一绝缘层124、第二导电层122的部分、第二绝缘层125、第三导电层123的部分和第三绝缘层126依次堆叠形成的电容结构。
第二堆叠结构由补偿层12c、第一绝缘层124、第二导电层122的部分、第二绝缘层125和第三绝缘层126堆叠形成。也就是说，补偿层12c与第一导电层121同层设置。
其中第一导电层121是遮光金属层。补偿层12c的材质与第一导电层121的材质一样，也可以是不同。第二导电层122包括第一电极1221和走线1222。第三导电层123包括第二电极1231。第一导电层121连接第二电极1231。
第一导电层121、第一电极1221和第二电极1231处于第一堆叠结构de1。走线1222处于第二堆叠结构de2。
可选的，补偿层12c的厚度等于或略小于第一导电层121和第三导电层的厚度之和。
可选的，在一些实施例中，也可以将第二堆叠结构de2的第二导电层122的部分替换为第三导电层123的部分，也即调整了走线1222的层级位置。
在一些实施例中，第一堆叠结构de1也可以有两层导电层12a和两层绝缘层12b堆叠形成，而第二堆叠结构de2由一层导电层12a和两层绝缘层12b堆叠形成；比如薄膜晶体管层为底栅型薄膜晶体管层时。
请参照图3，可选的，在本第一实施例的另一结构中，第一堆叠结构de1由第一导电层121的部分、第一绝缘层124、第二导电层122的部分、第二绝缘层125、第三导电层123的部分和第三绝缘层126依次堆叠形成的电容结构。
第二堆叠结构de2由第一绝缘层124、第二导电层122的部分、补偿层12c、第二绝缘层125和第三绝缘层126堆叠形成。也就是说，补偿层12c设置在第二导电层122和第二绝缘层125之间。
当然，补偿层12c也可以设置在第二绝缘层125和第三绝缘层126之间，或设置在第三绝缘层126上。
请参照图4，可选的，在本第一实施例的再一结构中，补偿层12c具有多个，在第二堆叠结构de2的堆叠的方向上，多个补偿层12c相互异层设置。
比如一补偿层12c与第一导电层121同层设置，一补偿层12c与第三导电层123同层设置。采用多个补偿层12c的设置起到逐步增高的效果，便于后续制程的成膜。
在一些实施例中，第二堆叠结构de2也可以是由补偿层12c和多层绝缘层12b堆叠形成。也就是说，第二堆叠结构de2没有导电层12a。
请参照图5，本第一实施例的显示面板100的又一种结构中，第二堆叠结构de2包括第一补偿结构d01和第二补偿结构d02，第一补偿结构d01包括第一补偿层12c1和多层绝缘层12c。第二补偿结构d02包括第二补偿层12c2和多层绝缘层12c。第二补偿结构d02的导电层12a的层数小于第一补偿结构d01的导电层12a的层数。
在第一补偿结构d01的堆叠的方向上，第一补偿层12c1设置在基板11上的任意位置。
在第二补偿结构d02的堆叠的方向上，第二补偿层12c2设置在基板11上的任意位置。
第一补偿结构d01由第一绝缘层124、第二导电层122的部分、第一补偿层12c1、第二绝缘层125和第三绝缘层126堆叠形成。也就是说，第一补偿层12c1与第一导电层121同层设置。
第二补偿结构d02由第二补偿层12c2、第一绝缘层124、第二绝缘层125和第三绝缘层126堆叠形成。
可选的，第一补偿层12c1和第二补偿层12c2相连，且为一体成型结构，也可以各自是独立结构。采用第一补偿层12c1和第二补偿层12c2相连且一体成型结构，不但节省了一道光罩制程，而且降低了第一补偿结构d01和第二补偿结构d02之间存在陡坡的风险。
可选的，第一补偿层12c1的厚度小于第二补偿层12c2的厚度，以减少第一补偿结构d01和第二补偿结构d02的高度差。
在一些实施例中，第一补偿层12c1的厚度和第二补偿层12c2的厚度也可以相等。
可选的，第一补偿结构d01远离基板11的一面与第二补偿结构d02远离基板11的一面齐平设置。这样的设置便于形成具有平坦面的平坦层13。
请参照图6和图7，本第二实施例的显示面板200与第一实施例的显示面板100的不同之处在于，多层导电层12a包括第一导电层121、第二导电层122、第三导电层123和第四导电层127，多个绝缘层12b包括第一绝缘层124、第二绝缘层125、第三绝缘层126和第四绝缘层128。
第一堆叠结构de1由第一导电层121的部分、第一绝缘层124、第四导电层127的部分、第四绝缘层128、第二导电层122的部分、第二绝缘层125、第三导电层123的部分和第三绝缘层126依次堆叠形成的薄膜晶体管结构。
第二堆叠结构de2由第一导电层121的部分、第一绝缘层124、补偿层12c、第二导电层122的部分、第二绝缘层125、第三导电层123的部分和第三绝缘层126依次堆叠形成的电容结构。
其中，第四导电层的材料可以是半导体材料。
也就是说，第二实施例的显示面板200和第一实施例的显示面板100的不同之处在于第一堆叠结构de1和第二堆叠结构de2的不同。
可选的，补偿层12c沿着至第一堆叠结构de1的边界处，以补偿第一堆叠结构de1和第二堆叠结构de2之间区域的高度。
需要说明的是，本第二实施例的显示面板200以第一实施例的显示面板100的第一种剖视结构为对比例进行说明，但不限于此，比如也可以以第二种、第三种或第四种剖视结构为对比例。
可选的，本第二实施例的显示面板200可以是顶发光架构，也即电极层14具有反光性能。
请参照图8和图9，本第三实施例的显示面板300与第二实施例的显示面板200的不同之处在于：
薄膜晶体管层12还包括对应开口151设置的第三堆叠结构de3。在同一开口151的区域中，第三堆叠结构de3位于第二堆叠结构de2的一侧。第三堆叠结构de3包括第三补偿层12c2和至少一导电层12a。第一堆叠结构de1的导电层12a的层数大于第三堆叠结构de3的导电层12a的层数。
在第三堆叠结构de3的堆叠的方向上，第三补偿层12c3设置在基板11上的任意位置。
本第三实施例的显示面板300采用补偿层12c垫高第二堆叠结构de2，采用第三补偿层12c3垫高第三堆叠结构de3，从而弥补了二者与第一堆叠结构de1的高度差，便于后续形成较为平坦或平坦的平坦层13。
可选的，第三补偿层也可以被定义为垫高层，用于垫高第三堆叠结构de3的高度。
可选的，补偿层12c和第三补偿层12c3同层设置。这样的设置以弥补第二堆叠结构de2和第三堆叠结构de3之间的高度差，且节省制程步骤。
可选的，第三补偿层12c3的厚度大于补偿层12c的厚度。这样的设置以弥补第二堆叠结构de2和第三堆叠结构de3的高度差。
可选的，第三补偿层12c3的厚度大于或等于第四绝缘层128和第四导电层127厚度之和。
可选的，第一堆叠结构de1远离基板11的一面a1、第二堆叠结构de2远离基板的一面a2以及第三堆叠结构de3远离基板11的一面a3齐平设置。这样的设置更便于平坦层13形成平坦面。
可选的，第一堆叠结构de1为薄膜晶体管结构，第二堆叠结构de2为电容结构，第三堆叠结构de3为单一走线堆叠结构。
可选的，在第二实施例的显示面板400的基础上，第三堆叠结构de3由第一绝缘层124、第三补偿层12c3、第二导电层122的部分、第二绝缘层125和第三绝缘层126堆叠形成。
请参照图10，本第四实施例的显示面板400与第三实施例的显示面板300的不同之处在于：在第三实施例的显示面板300的基础上，薄膜晶体管层12包括至少两个第三堆叠结构de3。本第四实施例的显示面板400以两个第三堆叠结构de3为例进行说明，但不限于此。
其中两个第三堆叠结构de3中的导电层12a异层设置，比如一个第三堆叠结构de3的导电层12a是第二导电层122，另一个第三堆叠结构de3的导电层12a是第三导电层123。
其中第四实施例中的第一堆叠结构de1和第二堆叠结构de2与第三实施例中的第一堆叠结构de1和第二堆叠结构de2的结构相同或相似。
本申请实施例的显示面板，包括依次设置的基板、薄膜晶体管层、平坦层、电极层、像素定义层和发光层；薄膜晶体管层包括第一堆叠结构和第二堆叠结构，第一堆叠结构和所述第二堆叠结构均对应设置于同一像素区，第一堆叠结构包括多层异层设置的导电层，第二堆叠结构包括补偿层和至少一导电层，第一堆叠结构的导电层的层数大于第二堆叠结构的导电层的层数；补偿层用于增高所述第二堆叠结构的高度；平坦层覆盖薄膜晶体管层，平坦层远离所述基板的表面为平坦面。本实施例的显示面板通过在第二堆叠结构增设补偿层以降低第一堆叠结构和第二堆叠结构的高度差，使得平坦层能平坦化第一堆叠结构和第二堆叠结构，为发光层的形成提供一个平坦的基准面，进而降低发光层的膜厚不均匀的风险。
以上对本申请实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，包括多个像素区，其中，所述显示面板包括：
    基板；
    薄膜晶体管层，所述薄膜晶体管层设置在所述基板上，所述薄膜晶体管层包括第一堆叠结构和第二堆叠结构，所述第一堆叠结构包括多层异层设置的导电层和多层绝缘层，所述第二堆叠结构包括补偿层和多层所述绝缘层，所述第一堆叠结构的导电层的层数大于所述第二堆叠结构的导电层的层数；所述第一堆叠结构的高度大于或等于所述第二堆叠结构的高度，所述补偿层用于增高所述第二堆叠结构的高度；
    平坦层，所述平坦层覆盖所述薄膜晶体管层；
    电极层，所述电极层设置在所述平坦层上；
    像素定义层，所述像素定义层设置在所述电极层上，所述像素定义层包括多个开口，一所述开口对应设置在一所述像素区，所述第一堆叠结构和所述第二堆叠结构对应同一所述开口设置；以及
    发光层，所述发光层设置在所述开口内。
  2. 根据权利要求1所述的显示面板，其中，所述第一堆叠结构远离所述基板的一面与所述第二堆叠结构远离所述基板的一面齐平。
  3. 根据权利要求1所述的显示面板，其中，所述平坦层远离所述基板的表面对应于所述像素区的部分为平坦面。
  4. 根据权利要求1所述的显示面板，其中，在所述第二堆叠结构的堆叠的方向上，所述补偿层设置在所述基板上的任意位置。
  5. 根据权利要求4所述的显示面板，其中，所述补偿层具有多个，在所述第二堆叠结构的堆叠的方向上，多个所述补偿层相互异层设置。
  6. 根据权利要求1所述的显示面板，其中，所述第二堆叠结构还包括至少一所述导电层。
  7. 根据权利要求6所述的显示面板，其中，所述第二堆叠结构包括第一补偿结构和第二补偿结构，所述第一补偿结构包括第一补偿层和多层所述绝缘层；所述第二补偿结构包括第二补偿层和多层所述绝缘层，所述第二补偿结构的所述导电层的层数小于所述第一补偿结构的所述导电层的层数；
    在所述第一补偿结构的堆叠的方向上，所述第一补偿层设置在所述基板上的任意位置；
    在所述第二补偿结构的堆叠的方向上，所述第二补偿层设置在所述基板上的任意位置。
  8. 根据权利要求7所述的显示面板，其中，所述第一补偿层和所述第二补偿层相连。
  9. 根据权利要求7所述的显示面板，其中，所述第一补偿层的厚度小于第二补偿层的厚度。
  10. 根据权利要求6所述的显示面板，其中，所述薄膜晶体管层还包括对应所述开口设置于的第三堆叠结构，在同一所述开口的区域中，所述第三堆叠结构位于所述第二堆叠结构的一侧，所述第三堆叠结构包括第三补偿层和至少一所述导电层，所述第一堆叠结构的所述导电层的层数大于所述第三堆叠结构的导电层的层数；
    在所述第三堆叠结构的堆叠方向上，所述第三补偿层设置在所述基板上的任意位置。
  11. 根据权利要求10所述的显示面板，其中，所述第一堆叠结构远离所述基板的一面、所述第二堆叠结构远离所述基板的一面以及所述第三堆叠结构远离所述基板的一面齐平设置。
  12. 根据权利要求4所述的显示面板，其中，多层所述导电层包括第一导电层、第二导电层和第三导电层，多个所述绝缘层包括第一绝缘层、第二绝缘层和第三绝缘层；
    所述第一堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述第二导电层的部分、所述第二绝缘层、所述第三导电层的部分和所述第三绝缘层依次堆叠形成的电容结构；所述第二堆叠结构由所述补偿层、所述第一绝缘层、所述第二导电层的部分、所述第二绝缘层和所述第三绝缘层堆叠形成。
  13. 根据权利要求12所述的显示面板，其中，所述补偿层的厚度等于或小于所述第一导电层和所述第三导电层的厚度之和。
  14. 根据权利要求4所述的显示面板，其中，多层所述导电层包括第一导电层、第二导电层、第三导电层和第四导电层，多个所述绝缘层包括第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
    所述第一堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述第四导电层的部分、所述第四绝缘层、所述第二导电层的部分、所述第二绝缘层、第三导电层的部分和所述第三绝缘层依次堆叠形成的薄膜晶体管结构；所述第二堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述补偿层、所述第二导电层的部分、所述第二绝缘层、所述第三导电层的部分和所述第三绝缘层依次堆叠形成的电容结构。
  15. 根据权利要求10所述的显示面板，其中，多层所述导电层包括第一导电层、第二导电层、第三导电层和第四导电层，多个所述绝缘层包括第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
    所述第一堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述第四导电层的部分、所述第四绝缘层、所述第二导电层的部分、所述第二绝缘层、第三导电层的部分和所述第三绝缘层依次堆叠形成的薄膜晶体管结构；所述第二堆叠结构由所述第一导电层的部分、所述第一绝缘层、所述补偿层、所述第二导电层的部分、所述第二绝缘层、所述第三导电层的部分和所述第三绝缘层依次堆叠形成的电容结构；所述第三堆叠结构由所述第一绝缘层、所述第三补偿层、所述第二导电层的部分、所述第二绝缘层和所述第三绝缘层堆叠形成。
  16. 根据权利要求15所述的显示面板，其中，所述第三补偿层的厚度大于或等于所述第四绝缘层和所述第四导电层厚度之和。
  17. 一种显示面板，包括多个像素区，其中，所述显示面板包括：
    基板；
    薄膜晶体管层，所述薄膜晶体管层设置在所述基板上，所述薄膜晶体管层包括第一堆叠结构和第二堆叠结构，所述第一堆叠结构包括多层异层设置的导电层和多层绝缘层，所述第二堆叠结构包括补偿层和多层所述绝缘层，所述第一堆叠结构的导电层的层数大于所述第二堆叠结构的导电层的层数；所述第一堆叠结构的高度大于或等于所述第二堆叠结构的高度，所述补偿层用于增高所述第二堆叠结构的高度；
    平坦层，所述平坦层覆盖所述薄膜晶体管层；
    电极层，所述电极层设置在所述平坦层上；
    像素定义层，所述像素定义层设置在所述电极层上，所述像素定义层包括多个开口，一所述开口对应设置在一所述像素区，所述第一堆叠结构和所述第二堆叠结构对应同一所述开口设置；以及
    发光层，所述发光层设置在所述开口内；
    所述第一堆叠结构远离所述基板的一面与所述第二堆叠结构远离所述基板的一面齐平；所述平坦层远离所述基板的表面对应于所述像素区的部分为平坦面。
  18. 根据权利要求17所述的显示面板，其中，在所述第二堆叠结构的堆叠的方向上，所述补偿层设置在所述基板上的任意位置。
  19. 根据权利要求18所述的显示面板，其中，所述补偿层具有多个，在所述第二堆叠结构的堆叠的方向上，多个所述补偿层相互异层设置。
  20. 根据权利要求17所述的显示面板，其中，所述第二堆叠结构还包括至少一所述导电层。
PCT/CN2021/116072 2021-08-27 2021-09-01 显示面板 Ceased WO2023024136A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/599,822 US20240049520A1 (en) 2021-08-27 2021-09-01 Display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110996827.2 2021-08-27
CN202110996827.2A CN113745293B (zh) 2021-08-27 2021-08-27 显示面板

Publications (1)

Publication Number Publication Date
WO2023024136A1 true WO2023024136A1 (zh) 2023-03-02

Family

ID=78733549

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/116072 Ceased WO2023024136A1 (zh) 2021-08-27 2021-09-01 显示面板

Country Status (3)

Country Link
US (1) US20240049520A1 (zh)
CN (1) CN113745293B (zh)
WO (1) WO2023024136A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114843315B (zh) * 2022-04-06 2025-08-01 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法
CN119816119B (zh) * 2025-01-24 2026-01-02 广州华星光电半导体显示技术有限公司 显示面板以及显示设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107068719A (zh) * 2017-04-19 2017-08-18 京东方科技集团股份有限公司 一种显示基板、其制作方法及显示装置
CN111146215A (zh) * 2020-02-21 2020-05-12 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN111987136A (zh) * 2020-09-09 2020-11-24 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制备方法
CN112018159A (zh) * 2020-08-27 2020-12-01 京东方科技集团股份有限公司 触控显示面板
EP3806151A1 (en) * 2019-10-08 2021-04-14 Imec VZW Thin-film transistor architecture for high resolution displays
CN113097223A (zh) * 2021-03-17 2021-07-09 深圳市华星光电半导体显示技术有限公司 阵列基板、显示面板及阵列基板的制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100700642B1 (ko) * 2004-12-13 2007-03-27 삼성에스디아이 주식회사 유기전계발광표시소자 및 그 제조방법
KR102437180B1 (ko) * 2017-12-06 2022-08-26 엘지디스플레이 주식회사 투명 유기발광 다이오드 표시장치
KR102491883B1 (ko) * 2018-01-18 2023-01-27 삼성디스플레이 주식회사 표시 장치 및 그 제조방법
CN208521937U (zh) * 2018-05-30 2019-02-19 云谷（固安）科技有限公司 柔性显示面板
CN110767714B (zh) * 2019-03-25 2022-03-08 昆山国显光电有限公司 透明阵列基板、透明显示面板、显示面板及显示终端
CN112909196B (zh) * 2021-02-05 2022-08-30 合肥维信诺科技有限公司 显示面板及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107068719A (zh) * 2017-04-19 2017-08-18 京东方科技集团股份有限公司 一种显示基板、其制作方法及显示装置
EP3806151A1 (en) * 2019-10-08 2021-04-14 Imec VZW Thin-film transistor architecture for high resolution displays
CN111146215A (zh) * 2020-02-21 2020-05-12 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN112018159A (zh) * 2020-08-27 2020-12-01 京东方科技集团股份有限公司 触控显示面板
CN111987136A (zh) * 2020-09-09 2020-11-24 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制备方法
CN113097223A (zh) * 2021-03-17 2021-07-09 深圳市华星光电半导体显示技术有限公司 阵列基板、显示面板及阵列基板的制作方法

Also Published As

Publication number Publication date
CN113745293B (zh) 2023-05-09
CN113745293A (zh) 2021-12-03
US20240049520A1 (en) 2024-02-08

Similar Documents

Publication Publication Date Title
CN112018153B (zh) 显示设备
CN109192878B (zh) 柔性oled显示面板
US10325892B2 (en) Light emitting device and manufacturing method thereof
US11335870B2 (en) Display substrate and preparation method thereof, and display device
US20240196721A1 (en) Display panel and display device
US11075228B2 (en) Display substrate, method for manufacturing the same, and display device
US12082463B2 (en) Display apparatus
KR20180061903A (ko) 두 개의 전극들 사이에 위치하는 다수의 절연막들을 포함하는 디스플레이 장치
WO2021093687A1 (zh) 显示基板及其制备方法、显示装置
WO2020113794A1 (zh) 显示面板及其制造方法
WO2019037520A1 (zh) 显示基板及显示装置
US11043545B2 (en) Display substrate, fabricating method thereof, and display device
CN107079561A (zh) 显示装置、制造显示装置的方法以及电子装置
KR102555411B1 (ko) 발광 소자를 포함하는 디스플레이 장치
WO2022073284A1 (zh) Oled显示面板及其制作方法
CN112086465A (zh) 显示装置
CN111430383B (zh) 阵列基板及其制作方法、显示装置
CN107910349A (zh) 一种柔性显示面板及制作方法
WO2023024136A1 (zh) 显示面板
CN113097223A (zh) 阵列基板、显示面板及阵列基板的制作方法
WO2022077771A1 (zh) 显示面板及其制作方法
WO2020118920A1 (zh) 有机发光二极管阵列基板及其制造方法
US12610694B2 (en) Method of manufacturing display device and mother substrate
US12426449B2 (en) Display panel and method for fabricating display panel
CN115064568B (zh) 显示面板及其制造方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17599822

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21954659

Country of ref document: EP

Kind code of ref document: A1